[ARM] Select a number of fp16 rounding functions

[dmgreen]

Summary

This add patterns for fp16 round and ceil etc. Same as the float and double patterns.

Round needs to be marked as legal. The others already are.

[SjoerdMeijer]

llvm/test/CodeGen/ARM/fp16-full.ll

491 ↗

(On Diff #200989)

There's a TODO in fp16-instructions.ll for these instructions. Either move the test there, or remove the TODOs.

[dmgreen]

llvm/test/CodeGen/ARM/fp16-full.ll

491 ↗

(On Diff #200989)

Oh yeah. I think I saw that file and decided it was too messy and was trying to do too much. I really needed something that could auto-generate the tests.

There is also fp16-promote.ll which is where a lot of these tests came from and seemed a lot cleaner. Ideally neither of these tests would require loading from half pointers or the float coerce thing, which would make them cleaner still.

Anyway. I'll remove the TODO's, seeing as they are covered elsewhere.

[SjoerdMeijer]

This looks good to me.

Bikeshedding names: perhaps you can think about the filename fp16-full.ll as it is not really descriptive.

llvm/lib/Target/ARM/ARMISelLowering.cpp

if (Subtarget->hasFullFP16()) {
     setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
     setOperationAction(ISD::FPOWI, MVT::f16, Promote);
     setOperationAction(ISD::FPOW, MVT::f16, Promote);
     setOperationAction(ISD::FEXP, MVT::f16, Promote);
     setOperationAction(ISD::FEXP2, MVT::f16, Promote);
     setOperationAction(ISD::FLOG, MVT::f16, Promote);
     setOperationAction(ISD::FLOG10, MVT::f16, Promote);
     setOperationAction(ISD::FLOG2, MVT::f16, Promote);
+
+    setOperationAction(ISD::FROUND, MVT::f16, Legal);
   }
 
   if (Subtarget->hasNEON()) {
     // vmin and vmax aren't available in a scalar form, so we use
     // a NEON instruction with an undef lane instead.
     setOperationAction(ISD::FMINIMUM, MVT::f16, Legal);
     setOperationAction(ISD::FMAXIMUM, MVT::f16, Legal);
     setOperationAction(ISD::FMINIMUM, MVT::f32, Legal);

llvm/lib/Target/ARM/ARMInstrVFP.td

 
 def VNEGH  : AHuI<0b11101, 0b11, 0b0001, 0b01, 0,
                   (outs HPR:$Sd), (ins HPR:$Sm),
                   IIC_fpUNA16, "vneg", ".f16\t$Sd, $Sm",
                   [(set HPR:$Sd, (fneg HPR:$Sm))]>;
 
 multiclass vrint_inst_zrx<string opc, bit op, bit op2, SDPatternOperator node> {
   def H : AHuI<0b11101, 0b11, 0b0110, 0b11, 0,
-               (outs SPR:$Sd), (ins SPR:$Sm),
+               (outs HPR:$Sd), (ins HPR:$Sm),
                NoItinerary, !strconcat("vrint", opc), ".f16\t$Sd, $Sm",
-               []>,
+               [(set (f16 HPR:$Sd), (node (f16 HPR:$Sm)))]>,
                Requires<[HasFullFP16]> {
     let Inst{7} = op2;
     let Inst{16} = op;
   }
 
   def S : ASuI<0b11101, 0b11, 0b0110, 0b11, 0,
                (outs SPR:$Sd), (ins SPR:$Sm),
                NoItinerary, !strconcat("vrint", opc), ".f32\t$Sd, $Sm",

 defm VRINTR : vrint_inst_zrx<"r", 0, 0, fnearbyint>;
 defm VRINTX : vrint_inst_zrx<"x", 1, 0, frint>;
 
 multiclass vrint_inst_anpm<string opc, bits<2> rm,
                            SDPatternOperator node = null_frag> {
   let PostEncoderMethod = "", DecoderNamespace = "VFPV8",
       isUnpredicable = 1 in {
     def H : AHuInp<0b11101, 0b11, 0b1000, 0b01, 0,
-                   (outs SPR:$Sd), (ins SPR:$Sm),
+                   (outs HPR:$Sd), (ins HPR:$Sm),
                    NoItinerary, !strconcat("vrint", opc, ".f16\t$Sd, $Sm"),
-                   []>,
+                   [(set (f16 HPR:$Sd), (node (f16 HPR:$Sm)))]>,
                    Requires<[HasFullFP16]> {
       let Inst{17-16} = rm;
     }
     def S : ASuInp<0b11101, 0b11, 0b1000, 0b01, 0,
                    (outs SPR:$Sd), (ins SPR:$Sm),
                    NoItinerary, !strconcat("vrint", opc, ".f32\t$Sd, $Sm"),
                    [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
                    Requires<[HasFPARMv8]> {

llvm/test/CodeGen/ARM/fp16-fullfp16.ll

 ; CHECK-NEXT:    bx lr
   %a = load half, half* %p, align 2
   %b = load half, half* %q, align 2
   %r = call half @llvm.copysign.f16(half %a, half %b)
   store half %r, half* %p
   ret void
 }
 
-; FIXME
-;define void @test_floor(half* %p) {
-;  %a = load half, half* %p, align 2
-;  %r = call half @llvm.floor.f16(half %a)
-;  store half %r, half* %p
-;  ret void
-;}
+define void @test_floor(half* %p) {
+; CHECK-LABEL: test_floor:
+; CHECK:         vldr.16 s0, [r0]
+; CHECK-NEXT:    vrintm.f16 s0, s0
+; CHECK-NEXT:    vstr.16 s0, [r0]
+; CHECK-NEXT:    bx lr
+  %a = load half, half* %p, align 2
+  %r = call half @llvm.floor.f16(half %a)
+  store half %r, half* %p
+  ret void
+}
 
-; FIXME
-;define void @test_ceil(half* %p) {
-;  %a = load half, half* %p, align 2
-;  %r = call half @llvm.ceil.f16(half %a)
-;  store half %r, half* %p
-;  ret void
-;}
+define void @test_ceil(half* %p) {
+; CHECK-LABEL: test_ceil:
+; CHECK:         vldr.16 s0, [r0]
+; CHECK-NEXT:    vrintp.f16 s0, s0
+; CHECK-NEXT:    vstr.16 s0, [r0]
+; CHECK-NEXT:    bx lr
+  %a = load half, half* %p, align 2
+  %r = call half @llvm.ceil.f16(half %a)
+  store half %r, half* %p
+  ret void
+}
 
-; FIXME
-;define void @test_trunc(half* %p) {
-;  %a = load half, half* %p, align 2
-;  %r = call half @llvm.trunc.f16(half %a)
-;  store half %r, half* %p
-;  ret void
-;}
+define void @test_trunc(half* %p) {
+; CHECK-LABEL: test_trunc:
+; CHECK:         vldr.16 s0, [r0]
+; CHECK-NEXT:    vrintz.f16 s0, s0
+; CHECK-NEXT:    vstr.16 s0, [r0]
+; CHECK-NEXT:    bx lr
+  %a = load half, half* %p, align 2
+  %r = call half @llvm.trunc.f16(half %a)
+  store half %r, half* %p
+  ret void
+}
 
-; FIXME
-;define void @test_rint(half* %p) {
-;  %a = load half, half* %p, align 2
-;  %r = call half @llvm.rint.f16(half %a)
-;  store half %r, half* %p
-;  ret void
-;}
+define void @test_rint(half* %p) {
+; CHECK-LABEL: test_rint:
+; CHECK:         vldr.16 s0, [r0]
+; CHECK-NEXT:    vrintx.f16 s0, s0
+; CHECK-NEXT:    vstr.16 s0, [r0]
+; CHECK-NEXT:    bx lr
+  %a = load half, half* %p, align 2
+  %r = call half @llvm.rint.f16(half %a)
+  store half %r, half* %p
+  ret void
+}
 
-; FIXME
-;define void @test_nearbyint(half* %p) {
-;  %a = load half, half* %p, align 2
-;  %r = call half @llvm.nearbyint.f16(half %a)
-;  store half %r, half* %p
-;  ret void
-;}
+define void @test_nearbyint(half* %p) {
+; CHECK-LABEL: test_nearbyint:
+; CHECK:         vldr.16 s0, [r0]
+; CHECK-NEXT:    vrintr.f16 s0, s0
+; CHECK-NEXT:    vstr.16 s0, [r0]
+; CHECK-NEXT:    bx lr
+  %a = load half, half* %p, align 2
+  %r = call half @llvm.nearbyint.f16(half %a)
+  store half %r, half* %p
+  ret void
+}
 
-; FIXME
-;define void @test_round(half* %p) {
-;  %a = load half, half* %p, align 2
-;  %r = call half @llvm.round.f16(half %a)
-;  store half %r, half* %p
-;  ret void
-;}
+define void @test_round(half* %p) {
+; CHECK-LABEL: test_round:
+; CHECK:         vldr.16 s0, [r0]
+; CHECK-NEXT:    vrinta.f16 s0, s0
+; CHECK-NEXT:    vstr.16 s0, [r0]
+; CHECK-NEXT:    bx lr
+  %a = load half, half* %p, align 2
+  %r = call half @llvm.round.f16(half %a)
+  store half %r, half* %p
+  ret void
+}
 
 define void @test_fmuladd(half* %p, half* %q, half* %r) {
 ; CHECK-LABEL: test_fmuladd:
 ; CHECK:         vldr.16 s0, [r1]
 ; CHECK-NEXT:    vldr.16 s2, [r0]
 ; CHECK-NEXT:    vldr.16 s4, [r2]
 ; CHECK-NEXT:    vmla.f16 s4, s2, s0
 ; CHECK-NEXT:    vstr.16 s4, [r0]

llvm/test/CodeGen/ARM/fp16-instructions.ll

entry:
   ret float undef
 ; Check thatLowerReturn can handle undef nodes (i.e. nodes which do not have
 ; any operands) when FullFP16 is enabled.
 ;
 ; CHECK-LABEL:            RetValBug:
 ; CHECK-HARDFP-FULLFP16:  {{.*}} lr
 }
 
-; 1. VABS: TODO
-
 ; 2. VADD
 define float @Add(float %a.coerce, float %b.coerce) {
 entry:
   %0 = bitcast float %a.coerce to i32
   %tmp.0.extract.trunc = trunc i32 %0 to i16
   %1 = bitcast i16 %tmp.0.extract.trunc to half
   %2 = bitcast float %b.coerce to i32
   %tmp1.0.extract.trunc = trunc i32 %2 to i16
entry:
   %tmp4.0.insert.ext = zext i16 %4 to i32
   %5 = bitcast i32 %tmp4.0.insert.ext to float
   ret float %5
 
 ; CHECK-LABEL:                 NMul:
 ; CHECK-HARDFP-FULLFP16:       vnmul.f16  s0, s0, s1
 }
 
-; TODO:
-; 28. VRINTA
-; 29. VRINTM
-; 30. VRINTN
-; 31. VRINTP
-; 32. VRINTR
-; 33. VRINTX
-; 34. VRINTZ
-
 ; 35. VSELEQ
 define half @select_cc1(half* %a0)  {
   %1 = load half, half* %a0
   %2 = fcmp nsz oeq half %1, 0xH0001
   %3 = select i1 %2, half 0xHC000, half 0xH0002
   ret half %3
 
 ; CHECK-LABEL:                 select_cc1:

 ; CHECK-SOFTFP-FP16-T32:       vmrs APSR_nzcv, fpscr
 ; CHECK-SOFTFP-FP16-T32:       it eq
 ; CHECK-SOFTFP-FP16-T32:       vmoveq.f32 [[S4]], [[S2]]
 ; CHECK-SOFTFP-FP16-T32:       it vs
 ; CHECK-SOFTFP-FP16-T32-NEXT:  vmovvs.f32 [[S4]], [[S2]]
 ; CHECK-SOFTFP-FP16-T32-NEXT:  vcvtb.f16.f32 s0, [[S4]]
 }
 
-; 39. VSQRT - TODO
-
 ; 40. VSUB
 define float @Sub(float %a.coerce, float %b.coerce) {
 entry:
   %0 = bitcast float %a.coerce to i32
   %tmp.0.extract.trunc = trunc i32 %0 to i16
   %1 = bitcast i16 %tmp.0.extract.trunc to half
   %2 = bitcast float %b.coerce to i32
   %tmp1.0.extract.trunc = trunc i32 %2 to i16