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Differential D61976

[PowerPC] Reorder CSR reloads in epilogue to follow the same order as CSR saves in the prologue
AbandonedPublic

Authored by Yi-Hong.Lyu on May 15 2019, 7:23 PM.

Details

Reviewers
power-llvm-team
hfinkel
echristo
nemanjai
Group Reviewers
Restricted Project
Summary

This is the following patch for https://reviews.llvm.org/D61966

Diff Detail

Event Timeline

Yi-Hong.Lyu created this revision.May 15 2019, 7:23 PM
Herald added a project: Restricted Project. · View Herald TranscriptMay 15 2019, 7:23 PM
Herald added subscribers: llvm-commits, jsji, kbarton and 2 others. · View Herald Transcript
jsji added a reviewer: Restricted Project.Aug 23 2019, 7:45 AM
Herald added subscribers: shchenz, • wuzish, MaskRay. · View Herald TranscriptAug 23 2019, 7:45 AM
jsji added a comment.Aug 27 2019, 7:43 PM

Are you still pursuing this Patch?

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
2336

Can you be more specific about some PPC CPUs? And how much better?
Have you tried other CPU? Any performance change for other CPU?
If this is not general better for all CPUs, have you considered at least add some options to revert to old order?

Yi-Hong.Lyu abandoned this revision.Sep 18 2019, 11:08 AM

Revision Contents

Diff 199717

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

Show First 20 Lines • Show All 2,325 Lines • ▼ Show 20 LinesPPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
// Initialize insertion-point logic; we will be restoring in reverse // Initialize insertion-point logic; we will be restoring in reverse
// order of spill. // order of spill.
MachineBasicBlock::iterator I = MI, BeforeI = I; MachineBasicBlock::iterator I = MI, BeforeI = I;
bool AtStart = I == MBB.begin(); bool AtStart = I == MBB.begin();
if (!AtStart) if (!AtStart)
--BeforeI; --BeforeI;
for (unsigned i = 0, e = CSI.size(); i != e; ++i) { // Reorder CSR reloads in epilogue to follow the same order as CSR saves in
// the prologue as consecutive loads/stores in increasing order perform better
// on some PPC CPUs.
jsjiUnsubmitted
Not Done
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Can you be more specific about some PPC CPUs? And how much better?
Have you tried other CPU? Any performance change for other CPU?
If this is not general better for all CPUs, have you considered at least add some options to revert to old order?

jsji: Can you be more specific about `some PPC CPUs`? And how much better? Have you tried other CPU?
for (unsigned i = CSI.size(), e = 0; i-- != e;) {
unsigned Reg = CSI[i].getReg(); unsigned Reg = CSI[i].getReg();
// Only Darwin actually uses the VRSAVE register, but it can still appear // Only Darwin actually uses the VRSAVE register, but it can still appear
// here if, for example, @llvm.eh.unwind.init() is used. If we're not on // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
// Darwin, ignore it. // Darwin, ignore it.
if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI()) if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
continue; continue;
▲ Show 20 Lines • Show All 63 Lines • Show Last 20 Lines

llvm/test/CodeGen/MIR/PowerPC/prolog_vec_spills.mir

Show All 13 Lines bb.0.entry:
$v20 = IMPLICIT_DEF $v20 = IMPLICIT_DEF
BLR8 implicit undef $lr8, implicit undef $rm BLR8 implicit undef $lr8, implicit undef $rm
# CHECK-LABEL: name: test1BB # CHECK-LABEL: name: test1BB
# CHECK: body: | # CHECK: body: |
# CHECK: $f1 = MTVSRD killed $x14 # CHECK: $f1 = MTVSRD killed $x14
# CHECK-NEXT: $f2 = MTVSRD killed $x15 # CHECK-NEXT: $f2 = MTVSRD killed $x15
# CHECK-NEXT: $f3 = MTVSRD killed $x16 # CHECK-NEXT: $f3 = MTVSRD killed $x16
# CHECK: $x16 = MFVSRD killed $f3 # CHECK: $x14 = MFVSRD killed $f1
# CHECK-NEXT: $x15 = MFVSRD killed $f2 # CHECK-NEXT: $x15 = MFVSRD killed $f2
# CHECK-NEXT: $x14 = MFVSRD killed $f1 # CHECK-NEXT: $x16 = MFVSRD killed $f3
... ...
--- ---
name: test2BBs name: test2BBs
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
body: | body: |
Show All 18 Linesbody: |
bb.3: bb.3:
BLR8 implicit undef $lr8, implicit undef $rm BLR8 implicit undef $lr8, implicit undef $rm
# CHECK-LABEL: name: test2BB # CHECK-LABEL: name: test2BB
# CHECK: body: | # CHECK: body: |
# CHECK: $f0 = MTVSRD killed $x14 # CHECK: $f0 = MTVSRD killed $x14
# CHECK-NEXT: $f1 = MTVSRD killed $x15 # CHECK-NEXT: $f1 = MTVSRD killed $x15
# CHECK-NEXT: $f2 = MTVSRD killed $x16 # CHECK-NEXT: $f2 = MTVSRD killed $x16
# CHECK: $x16 = MFVSRD killed $f2 # CHECK: $x14 = MFVSRD killed $f0
# CHECK-NEXT: $x15 = MFVSRD killed $f1 # CHECK-NEXT: $x15 = MFVSRD killed $f1
# CHECK-NEXT: $x14 = MFVSRD killed $f0 # CHECK-NEXT: $x16 = MFVSRD killed $f2
... ...

llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll

Show First 20 Lines • Show All 287 Lines • ▼ Show 20 Lines
; CHECK-NEXT: addis 3, 3, -32768 ; CHECK-NEXT: addis 3, 3, -32768
; CHECK-NEXT: bc 12, 20, .LBB0_14 ; CHECK-NEXT: bc 12, 20, .LBB0_14
; CHECK-NEXT: b .LBB0_15 ; CHECK-NEXT: b .LBB0_15
; CHECK-NEXT: .LBB0_14: # %bb3 ; CHECK-NEXT: .LBB0_14: # %bb3
; CHECK-NEXT: addi 4, 3, 0 ; CHECK-NEXT: addi 4, 3, 0
; CHECK-NEXT: .LBB0_15: # %bb3 ; CHECK-NEXT: .LBB0_15: # %bb3
; CHECK-NEXT: mr 3, 30 ; CHECK-NEXT: mr 3, 30
; CHECK-NEXT: .LBB0_16: # %bb5 ; CHECK-NEXT: .LBB0_16: # %bb5
; CHECK-NEXT: lfd 31, 456(1) # 8-byte Folded Reload ; CHECK-NEXT: lwz 29, 412(1) # 4-byte Folded Reload
; CHECK-NEXT: lfd 30, 448(1) # 8-byte Folded Reload
; CHECK-NEXT: lfd 29, 440(1) # 8-byte Folded Reload
; CHECK-NEXT: lfd 28, 432(1) # 8-byte Folded Reload
; CHECK-NEXT: lwz 12, 408(1) ; CHECK-NEXT: lwz 12, 408(1)
; CHECK-NEXT: lfd 27, 424(1) # 8-byte Folded Reload
; CHECK-NEXT: lwz 30, 416(1) # 4-byte Folded Reload ; CHECK-NEXT: lwz 30, 416(1) # 4-byte Folded Reload
; CHECK-NEXT: lfd 27, 424(1) # 8-byte Folded Reload
; CHECK-NEXT: mtcrf 32, 12 # cr2 ; CHECK-NEXT: mtcrf 32, 12 # cr2
; CHECK-NEXT: lwz 29, 412(1) # 4-byte Folded Reload ; CHECK-NEXT: lfd 28, 432(1) # 8-byte Folded Reload
; CHECK-NEXT: lfd 29, 440(1) # 8-byte Folded Reload
; CHECK-NEXT: lfd 30, 448(1) # 8-byte Folded Reload
; CHECK-NEXT: lfd 31, 456(1) # 8-byte Folded Reload
; CHECK-NEXT: lwz 0, 468(1) ; CHECK-NEXT: lwz 0, 468(1)
; CHECK-NEXT: addi 1, 1, 464 ; CHECK-NEXT: addi 1, 1, 464
; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = fcmp olt ppc_fp128 %a, 0xM00000000000000000000000000000000 ; <i1> [#uses=1] %0 = fcmp olt ppc_fp128 %a, 0xM00000000000000000000000000000000 ; <i1> [#uses=1]
br i1 %0, label %bb5, label %bb1 br i1 %0, label %bb5, label %bb1
Show All 26 Lines

llvm/test/CodeGen/PowerPC/CSR-fit.ll

Show All 22 Lines
; CHECK-PWR8-NEXT: add r3, r3, r4 ; CHECK-PWR8-NEXT: add r3, r3, r4
; CHECK-PWR8-NEXT: #NO_APP ; CHECK-PWR8-NEXT: #NO_APP
; CHECK-PWR8-NEXT: extsw r3, r3 ; CHECK-PWR8-NEXT: extsw r3, r3
; CHECK-PWR8-NEXT: bl callee ; CHECK-PWR8-NEXT: bl callee
; CHECK-PWR8-NEXT: nop ; CHECK-PWR8-NEXT: nop
; CHECK-PWR8-NEXT: addi r1, r1, 176 ; CHECK-PWR8-NEXT: addi r1, r1, 176
; CHECK-PWR8-NEXT: ld r0, 16(r1) ; CHECK-PWR8-NEXT: ld r0, 16(r1)
; CHECK-PWR8-NEXT: mtlr r0 ; CHECK-PWR8-NEXT: mtlr r0
; CHECK-PWR8-NEXT: ld r15, -136(r1) # 8-byte Folded Reload
; CHECK-PWR8-NEXT: ld r14, -144(r1) # 8-byte Folded Reload ; CHECK-PWR8-NEXT: ld r14, -144(r1) # 8-byte Folded Reload
; CHECK-PWR8-NEXT: ld r15, -136(r1) # 8-byte Folded Reload
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
; ;
; CHECK-PWR9-LABEL: caller1: ; CHECK-PWR9-LABEL: caller1:
; CHECK-PWR9: # %bb.0: # %entry ; CHECK-PWR9: # %bb.0: # %entry
; CHECK-PWR9-NEXT: mflr r0 ; CHECK-PWR9-NEXT: mflr r0
; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 176 ; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 176
; CHECK-PWR9-NEXT: .cfi_offset lr, 16 ; CHECK-PWR9-NEXT: .cfi_offset lr, 16
; CHECK-PWR9-NEXT: .cfi_offset r14, -144 ; CHECK-PWR9-NEXT: .cfi_offset r14, -144
; CHECK-PWR9-NEXT: .cfi_offset r15, -136 ; CHECK-PWR9-NEXT: .cfi_offset r15, -136
; CHECK-PWR9-NEXT: std r14, -144(r1) # 8-byte Folded Spill ; CHECK-PWR9-NEXT: std r14, -144(r1) # 8-byte Folded Spill
; CHECK-PWR9-NEXT: std r15, -136(r1) # 8-byte Folded Spill ; CHECK-PWR9-NEXT: std r15, -136(r1) # 8-byte Folded Spill
; CHECK-PWR9-NEXT: std r0, 16(r1) ; CHECK-PWR9-NEXT: std r0, 16(r1)
; CHECK-PWR9-NEXT: stdu r1, -176(r1) ; CHECK-PWR9-NEXT: stdu r1, -176(r1)
; CHECK-PWR9-NEXT: #APP ; CHECK-PWR9-NEXT: #APP
; CHECK-PWR9-NEXT: add r3, r3, r4 ; CHECK-PWR9-NEXT: add r3, r3, r4
; CHECK-PWR9-NEXT: #NO_APP ; CHECK-PWR9-NEXT: #NO_APP
; CHECK-PWR9-NEXT: extsw r3, r3 ; CHECK-PWR9-NEXT: extsw r3, r3
; CHECK-PWR9-NEXT: bl callee ; CHECK-PWR9-NEXT: bl callee
; CHECK-PWR9-NEXT: nop ; CHECK-PWR9-NEXT: nop
; CHECK-PWR9-NEXT: addi r1, r1, 176 ; CHECK-PWR9-NEXT: addi r1, r1, 176
; CHECK-PWR9-NEXT: ld r0, 16(r1) ; CHECK-PWR9-NEXT: ld r0, 16(r1)
; CHECK-PWR9-NEXT: mtlr r0 ; CHECK-PWR9-NEXT: mtlr r0
; CHECK-PWR9-NEXT: ld r15, -136(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r14, -144(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: ld r14, -144(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r15, -136(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: blr ; CHECK-PWR9-NEXT: blr
entry: entry:
%0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r14},~{r15}"(i32 %a, i32 %b) %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r14},~{r15}"(i32 %a, i32 %b)
%call = tail call signext i32 @callee(i32 signext %0) %call = tail call signext i32 @callee(i32 signext %0)
ret i32 %call ret i32 %call
} }
define dso_local signext i32 @caller2(i32 signext %a, i32 signext %b) local_unnamed_addr { define dso_local signext i32 @caller2(i32 signext %a, i32 signext %b) local_unnamed_addr {
Show All 12 Lines
; CHECK-PWR8-NEXT: add r3, r3, r4 ; CHECK-PWR8-NEXT: add r3, r3, r4
; CHECK-PWR8-NEXT: #NO_APP ; CHECK-PWR8-NEXT: #NO_APP
; CHECK-PWR8-NEXT: extsw r3, r3 ; CHECK-PWR8-NEXT: extsw r3, r3
; CHECK-PWR8-NEXT: bl callee ; CHECK-PWR8-NEXT: bl callee
; CHECK-PWR8-NEXT: nop ; CHECK-PWR8-NEXT: nop
; CHECK-PWR8-NEXT: addi r1, r1, 176 ; CHECK-PWR8-NEXT: addi r1, r1, 176
; CHECK-PWR8-NEXT: ld r0, 16(r1) ; CHECK-PWR8-NEXT: ld r0, 16(r1)
; CHECK-PWR8-NEXT: mtlr r0 ; CHECK-PWR8-NEXT: mtlr r0
; CHECK-PWR8-NEXT: lfd f15, -136(r1) # 8-byte Folded Reload
; CHECK-PWR8-NEXT: lfd f14, -144(r1) # 8-byte Folded Reload ; CHECK-PWR8-NEXT: lfd f14, -144(r1) # 8-byte Folded Reload
; CHECK-PWR8-NEXT: lfd f15, -136(r1) # 8-byte Folded Reload
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
; ;
; CHECK-PWR9-LABEL: caller2: ; CHECK-PWR9-LABEL: caller2:
; CHECK-PWR9: # %bb.0: # %entry ; CHECK-PWR9: # %bb.0: # %entry
; CHECK-PWR9-NEXT: mflr r0 ; CHECK-PWR9-NEXT: mflr r0
; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 176 ; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 176
; CHECK-PWR9-NEXT: .cfi_offset lr, 16 ; CHECK-PWR9-NEXT: .cfi_offset lr, 16
; CHECK-PWR9-NEXT: .cfi_offset f14, -144 ; CHECK-PWR9-NEXT: .cfi_offset f14, -144
; CHECK-PWR9-NEXT: .cfi_offset f15, -136 ; CHECK-PWR9-NEXT: .cfi_offset f15, -136
; CHECK-PWR9-NEXT: stfd f14, -144(r1) # 8-byte Folded Spill ; CHECK-PWR9-NEXT: stfd f14, -144(r1) # 8-byte Folded Spill
; CHECK-PWR9-NEXT: stfd f15, -136(r1) # 8-byte Folded Spill ; CHECK-PWR9-NEXT: stfd f15, -136(r1) # 8-byte Folded Spill
; CHECK-PWR9-NEXT: std r0, 16(r1) ; CHECK-PWR9-NEXT: std r0, 16(r1)
; CHECK-PWR9-NEXT: stdu r1, -176(r1) ; CHECK-PWR9-NEXT: stdu r1, -176(r1)
; CHECK-PWR9-NEXT: #APP ; CHECK-PWR9-NEXT: #APP
; CHECK-PWR9-NEXT: add r3, r3, r4 ; CHECK-PWR9-NEXT: add r3, r3, r4
; CHECK-PWR9-NEXT: #NO_APP ; CHECK-PWR9-NEXT: #NO_APP
; CHECK-PWR9-NEXT: extsw r3, r3 ; CHECK-PWR9-NEXT: extsw r3, r3
; CHECK-PWR9-NEXT: bl callee ; CHECK-PWR9-NEXT: bl callee
; CHECK-PWR9-NEXT: nop ; CHECK-PWR9-NEXT: nop
; CHECK-PWR9-NEXT: addi r1, r1, 176 ; CHECK-PWR9-NEXT: addi r1, r1, 176
; CHECK-PWR9-NEXT: ld r0, 16(r1) ; CHECK-PWR9-NEXT: ld r0, 16(r1)
; CHECK-PWR9-NEXT: mtlr r0 ; CHECK-PWR9-NEXT: mtlr r0
; CHECK-PWR9-NEXT: lfd f15, -136(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f14, -144(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: lfd f14, -144(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f15, -136(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: blr ; CHECK-PWR9-NEXT: blr
entry: entry:
%0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{f14},~{f15}"(i32 %a, i32 %b) %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{f14},~{f15}"(i32 %a, i32 %b)
%call = tail call signext i32 @callee(i32 signext %0) %call = tail call signext i32 @callee(i32 signext %0)
ret i32 %call ret i32 %call
} }
define dso_local signext i32 @caller3(i32 signext %a, i32 signext %b) local_unnamed_addr { define dso_local signext i32 @caller3(i32 signext %a, i32 signext %b) local_unnamed_addr {
Show All 11 Lines
; CHECK-PWR8-NEXT: li r5, 64 ; CHECK-PWR8-NEXT: li r5, 64
; CHECK-PWR8-NEXT: stxvd2x v21, r1, r5 # 16-byte Folded Spill ; CHECK-PWR8-NEXT: stxvd2x v21, r1, r5 # 16-byte Folded Spill
; CHECK-PWR8-NEXT: #APP ; CHECK-PWR8-NEXT: #APP
; CHECK-PWR8-NEXT: add r3, r3, r4 ; CHECK-PWR8-NEXT: add r3, r3, r4
; CHECK-PWR8-NEXT: #NO_APP ; CHECK-PWR8-NEXT: #NO_APP
; CHECK-PWR8-NEXT: extsw r3, r3 ; CHECK-PWR8-NEXT: extsw r3, r3
; CHECK-PWR8-NEXT: bl callee ; CHECK-PWR8-NEXT: bl callee
; CHECK-PWR8-NEXT: nop ; CHECK-PWR8-NEXT: nop
; CHECK-PWR8-NEXT: li r4, 64
; CHECK-PWR8-NEXT: lxvd2x v21, r1, r4 # 16-byte Folded Reload
; CHECK-PWR8-NEXT: li r4, 48 ; CHECK-PWR8-NEXT: li r4, 48
; CHECK-PWR8-NEXT: lxvd2x v20, r1, r4 # 16-byte Folded Reload ; CHECK-PWR8-NEXT: lxvd2x v20, r1, r4 # 16-byte Folded Reload
; CHECK-PWR8-NEXT: li r4, 64
; CHECK-PWR8-NEXT: lxvd2x v21, r1, r4 # 16-byte Folded Reload
; CHECK-PWR8-NEXT: addi r1, r1, 240 ; CHECK-PWR8-NEXT: addi r1, r1, 240
; CHECK-PWR8-NEXT: ld r0, 16(r1) ; CHECK-PWR8-NEXT: ld r0, 16(r1)
; CHECK-PWR8-NEXT: mtlr r0 ; CHECK-PWR8-NEXT: mtlr r0
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
; ;
; CHECK-PWR9-LABEL: caller3: ; CHECK-PWR9-LABEL: caller3:
; CHECK-PWR9: # %bb.0: # %entry ; CHECK-PWR9: # %bb.0: # %entry
; CHECK-PWR9-NEXT: mflr r0 ; CHECK-PWR9-NEXT: mflr r0
; CHECK-PWR9-NEXT: std r0, 16(r1) ; CHECK-PWR9-NEXT: std r0, 16(r1)
; CHECK-PWR9-NEXT: stdu r1, -224(r1) ; CHECK-PWR9-NEXT: stdu r1, -224(r1)
; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 224 ; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 224
; CHECK-PWR9-NEXT: .cfi_offset lr, 16 ; CHECK-PWR9-NEXT: .cfi_offset lr, 16
; CHECK-PWR9-NEXT: .cfi_offset v20, -192 ; CHECK-PWR9-NEXT: .cfi_offset v20, -192
; CHECK-PWR9-NEXT: .cfi_offset v21, -176 ; CHECK-PWR9-NEXT: .cfi_offset v21, -176
; CHECK-PWR9-NEXT: stxv v20, 32(r1) # 16-byte Folded Spill ; CHECK-PWR9-NEXT: stxv v20, 32(r1) # 16-byte Folded Spill
; CHECK-PWR9-NEXT: stxv v21, 48(r1) # 16-byte Folded Spill ; CHECK-PWR9-NEXT: stxv v21, 48(r1) # 16-byte Folded Spill
; CHECK-PWR9-NEXT: #APP ; CHECK-PWR9-NEXT: #APP
; CHECK-PWR9-NEXT: add r3, r3, r4 ; CHECK-PWR9-NEXT: add r3, r3, r4
; CHECK-PWR9-NEXT: #NO_APP ; CHECK-PWR9-NEXT: #NO_APP
; CHECK-PWR9-NEXT: extsw r3, r3 ; CHECK-PWR9-NEXT: extsw r3, r3
; CHECK-PWR9-NEXT: bl callee ; CHECK-PWR9-NEXT: bl callee
; CHECK-PWR9-NEXT: nop ; CHECK-PWR9-NEXT: nop
; CHECK-PWR9-NEXT: lxv v21, 48(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lxv v20, 32(r1) # 16-byte Folded Reload ; CHECK-PWR9-NEXT: lxv v20, 32(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lxv v21, 48(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: addi r1, r1, 224 ; CHECK-PWR9-NEXT: addi r1, r1, 224
; CHECK-PWR9-NEXT: ld r0, 16(r1) ; CHECK-PWR9-NEXT: ld r0, 16(r1)
; CHECK-PWR9-NEXT: mtlr r0 ; CHECK-PWR9-NEXT: mtlr r0
; CHECK-PWR9-NEXT: blr ; CHECK-PWR9-NEXT: blr
entry: entry:
%0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{v20},~{v21}"(i32 %a, i32 %b) %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{v20},~{v21}"(i32 %a, i32 %b)
%call = tail call signext i32 @callee(i32 signext %0) %call = tail call signext i32 @callee(i32 signext %0)
ret i32 %call ret i32 %call
▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
; CHECK-PWR9-NEXT: stxv v20, 32(r1) # 16-byte Folded Spill ; CHECK-PWR9-NEXT: stxv v20, 32(r1) # 16-byte Folded Spill
; CHECK-PWR9-NEXT: #APP ; CHECK-PWR9-NEXT: #APP
; CHECK-PWR9-NEXT: add r3, r3, r4 ; CHECK-PWR9-NEXT: add r3, r3, r4
; CHECK-PWR9-NEXT: #NO_APP ; CHECK-PWR9-NEXT: #NO_APP
; CHECK-PWR9-NEXT: extsw r3, r3 ; CHECK-PWR9-NEXT: extsw r3, r3
; CHECK-PWR9-NEXT: bl callee ; CHECK-PWR9-NEXT: bl callee
; CHECK-PWR9-NEXT: nop ; CHECK-PWR9-NEXT: nop
; CHECK-PWR9-NEXT: lxv v20, 32(r1) # 16-byte Folded Reload ; CHECK-PWR9-NEXT: lxv v20, 32(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f14, 368(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r14, 224(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: ld r14, 224(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f14, 368(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: addi r1, r1, 512 ; CHECK-PWR9-NEXT: addi r1, r1, 512
; CHECK-PWR9-NEXT: ld r0, 16(r1) ; CHECK-PWR9-NEXT: ld r0, 16(r1)
; CHECK-PWR9-NEXT: mtlr r0 ; CHECK-PWR9-NEXT: mtlr r0
; CHECK-PWR9-NEXT: blr ; CHECK-PWR9-NEXT: blr
entry: entry:
%0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r14},~{f14},~{v20},~{vs53}"(i32 %a, i32 %b) %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r14},~{f14},~{v20},~{vs53}"(i32 %a, i32 %b)
%call = tail call signext i32 @callee(i32 signext %0) %call = tail call signext i32 @callee(i32 signext %0)
ret i32 %call ret i32 %call
} }

llvm/test/CodeGen/PowerPC/coldcc.ll

Show All 24 Lines
define internal coldcc signext i32 @callee(i32 signext %a, i32 signext %b) local_unnamed_addr #0 { define internal coldcc signext i32 @callee(i32 signext %a, i32 signext %b) local_unnamed_addr #0 {
entry: entry:
; COLDCC: @callee ; COLDCC: @callee
; COLDCC: std 6, -8(1) ; COLDCC: std 6, -8(1)
; COLDCC: std 7, -16(1) ; COLDCC: std 7, -16(1)
; COLDCC: std 8, -24(1) ; COLDCC: std 8, -24(1)
; COLDCC: std 9, -32(1) ; COLDCC: std 9, -32(1)
; COLDCC: std 10, -40(1) ; COLDCC: std 10, -40(1)
; COLDCC: ld 10, -40(1)
; COLDCC: ld 9, -32(1)
; COLDCC: ld 8, -24(1)
; COLDCC: ld 7, -16(1)
; COLDCC: ld 6, -8(1) ; COLDCC: ld 6, -8(1)
; COLDCC: ld 7, -16(1)
; COLDCC: ld 8, -24(1)
; COLDCC: ld 9, -32(1)
; COLDCC: ld 10, -40(1)
%0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r6},~{r7},~{r8},~{r9},~{r10}"(i32 %a, i32 %b) %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r6},~{r7},~{r8},~{r9},~{r10}"(i32 %a, i32 %b)
%mul = mul nsw i32 %a, 3 %mul = mul nsw i32 %a, 3
%1 = mul i32 %b, -5 %1 = mul i32 %b, -5
%add = add i32 %1, %mul %add = add i32 %1, %mul
%sub = add i32 %add, %0 %sub = add i32 %add, %0
ret i32 %sub ret i32 %sub
} }
attributes #0 = { noinline } attributes #0 = { noinline }

llvm/test/CodeGen/PowerPC/larger-than-red-zone.ll

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; CHECK-NEXT: std r31, 168(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r31, 168(r1) # 8-byte Folded Spill
; CHECK-NEXT: stfd f14, 176(r1) # 8-byte Folded Spill ; CHECK-NEXT: stfd f14, 176(r1) # 8-byte Folded Spill
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: add r3, r3, r4 ; CHECK-NEXT: add r3, r3, r4
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: bl callee ; CHECK-NEXT: bl callee
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: lfd f14, 176(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r31, 168(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r30, 160(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r29, 152(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r28, 144(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r27, 136(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r26, 128(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r25, 120(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r24, 112(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r23, 104(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r22, 96(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r21, 88(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r20, 80(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r19, 72(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r18, 64(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r17, 56(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r16, 48(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r15, 40(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r14, 32(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r14, 32(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r15, 40(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r16, 48(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r17, 56(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r18, 64(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r19, 72(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r20, 80(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r21, 88(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r22, 96(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r23, 104(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r24, 112(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r25, 120(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r26, 128(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r27, 136(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r28, 144(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r29, 152(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r30, 160(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r31, 168(r1) # 8-byte Folded Reload
; CHECK-NEXT: lfd f14, 176(r1) # 8-byte Folded Reload
; CHECK-NEXT: addi r1, r1, 320 ; CHECK-NEXT: addi r1, r1, 320
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31},~{f14}"(i32 %a, i32 %b) %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31},~{f14}"(i32 %a, i32 %b)
%call = tail call signext i32 @callee(i32 signext %0) %call = tail call signext i32 @callee(i32 signext %0)
ret i32 %call ret i32 %call
} }
declare signext i32 @callee(i32 signext) local_unnamed_addr declare signext i32 @callee(i32 signext) local_unnamed_addr

llvm/test/CodeGen/PowerPC/not-fixed-frame-object.ll

Show First 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ld r6, 32(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r6, 32(r1) # 8-byte Folded Reload
; CHECK-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: mr r5, r0 ; CHECK-NEXT: mr r5, r0
; CHECK-NEXT: bl callee ; CHECK-NEXT: bl callee
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 192 ; CHECK-NEXT: addi r1, r1, 192
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: ld r31, -8(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r28, -32(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r27, -40(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r26, -48(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r25, -56(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r24, -64(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r23, -72(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r22, -80(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r21, -88(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r20, -96(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r19, -104(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r18, -112(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r17, -120(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r16, -128(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r15, -136(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r14, -144(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r14, -144(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r15, -136(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r16, -128(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r17, -120(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r18, -112(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r19, -104(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r20, -96(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r21, -88(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r22, -80(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r23, -72(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r24, -64(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r25, -56(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r26, -48(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r27, -40(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r28, -32(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r31, -8(r1) # 8-byte Folded Reload
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13}"(i32 %a, i32 %b) %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13}"(i32 %a, i32 %b)
%call = tail call signext i32 @callee(i32 signext %0, i32 signext %a, i32 signext %b, i32 signext %c) %call = tail call signext i32 @callee(i32 signext %0, i32 signext %a, i32 signext %b, i32 signext %c)
ret i32 %call ret i32 %call
} }
declare signext i32 @callee(i32 signext, i32 signext, i32 signext, i32 signext) local_unnamed_addr declare signext i32 @callee(i32 signext, i32 signext, i32 signext, i32 signext) local_unnamed_addr

llvm/test/CodeGen/PowerPC/reverse-callee-saved-register-reloads.ll

Show First 20 Lines • Show All 104 Lines • ▼ Show 20 Lines
; CHECK-PWR9-NEXT: stxv v29, 192(r1) # 16-byte Folded Spill ; CHECK-PWR9-NEXT: stxv v29, 192(r1) # 16-byte Folded Spill
; CHECK-PWR9-NEXT: stxv v30, 208(r1) # 16-byte Folded Spill ; CHECK-PWR9-NEXT: stxv v30, 208(r1) # 16-byte Folded Spill
; CHECK-PWR9-NEXT: stxv v31, 224(r1) # 16-byte Folded Spill ; CHECK-PWR9-NEXT: stxv v31, 224(r1) # 16-byte Folded Spill
; CHECK-PWR9-NEXT: #APP ; CHECK-PWR9-NEXT: #APP
; CHECK-PWR9-NEXT: nop ; CHECK-PWR9-NEXT: nop
; CHECK-PWR9-NEXT: #NO_APP ; CHECK-PWR9-NEXT: #NO_APP
; CHECK-PWR9-NEXT: ld r3, 40(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: ld r3, 40(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r4, 32(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: ld r4, 32(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lxv v31, 224(r1) # 16-byte Folded Reload ; CHECK-PWR9-NEXT: lxv v20, 48(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lxv v30, 208(r1) # 16-byte Folded Reload ; CHECK-PWR9-NEXT: lxv v21, 64(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lxv v29, 192(r1) # 16-byte Folded Reload ; CHECK-PWR9-NEXT: lxv v22, 80(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: add r3, r4, r3 ; CHECK-PWR9-NEXT: add r3, r4, r3
; CHECK-PWR9-NEXT: lxv v28, 176(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lxv v27, 160(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lxv v26, 144(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lxv v25, 128(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lxv v24, 112(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lxv v23, 96(r1) # 16-byte Folded Reload ; CHECK-PWR9-NEXT: lxv v23, 96(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lxv v22, 80(r1) # 16-byte Folded Reload ; CHECK-PWR9-NEXT: lxv v24, 112(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lxv v21, 64(r1) # 16-byte Folded Reload ; CHECK-PWR9-NEXT: lxv v25, 128(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lxv v20, 48(r1) # 16-byte Folded Reload ; CHECK-PWR9-NEXT: lxv v26, 144(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f31, 520(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: lxv v27, 160(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f30, 512(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: lxv v28, 176(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f29, 504(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: lxv v29, 192(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f28, 496(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: lxv v30, 208(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f27, 488(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: lxv v31, 224(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f26, 480(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f25, 472(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f24, 464(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f23, 456(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f22, 448(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f21, 440(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f20, 432(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f19, 424(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f18, 416(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f17, 408(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f16, 400(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f15, 392(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f14, 384(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r31, 376(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r30, 368(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r29, 360(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r28, 352(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r27, 344(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r26, 336(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r25, 328(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r24, 320(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r23, 312(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r22, 304(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r21, 296(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r20, 288(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r19, 280(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r18, 272(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r17, 264(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r16, 256(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r15, 248(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r14, 240(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: ld r14, 240(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r15, 248(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r16, 256(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r17, 264(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r18, 272(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r19, 280(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r20, 288(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r21, 296(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r22, 304(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r23, 312(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r24, 320(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r25, 328(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r26, 336(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r27, 344(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r28, 352(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r29, 360(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r30, 368(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r31, 376(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f14, 384(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f15, 392(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f16, 400(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f17, 408(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f18, 416(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f19, 424(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f20, 432(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f21, 440(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f22, 448(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f23, 456(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f24, 464(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f25, 472(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f26, 480(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f27, 488(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f28, 496(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f29, 504(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f30, 512(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f31, 520(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: addi r1, r1, 528 ; CHECK-PWR9-NEXT: addi r1, r1, 528
; CHECK-PWR9-NEXT: blr ; CHECK-PWR9-NEXT: blr
entry: entry:
tail call void asm sideeffect "nop", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31},~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31},~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"() nounwind tail call void asm sideeffect "nop", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31},~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31},~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"() nounwind
%result = add i64 %p1, %p2 %result = add i64 %p1, %p2
ret i64 %result ret i64 %result
} }

llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll

Show First 20 Lines • Show All 124 Lines • ▼ Show 20 Lines
; PPC32-NEXT: crorc 25, 9, 30 ; PPC32-NEXT: crorc 25, 9, 30
; PPC32-NEXT: or. 3, 27, 26 ; PPC32-NEXT: or. 3, 27, 26
; PPC32-NEXT: cror 24, 20, 10 ; PPC32-NEXT: cror 24, 20, 10
; PPC32-NEXT: mcrf 5, 0 ; PPC32-NEXT: mcrf 5, 0
; PPC32-NEXT: crorc 25, 25, 6 ; PPC32-NEXT: crorc 25, 25, 6
; PPC32-NEXT: or. 3, 30, 29 ; PPC32-NEXT: or. 3, 30, 29
; PPC32-NEXT: cror 25, 25, 11 ; PPC32-NEXT: cror 25, 25, 11
; PPC32-NEXT: crnor 20, 2, 22 ; PPC32-NEXT: crnor 20, 2, 22
; PPC32-NEXT: lwz 12, 28(1) ; PPC32-NEXT: lwz 20, 32(1)
; PPC32-NEXT: lwz 21, 36(1)
; PPC32-NEXT: lwz 22, 40(1)
; PPC32-NEXT: lwz 23, 44(1)
; PPC32-NEXT: lwz 24, 48(1)
; PPC32-NEXT: lwz 25, 52(1)
; PPC32-NEXT: lwz 26, 56(1)
; PPC32-NEXT: lwz 27, 60(1)
; PPC32-NEXT: lwz 28, 64(1)
; PPC32-NEXT: lwz 29, 68(1)
; PPC32-NEXT: cror 20, 20, 25 ; PPC32-NEXT: cror 20, 20, 25
; PPC32-NEXT: lwz 12, 28(1)
; PPC32-NEXT: cror 20, 20, 24 ; PPC32-NEXT: cror 20, 20, 24
; PPC32-NEXT: crnor 20, 20, 12 ; PPC32-NEXT: crnor 20, 20, 12
; PPC32-NEXT: li 3, 1 ; PPC32-NEXT: li 3, 1
; PPC32-NEXT: bc 12, 20, .LBB0_2 ; PPC32-NEXT: bc 12, 20, .LBB0_2
; PPC32: ori 7, 3, 0 ; PPC32: ori 7, 3, 0
; PPC32-NEXT: b .LBB0_3 ; PPC32-NEXT: b .LBB0_3
; PPC32-NEXT:.LBB0_2: ; PPC32-NEXT:.LBB0_2:
; PPC32-NEXT: addi 7, 0, 0 ; PPC32-NEXT: addi 7, 0, 0
; PPC32-NEXT:.LBB0_3: ; PPC32-NEXT:.LBB0_3:
; PPC32-NEXT: mr 3, 8 ; PPC32-NEXT: mr 3, 8
; PPC32-NEXT: mtcrf 32, 12 ; PPC32-NEXT: mtcrf 32, 12
; PPC32-NEXT: mtcrf 16, 12 ; PPC32-NEXT: mtcrf 16, 12
; PPC32-NEXT: lwz 30, 72(1) ; PPC32-NEXT: lwz 30, 72(1)
; PPC32-NEXT: lwz 29, 68(1)
; PPC32-NEXT: lwz 28, 64(1)
; PPC32-NEXT: lwz 27, 60(1)
; PPC32-NEXT: lwz 26, 56(1)
; PPC32-NEXT: lwz 25, 52(1)
; PPC32-NEXT: lwz 24, 48(1)
; PPC32-NEXT: lwz 23, 44(1)
; PPC32-NEXT: lwz 22, 40(1)
; PPC32-NEXT: lwz 21, 36(1)
; PPC32-NEXT: lwz 20, 32(1)
; PPC32-NEXT: lwz 0, 84(1) ; PPC32-NEXT: lwz 0, 84(1)
; PPC32-NEXT: addi 1, 1, 80 ; PPC32-NEXT: addi 1, 1, 80
; PPC32-NEXT: mtlr 0 ; PPC32-NEXT: mtlr 0
; PPC32-NEXT: blr ; PPC32-NEXT: blr
start: start:
%0 = tail call { i128, i1 } @llvm.umul.with.overflow.i128(i128 %l, i128 %r) #2 %0 = tail call { i128, i1 } @llvm.umul.with.overflow.i128(i128 %l, i128 %r) #2
%1 = extractvalue { i128, i1 } %0, 0 %1 = extractvalue { i128, i1 } %0, 0
%2 = extractvalue { i128, i1 } %0, 1 %2 = extractvalue { i128, i1 } %0, 1
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