[AMDGPU][MC][GFX8][GFX9] Corrected predicate of v_*_co_u32 aliases

[dp]

Summary

Summary of changes:

• corrected predicate for v_*_co_u32 aliases (this should fix SWDEV-188513);
• added lit tests.

[rampitec]

GFX10 changes are not yet complete.

[dp]

SWDEV-188513 is P2. Could you correct the offending predicate by your next commit?
Or I can remove all changes except the predicate correction - that will not affect GFX10.

[rampitec]

In D61905#1501536, @dp wrote:

SWDEV-188513 is P2. Could you correct the offending predicate by your next commit?
Or I can remove all changes except the predicate correction - that will not affect GFX10.

Please strip it to predicate and test only.

[dp]

Removed GFX10-relevant changes

[rampitec]

The comment does not belong here. Also please retitle.

lib/Target/AMDGPU/VOP2Instructions.td

1347

Remove this line please.

[dp]

Retitled and removed a comment

[rampitec]

LGTM

lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

else
       O << "_e32 ";
   }
 
   printOperand(MI, OpNo, STI, O);
 
   switch (MI->getOpcode()) {
   default: break;
 
-  case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
-  case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
-  case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
   case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
   case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
   case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
     printDefaultVccOperand(1, STI, O);
     break;
   }
 }
 
void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
   } else {
     O << "/*INV_OP*/";
   }
 
   switch (MI->getOpcode()) {
   default: break;
 
   case AMDGPU::V_CNDMASK_B32_e32_gfx10:
-  case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
-  case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
-  case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
-
   case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7:
   case AMDGPU::V_CNDMASK_B32_e32_vi:
     if ((int)OpNo == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
                                                 AMDGPU::OpName::src1))
       printDefaultVccOperand(OpNo, STI, O);
     break;
   }
 }

lib/Target/AMDGPU/VOP2Instructions.td

let SchedRW = [Write32Bit, WriteSALU] in {
       }
 
       def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
                  Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
     }
   }
 }
 
-class VOP2bInstAlias <VOP2_Pseudo ps, Instruction inst,
-                      string OpName, string opnd> :
-  InstAlias <OpName#" "#!subst("vcc", opnd, ps.Pfl.Asm32),
+class VOP2bInstAlias <VOP2_Pseudo ps, Instruction inst, string OpName> :
+  InstAlias <OpName#" "#!subst(", vcc", "", ps.Pfl.Asm32),
              (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0,
                    ps.Pfl.Src1RC32:$src1)>,
   PredicateControl {
 }
 
+// Make vcc operands optional
 multiclass VOP2bInstAliases<VOP2_Pseudo ps, VOP2_Real inst, string OpName> {
-    def : VOP2bInstAlias<ps, inst, OpName, "vcc">;
+  def : VOP2bInstAlias<ps, inst, OpName>;
 }
 
 multiclass VOP2eInst <string opName,
                       VOPProfile P,
                       SDPatternOperator node = null_frag,
                       string revOp = opName,
                       bit useSGPRInput = !eq(P.NumSrcArgs, 3)> {
 
let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
   } // End DecoderNamespace = "SDWA10"
 
   //===------------------------------ VOP2be ------------------------------===//
   multiclass VOP2be_Real_gfx10<bits<6> op, string opName, string asmName> {
     def _e32_gfx10 :
       VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.GFX10>,
       VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl> {
         VOP2_Pseudo Ps = !cast<VOP2_Pseudo>(opName#"_e32");
-        let AsmString = asmName # !subst(", vcc", "", Ps.AsmOperands);
+        let AsmString = asmName # Ps.AsmOperands;
       }
     def _e64_gfx10 :
       VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>,
       VOP3be_gfx10<{0, 1, 0, 0, op{5-0}},
                    !cast<VOP3_Pseudo>(opName#"_e64").Pfl> {
         VOP3_Pseudo Ps = !cast<VOP3_Pseudo>(opName#"_e64");
         let AsmString = asmName # Ps.AsmOperands;
       }

 def : SI2_VI3Alias <"v_ldexp_f32", V_LDEXP_F32_e64_vi>;
 def : SI2_VI3Alias <"v_cvt_pkaccum_u8_f32", V_CVT_PKACCUM_U8_F32_e64_vi>;
 def : SI2_VI3Alias <"v_cvt_pknorm_i16_f32", V_CVT_PKNORM_I16_F32_e64_vi>;
 def : SI2_VI3Alias <"v_cvt_pknorm_u16_f32", V_CVT_PKNORM_U16_F32_e64_vi>;
 def : SI2_VI3Alias <"v_cvt_pkrtz_f16_f32", V_CVT_PKRTZ_F16_F32_e64_vi>;
 
 defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_vi>;
 
+} // End SubtargetPredicate = isGFX8GFX9
+
+let SubtargetPredicate = isGFX9Only in {
+
 defm : VOP2bInstAliases<V_ADD_I32_e32,     V_ADD_CO_U32_e32_gfx9,     "v_add_co_u32">;
 defm : VOP2bInstAliases<V_ADDC_U32_e32,    V_ADDC_CO_U32_e32_gfx9,    "v_addc_co_u32">;
 defm : VOP2bInstAliases<V_SUB_I32_e32,     V_SUB_CO_U32_e32_gfx9,     "v_sub_co_u32">;
 defm : VOP2bInstAliases<V_SUBB_U32_e32,    V_SUBB_CO_U32_e32_gfx9,    "v_subb_co_u32">;
 defm : VOP2bInstAliases<V_SUBREV_I32_e32,  V_SUBREV_CO_U32_e32_gfx9,  "v_subrev_co_u32">;
 defm : VOP2bInstAliases<V_SUBBREV_U32_e32, V_SUBBREV_CO_U32_e32_gfx9, "v_subbrev_co_u32">;
-} // End SubtargetPredicate = isGFX8GFX9
+
+} // End SubtargetPredicate = isGFX9Only
 
 let SubtargetPredicate = HasDLInsts in {
 
 defm V_FMAC_F32 : VOP2_Real_e32e64_vi <0x3b>;
 defm V_XNOR_B32 : VOP2_Real_e32e64_vi <0x3d>;
 
 } // End SubtargetPredicate = HasDLInsts

test/MC/AMDGPU/vop3-gfx9.s

 v_sub_co_u32 v84, s[2:3], v13, v31 clamp
 // GFX9: v_sub_co_u32_e64 v84, s[2:3], v13, v31 clamp ; encoding: [0x54,0x82,0x1a,0xd1,0x0d,0x3f,0x02,0x00]
 // NOVI: error:
 
 v_subrev_co_u32 v84, vcc, v13, v31 clamp
 // GFX9: v_subrev_co_u32_e64 v84, vcc, v13, v31 clamp ; encoding: [0x54,0xea,0x1b,0xd1,0x0d,0x3f,0x02,0x00]
 // NOVI: error:
 
+v_addc_co_u32 v84, vcc, v13, v31, vcc
+// GFX9: v_addc_co_u32_e32 v84, vcc, v13, v31, vcc ; encoding: [0x0d,0x3f,0xa8,0x38]
+// NOVI: error: instruction not supported on this GPU
+
+v_subb_co_u32 v84, vcc, v13, v31, vcc
+// GFX9: v_subb_co_u32_e32 v84, vcc, v13, v31, vcc ; encoding: [0x0d,0x3f,0xa8,0x3a]
+// NOVI: error: instruction not supported on this GPU
+
+v_subbrev_co_u32 v84, vcc, v13, v31, vcc
+// GFX9: v_subbrev_co_u32_e32 v84, vcc, v13, v31, vcc ; encoding: [0x0d,0x3f,0xa8,0x3c]
+// NOVI: error: instruction not supported on this GPU
+
+v_add_co_u32 v84, vcc, v13, v31
+// GFX9: v_add_co_u32_e32 v84, vcc, v13, v31 ; encoding: [0x0d,0x3f,0xa8,0x32]
+// NOVI: error: instruction not supported on this GPU
+
+v_sub_co_u32 v84, vcc, v13, v31
+// GFX9: v_sub_co_u32_e32 v84, vcc, v13, v31 ; encoding: [0x0d,0x3f,0xa8,0x34]
+// NOVI: error: instruction not supported on this GPU
+
+v_subrev_co_u32 v84, vcc, v13, v31
+// GFX9: v_subrev_co_u32_e32 v84, vcc, v13, v31 ; encoding: [0x0d,0x3f,0xa8,0x36]
+// NOVI: error: instruction not supported on this GPU
+
+// vcc operands may be omitted
+
+v_addc_co_u32 v84, v13, v31
+// GFX9: v_addc_co_u32_e32 v84, vcc, v13, v31, vcc ; encoding: [0x0d,0x3f,0xa8,0x38]
+// NOVI: error: instruction not supported on this GPU
+
+v_subb_co_u32 v84, v13, v31
+// GFX9: v_subb_co_u32_e32 v84, vcc, v13, v31, vcc ; encoding: [0x0d,0x3f,0xa8,0x3a]
+// NOVI: error: instruction not supported on this GPU
+
+v_subbrev_co_u32 v84, v13, v31
+// GFX9: v_subbrev_co_u32_e32 v84, vcc, v13, v31, vcc ; encoding: [0x0d,0x3f,0xa8,0x3c]
+// NOVI: error: instruction not supported on this GPU
+
+v_add_co_u32 v84, v13, v31
+// GFX9: v_add_co_u32_e32 v84, vcc, v13, v31 ; encoding: [0x0d,0x3f,0xa8,0x32]
+// NOVI: error: instruction not supported on this GPU
+
+v_sub_co_u32 v84, v13, v31
+// GFX9: v_sub_co_u32_e32 v84, vcc, v13, v31 ; encoding: [0x0d,0x3f,0xa8,0x34]
+// NOVI: error: instruction not supported on this GPU
+
+v_subrev_co_u32 v84, v13, v31
+// GFX9: v_subrev_co_u32_e32 v84, vcc, v13, v31 ; encoding: [0x0d,0x3f,0xa8,0x36]
+// NOVI: error: instruction not supported on this GPU
+
+
 //===----------------------------------------------------------------------===//
 // Validate register size checks (bug 37943)
 //===----------------------------------------------------------------------===//
 
 // NOVI: error: invalid operand for instruction
 // NOGFX9: error: invalid operand for instruction
 v_add_f64 v[0:1], s0, v[0:1]