[PowerPC] Emit XXSEL for vec_sel and code that has the same pattern

[nemanjai]

Summary

As pointed out in https://bugs.llvm.org/show_bug.cgi?id=41777
we do not emit a vector select even when the pretty much asks for one. This patch changes that.

[nemanjai]

Add tests for some other types as well.

[shawnl]

I like that this also optimizes the case where C is a not

vec_sel(a, b, ~c) => vec_sel(b, a, c)

[jsji]

Have we thought about adding support in DAGCombine or even InstCombine to combine into ISD::VSELECT too?

lib/Target/PowerPC/PPCInstrVSX.td

964 ↗

(On Diff #198539)

Why we need this pattern? and should be a commutable op?

test/CodeGen/PowerPC/vec-select.ll

24 ↗

(On Diff #198539)

I think it would be better if we swap %neg.i, %a to test commutable patterns.

26 ↗

(On Diff #198539)

I think it would be better if we swap %and.i, %and1.i to test commutable patterns.

41 ↗

(On Diff #198539)

How about adding a test of <2 x i64> for vector double too?
And maybe <4 x i1> as a negative test?

[nemanjai]

lib/Target/PowerPC/PPCInstrVSX.td

964 ↗

(On Diff #198539)

No good reason. I put it in to be safe in case ISEL somehow doesn't match a commuted pattern. That doesn't appear to happen so I'll remove it.

test/CodeGen/PowerPC/vec-select.ll

24 ↗

(On Diff #198539)

OK.

26 ↗

(On Diff #198539)

OK. I swapped the operands of the and on one and the operands of the or on another.

41 ↗

(On Diff #198539)

Will do.

[nemanjai]

Removed redundant pattern.
Added commuted tests, a v2i64 test and a negative (v4i1) test.

[jsji]

LGTM. Thanks for fixing!

llvm/lib/Target/PowerPC/PPCInstrVSX.td

def : InstAlias<"xxspltd $XT, $XB, 1",
                 (XXPERMDIs vsrc:$XT, vsfrc:$XB, 3)>;
 def : InstAlias<"xxswapd $XT, $XB",
                 (XXPERMDIs vsrc:$XT, vsfrc:$XB, 2)>;
 
 let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
 
 def : Pat<(v4i32 (vnot_ppc v4i32:$A)),
           (v4i32 (XXLNOR $A, $A))>;
+def : Pat<(v4i32 (or (and (vnot_ppc v4i32:$C), v4i32:$A),
+                     (and v4i32:$B, v4i32:$C))),
+          (v4i32 (XXSEL $A, $B, $C))>;
+
 let Predicates = [IsBigEndian] in {
 def : Pat<(v2f64 (scalar_to_vector f64:$A)),
           (v2f64 (SUBREG_TO_REG (i64 1), $A, sub_64))>;
 
 def : Pat<(f64 (extractelt v2f64:$S, 0)),
           (f64 (EXTRACT_SUBREG $S, sub_64))>;
 def : Pat<(f64 (extractelt v2f64:$S, 1)),
           (f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>;

llvm/test/CodeGen/PowerPC/vec-select.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:     -mcpu=pwr8 -ppc-asm-full-reg-names < %s | FileCheck %s
+define dso_local <4 x i32> @test(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxsel vs34, vs34, vs35, vs36
+; CHECK-NEXT:    blr
+entry:
+  %neg.i = xor <4 x i32> %c, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %and.i = and <4 x i32> %neg.i, %a
+  %and1.i = and <4 x i32> %c, %b
+  %or.i = or <4 x i32> %and1.i, %and.i
+  ret <4 x i32> %or.i
+}
+
+define dso_local <8 x i16> @test2(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
+; CHECK-LABEL: test2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxsel vs34, vs34, vs35, vs36
+; CHECK-NEXT:    blr
+entry:
+  %neg.i = xor <8 x i16> %c, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
+  %and.i = and <8 x i16> %a, %neg.i
+  %and1.i = and <8 x i16> %c, %b
+  %or.i = or <8 x i16> %and.i, %and1.i
+  ret <8 x i16> %or.i
+}
+
+define dso_local <16 x i8> @test3(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test3:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxsel vs34, vs34, vs35, vs36
+; CHECK-NEXT:    blr
+entry:
+  %neg.i = xor <16 x i8> %c, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
+  %and.i = and <16 x i8> %neg.i, %a
+  %and1.i = and <16 x i8> %c, %b
+  %or.i = or <16 x i8> %and.i, %and1.i
+  ret <16 x i8> %or.i
+}
+
+define dso_local <2 x i64> @test4(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
+; CHECK-LABEL: test4:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxsel vs34, vs34, vs35, vs36
+; CHECK-NEXT:    blr
+entry:
+  %neg.i = xor <2 x i64> %c, <i64 -1, i64 -1>
+  %and.i = and <2 x i64> %a, %neg.i
+  %and1.i = and <2 x i64> %c, %b
+  %or.i = or <2 x i64> %and.i, %and1.i
+  ret <2 x i64> %or.i
+}
+
+; Not valid to emit XXSEL for this illegal type.
+define dso_local <4 x i1> @test5(<4 x i1> %a, <4 x i1> %b, <4 x i1> %c) {
+; CHECK-LABEL: test5:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vspltisw v5, 1
+; CHECK-NEXT:    xxland vs0, vs36, vs35
+; CHECK-NEXT:    xxlxor vs1, vs36, vs37
+; CHECK-NEXT:    xxland vs1, vs34, vs1
+; CHECK-NEXT:    xxlor vs34, vs1, vs0
+; CHECK-NEXT:    blr
+entry:
+  %neg.i = xor <4 x i1> %c, <i1 -1, i1 -1, i1 -1, i1 -1>
+  %and.i = and <4 x i1> %a, %neg.i
+  %and1.i = and <4 x i1> %c, %b
+  %or.i = or <4 x i1> %and.i, %and1.i
+  ret <4 x i1> %or.i
+}