RegAlloc: try to fail more gracefully when out of registers

[nhaehnle]

Summary

The emitError path allows the program to continue, unlike report_fatal_error.
This is friendlier to use cases where LLVM is embedded in a larger program,
because the caller may be able to deal with the error somewhat gracefully.

Change the number of requested NOP bytes in the AArch64 and PowerPC
test cases to avoid triggering an unrelated assertion. The compilation
still fails, as verified by the test.

Change-Id: Iafb9ca341002a597b82e59ddc7a1f13c78758e3d

[arsenm]

LGTM. Note I think this is also broken in fast regalloc. I'm also aware of a crash there on out of registers, which I was hoping to fix after the rewrite series is (finally) committed

[qcolombet]

lib/CodeGen/RegAllocBase.cpp

129

Although I find the patch sensible, the new behavior is somewhat misleading:
If MI is not an inline asm statement, we are still going to report a source location (if any), whereas unlike inline asm statement, there is little to nothing that the user can do with that information. It could actually be counter productive to give them that location.

[arsenm]

lib/CodeGen/RegAllocBase.cpp

129

It should probably report the source location for the function, rather than the instruction in that case

[efriedma]

I think there's a fundamental distinction between the two cases of running out of registers. We expect that the user of a programming language will write inline asm directives, and some of those directives will require more registers than the architecture actually supports. But for other instructions, the user isn't writing the register inputs/outputs explicitly; we can't run out of registers unless there's a compiler bug (either in the register allocator, or elsewhere).

Given that, there needs to be some way for error reporting to distinguish the two errors. When we run out of registers due to a non-inline-asm construct in clang, we want to make it clear to the user that the issue is a compiler bug, not user error. This means we need to trigger the code in the clang driver that asks for a bug report and generates preprocessed source.

Of course, that isn't fundamentally tied to calling abort() from the register allocator; some alternate mechanism for reporting ICEs which doesn't immediately kill the process would be reasonable.

[nhaehnle]

In D61489#1490079, @efriedma wrote:

Given that, there needs to be some way for error reporting to distinguish the two errors. When we run out of registers due to a non-inline-asm construct in clang, we want to make it clear to the user that the issue is a compiler bug, not user error. This means we need to trigger the code in the clang driver that asks for a bug report and generates preprocessed source.

Of course, that isn't fundamentally tied to calling abort() from the register allocator; some alternate mechanism for reporting ICEs which doesn't immediately kill the process would be reasonable.

That seems reasonable, though presumably something for a separate change.

[nhaehnle]

Changing the error reporting not to report the instruction location
in the non-inline asm case.

[nhaehnle]

I've changed the patch to not report the location in the non-inline case on the basis that it's an internal compiler error. Will keep it up for a while here and commit if there are no further comments.

lib/CodeGen/RegAllocBase.cpp

while (LiveInterval *VirtReg = dequeue()) {
 
     if (AvailablePhysReg == ~0u) {
       // selectOrSplit failed to find a register!
       // Probably caused by an inline asm.
       MachineInstr *MI = nullptr;
       for (MachineRegisterInfo::reg_instr_iterator
            I = MRI->reg_instr_begin(VirtReg->reg), E = MRI->reg_instr_end();
            I != E; ) {
-        MachineInstr *TmpMI = &*(I++);
-        if (TmpMI->isInlineAsm()) {
-          MI = TmpMI;
+        MI = &*(I++);
+        if (MI->isInlineAsm())
           break;
-        }
-      }
-      if (MI)
-        MI->emitError("inline assembly requires more registers than available");
-      else
+      if (MI) {
+        MI->emitError(
+            MI->isInlineAsm()
+                ? "inline assembly requires more registers than available"
+                : "ran out of registers during register allocation");
+      } else {
         report_fatal_error("ran out of registers during register allocation");
+      }
       // Keep going after reporting the error.
       VRM->assignVirt2Phys(VirtReg->reg,
                  RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
       continue;
     }
 
     if (AvailablePhysReg)
       Matrix->assign(*VirtReg, AvailablePhysReg);

test/CodeGen/AArch64/arm64-anyregcc-crash.ll

 ; RUN: not llc < %s -mtriple=arm64-apple-darwin 2>&1 | FileCheck %s
 ;
 ; Check that misuse of anyregcc results in a compile time error.
 
-; CHECK: LLVM ERROR: ran out of registers during register allocation
+; CHECK: error: ran out of registers during register allocation
 define i64 @anyreglimit(i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6, i64 %v7, i64 %v8,
                         i64 %v9, i64 %v10, i64 %v11, i64 %v12, i64 %v13, i64 %v14, i64 %v15, i64 %v16,
                         i64 %v17, i64 %v18, i64 %v19, i64 %v20, i64 %v21, i64 %v22, i64 %v23, i64 %v24,
                         i64 %v25, i64 %v26, i64 %v27, i64 %v28, i64 %v29, i64 %v30, i64 %v31, i64 %v32) {
 entry:
-  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 15, i8* inttoptr (i64 0 to i8*), i32 32,
+  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 16, i8* inttoptr (i64 0 to i8*), i32 32,
                 i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6, i64 %v7, i64 %v8,
                 i64 %v9, i64 %v10, i64 %v11, i64 %v12, i64 %v13, i64 %v14, i64 %v15, i64 %v16,
                 i64 %v17, i64 %v18, i64 %v19, i64 %v20, i64 %v21, i64 %v22, i64 %v23, i64 %v24,
                 i64 %v25, i64 %v26, i64 %v27, i64 %v28, i64 %v29, i64 %v30, i64 %v31, i64 %v32)
   ret i64 %result
 }
 
 declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)

test/CodeGen/PowerPC/ppc64-anyregcc-crash.ll

 ; RUN: not llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
 ;
 ; Check that misuse of anyregcc results in a compile time error.
 
-; CHECK: LLVM ERROR: ran out of registers during register allocation
+; CHECK: error: ran out of registers during register allocation
 define i64 @anyreglimit(i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6, i64 %v7, i64 %v8,
                         i64 %v9, i64 %v10, i64 %v11, i64 %v12, i64 %v13, i64 %v14, i64 %v15, i64 %v16,
                         i64 %v17, i64 %v18, i64 %v19, i64 %v20, i64 %v21, i64 %v22, i64 %v23, i64 %v24,
                         i64 %v25, i64 %v26, i64 %v27, i64 %v28, i64 %v29, i64 %v30, i64 %v31, i64 %v32) {
 entry:
-  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 15, i8* inttoptr (i64 0 to i8*), i32 32,
+  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 16, i8* inttoptr (i64 0 to i8*), i32 32,
                 i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6, i64 %v7, i64 %v8,
                 i64 %v9, i64 %v10, i64 %v11, i64 %v12, i64 %v13, i64 %v14, i64 %v15, i64 %v16,
                 i64 %v17, i64 %v18, i64 %v19, i64 %v20, i64 %v21, i64 %v22, i64 %v23, i64 %v24,
                 i64 %v25, i64 %v26, i64 %v27, i64 %v28, i64 %v29, i64 %v30, i64 %v31, i64 %v32)
   ret i64 %result
 }
 
 declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)

test/CodeGen/X86/anyregcc-crash.ll

 ; RUN: not llc < %s -mtriple=x86_64-apple-darwin 2>&1 | FileCheck %s
 ;
 ; Check that misuse of anyregcc results in a compile time error.
 
-; CHECK: LLVM ERROR: ran out of registers during register allocation
+; CHECK: error: ran out of registers during register allocation
 define i64 @anyreglimit(i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6,
                         i64 %v7, i64 %v8, i64 %v9, i64 %v10, i64 %v11, i64 %v12,
                         i64 %v13, i64 %v14, i64 %v15, i64 %v16) {
 entry:
   %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 15, i8* inttoptr (i64 0 to i8*), i32 16,
                 i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6,
                 i64 %v7, i64 %v8, i64 %v9, i64 %v10, i64 %v11, i64 %v12,
                 i64 %v13, i64 %v14, i64 %v15, i64 %v16)
   ret i64 %result
 }
 
 declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)