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Differential D61261

[AMDGPU] Increases available SGPR for Calling Convention
ClosedPublic

Authored by rtaylor on Apr 29 2019, 7:11 AM.

Details

Reviewers
arsenm
nhaehnle
dstuttard
tpr
mareko
Commits
rZORG4aa3bd4976a4: [AMDGPU] Increases available SGPR for Calling Convention
rZORG43745c95a9e8: [AMDGPU] Increases available SGPR for Calling Convention
rG4aa3bd4976a4: [AMDGPU] Increases available SGPR for Calling Convention
rG43745c95a9e8: [AMDGPU] Increases available SGPR for Calling Convention
rG29257eb76c8d: [AMDGPU] Increases available SGPR for Calling Convention
rL360778: [AMDGPU] Increases available SGPR for Calling Convention
Summary

SGPR in CC can be either hw initialized or set by other chained shaders
and so this increases the SGPR count availalbe to CC to 104.

Change-Id: I3dfadc750fe4a3e2bd07117a2899fd13f3e2fef3

Diff Detail

Event Timeline

rtaylor created this revision.Apr 29 2019, 7:11 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 29 2019, 7:11 AM
Herald added subscribers: llvm-commits, t-tye, tpr and 7 others. · View Herald Transcript
rtaylor added reviewers: arsenm, nhaehnle, dstuttard, tpr, mareko.Apr 29 2019, 7:12 AM
Harbormaster completed remote builds in B31091: Diff 197106.Apr 29 2019, 7:14 AM
arsenm added inline comments.Apr 29 2019, 11:49 AM
lib/Target/AMDGPU/AMDGPUCallingConv.td
34

I think this goes up to sgpr105 now

64

The test doesn't cover this

rtaylor updated this revision to Diff 197363.Apr 30 2019, 9:59 AM

[AMDGPU] Increased SGPR Count for Calling Convention

Up the sgpr count to 105 and included test case covers both in and return arguments

Harbormaster completed remote builds in B31169: Diff 197363.Apr 30 2019, 10:02 AM
arsenm added inline comments.May 2 2019, 4:36 AM
lib/Target/AMDGPU/AMDGPUCallingConv.td
35

It's up to SGPR105, not 105 SGPRs. SGPR105 should also be included

39–40

I think this needs more work. I think allocateSGPRTuple hard codes the limit as well

rtaylor updated this revision to Diff 197824.May 2 2019, 10:33 AM

Fixed 105 SGPR to 106 SGPR, increased limit count for allocateSGPRTuple

Harbormaster completed remote builds in B31299: Diff 197824.May 2 2019, 10:33 AM
arsenm added a comment.May 10 2019, 2:47 AM

LGTM, though I would like another test with i64 to make sure the SGPR tuple thing works

rtaylor updated this revision to Diff 199037.May 10 2019, 10:49 AM

Added test for SGPR tuple

Harbormaster completed remote builds in B31748: Diff 199037.May 10 2019, 10:49 AM
nhaehnle accepted this revision.May 14 2019, 6:01 AM

LGTM

This revision is now accepted and ready to land.May 14 2019, 6:01 AM
Closed by commit rL360778: [AMDGPU] Increases available SGPR for Calling Convention (authored by rtayl). · Explain WhyMay 15 2019, 7:41 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
AMDGPU/
20 lines
test/
CodeGen/
AMDGPU/
121 lines

Diff 197106

lib/Target/AMDGPU/AMDGPUCallingConv.td

Show All 17 Lines
// Calling convention for SI // Calling convention for SI
def CC_SI : CallingConv<[ def CC_SI : CallingConv<[
CCIfInReg<CCIfType<[f32, i32, f16, v2i16, v2f16] , CCAssignToReg<[ CCIfInReg<CCIfType<[f32, i32, f16, v2i16, v2f16] , CCAssignToReg<[
SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7, SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7,
SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15, SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15,
SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23, SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23,
SGPR24, SGPR25, SGPR26, SGPR27, SGPR28, SGPR29, SGPR30, SGPR31, SGPR24, SGPR25, SGPR26, SGPR27, SGPR28, SGPR29, SGPR30, SGPR31,
SGPR32, SGPR33, SGPR34, SGPR35, SGPR36, SGPR37, SGPR38, SGPR39 SGPR32, SGPR33, SGPR34, SGPR35, SGPR36, SGPR37, SGPR38, SGPR39,
SGPR40, SGPR41, SGPR42, SGPR43, SGPR44, SGPR45, SGPR46, SGPR47,
SGPR48, SGPR49, SGPR50, SGPR51, SGPR52, SGPR53, SGPR54, SGPR55,
SGPR56, SGPR57, SGPR58, SGPR59, SGPR60, SGPR61, SGPR62, SGPR63,
SGPR64, SGPR65, SGPR66, SGPR67, SGPR68, SGPR69, SGPR70, SGPR71,
SGPR72, SGPR73, SGPR74, SGPR75, SGPR76, SGPR77, SGPR78, SGPR79,
SGPR80, SGPR81, SGPR82, SGPR83, SGPR84, SGPR85, SGPR86, SGPR87,
SGPR88, SGPR89, SGPR90, SGPR91, SGPR92, SGPR93, SGPR94, SGPR95,
SGPR96, SGPR97, SGPR98, SGPR99, SGPR100, SGPR101, SGPR102, SGPR103
arsenmUnsubmitted
Not Done
ReplyInline Actions

I think this goes up to sgpr105 now

arsenm: I think this goes up to sgpr105 now
]>>>, ]>>>,
arsenmUnsubmitted
Not Done
ReplyInline Actions

It's up to SGPR105, not 105 SGPRs. SGPR105 should also be included

arsenm: It's up to SGPR105, not 105 SGPRs. SGPR105 should also be included
// We have no way of referring to the generated register tuples // We have no way of referring to the generated register tuples
// here, so use a custom function. // here, so use a custom function.
CCIfInReg<CCIfType<[i64], CCCustom<"allocateSGPRTuple">>>, CCIfInReg<CCIfType<[i64], CCCustom<"allocateSGPRTuple">>>,
CCIfByVal<CCIfType<[i64], CCCustom<"allocateSGPRTuple">>>, CCIfByVal<CCIfType<[i64], CCCustom<"allocateSGPRTuple">>>,
arsenmUnsubmitted
Not Done
ReplyInline Actions

I think this needs more work. I think allocateSGPRTuple hard codes the limit as well

arsenm: I think this needs more work. I think allocateSGPRTuple hard codes the limit as well
// 32*4 + 4 is the minimum for a fetch shader consumer with 32 inputs. // 32*4 + 4 is the minimum for a fetch shader consumer with 32 inputs.
CCIfNotInReg<CCIfType<[f32, i32, f16, v2i16, v2f16] , CCAssignToReg<[ CCIfNotInReg<CCIfType<[f32, i32, f16, v2i16, v2f16] , CCAssignToReg<[
VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7, VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15, VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23, VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31, VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31,
VGPR32, VGPR33, VGPR34, VGPR35, VGPR36, VGPR37, VGPR38, VGPR39, VGPR32, VGPR33, VGPR34, VGPR35, VGPR36, VGPR37, VGPR38, VGPR39,
VGPR40, VGPR41, VGPR42, VGPR43, VGPR44, VGPR45, VGPR46, VGPR47, VGPR40, VGPR41, VGPR42, VGPR43, VGPR44, VGPR45, VGPR46, VGPR47,
VGPR48, VGPR49, VGPR50, VGPR51, VGPR52, VGPR53, VGPR54, VGPR55, VGPR48, VGPR49, VGPR50, VGPR51, VGPR52, VGPR53, VGPR54, VGPR55,
VGPR56, VGPR57, VGPR58, VGPR59, VGPR60, VGPR61, VGPR62, VGPR63, VGPR56, VGPR57, VGPR58, VGPR59, VGPR60, VGPR61, VGPR62, VGPR63,
VGPR64, VGPR65, VGPR66, VGPR67, VGPR68, VGPR69, VGPR70, VGPR71, VGPR64, VGPR65, VGPR66, VGPR67, VGPR68, VGPR69, VGPR70, VGPR71,
VGPR72, VGPR73, VGPR74, VGPR75, VGPR76, VGPR77, VGPR78, VGPR79, VGPR72, VGPR73, VGPR74, VGPR75, VGPR76, VGPR77, VGPR78, VGPR79,
VGPR80, VGPR81, VGPR82, VGPR83, VGPR84, VGPR85, VGPR86, VGPR87, VGPR80, VGPR81, VGPR82, VGPR83, VGPR84, VGPR85, VGPR86, VGPR87,
VGPR88, VGPR89, VGPR90, VGPR91, VGPR92, VGPR93, VGPR94, VGPR95, VGPR88, VGPR89, VGPR90, VGPR91, VGPR92, VGPR93, VGPR94, VGPR95,
VGPR96, VGPR97, VGPR98, VGPR99, VGPR100, VGPR101, VGPR102, VGPR103, VGPR96, VGPR97, VGPR98, VGPR99, VGPR100, VGPR101, VGPR102, VGPR103,
VGPR104, VGPR105, VGPR106, VGPR107, VGPR108, VGPR109, VGPR110, VGPR111, VGPR104, VGPR105, VGPR106, VGPR107, VGPR108, VGPR109, VGPR110, VGPR111,
VGPR112, VGPR113, VGPR114, VGPR115, VGPR116, VGPR117, VGPR118, VGPR119, VGPR112, VGPR113, VGPR114, VGPR115, VGPR116, VGPR117, VGPR118, VGPR119,
VGPR120, VGPR121, VGPR122, VGPR123, VGPR124, VGPR125, VGPR126, VGPR127, VGPR120, VGPR121, VGPR122, VGPR123, VGPR124, VGPR125, VGPR126, VGPR127,
VGPR128, VGPR129, VGPR130, VGPR131, VGPR132, VGPR133, VGPR134, VGPR135 VGPR128, VGPR129, VGPR130, VGPR131, VGPR132, VGPR133, VGPR134, VGPR135
]>>> ]>>>
]>; ]>;
def RetCC_SI_Shader : CallingConv<[ def RetCC_SI_Shader : CallingConv<[
arsenmUnsubmitted
Not Done
ReplyInline Actions

The test doesn't cover this

arsenm: The test doesn't cover this
CCIfType<[i32] , CCAssignToReg<[ CCIfType<[i32] , CCAssignToReg<[
SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7, SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7,
SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15, SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15,
SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23, SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23,
SGPR24, SGPR25, SGPR26, SGPR27, SGPR28, SGPR29, SGPR30, SGPR31, SGPR24, SGPR25, SGPR26, SGPR27, SGPR28, SGPR29, SGPR30, SGPR31,
SGPR32, SGPR33, SGPR34, SGPR35, SGPR36, SGPR37, SGPR38, SGPR39 SGPR32, SGPR33, SGPR34, SGPR35, SGPR36, SGPR37, SGPR38, SGPR39,
SGPR40, SGPR41, SGPR42, SGPR43, SGPR44, SGPR45, SGPR46, SGPR47,
SGPR48, SGPR49, SGPR50, SGPR51, SGPR52, SGPR53, SGPR54, SGPR55,
SGPR56, SGPR57, SGPR58, SGPR59, SGPR60, SGPR61, SGPR62, SGPR63,
SGPR64, SGPR65, SGPR66, SGPR67, SGPR68, SGPR69, SGPR70, SGPR71,
SGPR72, SGPR73, SGPR74, SGPR75, SGPR76, SGPR77, SGPR78, SGPR79,
SGPR80, SGPR81, SGPR82, SGPR83, SGPR84, SGPR85, SGPR86, SGPR87,
SGPR88, SGPR89, SGPR90, SGPR91, SGPR92, SGPR93, SGPR94, SGPR95,
SGPR96, SGPR97, SGPR98, SGPR99, SGPR100, SGPR101, SGPR102, SGPR103
]>>, ]>>,
// 32*4 + 4 is the minimum for a fetch shader with 32 outputs. // 32*4 + 4 is the minimum for a fetch shader with 32 outputs.
CCIfType<[f32, f16, v2f16] , CCAssignToReg<[ CCIfType<[f32, f16, v2f16] , CCAssignToReg<[
VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7, VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15, VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23, VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31, VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31,
▲ Show 20 Lines • Show All 74 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/sgpr-limit.ll

  • This file was added.
; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck %s
;CHECK: s_add_i32 s0, s0, s2
;CHECK: s_add_i32 s0, s0, s3
;CHECK: s_add_i32 s0, s0, s4
;CHECK: s_add_i32 s0, s0, s5
;CHECK: s_add_i32 s0, s0, s6
;CHECK: s_add_i32 s0, s0, s7
;CHECK: s_add_i32 s0, s0, s8
;CHECK: s_add_i32 s0, s0, s9
;CHECK: s_add_i32 s0, s0, s10
;CHECK: s_add_i32 s0, s0, s11
;CHECK: s_add_i32 s0, s0, s12
;CHECK: s_add_i32 s0, s0, s13
;CHECK: s_add_i32 s0, s0, s14
;CHECK: s_add_i32 s0, s0, s15
;CHECK: s_add_i32 s0, s0, s16
;CHECK: s_add_i32 s0, s0, s17
;CHECK: s_add_i32 s0, s0, s18
;CHECK: s_add_i32 s0, s0, s19
;CHECK: s_add_i32 s0, s0, s20
;CHECK: s_add_i32 s0, s0, s21
;CHECK: s_add_i32 s0, s0, s22
;CHECK: s_add_i32 s0, s0, s23
;CHECK: s_add_i32 s0, s0, s24
;CHECK: s_add_i32 s0, s0, s25
;CHECK: s_add_i32 s0, s0, s26
;CHECK: s_add_i32 s0, s0, s27
;CHECK: s_add_i32 s0, s0, s28
;CHECK: s_add_i32 s0, s0, s29
;CHECK: s_add_i32 s0, s0, s30
;CHECK: s_add_i32 s0, s0, s31
;CHECK: s_add_i32 s0, s0, s32
;CHECK: s_add_i32 s0, s0, s33
;CHECK: s_add_i32 s0, s0, s34
;CHECK: s_add_i32 s0, s0, s35
;CHECK: s_add_i32 s0, s0, s36
;CHECK: s_add_i32 s0, s0, s37
;CHECK: s_add_i32 s0, s0, s38
;CHECK: s_add_i32 s0, s0, s39
;CHECK: s_add_i32 s0, s0, s40
;CHECK: s_add_i32 s0, s0, s41
;CHECK: s_add_i32 s0, s0, s42
;CHECK: s_add_i32 s0, s0, s43
;CHECK: s_add_i32 s0, s0, s44
;CHECK: s_add_i32 s0, s0, s45
;CHECK: s_add_i32 s0, s0, s46
;CHECK: s_add_i32 s0, s0, s47
;CHECK: s_add_i32 s0, s0, s48
;CHECK: s_add_i32 s0, s0, s49
;CHECK: s_add_i32 s0, s0, s50
;CHECK: s_add_i32 s0, s0, s51
;CHECK: s_add_i32 s0, s0, s52
;CHECK: s_add_i32 s0, s0, s53
;CHECK: s_add_i32 s0, s0, s54
;CHECK: v_mov_b32_e32 v0, s0
;CHECK: buffer_store_short v0, off, s[56:59], 0 offset:16
;CHECK: s_endpgm
define amdgpu_gs void @_amdgpu_gs_main(i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, <4 x i32> inreg) {
.entry:
%56 = add i32 %0, %1
%57 = add i32 %56, %2
%58 = add i32 %57, %3
%59 = add i32 %58, %4
%60 = add i32 %59, %5
%61 = add i32 %60, %6
%62 = add i32 %61, %7
%63 = add i32 %62, %8
%64 = add i32 %63, %9
%65 = add i32 %64, %10
%66 = add i32 %65, %11
%67 = add i32 %66, %12
%68 = add i32 %67, %13
%69 = add i32 %68, %14
%70 = add i32 %69, %15
%71 = add i32 %70, %16
%72 = add i32 %71, %17
%73 = add i32 %72, %18
%74 = add i32 %73, %19
%75 = add i32 %74, %20
%76 = add i32 %75, %21
%77 = add i32 %76, %22
%78 = add i32 %77, %23
%79 = add i32 %78, %24
%80 = add i32 %79, %25
%81 = add i32 %80, %26
%82 = add i32 %81, %27
%83 = add i32 %82, %28
%84 = add i32 %83, %29
%85 = add i32 %84, %30
%86 = add i32 %85, %31
%87 = add i32 %86, %32
%88 = add i32 %87, %33
%89 = add i32 %88, %34
%90 = add i32 %89, %35
%91 = add i32 %90, %36
%92 = add i32 %91, %37
%93 = add i32 %92, %38
%94 = add i32 %93, %39
%95 = add i32 %94, %40
%96 = add i32 %95, %41
%97 = add i32 %96, %42
%98 = add i32 %97, %43
%99 = add i32 %98, %44
%100 = add i32 %99, %45
%101 = add i32 %100, %46
%102 = add i32 %101, %47
%103 = add i32 %102, %48
%104 = add i32 %103, %49
%105 = add i32 %104, %50
%106 = add i32 %105, %51
%107 = add i32 %106, %52
%108 = add i32 %107, %53
%109 = add i32 %108, %54
%res = trunc i32 %109 to i16
call void @llvm.amdgcn.buffer.store.i16(i16 %res, <4 x i32> %55, i32 0, i32 16, i1 0, i1 0)
ret void
}
declare void @llvm.amdgcn.buffer.store.i16(i16, <4 x i32>, i32, i32, i1, i1) #0