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Differential D61258

AArch64: support binutils-like things on arm64_32.
ClosedPublic

Authored by t.p.northover on Apr 29 2019, 6:34 AM.

Details

Reviewers
fhahn
rengolin
kristof.beyls
olista01
Summary

This adds support for the arm64_32 watchOS ABI to LLVM's low level tools, teaching them about the specific MachO choices and constants needed to disassemble things sensibly.

Diff Detail

Repository
rL LLVM

Event Timeline

t.p.northover created this revision.Apr 29 2019, 6:34 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 29 2019, 6:34 AM
Herald added subscribers: kristina, rupprecht, dexonsmith and 4 others. · View Herald Transcript
t.p.northover added a child revision: D61259: AArch64: support arm64_32, an ILP32 slice for watchOS..Apr 29 2019, 6:37 AM
t.p.northover added a comment.May 8 2019, 6:41 AM

Ping.

fhahn added a subscriber: fhahn.May 8 2019, 7:05 AM
fhahn added inline comments.
llvm/lib/Support/ARMTargetParser.cpp
292–294

It might be good to add arm64_32 tests to llvm/unittests/Support/TargetParserTest.cpp

llvm/lib/Support/Triple.cpp
25

It might be good to add arm64_32 tests to llvm/unittests/ADT/TripleTest.cpp

t.p.northover updated this revision to Diff 198785.May 9 2019, 4:03 AM

Added unittests in suggested places.

fhahn accepted this revision.May 13 2019, 3:40 AM
fhahn added reviewers: rengolin, kristof.beyls, olista01.

LGTM. I've also added a few other reviewers, in case they have additional thoughts.

llvm/tools/llvm-objdump/MachODump.cpp
2048

Could we check for this in one of the tests?

8137

Could we check for this in one of the tests?

This revision is now accepted and ready to land.May 13 2019, 3:40 AM
t.p.northover closed this revision.May 14 2019, 4:26 AM

Thanks Florian, I've committed it as r360663, with the extra tests you suggested.

Revision Contents

PathSize
llvm/
include/
llvm/
ADT/
1 line
BinaryFormat/
6 lines
lib/
Object/
22 lines
Support/
8 lines
13 lines
Target/
AArch64/
AsmParser/
2 lines
Disassembler/
8 lines
MCTargetDesc/
20 lines
5 lines
6 lines
10 lines
TargetInfo/
15 lines
test/
Object/
AArch64/
5 lines
Inputs/
tools/
llvm-objdump/
AArch64/
Inputs/
5 lines
19 lines
tools/
llvm-objdump/
29 lines
unittests/
ADT/
11 lines
Support/
3 lines

Diff 198785

llvm/include/llvm/ADT/Triple.h

Show First 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
public: public:
enum ArchType { enum ArchType {
UnknownArch, UnknownArch,
arm, // ARM (little endian): arm, armv.*, xscale arm, // ARM (little endian): arm, armv.*, xscale
armeb, // ARM (big endian): armeb armeb, // ARM (big endian): armeb
aarch64, // AArch64 (little endian): aarch64 aarch64, // AArch64 (little endian): aarch64
aarch64_be, // AArch64 (big endian): aarch64_be aarch64_be, // AArch64 (big endian): aarch64_be
aarch64_32, // AArch64 (little endian) ILP32: aarch64_32
arc, // ARC: Synopsys ARC arc, // ARC: Synopsys ARC
avr, // AVR: Atmel AVR microcontroller avr, // AVR: Atmel AVR microcontroller
bpfel, // eBPF or extended BPF or 64-bit BPF (little endian) bpfel, // eBPF or extended BPF or 64-bit BPF (little endian)
bpfeb, // eBPF or extended BPF or 64-bit BPF (big endian) bpfeb, // eBPF or extended BPF or 64-bit BPF (big endian)
hexagon, // Hexagon: hexagon hexagon, // Hexagon: hexagon
mips, // MIPS: mips, mipsallegrex, mipsr6 mips, // MIPS: mips, mipsallegrex, mipsr6
mipsel, // MIPSEL: mipsel, mipsallegrexe, mipsr6el mipsel, // MIPSEL: mipsel, mipsallegrexe, mipsr6el
mips64, // MIPS64: mips64, mips64r6, mipsn32, mipsn32r6 mips64, // MIPS64: mips64, mips64r6, mipsn32, mipsn32r6
▲ Show 20 Lines • Show All 798 Lines • Show Last 20 Lines

llvm/include/llvm/BinaryFormat/MachO.h

Show First 20 Lines • Show All 1,395 Lines • ▼ Show 20 Lines
inline void SET_COMM_ALIGN(uint16_t &n_desc, uint8_t align) { inline void SET_COMM_ALIGN(uint16_t &n_desc, uint8_t align) {
n_desc = ((n_desc & 0xf0ffu) | ((align & 0x0fu) << 8u)); n_desc = ((n_desc & 0xf0ffu) | ((align & 0x0fu) << 8u));
} }
// Enums from <mach/machine.h> // Enums from <mach/machine.h>
enum : uint32_t { enum : uint32_t {
// Capability bits used in the definition of cpu_type. // Capability bits used in the definition of cpu_type.
CPU_ARCH_MASK = 0xff000000, // Mask for architecture bits CPU_ARCH_MASK = 0xff000000, // Mask for architecture bits
CPU_ARCH_ABI64 = 0x01000000 // 64 bit ABI CPU_ARCH_ABI64 = 0x01000000, // 64 bit ABI
CPU_ARCH_ABI64_32 = 0x02000000, // ILP32 ABI on 64-bit hardware
}; };
// Constants for the cputype field. // Constants for the cputype field.
enum CPUType { enum CPUType {
CPU_TYPE_ANY = -1, CPU_TYPE_ANY = -1,
CPU_TYPE_X86 = 7, CPU_TYPE_X86 = 7,
CPU_TYPE_I386 = CPU_TYPE_X86, CPU_TYPE_I386 = CPU_TYPE_X86,
CPU_TYPE_X86_64 = CPU_TYPE_X86 | CPU_ARCH_ABI64, CPU_TYPE_X86_64 = CPU_TYPE_X86 | CPU_ARCH_ABI64,
/* CPU_TYPE_MIPS = 8, */ /* CPU_TYPE_MIPS = 8, */
CPU_TYPE_MC98000 = 10, // Old Motorola PowerPC CPU_TYPE_MC98000 = 10, // Old Motorola PowerPC
CPU_TYPE_ARM = 12, CPU_TYPE_ARM = 12,
CPU_TYPE_ARM64 = CPU_TYPE_ARM | CPU_ARCH_ABI64, CPU_TYPE_ARM64 = CPU_TYPE_ARM | CPU_ARCH_ABI64,
CPU_TYPE_ARM64_32 = CPU_TYPE_ARM | CPU_ARCH_ABI64_32,
CPU_TYPE_SPARC = 14, CPU_TYPE_SPARC = 14,
CPU_TYPE_POWERPC = 18, CPU_TYPE_POWERPC = 18,
CPU_TYPE_POWERPC64 = CPU_TYPE_POWERPC | CPU_ARCH_ABI64 CPU_TYPE_POWERPC64 = CPU_TYPE_POWERPC | CPU_ARCH_ABI64
}; };
enum : uint32_t { enum : uint32_t {
// Capability bits used in the definition of cpusubtype. // Capability bits used in the definition of cpusubtype.
CPU_SUBTYPE_MASK = 0xff000000, // Mask for architecture bits CPU_SUBTYPE_MASK = 0xff000000, // Mask for architecture bits
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Linesenum CPUSubTypeARM {
CPU_SUBTYPE_ARM_V7EM = 16 CPU_SUBTYPE_ARM_V7EM = 16
}; };
enum CPUSubTypeARM64 { enum CPUSubTypeARM64 {
CPU_SUBTYPE_ARM64_ALL = 0, CPU_SUBTYPE_ARM64_ALL = 0,
CPU_SUBTYPE_ARM64E = 2, CPU_SUBTYPE_ARM64E = 2,
}; };
enum CPUSubTypeARM64_32 { CPU_SUBTYPE_ARM64_32_V8 = 1 };
enum CPUSubTypeSPARC { CPU_SUBTYPE_SPARC_ALL = 0 }; enum CPUSubTypeSPARC { CPU_SUBTYPE_SPARC_ALL = 0 };
enum CPUSubTypePowerPC { enum CPUSubTypePowerPC {
CPU_SUBTYPE_POWERPC_ALL = 0, CPU_SUBTYPE_POWERPC_ALL = 0,
CPU_SUBTYPE_POWERPC_601 = 1, CPU_SUBTYPE_POWERPC_601 = 1,
CPU_SUBTYPE_POWERPC_602 = 2, CPU_SUBTYPE_POWERPC_602 = 2,
CPU_SUBTYPE_POWERPC_603 = 3, CPU_SUBTYPE_POWERPC_603 = 3,
CPU_SUBTYPE_POWERPC_603e = 4, CPU_SUBTYPE_POWERPC_603e = 4,
▲ Show 20 Lines • Show All 499 Lines • Show Last 20 Lines

llvm/lib/Object/MachOObjectFile.cpp

Show First 20 Lines • Show All 1,094 Lines • ▼ Show 20 Lines if (cputype == MachO::CPU_TYPE_I386) {
"command in " + CmdName + " command"); "command in " + CmdName + " command");
state += sizeof(MachO::arm_thread_state32_t); state += sizeof(MachO::arm_thread_state32_t);
} else { } else {
return malformedError("load command " + Twine(LoadCommandIndex) + return malformedError("load command " + Twine(LoadCommandIndex) +
" unknown flavor (" + Twine(flavor) + ") for " " unknown flavor (" + Twine(flavor) + ") for "
"flavor number " + Twine(nflavor) + " in " + "flavor number " + Twine(nflavor) + " in " +
CmdName + " command"); CmdName + " command");
} }
} else if (cputype == MachO::CPU_TYPE_ARM64) { } else if (cputype == MachO::CPU_TYPE_ARM64 ||
cputype == MachO::CPU_TYPE_ARM64_32) {
if (flavor == MachO::ARM_THREAD_STATE64) { if (flavor == MachO::ARM_THREAD_STATE64) {
if (count != MachO::ARM_THREAD_STATE64_COUNT) if (count != MachO::ARM_THREAD_STATE64_COUNT)
return malformedError("load command " + Twine(LoadCommandIndex) + return malformedError("load command " + Twine(LoadCommandIndex) +
" count not ARM_THREAD_STATE64_COUNT for " " count not ARM_THREAD_STATE64_COUNT for "
"flavor number " + Twine(nflavor) + " which is " "flavor number " + Twine(nflavor) + " which is "
"a ARM_THREAD_STATE64 flavor in " + CmdName + "a ARM_THREAD_STATE64 flavor in " + CmdName +
" command"); " command");
if (state + sizeof(MachO::arm_thread_state64_t) > end) if (state + sizeof(MachO::arm_thread_state64_t) > end)
▲ Show 20 Lines • Show All 1,054 Lines • ▼ Show 20 Lines case Triple::arm: {
"ARM_RELOC_HALF_SECTDIFF" }; "ARM_RELOC_HALF_SECTDIFF" };
if (RType > 9) if (RType > 9)
res = "Unknown"; res = "Unknown";
else else
res = Table[RType]; res = Table[RType];
break; break;
} }
case Triple::aarch64: { case Triple::aarch64:
case Triple::aarch64_32: {
static const char *const Table[] = { static const char *const Table[] = {
"ARM64_RELOC_UNSIGNED", "ARM64_RELOC_SUBTRACTOR", "ARM64_RELOC_UNSIGNED", "ARM64_RELOC_SUBTRACTOR",
"ARM64_RELOC_BRANCH26", "ARM64_RELOC_PAGE21", "ARM64_RELOC_BRANCH26", "ARM64_RELOC_PAGE21",
"ARM64_RELOC_PAGEOFF12", "ARM64_RELOC_GOT_LOAD_PAGE21", "ARM64_RELOC_PAGEOFF12", "ARM64_RELOC_GOT_LOAD_PAGE21",
"ARM64_RELOC_GOT_LOAD_PAGEOFF12", "ARM64_RELOC_POINTER_TO_GOT", "ARM64_RELOC_GOT_LOAD_PAGEOFF12", "ARM64_RELOC_POINTER_TO_GOT",
"ARM64_RELOC_TLVP_LOAD_PAGE21", "ARM64_RELOC_TLVP_LOAD_PAGEOFF12", "ARM64_RELOC_TLVP_LOAD_PAGE21", "ARM64_RELOC_TLVP_LOAD_PAGEOFF12",
"ARM64_RELOC_ADDEND" "ARM64_RELOC_ADDEND"
}; };
▲ Show 20 Lines • Show All 311 Lines • ▼ Show 20 Lines
StringRef MachOObjectFile::getFileFormatName() const { StringRef MachOObjectFile::getFileFormatName() const {
unsigned CPUType = getCPUType(*this); unsigned CPUType = getCPUType(*this);
if (!is64Bit()) { if (!is64Bit()) {
switch (CPUType) { switch (CPUType) {
case MachO::CPU_TYPE_I386: case MachO::CPU_TYPE_I386:
return "Mach-O 32-bit i386"; return "Mach-O 32-bit i386";
case MachO::CPU_TYPE_ARM: case MachO::CPU_TYPE_ARM:
return "Mach-O arm"; return "Mach-O arm";
case MachO::CPU_TYPE_ARM64_32:
return "Mach-O arm64 (ILP32)";
case MachO::CPU_TYPE_POWERPC: case MachO::CPU_TYPE_POWERPC:
return "Mach-O 32-bit ppc"; return "Mach-O 32-bit ppc";
default: default:
return "Mach-O 32-bit unknown"; return "Mach-O 32-bit unknown";
} }
} }
switch (CPUType) { switch (CPUType) {
Show All 13 LinesTriple::ArchType MachOObjectFile::getArch(uint32_t CPUType) {
case MachO::CPU_TYPE_I386: case MachO::CPU_TYPE_I386:
return Triple::x86; return Triple::x86;
case MachO::CPU_TYPE_X86_64: case MachO::CPU_TYPE_X86_64:
return Triple::x86_64; return Triple::x86_64;
case MachO::CPU_TYPE_ARM: case MachO::CPU_TYPE_ARM:
return Triple::arm; return Triple::arm;
case MachO::CPU_TYPE_ARM64: case MachO::CPU_TYPE_ARM64:
return Triple::aarch64; return Triple::aarch64;
case MachO::CPU_TYPE_ARM64_32:
return Triple::aarch64_32;
case MachO::CPU_TYPE_POWERPC: case MachO::CPU_TYPE_POWERPC:
return Triple::ppc; return Triple::ppc;
case MachO::CPU_TYPE_POWERPC64: case MachO::CPU_TYPE_POWERPC64:
return Triple::ppc64; return Triple::ppc64;
default: default:
return Triple::UnknownArch; return Triple::UnknownArch;
} }
} }
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines case MachO::CPU_SUBTYPE_ARM64_ALL:
if (McpuDefault) if (McpuDefault)
*McpuDefault = "cyclone"; *McpuDefault = "cyclone";
if (ArchFlag) if (ArchFlag)
*ArchFlag = "arm64"; *ArchFlag = "arm64";
return Triple("arm64-apple-darwin"); return Triple("arm64-apple-darwin");
default: default:
return Triple(); return Triple();
} }
case MachO::CPU_TYPE_ARM64_32:
switch (CPUSubType & ~MachO::CPU_SUBTYPE_MASK) {
case MachO::CPU_SUBTYPE_ARM64_32_V8:
if (McpuDefault)
*McpuDefault = "cyclone";
if (ArchFlag)
*ArchFlag = "arm64_32";
return Triple("arm64_32-apple-darwin");
default:
return Triple();
}
case MachO::CPU_TYPE_POWERPC: case MachO::CPU_TYPE_POWERPC:
switch (CPUSubType & ~MachO::CPU_SUBTYPE_MASK) { switch (CPUSubType & ~MachO::CPU_SUBTYPE_MASK) {
case MachO::CPU_SUBTYPE_POWERPC_ALL: case MachO::CPU_SUBTYPE_POWERPC_ALL:
if (ArchFlag) if (ArchFlag)
*ArchFlag = "ppc"; *ArchFlag = "ppc";
return Triple("ppc-apple-darwin"); return Triple("ppc-apple-darwin");
default: default:
return Triple(); return Triple();
Show All 27 Lines return StringSwitch<bool>(ArchFlag)
.Case("armv6", true) .Case("armv6", true)
.Case("armv6m", true) .Case("armv6m", true)
.Case("armv7", true) .Case("armv7", true)
.Case("armv7em", true) .Case("armv7em", true)
.Case("armv7k", true) .Case("armv7k", true)
.Case("armv7m", true) .Case("armv7m", true)
.Case("armv7s", true) .Case("armv7s", true)
.Case("arm64", true) .Case("arm64", true)
.Case("arm64_32", true)
.Case("ppc", true) .Case("ppc", true)
.Case("ppc64", true) .Case("ppc64", true)
.Default(false); .Default(false);
} }
Triple::ArchType MachOObjectFile::getArch() const { Triple::ArchType MachOObjectFile::getArch() const {
return getArch(getCPUType(*this)); return getArch(getCPUType(*this));
} }
▲ Show 20 Lines • Show All 1,900 Lines • Show Last 20 Lines

llvm/lib/Support/ARMTargetParser.cpp

Show First 20 Lines • Show All 242 Lines • ▼ Show 20 LinesARM::EndianKind ARM::parseArchEndian(StringRef Arch) {
if (Arch.startswith("arm") || Arch.startswith("thumb")) { if (Arch.startswith("arm") || Arch.startswith("thumb")) {
if (Arch.endswith("eb")) if (Arch.endswith("eb"))
return EndianKind::BIG; return EndianKind::BIG;
else else
return EndianKind::LITTLE; return EndianKind::LITTLE;
} }
if (Arch.startswith("aarch64")) if (Arch.startswith("aarch64") || Arch.startswith("aarch64_32"))
return EndianKind::LITTLE; return EndianKind::LITTLE;
return EndianKind::INVALID; return EndianKind::INVALID;
} }
// ARM, Thumb, AArch64 // ARM, Thumb, AArch64
ARM::ISAKind ARM::parseArchISA(StringRef Arch) { ARM::ISAKind ARM::parseArchISA(StringRef Arch) {
return StringSwitch<ISAKind>(Arch) return StringSwitch<ISAKind>(Arch)
Show All 24 Lines
// "v.+", if the latter, return unmodified string, minus 'eb'. // "v.+", if the latter, return unmodified string, minus 'eb'.
// If invalid, return empty string. // If invalid, return empty string.
StringRef ARM::getCanonicalArchName(StringRef Arch) { StringRef ARM::getCanonicalArchName(StringRef Arch) {
size_t offset = StringRef::npos; size_t offset = StringRef::npos;
StringRef A = Arch; StringRef A = Arch;
StringRef Error = ""; StringRef Error = "";
// Begins with "arm" / "thumb", move past it. // Begins with "arm" / "thumb", move past it.
if (A.startswith("arm64")) if (A.startswith("arm64_32"))
offset = 8;
else if (A.startswith("arm64"))
fhahnUnsubmitted
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It might be good to add arm64_32 tests to llvm/unittests/Support/TargetParserTest.cpp

fhahn: It might be good to add arm64_32 tests to llvm/unittests/Support/TargetParserTest.cpp
offset = 5; offset = 5;
else if (A.startswith("aarch64_32"))
offset = 10;
else if (A.startswith("arm")) else if (A.startswith("arm"))
offset = 3; offset = 3;
else if (A.startswith("thumb")) else if (A.startswith("thumb"))
offset = 5; offset = 5;
else if (A.startswith("aarch64")) { else if (A.startswith("aarch64")) {
offset = 7; offset = 7;
// AArch64 uses "_be", not "eb" suffix. // AArch64 uses "_be", not "eb" suffix.
if (A.find("eb") != StringRef::npos) if (A.find("eb") != StringRef::npos)
▲ Show 20 Lines • Show All 275 Lines • Show Last 20 Lines

llvm/lib/Support/Triple.cpp

Show All 16 Lines
using namespace llvm; using namespace llvm;
StringRef Triple::getArchTypeName(ArchType Kind) { StringRef Triple::getArchTypeName(ArchType Kind) {
switch (Kind) { switch (Kind) {
case UnknownArch: return "unknown"; case UnknownArch: return "unknown";
case aarch64: return "aarch64"; case aarch64: return "aarch64";
case aarch64_be: return "aarch64_be"; case aarch64_be: return "aarch64_be";
case aarch64_32: return "aarch64_32";
fhahnUnsubmitted
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It might be good to add arm64_32 tests to llvm/unittests/ADT/TripleTest.cpp

fhahn: It might be good to add arm64_32 tests to llvm/unittests/ADT/TripleTest.cpp
case arm: return "arm"; case arm: return "arm";
case armeb: return "armeb"; case armeb: return "armeb";
case arc: return "arc"; case arc: return "arc";
case avr: return "avr"; case avr: return "avr";
case bpfel: return "bpfel"; case bpfel: return "bpfel";
case bpfeb: return "bpfeb"; case bpfeb: return "bpfeb";
case hexagon: return "hexagon"; case hexagon: return "hexagon";
case mips: return "mips"; case mips: return "mips";
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
} }
StringRef Triple::getArchTypePrefix(ArchType Kind) { StringRef Triple::getArchTypePrefix(ArchType Kind) {
switch (Kind) { switch (Kind) {
default: default:
return StringRef(); return StringRef();
case aarch64: case aarch64:
case aarch64_be: return "aarch64"; case aarch64_be:
case aarch64_32: return "aarch64";
case arc: return "arc"; case arc: return "arc";
case arm: case arm:
case armeb: case armeb:
case thumb: case thumb:
case thumbeb: return "arm"; case thumbeb: return "arm";
▲ Show 20 Lines • Show All 163 Lines • ▼ Show 20 Linesstatic Triple::ArchType parseBPFArch(StringRef ArchName) {
} }
} }
Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) { Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) {
Triple::ArchType BPFArch(parseBPFArch(Name)); Triple::ArchType BPFArch(parseBPFArch(Name));
return StringSwitch<Triple::ArchType>(Name) return StringSwitch<Triple::ArchType>(Name)
.Case("aarch64", aarch64) .Case("aarch64", aarch64)
.Case("aarch64_be", aarch64_be) .Case("aarch64_be", aarch64_be)
.Case("aarch64_32", aarch64_32)
.Case("arc", arc) .Case("arc", arc)
.Case("arm64", aarch64) // "arm64" is an alias for "aarch64" .Case("arm64", aarch64) // "arm64" is an alias for "aarch64"
.Case("arm64_32", aarch64_32)
.Case("arm", arm) .Case("arm", arm)
.Case("armeb", armeb) .Case("armeb", armeb)
.Case("avr", avr) .Case("avr", avr)
.StartsWith("bpf", BPFArch) .StartsWith("bpf", BPFArch)
.Case("mips", mips) .Case("mips", mips)
.Case("mipsel", mipsel) .Case("mipsel", mipsel)
.Case("mips64", mips64) .Case("mips64", mips64)
.Case("mips64el", mips64el) .Case("mips64el", mips64el)
▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Lines auto AT = StringSwitch<Triple::ArchType>(ArchName)
.Cases("amd64", "x86_64", "x86_64h", Triple::x86_64) .Cases("amd64", "x86_64", "x86_64h", Triple::x86_64)
.Cases("powerpc", "ppc", "ppc32", Triple::ppc) .Cases("powerpc", "ppc", "ppc32", Triple::ppc)
.Cases("powerpc64", "ppu", "ppc64", Triple::ppc64) .Cases("powerpc64", "ppu", "ppc64", Triple::ppc64)
.Cases("powerpc64le", "ppc64le", Triple::ppc64le) .Cases("powerpc64le", "ppc64le", Triple::ppc64le)
.Case("xscale", Triple::arm) .Case("xscale", Triple::arm)
.Case("xscaleeb", Triple::armeb) .Case("xscaleeb", Triple::armeb)
.Case("aarch64", Triple::aarch64) .Case("aarch64", Triple::aarch64)
.Case("aarch64_be", Triple::aarch64_be) .Case("aarch64_be", Triple::aarch64_be)
.Case("aarch64_32", Triple::aarch64_32)
.Case("arc", Triple::arc) .Case("arc", Triple::arc)
.Case("arm64", Triple::aarch64) .Case("arm64", Triple::aarch64)
.Case("arm64_32", Triple::aarch64_32)
.Case("arm", Triple::arm) .Case("arm", Triple::arm)
.Case("armeb", Triple::armeb) .Case("armeb", Triple::armeb)
.Case("thumb", Triple::thumb) .Case("thumb", Triple::thumb)
.Case("thumbeb", Triple::thumbeb) .Case("thumbeb", Triple::thumbeb)
.Case("avr", Triple::avr) .Case("avr", Triple::avr)
.Case("msp430", Triple::msp430) .Case("msp430", Triple::msp430)
.Cases("mips", "mipseb", "mipsallegrex", "mipsisa32r6", .Cases("mips", "mipseb", "mipsallegrex", "mipsisa32r6",
"mipsr6", Triple::mips) "mipsr6", Triple::mips)
▲ Show 20 Lines • Show All 229 Lines • ▼ Show 20 Linesstatic StringRef getObjectFormatTypeName(Triple::ObjectFormatType Kind) {
} }
llvm_unreachable("unknown object format type"); llvm_unreachable("unknown object format type");
} }
static Triple::ObjectFormatType getDefaultFormat(const Triple &T) { static Triple::ObjectFormatType getDefaultFormat(const Triple &T) {
switch (T.getArch()) { switch (T.getArch()) {
case Triple::UnknownArch: case Triple::UnknownArch:
case Triple::aarch64: case Triple::aarch64:
case Triple::aarch64_32:
case Triple::arm: case Triple::arm:
case Triple::thumb: case Triple::thumb:
case Triple::x86: case Triple::x86:
case Triple::x86_64: case Triple::x86_64:
if (T.isOSDarwin()) if (T.isOSDarwin())
return Triple::MachO; return Triple::MachO;
else if (T.isOSWindows()) else if (T.isOSWindows())
return Triple::COFF; return Triple::COFF;
▲ Show 20 Lines • Show All 567 Lines • ▼ Show 20 Linesstatic unsigned getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
switch (Arch) { switch (Arch) {
case llvm::Triple::UnknownArch: case llvm::Triple::UnknownArch:
return 0; return 0;
case llvm::Triple::avr: case llvm::Triple::avr:
case llvm::Triple::msp430: case llvm::Triple::msp430:
return 16; return 16;
case llvm::Triple::aarch64_32:
case llvm::Triple::arc: case llvm::Triple::arc:
case llvm::Triple::arm: case llvm::Triple::arm:
case llvm::Triple::armeb: case llvm::Triple::armeb:
case llvm::Triple::hexagon: case llvm::Triple::hexagon:
case llvm::Triple::le32: case llvm::Triple::le32:
case llvm::Triple::mips: case llvm::Triple::mips:
case llvm::Triple::mipsel: case llvm::Triple::mipsel:
case llvm::Triple::nvptx: case llvm::Triple::nvptx:
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 LinesTriple Triple::get32BitArchVariant() const {
case Triple::bpfel: case Triple::bpfel:
case Triple::bpfeb: case Triple::bpfeb:
case Triple::msp430: case Triple::msp430:
case Triple::systemz: case Triple::systemz:
case Triple::ppc64le: case Triple::ppc64le:
T.setArch(UnknownArch); T.setArch(UnknownArch);
break; break;
case Triple::aarch64_32:
case Triple::amdil: case Triple::amdil:
case Triple::hsail: case Triple::hsail:
case Triple::spir: case Triple::spir:
case Triple::arc: case Triple::arc:
case Triple::arm: case Triple::arm:
case Triple::armeb: case Triple::armeb:
case Triple::hexagon: case Triple::hexagon:
case Triple::kalimba: case Triple::kalimba:
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 LinesTriple Triple::get64BitArchVariant() const {
case Triple::sparcv9: case Triple::sparcv9:
case Triple::systemz: case Triple::systemz:
case Triple::x86_64: case Triple::x86_64:
case Triple::wasm64: case Triple::wasm64:
case Triple::renderscript64: case Triple::renderscript64:
// Already 64-bit. // Already 64-bit.
break; break;
case Triple::aarch64_32: T.setArch(Triple::aarch64); break;
case Triple::arm: T.setArch(Triple::aarch64); break; case Triple::arm: T.setArch(Triple::aarch64); break;
case Triple::armeb: T.setArch(Triple::aarch64_be); break; case Triple::armeb: T.setArch(Triple::aarch64_be); break;
case Triple::le32: T.setArch(Triple::le64); break; case Triple::le32: T.setArch(Triple::le64); break;
case Triple::mips: T.setArch(Triple::mips64); break; case Triple::mips: T.setArch(Triple::mips64); break;
case Triple::mipsel: T.setArch(Triple::mips64el); break; case Triple::mipsel: T.setArch(Triple::mips64el); break;
case Triple::nvptx: T.setArch(Triple::nvptx64); break; case Triple::nvptx: T.setArch(Triple::nvptx64); break;
case Triple::ppc: T.setArch(Triple::ppc64); break; case Triple::ppc: T.setArch(Triple::ppc64); break;
case Triple::sparc: T.setArch(Triple::sparcv9); break; case Triple::sparc: T.setArch(Triple::sparcv9); break;
▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Lines default:
llvm_unreachable("getLittleEndianArchVariant: unknown triple."); llvm_unreachable("getLittleEndianArchVariant: unknown triple.");
} }
return T; return T;
} }
bool Triple::isLittleEndian() const { bool Triple::isLittleEndian() const {
switch (getArch()) { switch (getArch()) {
case Triple::aarch64: case Triple::aarch64:
case Triple::aarch64_32:
case Triple::amdgcn: case Triple::amdgcn:
case Triple::amdil64: case Triple::amdil64:
case Triple::amdil: case Triple::amdil:
case Triple::arm: case Triple::arm:
case Triple::avr: case Triple::avr:
case Triple::bpfel: case Triple::bpfel:
case Triple::hexagon: case Triple::hexagon:
case Triple::hsail64: case Triple::hsail64:
▲ Show 20 Lines • Show All 127 Lines • Show Last 20 Lines

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

Show First 20 Lines • Show All 5,501 Lines • ▼ Show 20 Lines return ELFRefKind == AArch64MCExpr::VK_INVALID ||
DarwinRefKind == MCSymbolRefExpr::VK_None; DarwinRefKind == MCSymbolRefExpr::VK_None;
} }
/// Force static initialization. /// Force static initialization.
extern "C" void LLVMInitializeAArch64AsmParser() { extern "C" void LLVMInitializeAArch64AsmParser() {
RegisterMCAsmParser<AArch64AsmParser> X(getTheAArch64leTarget()); RegisterMCAsmParser<AArch64AsmParser> X(getTheAArch64leTarget());
RegisterMCAsmParser<AArch64AsmParser> Y(getTheAArch64beTarget()); RegisterMCAsmParser<AArch64AsmParser> Y(getTheAArch64beTarget());
RegisterMCAsmParser<AArch64AsmParser> Z(getTheARM64Target()); RegisterMCAsmParser<AArch64AsmParser> Z(getTheARM64Target());
RegisterMCAsmParser<AArch64AsmParser> W(getTheARM64_32Target());
RegisterMCAsmParser<AArch64AsmParser> V(getTheAArch64_32Target());
} }
#define GET_REGISTER_MATCHER #define GET_REGISTER_MATCHER
#define GET_SUBTARGET_FEATURE_NAME #define GET_SUBTARGET_FEATURE_NAME
#define GET_MATCHER_IMPLEMENTATION #define GET_MATCHER_IMPLEMENTATION
#define GET_MNEMONIC_SPELL_CHECKER #define GET_MNEMONIC_SPELL_CHECKER
#include "AArch64GenAsmMatcher.inc" #include "AArch64GenAsmMatcher.inc"
▲ Show 20 Lines • Show All 230 Lines • Show Last 20 Lines

llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

Show First 20 Lines • Show All 280 Lines • ▼ Show 20 Linesextern "C" void LLVMInitializeAArch64Disassembler() {
TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(), TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(),
createAArch64Disassembler); createAArch64Disassembler);
TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(), TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(),
createAArch64Disassembler); createAArch64Disassembler);
TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(), TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(),
createAArch64ExternalSymbolizer); createAArch64ExternalSymbolizer);
TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(), TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(),
createAArch64ExternalSymbolizer); createAArch64ExternalSymbolizer);
TargetRegistry::RegisterMCDisassembler(getTheAArch64_32Target(),
createAArch64Disassembler);
TargetRegistry::RegisterMCSymbolizer(getTheAArch64_32Target(),
createAArch64ExternalSymbolizer);
TargetRegistry::RegisterMCDisassembler(getTheARM64Target(), TargetRegistry::RegisterMCDisassembler(getTheARM64Target(),
createAArch64Disassembler); createAArch64Disassembler);
TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(), TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(),
createAArch64ExternalSymbolizer); createAArch64ExternalSymbolizer);
TargetRegistry::RegisterMCDisassembler(getTheARM64_32Target(),
createAArch64Disassembler);
TargetRegistry::RegisterMCSymbolizer(getTheARM64_32Target(),
createAArch64ExternalSymbolizer);
} }
static const unsigned FPR128DecoderTable[] = { static const unsigned FPR128DecoderTable[] = {
AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
▲ Show 20 Lines • Show All 1,547 Lines • Show Last 20 Lines

llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp

Show First 20 Lines • Show All 506 Lines • ▼ Show 20 Linesenum CompactUnwindEncodings {
UNWIND_ARM64_FRAME_D14_D15_PAIR = 0x00000800 UNWIND_ARM64_FRAME_D14_D15_PAIR = 0x00000800
}; };
} // end CU namespace } // end CU namespace
// FIXME: This should be in a separate file. // FIXME: This should be in a separate file.
class DarwinAArch64AsmBackend : public AArch64AsmBackend { class DarwinAArch64AsmBackend : public AArch64AsmBackend {
const MCRegisterInfo &MRI; const MCRegisterInfo &MRI;
bool IsILP32;
/// Encode compact unwind stack adjustment for frameless functions. /// Encode compact unwind stack adjustment for frameless functions.
/// See UNWIND_ARM64_FRAMELESS_STACK_SIZE_MASK in compact_unwind_encoding.h. /// See UNWIND_ARM64_FRAMELESS_STACK_SIZE_MASK in compact_unwind_encoding.h.
/// The stack size always needs to be 16 byte aligned. /// The stack size always needs to be 16 byte aligned.
uint32_t encodeStackAdjustment(uint32_t StackSize) const { uint32_t encodeStackAdjustment(uint32_t StackSize) const {
return (StackSize / 16) << 12; return (StackSize / 16) << 12;
} }
public: public:
DarwinAArch64AsmBackend(const Target &T, const Triple &TT, DarwinAArch64AsmBackend(const Target &T, const Triple &TT,
const MCRegisterInfo &MRI) const MCRegisterInfo &MRI, bool IsILP32)
: AArch64AsmBackend(T, TT, /*IsLittleEndian*/ true), MRI(MRI) {} : AArch64AsmBackend(T, TT, /*IsLittleEndian*/ true), MRI(MRI),
IsILP32(IsILP32) {}
std::unique_ptr<MCObjectTargetWriter> std::unique_ptr<MCObjectTargetWriter>
createObjectTargetWriter() const override { createObjectTargetWriter() const override {
if (IsILP32)
return createAArch64MachObjectWriter(
MachO::CPU_TYPE_ARM64_32, MachO::CPU_SUBTYPE_ARM64_32_V8, true);
else
return createAArch64MachObjectWriter(MachO::CPU_TYPE_ARM64, return createAArch64MachObjectWriter(MachO::CPU_TYPE_ARM64,
MachO::CPU_SUBTYPE_ARM64_ALL); MachO::CPU_SUBTYPE_ARM64_ALL, false);
} }
/// Generate the compact unwind encoding from the CFI directives. /// Generate the compact unwind encoding from the CFI directives.
uint32_t generateCompactUnwindEncoding( uint32_t generateCompactUnwindEncoding(
ArrayRef<MCCFIInstruction> Instrs) const override { ArrayRef<MCCFIInstruction> Instrs) const override {
if (Instrs.empty()) if (Instrs.empty())
return CU::UNWIND_ARM64_MODE_FRAMELESS; return CU::UNWIND_ARM64_MODE_FRAMELESS;
▲ Show 20 Lines • Show All 165 Lines • ▼ Show 20 Lines
}; };
} }
MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T, MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
const Triple &TheTriple = STI.getTargetTriple(); const Triple &TheTriple = STI.getTargetTriple();
if (TheTriple.isOSBinFormatMachO()) if (TheTriple.isOSBinFormatMachO()) {
return new DarwinAArch64AsmBackend(T, TheTriple, MRI); const bool IsILP32 = TheTriple.isArch32Bit();
return new DarwinAArch64AsmBackend(T, TheTriple, MRI, IsILP32);
}
if (TheTriple.isOSBinFormatCOFF()) if (TheTriple.isOSBinFormatCOFF())
return new COFFAArch64AsmBackend(T, TheTriple); return new COFFAArch64AsmBackend(T, TheTriple);
assert(TheTriple.isOSBinFormatELF() && "Invalid target"); assert(TheTriple.isOSBinFormatELF() && "Invalid target");
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
bool IsILP32 = Options.getABIName() == "ilp32"; bool IsILP32 = Options.getABIName() == "ilp32";
Show All 16 Lines

llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h

Show All 32 Lines
class StringRef; class StringRef;
class Target; class Target;
class Triple; class Triple;
class raw_ostream; class raw_ostream;
class raw_pwrite_stream; class raw_pwrite_stream;
Target &getTheAArch64leTarget(); Target &getTheAArch64leTarget();
Target &getTheAArch64beTarget(); Target &getTheAArch64beTarget();
Target &getTheAArch64_32Target();
Target &getTheARM64Target(); Target &getTheARM64Target();
Target &getTheARM64_32Target();
MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII, MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createAArch64leAsmBackend(const Target &T, MCAsmBackend *createAArch64leAsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
MCAsmBackend *createAArch64beAsmBackend(const Target &T, MCAsmBackend *createAArch64beAsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
std::unique_ptr<MCObjectTargetWriter> std::unique_ptr<MCObjectTargetWriter>
createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32); createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32);
std::unique_ptr<MCObjectTargetWriter> std::unique_ptr<MCObjectTargetWriter>
createAArch64MachObjectWriter(uint32_t CPUType, uint32_t CPUSubtype); createAArch64MachObjectWriter(uint32_t CPUType, uint32_t CPUSubtype,
bool IsILP32);
std::unique_ptr<MCObjectTargetWriter> createAArch64WinCOFFObjectWriter(); std::unique_ptr<MCObjectTargetWriter> createAArch64WinCOFFObjectWriter();
MCTargetStreamer *createAArch64AsmTargetStreamer(MCStreamer &S, MCTargetStreamer *createAArch64AsmTargetStreamer(MCStreamer &S,
formatted_raw_ostream &OS, formatted_raw_ostream &OS,
MCInstPrinter *InstPrint, MCInstPrinter *InstPrint,
bool isVerboseAsm); bool isVerboseAsm);
Show All 25 Lines

llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp

Show First 20 Lines • Show All 185 Lines • ▼ Show 20 Lines
static MCInstrAnalysis *createAArch64InstrAnalysis(const MCInstrInfo *Info) { static MCInstrAnalysis *createAArch64InstrAnalysis(const MCInstrInfo *Info) {
return new AArch64MCInstrAnalysis(Info); return new AArch64MCInstrAnalysis(Info);
} }
// Force static initialization. // Force static initialization.
extern "C" void LLVMInitializeAArch64TargetMC() { extern "C" void LLVMInitializeAArch64TargetMC() {
for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64beTarget(), for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64beTarget(),
&getTheARM64Target()}) { &getTheAArch64_32Target(), &getTheARM64Target(),
&getTheARM64_32Target()}) {
// Register the MC asm info. // Register the MC asm info.
RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo); RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo);
// Register the MC instruction info. // Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(*T, createAArch64MCInstrInfo); TargetRegistry::RegisterMCInstrInfo(*T, createAArch64MCInstrInfo);
// Register the MC register info. // Register the MC register info.
TargetRegistry::RegisterMCRegInfo(*T, createAArch64MCRegisterInfo); TargetRegistry::RegisterMCRegInfo(*T, createAArch64MCRegisterInfo);
Show All 19 Lines for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64beTarget(),
// Register the asm streamer. // Register the asm streamer.
TargetRegistry::RegisterAsmTargetStreamer(*T, TargetRegistry::RegisterAsmTargetStreamer(*T,
createAArch64AsmTargetStreamer); createAArch64AsmTargetStreamer);
// Register the MCInstPrinter. // Register the MCInstPrinter.
TargetRegistry::RegisterMCInstPrinter(*T, createAArch64MCInstPrinter); TargetRegistry::RegisterMCInstPrinter(*T, createAArch64MCInstPrinter);
} }
// Register the asm backend. // Register the asm backend.
for (Target *T : {&getTheAArch64leTarget(), &getTheARM64Target()}) for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64_32Target(),
&getTheARM64Target(), &getTheARM64_32Target()})
TargetRegistry::RegisterMCAsmBackend(*T, createAArch64leAsmBackend); TargetRegistry::RegisterMCAsmBackend(*T, createAArch64leAsmBackend);
TargetRegistry::RegisterMCAsmBackend(getTheAArch64beTarget(), TargetRegistry::RegisterMCAsmBackend(getTheAArch64beTarget(),
createAArch64beAsmBackend); createAArch64beAsmBackend);
} }

llvm/lib/Target/AArch64/MCTargetDesc/AArch64MachObjectWriter.cpp

Show All 31 Lines
namespace { namespace {
class AArch64MachObjectWriter : public MCMachObjectTargetWriter { class AArch64MachObjectWriter : public MCMachObjectTargetWriter {
bool getAArch64FixupKindMachOInfo(const MCFixup &Fixup, unsigned &RelocType, bool getAArch64FixupKindMachOInfo(const MCFixup &Fixup, unsigned &RelocType,
const MCSymbolRefExpr *Sym, const MCSymbolRefExpr *Sym,
unsigned &Log2Size, const MCAssembler &Asm); unsigned &Log2Size, const MCAssembler &Asm);
public: public:
AArch64MachObjectWriter(uint32_t CPUType, uint32_t CPUSubtype) AArch64MachObjectWriter(uint32_t CPUType, uint32_t CPUSubtype, bool IsILP32)
: MCMachObjectTargetWriter(true /* is64Bit */, CPUType, CPUSubtype) {} : MCMachObjectTargetWriter(!IsILP32 /* is64Bit */, CPUType, CPUSubtype) {}
void recordRelocation(MachObjectWriter *Writer, MCAssembler &Asm, void recordRelocation(MachObjectWriter *Writer, MCAssembler &Asm,
const MCAsmLayout &Layout, const MCFragment *Fragment, const MCAsmLayout &Layout, const MCFragment *Fragment,
const MCFixup &Fixup, MCValue Target, const MCFixup &Fixup, MCValue Target,
uint64_t &FixedValue) override; uint64_t &FixedValue) override;
}; };
} // end anonymous namespace } // end anonymous namespace
▲ Show 20 Lines • Show All 349 Lines • ▼ Show 20 Linesvoid AArch64MachObjectWriter::recordRelocation(
MachO::any_relocation_info MRE; MachO::any_relocation_info MRE;
MRE.r_word0 = FixupOffset; MRE.r_word0 = FixupOffset;
MRE.r_word1 = MRE.r_word1 =
(Index << 0) | (IsPCRel << 24) | (Log2Size << 25) | (Type << 28); (Index << 0) | (IsPCRel << 24) | (Log2Size << 25) | (Type << 28);
Writer->addRelocation(RelSymbol, Fragment->getParent(), MRE); Writer->addRelocation(RelSymbol, Fragment->getParent(), MRE);
} }
std::unique_ptr<MCObjectTargetWriter> std::unique_ptr<MCObjectTargetWriter>
llvm::createAArch64MachObjectWriter(uint32_t CPUType, uint32_t CPUSubtype) { llvm::createAArch64MachObjectWriter(uint32_t CPUType, uint32_t CPUSubtype,
return llvm::make_unique<AArch64MachObjectWriter>(CPUType, CPUSubtype); bool IsILP32) {
return llvm::make_unique<AArch64MachObjectWriter>(CPUType, CPUSubtype,
IsILP32);
} }

llvm/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp

Show All 12 Lines
Target &getTheAArch64leTarget() { Target &getTheAArch64leTarget() {
static Target TheAArch64leTarget; static Target TheAArch64leTarget;
return TheAArch64leTarget; return TheAArch64leTarget;
} }
Target &getTheAArch64beTarget() { Target &getTheAArch64beTarget() {
static Target TheAArch64beTarget; static Target TheAArch64beTarget;
return TheAArch64beTarget; return TheAArch64beTarget;
} }
Target &getTheAArch64_32Target() {
static Target TheAArch64leTarget;
return TheAArch64leTarget;
}
Target &getTheARM64Target() { Target &getTheARM64Target() {
static Target TheARM64Target; static Target TheARM64Target;
return TheARM64Target; return TheARM64Target;
} }
Target &getTheARM64_32Target() {
static Target TheARM64_32Target;
return TheARM64_32Target;
}
} // namespace llvm } // namespace llvm
extern "C" void LLVMInitializeAArch64TargetInfo() { extern "C" void LLVMInitializeAArch64TargetInfo() {
// Now register the "arm64" name for use with "-march". We don't want it to // Now register the "arm64" name for use with "-march". We don't want it to
// take possession of the Triple::aarch64 tag though. // take possession of the Triple::aarch64 tags though.
TargetRegistry::RegisterTarget(getTheARM64Target(), "arm64", TargetRegistry::RegisterTarget(getTheARM64Target(), "arm64",
"ARM64 (little endian)", "AArch64", "ARM64 (little endian)", "AArch64",
[](Triple::ArchType) { return false; }, true); [](Triple::ArchType) { return false; }, true);
TargetRegistry::RegisterTarget(getTheARM64_32Target(), "arm64_32",
"ARM64 (little endian ILP32)", "AArch64",
[](Triple::ArchType) { return false; }, true);
RegisterTarget<Triple::aarch64, /*HasJIT=*/true> Z( RegisterTarget<Triple::aarch64, /*HasJIT=*/true> Z(
getTheAArch64leTarget(), "aarch64", "AArch64 (little endian)", "AArch64"); getTheAArch64leTarget(), "aarch64", "AArch64 (little endian)", "AArch64");
RegisterTarget<Triple::aarch64_be, /*HasJIT=*/true> W( RegisterTarget<Triple::aarch64_be, /*HasJIT=*/true> W(
getTheAArch64beTarget(), "aarch64_be", "AArch64 (big endian)", "AArch64"); getTheAArch64beTarget(), "aarch64_be", "AArch64 (big endian)", "AArch64");
RegisterTarget<Triple::aarch64_32, /*HasJIT=*/true> X(
getTheAArch64_32Target(), "aarch64_32", "AArch64 (little endian ILP32)", "AArch64");
} }

llvm/test/Object/AArch64/nm-trivial-object-arm64_32.test

  • This file was added.
RUN: llvm-nm -arch arm64_32 %p/../Inputs/trivial-object-test.macho-arm64_32 \
RUN: | FileCheck %s
CHECK: 00000000 T _foo
CHECK: 00000000 t ltmp0

llvm/test/Object/Inputs/trivial-object-test.macho-arm64_32

  • This binary file was added.

llvm/test/tools/llvm-objdump/AArch64/Inputs/thread.macho-arm64_32

  • This binary file was added.

llvm/test/tools/llvm-objdump/AArch64/arm64_32.s

  • This file was added.
// RUN: llvm-mc -triple arm64_32-apple-watchos %s -filetype=obj -o %t
// RUN: llvm-objdump -macho -d %t | FileCheck %s
// CHECK: ldr x0, [x2]
ldr x0, [x2]

llvm/test/tools/llvm-objdump/AArch64/macho-print-thread-arm64_32.test

  • This file was added.
RUN: llvm-objdump -macho -private-headers %p/Inputs/thread.macho-arm64_32 | FileCheck %s
CHECK: Load command 0
CHECK: cmd LC_UNIXTHREAD
CHECK: cmdsize 288
CHECK: flavor ARM_THREAD_STATE64
CHECK: count ARM_THREAD_STATE64_COUNT
CHECK: x0 0x0000000000000000 x1 0x0000000000000000 x2 0x0000000000000000
CHECK: x3 0x0000000000000000 x4 0x0000000000000000 x5 0x0000000000000000
CHECK: x6 0x0000000000000000 x7 0x0000000000000000 x8 0x0000000000000000
CHECK: x9 0x0000000000000000 x10 0x0000000000000000 x11 0x0000000000000000
CHECK: x12 0x0000000000000000 x13 0x0000000000000000 x14 0x0000000000000000
CHECK: x15 0x0000000000000000 x16 0x0000000000000000 x17 0x0000000000000000
CHECK: x18 0x0000000000000000 x19 0x0000000000000000 x20 0x0000000000000000
CHECK: x21 0x0000000000000000 x22 0x0000000000000000 x23 0x0000000000000000
CHECK: x24 0x0000000000000000 x25 0x0000000000000000 x26 0x0000000000000000
CHECK: x27 0x0000000000000000 x28 0x0000000000000000 fp 0x0000000000000000
CHECK: lr 0x0000000000000000 sp 0x0000000000000000 pc 0x0000000000007fd4
CHECK: cpsr 0x00000000

llvm/tools/llvm-objdump/MachODump.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 770 Lines • ▼ Show 20 Lines case MachO::CPU_TYPE_I386:
break; break;
case MachO::CPU_TYPE_X86_64: case MachO::CPU_TYPE_X86_64:
outs() << x86_64_r_types[r_type]; outs() << x86_64_r_types[r_type];
break; break;
case MachO::CPU_TYPE_ARM: case MachO::CPU_TYPE_ARM:
outs() << arm_r_types[r_type]; outs() << arm_r_types[r_type];
break; break;
case MachO::CPU_TYPE_ARM64: case MachO::CPU_TYPE_ARM64:
case MachO::CPU_TYPE_ARM64_32:
outs() << arm64_r_types[r_type]; outs() << arm64_r_types[r_type];
break; break;
default: default:
outs() << format("%-7u ", r_type); outs() << format("%-7u ", r_type);
} }
} }
static void PrintRLength(const uint64_t cputype, const unsigned r_type, static void PrintRLength(const uint64_t cputype, const unsigned r_type,
▲ Show 20 Lines • Show All 159 Lines • ▼ Show 20 Lines else {
// plain: extern & type & scattered // plain: extern & type & scattered
outs() << "False "; outs() << "False ";
PrintRType(cputype, r_type); PrintRType(cputype, r_type);
outs() << "False "; outs() << "False ";
// plain: symbolnum/value // plain: symbolnum/value
if (cputype == MachO::CPU_TYPE_ARM && r_type == MachO::ARM_RELOC_PAIR) if (cputype == MachO::CPU_TYPE_ARM && r_type == MachO::ARM_RELOC_PAIR)
outs() << format("other_half = 0x%04x\n", (unsigned int)r_address); outs() << format("other_half = 0x%04x\n", (unsigned int)r_address);
else if (cputype == MachO::CPU_TYPE_ARM64 && else if ((cputype == MachO::CPU_TYPE_ARM64 ||
cputype == MachO::CPU_TYPE_ARM64_32) &&
r_type == MachO::ARM64_RELOC_ADDEND) r_type == MachO::ARM64_RELOC_ADDEND)
outs() << format("addend = 0x%06x\n", (unsigned int)r_symbolnum); outs() << format("addend = 0x%06x\n", (unsigned int)r_symbolnum);
else { else {
outs() << format("%d ", r_symbolnum); outs() << format("%d ", r_symbolnum);
if (r_symbolnum == MachO::R_ABS) if (r_symbolnum == MachO::R_ABS)
outs() << "R_ABS\n"; outs() << "R_ABS\n";
else { else {
// in this case, r_symbolnum is actually a 1-based section number // in this case, r_symbolnum is actually a 1-based section number
▲ Show 20 Lines • Show All 1,072 Lines • ▼ Show 20 Lines case MachO::CPU_SUBTYPE_ARM64E:
outs() << " cputype CPU_TYPE_ARM64\n"; outs() << " cputype CPU_TYPE_ARM64\n";
outs() << " cpusubtype CPU_SUBTYPE_ARM64E\n"; outs() << " cpusubtype CPU_SUBTYPE_ARM64E\n";
break; break;
default: default:
printUnknownCPUType(cputype, cpusubtype); printUnknownCPUType(cputype, cpusubtype);
break; break;
} }
break; break;
case MachO::CPU_TYPE_ARM64_32:
switch (cpusubtype & ~MachO::CPU_SUBTYPE_MASK) {
case MachO::CPU_SUBTYPE_ARM64_32_V8:
outs() << " cputype CPU_TYPE_ARM64_32\n";
fhahnUnsubmitted
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Could we check for this in one of the tests?

fhahn: Could we check for this in one of the tests?
outs() << " cpusubtype CPU_SUBTYPE_ARM64_V8\n";
break;
default:
printUnknownCPUType(cputype, cpusubtype);
break;
}
break;
default: default:
printUnknownCPUType(cputype, cpusubtype); printUnknownCPUType(cputype, cpusubtype);
break; break;
} }
} }
static void printMachOUniversalHeaders(const object::MachOUniversalBinary *UB, static void printMachOUniversalHeaders(const object::MachOUniversalBinary *UB,
bool verbose) { bool verbose) {
▲ Show 20 Lines • Show All 6,062 Lines • ▼ Show 20 Lines case MachO::CPU_TYPE_ARM64:
case MachO::CPU_SUBTYPE_ARM64E: case MachO::CPU_SUBTYPE_ARM64E:
outs() << " E"; outs() << " E";
break; break;
default: default:
outs() << format(" %10d", cpusubtype & ~MachO::CPU_SUBTYPE_MASK); outs() << format(" %10d", cpusubtype & ~MachO::CPU_SUBTYPE_MASK);
break; break;
} }
break; break;
case MachO::CPU_TYPE_ARM64_32:
outs() << " ARM64_32";
switch (cpusubtype & ~MachO::CPU_SUBTYPE_MASK) {
case MachO::CPU_SUBTYPE_ARM64_32_V8:
fhahnUnsubmitted
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Could we check for this in one of the tests?

fhahn: Could we check for this in one of the tests?
outs() << " V8";
break;
default:
outs() << format(" %10d", cpusubtype & ~MachO::CPU_SUBTYPE_MASK);
break;
}
break;
case MachO::CPU_TYPE_POWERPC: case MachO::CPU_TYPE_POWERPC:
outs() << " PPC"; outs() << " PPC";
switch (cpusubtype & ~MachO::CPU_SUBTYPE_MASK) { switch (cpusubtype & ~MachO::CPU_SUBTYPE_MASK) {
case MachO::CPU_SUBTYPE_POWERPC_ALL: case MachO::CPU_SUBTYPE_POWERPC_ALL:
outs() << " ALL"; outs() << " ALL";
break; break;
default: default:
outs() << format(" %10d", cpusubtype & ~MachO::CPU_SUBTYPE_MASK); outs() << format(" %10d", cpusubtype & ~MachO::CPU_SUBTYPE_MASK);
▲ Show 20 Lines • Show All 1,547 Lines • ▼ Show 20 Lines while (begin < end) {
Print_arm_thread_state32_t(cpu32); Print_arm_thread_state32_t(cpu32);
} else { } else {
outs() << " flavor " << flavor << " (unknown)\n"; outs() << " flavor " << flavor << " (unknown)\n";
outs() << " count " << count << "\n"; outs() << " count " << count << "\n";
outs() << " state (unknown)\n"; outs() << " state (unknown)\n";
begin += count * sizeof(uint32_t); begin += count * sizeof(uint32_t);
} }
} }
} else if (cputype == MachO::CPU_TYPE_ARM64) { } else if (cputype == MachO::CPU_TYPE_ARM64 ||
cputype == MachO::CPU_TYPE_ARM64_32) {
while (begin < end) { while (begin < end) {
if (end - begin > (ptrdiff_t)sizeof(uint32_t)) { if (end - begin > (ptrdiff_t)sizeof(uint32_t)) {
memcpy((char *)&flavor, begin, sizeof(uint32_t)); memcpy((char *)&flavor, begin, sizeof(uint32_t));
begin += sizeof(uint32_t); begin += sizeof(uint32_t);
} else { } else {
flavor = 0; flavor = 0;
begin = end; begin = end;
} }
▲ Show 20 Lines • Show All 600 Lines • Show Last 20 Lines

llvm/unittests/ADT/TripleTest.cpp

Show First 20 Lines • Show All 546 Lines • ▼ Show 20 LinesTEST(TripleTest, ParsedIDs) {
EXPECT_EQ(Triple::Linux, T.getOS()); EXPECT_EQ(Triple::Linux, T.getOS());
EXPECT_EQ(Triple::GNUEABI, T.getEnvironment()); EXPECT_EQ(Triple::GNUEABI, T.getEnvironment());
T = Triple("aarch64-oe-linux"); T = Triple("aarch64-oe-linux");
EXPECT_EQ(Triple::aarch64, T.getArch()); EXPECT_EQ(Triple::aarch64, T.getArch());
EXPECT_EQ(Triple::OpenEmbedded, T.getVendor()); EXPECT_EQ(Triple::OpenEmbedded, T.getVendor());
EXPECT_EQ(Triple::Linux, T.getOS()); EXPECT_EQ(Triple::Linux, T.getOS());
EXPECT_EQ(Triple::UnknownEnvironment, T.getEnvironment()); EXPECT_EQ(Triple::UnknownEnvironment, T.getEnvironment());
EXPECT_TRUE(T.isArch64Bit());
T = Triple("arm64_32-apple-ios");
EXPECT_EQ(Triple::aarch64_32, T.getArch());
EXPECT_EQ(Triple::IOS, T.getOS());
EXPECT_EQ(Triple::UnknownEnvironment, T.getEnvironment());
EXPECT_TRUE(T.isArch32Bit());
T = Triple("huh"); T = Triple("huh");
EXPECT_EQ(Triple::UnknownArch, T.getArch()); EXPECT_EQ(Triple::UnknownArch, T.getArch());
} }
static std::string Join(StringRef A, StringRef B, StringRef C) { static std::string Join(StringRef A, StringRef B, StringRef C) {
std::string Str = A; std::string Str = A;
Str += '-'; Str += '-';
▲ Show 20 Lines • Show All 890 Lines • ▼ Show 20 Lines // THUMB
EXPECT_EQ(Triple::thumbeb, T.getArch()); EXPECT_EQ(Triple::thumbeb, T.getArch());
} }
// AARCH64 // AARCH64
{ {
Triple T = Triple("arm64"); Triple T = Triple("arm64");
EXPECT_EQ(Triple::aarch64, T.getArch()); EXPECT_EQ(Triple::aarch64, T.getArch());
} }
{ {
Triple T = Triple("arm64_32");
EXPECT_EQ(Triple::aarch64_32, T.getArch());
}
{
Triple T = Triple("aarch64"); Triple T = Triple("aarch64");
EXPECT_EQ(Triple::aarch64, T.getArch()); EXPECT_EQ(Triple::aarch64, T.getArch());
} }
{ {
Triple T = Triple("aarch64_be"); Triple T = Triple("aarch64_be");
EXPECT_EQ(Triple::aarch64_be, T.getArch()); EXPECT_EQ(Triple::aarch64_be, T.getArch());
} }
} }
} // end anonymous namespace } // end anonymous namespace

llvm/unittests/Support/TargetParserTest.cpp

Show First 20 Lines • Show All 652 Lines • ▼ Show 20 Lines if (i >= 4) {
EXPECT_EQ(ARM::ISAKind::THUMB, ARM::parseArchISA(thumb_1)); EXPECT_EQ(ARM::ISAKind::THUMB, ARM::parseArchISA(thumb_1));
EXPECT_EQ(ARM::ISAKind::THUMB, ARM::parseArchISA(thumb_2)); EXPECT_EQ(ARM::ISAKind::THUMB, ARM::parseArchISA(thumb_2));
EXPECT_EQ(ARM::ISAKind::THUMB, ARM::parseArchISA(thumb_3)); EXPECT_EQ(ARM::ISAKind::THUMB, ARM::parseArchISA(thumb_3));
} }
} }
EXPECT_EQ(ARM::EndianKind::LITTLE, ARM::parseArchEndian("aarch64")); EXPECT_EQ(ARM::EndianKind::LITTLE, ARM::parseArchEndian("aarch64"));
EXPECT_EQ(ARM::EndianKind::LITTLE, ARM::parseArchEndian("arm64_32"));
EXPECT_EQ(ARM::EndianKind::BIG, ARM::parseArchEndian("aarch64_be")); EXPECT_EQ(ARM::EndianKind::BIG, ARM::parseArchEndian("aarch64_be"));
EXPECT_EQ(ARM::ISAKind::AARCH64, ARM::parseArchISA("aarch64")); EXPECT_EQ(ARM::ISAKind::AARCH64, ARM::parseArchISA("aarch64"));
EXPECT_EQ(ARM::ISAKind::AARCH64, ARM::parseArchISA("aarch64_be")); EXPECT_EQ(ARM::ISAKind::AARCH64, ARM::parseArchISA("aarch64_be"));
EXPECT_EQ(ARM::ISAKind::AARCH64, ARM::parseArchISA("arm64")); EXPECT_EQ(ARM::ISAKind::AARCH64, ARM::parseArchISA("arm64"));
EXPECT_EQ(ARM::ISAKind::AARCH64, ARM::parseArchISA("arm64_be")); EXPECT_EQ(ARM::ISAKind::AARCH64, ARM::parseArchISA("arm64_be"));
EXPECT_EQ(ARM::ISAKind::AARCH64, ARM::parseArchISA("arm64_32"));
EXPECT_EQ(ARM::ISAKind::AARCH64, ARM::parseArchISA("aarch64_32"));
} }
TEST(TargetParserTest, ARMparseArchProfile) { TEST(TargetParserTest, ARMparseArchProfile) {
for (unsigned i = 0; i < array_lengthof(ARMArch); i++) { for (unsigned i = 0; i < array_lengthof(ARMArch); i++) {
switch (ARM::parseArch(ARMArch[i])) { switch (ARM::parseArch(ARMArch[i])) {
case ARM::ArchKind::ARMV6M: case ARM::ArchKind::ARMV6M:
case ARM::ArchKind::ARMV7M: case ARM::ArchKind::ARMV7M:
case ARM::ArchKind::ARMV7EM: case ARM::ArchKind::ARMV7EM:
▲ Show 20 Lines • Show All 388 Lines • Show Last 20 Lines