AMDGPU: Fix LCSSA phi lowering in SILowerI1Copies

[nhaehnle]

Summary

When an LCSSA phi survives through instruction selection, the pass
ends up removing that phi entirely because it is dominated by the
logic that does the lanemask merging.

This then used to trigger an assertion when processing a dependent
phi instruction.

Change-Id: Id4949719f8298062fe476a25718acccc109113b6

[dstuttard]

LGTM

[alex-t]

LGTM

[arsenm]

llvm/trunk/lib/Target/AMDGPU/SILowerI1Copies.cpp

508

I think PhiDefs would be a slightly better name

llvm/trunk/test/CodeGen/AMDGPU/si-lower-i1-copies.mir

12

With ever looming changes to how control flow is lowered, MIR tests including the control flow pseudos make me slightly nervous. Maybe it would be good to include the IR version as well and have them cross reference each other?

llvm/trunk/lib/Target/AMDGPU/SILowerI1Copies.cpp

 void SILowerI1Copies::lowerPhis() {
   MachineSSAUpdater SSAUpdater(*MF);
   LoopFinder LF(*DT, *PDT);
   PhiIncomingAnalysis PIA(*PDT);
   SmallVector<MachineInstr *, 4> DeadPhis;
   SmallVector<MachineBasicBlock *, 4> IncomingBlocks;
   SmallVector<unsigned, 4> IncomingRegs;
   SmallVector<unsigned, 4> IncomingUpdated;
+#ifndef NDEBUG
+  DenseSet<unsigned> PhiRegisters;
+#endif
 
   for (MachineBasicBlock &MBB : *MF) {
     LF.initialize(MBB);
 
     for (MachineInstr &MI : MBB.phis()) {
       unsigned DstReg = MI.getOperand(0).getReg();
       if (MRI->getRegClass(DstReg) != &AMDGPU::VReg_1RegClass)
         continue;
for (MachineInstr &MI : MBB.phis()) {
 
         if (IncomingDef->getOpcode() == AMDGPU::COPY) {
           IncomingReg = IncomingDef->getOperand(1).getReg();
           assert(isLaneMaskReg(IncomingReg));
           assert(!IncomingDef->getOperand(1).getSubReg());
         } else if (IncomingDef->getOpcode() == AMDGPU::IMPLICIT_DEF) {
           continue;
         } else {
-          assert(IncomingDef->isPHI());
+          assert(IncomingDef->isPHI() || PhiRegisters.count(IncomingReg));
         }
 
         IncomingBlocks.push_back(IncomingMBB);
         IncomingRegs.push_back(IncomingReg);
       }
 
+#ifndef NDEBUG
+      PhiRegisters.insert(DstReg);
+#endif
+
       // Phis in a loop that are observed outside the loop receive a simple but
       // conservatively correct treatment.
       MachineBasicBlock *PostDomBound = &MBB;
       for (MachineInstr &Use : MRI->use_instructions(DstReg)) {
         PostDomBound =
             PDT->findNearestCommonDominator(PostDomBound, Use.getParent());
       }
 

llvm/trunk/test/CodeGen/AMDGPU/si-lower-i1-copies.mir

+# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=si-i1-copies -o - %s | FileCheck -check-prefixes=GCN %s
+
+# GCN-LABEL: name: lcssa_phi
+---
+name:              lcssa_phi
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    %0:sreg_64 = S_MOV_B64 0
+    %8:vreg_1 = IMPLICIT_DEF
+    %10:sreg_64 = IMPLICIT_DEF
+    %11:sreg_64 = SI_IF %10, %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.1
+
+  bb.1:
+    %1:sreg_64 = PHI %0, %bb.0, %3, %bb.1
+    %2:sreg_64 = IMPLICIT_DEF
+    %3:sreg_64 = SI_IF_BREAK %2, %1, implicit-def dead $scc
+    %4:sreg_64 = IMPLICIT_DEF
+    %5:vreg_1 = COPY %4
+    SI_LOOP %3, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.2
+
+  bb.2:
+    %6:vreg_1 = PHI %5, %bb.1
+    SI_END_CF %3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+
+  bb.3:
+    %7:vreg_1 = PHI %6, %bb.2, %8, %bb.0
+    SI_END_CF %11, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_ENDPGM 0
+
+...