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AMDGPU: Fix LCSSA phi lowering in SILowerI1Copies
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Authored by nhaehnle on Apr 23 2019, 3:38 AM.

Details

Summary

When an LCSSA phi survives through instruction selection, the pass
ends up removing that phi entirely because it is dominated by the
logic that does the lanemask merging.

This then used to trigger an assertion when processing a dependent
phi instruction.

Change-Id: Id4949719f8298062fe476a25718acccc109113b6

Diff Detail

Repository
rL LLVM

Event Timeline

nhaehnle created this revision.Apr 23 2019, 3:38 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 23 2019, 3:38 AM
Herald added subscribers: t-tye, yaxunl, wdng and 2 others. · View Herald Transcript
This revision is now accepted and ready to land.Apr 23 2019, 4:20 AM
alex-t accepted this revision.Apr 23 2019, 4:53 AM
alex-t added a subscriber: alex-t.

LGTM

This revision was automatically updated to reflect the committed changes.
arsenm added inline comments.Apr 23 2019, 6:20 AM
llvm/trunk/lib/Target/AMDGPU/SILowerI1Copies.cpp
508

I think PhiDefs would be a slightly better name

llvm/trunk/test/CodeGen/AMDGPU/si-lower-i1-copies.mir
12

With ever looming changes to how control flow is lowered, MIR tests including the control flow pseudos make me slightly nervous. Maybe it would be good to include the IR version as well and have them cross reference each other?