This is an archive of the discontinued LLVM Phabricator instance.

[X86] Use MOVQ for i64 atomic_stores when SSE2 is enabled
ClosedPublic

Authored by craig.topper on Apr 10 2019, 3:44 PM.

Details

Summary

If we have SSE2 we can use a MOVQ to store 64-bits and avoid falling back to a cmpxchg8b loop. If its a seq_cst store we need to insert an mfence after the store.

Diff Detail

Event Timeline

craig.topper created this revision.Apr 10 2019, 3:44 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 10 2019, 3:44 PM
craig.topper marked 2 inline comments as done.Apr 10 2019, 3:48 PM
craig.topper added inline comments.
llvm/test/CodeGen/X86/atomic-fp.ll
152

There is an extra stack temporary here due to type legalization of the bitcast from f64 to i64 being legalized as a stack store f64 and then two i32 loads. DAG combine was able to merge the loads probably using merge elts from consecutive loads to create a VZEXT_LOAD.

llvm/test/CodeGen/X86/atomic6432.ll
841

Not sure why we didn't merge consecutive loads here.

Update a another test I missed previously

Support seq_cst store by inserting an mfence after the store.

craig.topper retitled this revision from [X86] Use MOVQ for i64 non-seq_cst atomic_stores when SSE2 is enabled to [X86] Use MOVQ for i64 atomic_stores when SSE2 is enabled.Apr 10 2019, 10:40 PM
craig.topper edited the summary of this revision. (Show Details)
RKSimon added inline comments.Apr 11 2019, 1:36 AM
llvm/lib/Target/X86/X86ISelLowering.cpp
26230

cast<AtomicSDNode>(Op) should work ?

llvm/test/CodeGen/X86/atomic6432.ll
841
RKSimon added inline comments.Apr 11 2019, 2:54 AM
llvm/lib/Target/X86/X86ISelLowering.h
594

If we used MOVSD (f64 store) could we avoid needing this NodeType?

craig.topper marked an inline comment as done.Apr 11 2019, 11:25 AM
craig.topper added inline comments.
llvm/lib/Target/X86/X86ISelLowering.h
594

if we don't use a dedicated X86ISD opcode, then we have to use ISD::ATOMIC_STORE. TargetSelectinoDAG has this type constraint which says that the store value type is integer. Perhaps we can relax that, but I don't know if there is some code assuming this.

def SDTAtomicStore : SDTypeProfile<0, 2, [
  SDTCisPtrTy<0>, SDTCisInt<1>
]>;
def atomic_store     : SDNode<"ISD::ATOMIC_STORE", SDTAtomicStore,
                    [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
RKSimon accepted this revision.Apr 24 2019, 12:16 PM

LGTM

llvm/lib/Target/X86/X86ISelLowering.h
594

OK - please can you raise a bug about whether SDTCisInt<1> can be relaxed?

This revision is now accepted and ready to land.Apr 24 2019, 12:16 PM
This revision was automatically updated to reflect the committed changes.