[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.

[craig.topper]

Summary

This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes.

Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser.

[RKSimon]

llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp

1333

Worth doing a LLVM_FALLTHROUGH here?

[craig.topper]

llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp

1333

By hoisting Adder out of the switch and initializing to 0?

[RKSimon]

llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp

1333

Yeah - "OpcodeOffset" or something.......

[craig.topper]

Use LLVM_FALLTHROUGH in the encoder

[RKSimon]

LGTM

llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp

static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand,
   case ENCODING_RB:
   case ENCODING_RW:
   case ENCODING_RD:
   case ENCODING_RO:
   case ENCODING_Rv:
     translateRegister(mcInst, insn.opcodeRegister);
     return false;
   case ENCODING_CC:
-    mcInst.addOperand(MCOperand::createImm(insn.immediates[0]));
+    mcInst.addOperand(MCOperand::createImm(insn.immediates[1]));
     return false;
   case ENCODING_FP:
     translateFPRegister(mcInst, insn.modRM & 7);
     return false;
   case ENCODING_VVVV:
     translateRegister(mcInst, insn.vvvv);
     return false;
   case ENCODING_DUP:

llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp

case ENCODING_RO:
       if (readOpcodeRegister(insn, 8))
         return -1;
       break;
     case ENCODING_Rv:
       if (readOpcodeRegister(insn, 0))
         return -1;
       break;
     case ENCODING_CC:
-      insn->immediates[0] = insn->opcode & 0xf;
+      insn->immediates[1] = insn->opcode & 0xf;
       break;
     case ENCODING_FP:
       break;
     case ENCODING_VVVV:
       needVVVV = 0; /* Mark that we have found a VVVV operand. */
       if (!hasVVVV)
         return -1;
       if (insn->mode != MODE_64BIT)

llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp

 };
 } // end anonymous namespace
 
 static unsigned getRelaxedOpcodeBranch(const MCInst &Inst, bool is16BitMode) {
   unsigned Op = Inst.getOpcode();
   switch (Op) {
   default:
     return Op;
-  case X86::JAE_1:
-    return (is16BitMode) ? X86::JAE_2 : X86::JAE_4;
-  case X86::JA_1:
-    return (is16BitMode) ? X86::JA_2 : X86::JA_4;
-  case X86::JBE_1:
-    return (is16BitMode) ? X86::JBE_2 : X86::JBE_4;
-  case X86::JB_1:
-    return (is16BitMode) ? X86::JB_2 : X86::JB_4;
-  case X86::JE_1:
-    return (is16BitMode) ? X86::JE_2 : X86::JE_4;
-  case X86::JGE_1:
-    return (is16BitMode) ? X86::JGE_2 : X86::JGE_4;
-  case X86::JG_1:
-    return (is16BitMode) ? X86::JG_2 : X86::JG_4;
-  case X86::JLE_1:
-    return (is16BitMode) ? X86::JLE_2 : X86::JLE_4;
-  case X86::JL_1:
-    return (is16BitMode) ? X86::JL_2 : X86::JL_4;
+  case X86::JCC_1:
+    return (is16BitMode) ? X86::JCC_2 : X86::JCC_4;
   case X86::JMP_1:
     return (is16BitMode) ? X86::JMP_2 : X86::JMP_4;
-  case X86::JNE_1:
-    return (is16BitMode) ? X86::JNE_2 : X86::JNE_4;
-  case X86::JNO_1:
-    return (is16BitMode) ? X86::JNO_2 : X86::JNO_4;
-  case X86::JNP_1:
-    return (is16BitMode) ? X86::JNP_2 : X86::JNP_4;
-  case X86::JNS_1:
-    return (is16BitMode) ? X86::JNS_2 : X86::JNS_4;
-  case X86::JO_1:
-    return (is16BitMode) ? X86::JO_2 : X86::JO_4;
-  case X86::JP_1:
-    return (is16BitMode) ? X86::JP_2 : X86::JP_4;
-  case X86::JS_1:
-    return (is16BitMode) ? X86::JS_2 : X86::JS_4;
   }
 }
 
 static unsigned getRelaxedOpcodeArith(const MCInst &Inst) {
   unsigned Op = Inst.getOpcode();
   switch (Op) {
   default:
     return Op;

llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h

enum : uint64_t {
     RawFrmImm8 = 7,
 
     /// RawFrmImm16 - This is used for CALL FAR instructions, which have two
     /// immediates, the first of which is a 16 or 32-bit immediate (specified by
     /// the imm encoding) and the second is a 16-bit fixed value.  In the AMD
     /// manual, this operand is described as pntr16:32 and pntr16:16
     RawFrmImm16 = 8,
 
+    /// AddCCFrm - This form is used for Jcc that encode the condition code
+    /// in the lower 4 bits of the opcode.
+    AddCCFrm = 9,
+
     /// MRM[0-7][rm] - These forms are used to represent instructions that use
     /// a Mod/RM byte, and use the middle field to hold extended opcode
     /// information.  In the intel manual these are represented as /0, /1, ...
     ///
 
     /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
     /// to specify a destination, which in this case is memory.
     ///
inline int getMemoryOperandNo(uint64_t TSFlags) {
     case X86II::RawFrm:
     case X86II::AddRegFrm:
     case X86II::RawFrmImm8:
     case X86II::RawFrmImm16:
     case X86II::RawFrmMemOffs:
     case X86II::RawFrmSrc:
     case X86II::RawFrmDst:
     case X86II::RawFrmDstSrc:
+    case X86II::AddCCFrm:
       return -1;
     case X86II::MRMDestMem:
       return 0;
     case X86II::MRMSrcMem:
       // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a
       // mask register.
       return 1 + HasVEX_4V + HasEVEX_K;
     case X86II::MRMSrcMem4VOp3:

llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp

encodeInstruction(const MCInst &MI, raw_ostream &OS,
   else
     EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
 
   uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
 
   if ((TSFlags & X86II::OpMapMask) == X86II::ThreeDNow)
     BaseOpcode = 0x0F;   // Weird 3DNow! encoding.
 
+  unsigned OpcodeOffset = 0;
+
   uint64_t Form = TSFlags & X86II::FormMask;
   switch (Form) {
   default: errs() << "FORM: " << Form << "\n";
     llvm_unreachable("Unknown FormMask value in X86MCCodeEmitter!");
   case X86II::Pseudo:
     llvm_unreachable("Pseudo instruction shouldn't be emitted");
   case X86II::RawFrmDstSrc: {
     unsigned siReg = MI.getOperand(1).getReg();
case X86II::RawFrmDst: {
     // Emit AdSize prefix as needed.
     if ((!is32BitMode(STI) && siReg == X86::EDI) ||
         (is32BitMode(STI) && siReg == X86::DI))
       EmitByte(0x67, CurByte, OS);
     ++CurOp; // Consume operand.
     EmitByte(BaseOpcode, CurByte, OS);
     break;
   }
-  case X86II::RawFrm: {
-    EmitByte(BaseOpcode, CurByte, OS);
+  case X86II::AddCCFrm: {
+    // This will be added to the opcode in the fallthrough.
+    OpcodeOffset = MI.getOperand(NumOps - 1).getImm();
+    assert(OpcodeOffset < 16 && "Unexpected opcode offset!");
+    --NumOps; // Drop the operand from the end.
+    LLVM_FALLTHROUGH;
+  case X86II::RawFrm:
+    EmitByte(BaseOpcode + OpcodeOffset, CurByte, OS);
 
     if (!is64BitMode(STI) || !isPCRel32Branch(MI))
       break;
 
     const MCOperand &Op = MI.getOperand(CurOp++);
     EmitImmediate(Op, MI.getLoc(), X86II::getSizeOfImm(TSFlags),
                   MCFixupKind(X86::reloc_branch_4byte_pcrel), CurByte, OS,
                   Fixups);
     break;
   }

llvm/lib/Target/X86/X86CmovConversion.cpp

SinkMBB->splice(SinkMBB->begin(), MBB,
                   std::next(MachineBasicBlock::iterator(LastCMOV)), MBB->end());
   SinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
 
   // Add the false and sink blocks as its successors.
   MBB->addSuccessor(FalseMBB);
   MBB->addSuccessor(SinkMBB);
 
   // Create the conditional branch instruction.
-  BuildMI(MBB, DL, TII->get(X86::GetCondBranchFromCond(CC))).addMBB(SinkMBB);
+  BuildMI(MBB, DL, TII->get(X86::JCC_1)).addMBB(SinkMBB).addImm(CC);
 
   // Add the sink block to the false block successors.
   FalseMBB->addSuccessor(SinkMBB);
 
   MachineInstrBuilder MIB;
   MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
   MachineBasicBlock::iterator MIItEnd =
       std::next(MachineBasicBlock::iterator(LastCMOV));

llvm/lib/Target/X86/X86CondBrFolding.cpp

 // Also update the MBBInfo for MBB.
 void X86CondBrFolding::replaceBrDest(MachineBasicBlock *MBB,
                                      MachineBasicBlock *OrigDest,
                                      MachineBasicBlock *NewDest) {
   TargetMBBInfo *MBBInfo = getMBBInfo(MBB);
   MachineInstr *BrMI;
   if (MBBInfo->TBB == OrigDest) {
     BrMI = MBBInfo->BrInstr;
-    unsigned JNCC = GetCondBranchFromCond(MBBInfo->BranchCode);
     MachineInstrBuilder MIB =
-        BuildMI(*MBB, BrMI, MBB->findDebugLoc(BrMI), TII->get(JNCC))
-            .addMBB(NewDest);
+        BuildMI(*MBB, BrMI, MBB->findDebugLoc(BrMI), TII->get(X86::JCC_1))
+            .addMBB(NewDest).addImm(MBBInfo->BranchCode);
     MBBInfo->TBB = NewDest;
     MBBInfo->BrInstr = MIB.getInstr();
   } else { // Should be the unconditional jump stmt.
     MachineBasicBlock::iterator UncondBrI = findUncondBrI(MBB);
     BuildMI(*MBB, UncondBrI, MBB->findDebugLoc(UncondBrI), TII->get(X86::JMP_1))
         .addMBB(NewDest);
     MBBInfo->FBB = NewDest;
     BrMI = &*UncondBrI;

 void X86CondBrFolding::fixupModifiedCond(MachineBasicBlock *MBB) {
   TargetMBBInfo *MBBInfo = getMBBInfo(MBB);
   if (!MBBInfo->Modified)
     return;
 
   MachineInstr *BrMI = MBBInfo->BrInstr;
   X86::CondCode CC = MBBInfo->BranchCode;
   MachineInstrBuilder MIB = BuildMI(*MBB, BrMI, MBB->findDebugLoc(BrMI),
-                                    TII->get(GetCondBranchFromCond(CC)))
-                                .addMBB(MBBInfo->TBB);
+                                    TII->get(X86::JCC_1))
+                                .addMBB(MBBInfo->TBB).addImm(CC);
   BrMI->eraseFromParent();
   MBBInfo->BrInstr = MIB.getInstr();
 
   MachineBasicBlock::iterator UncondBrI = findUncondBrI(MBB);
   BuildMI(*MBB, UncondBrI, MBB->findDebugLoc(UncondBrI), TII->get(X86::JMP_1))
       .addMBB(MBBInfo->FBB);
   MBB->erase(UncondBrI);
   MBBInfo->Modified = false;
case X86::COND_L:
       break;
     case X86::COND_G:
       NewCC = X86::COND_L;
       break;
     default:
       llvm_unreachable("unexpected condtional code.");
     }
     BuildMI(*RootMBB, UncondBrI, RootMBB->findDebugLoc(UncondBrI),
-            TII->get(GetCondBranchFromCond(NewCC)))
-        .addMBB(RootMBBInfo->FBB);
+            TII->get(X86::JCC_1))
+        .addMBB(RootMBBInfo->FBB).addImm(NewCC);
 
     // RootMBB: Jump to TargetMBB
     BuildMI(*RootMBB, UncondBrI, RootMBB->findDebugLoc(UncondBrI),
             TII->get(X86::JMP_1))
         .addMBB(TargetMBB);
     RootMBB->addSuccessor(TargetMBB);
     fixPHIsInSucc(TargetMBB, &MBB, RootMBB);
     RootMBB->erase(UncondBrI);
if (I->getOpcode() == X86::JMP_1) {
       if (FBB)
         return nullptr;
       FBB = I->getOperand(0).getMBB();
       continue;
     }
     if (I->isBranch()) {
       if (TBB)
         return nullptr;
-      CC = X86::getCondFromBranchOpc(I->getOpcode());
+      CC = X86::getCondFromBranch(*I);
       switch (CC) {
       default:
         return nullptr;
       case X86::COND_E:
       case X86::COND_L:
       case X86::COND_G:
       case X86::COND_NE:
       case X86::COND_LE:

llvm/lib/Target/X86/X86ExpandPseudo.cpp

void X86ExpandPseudo::ExpandICallBranchFunnel(
   };
 
   auto CreateMBB = [&]() {
     auto *NewMBB = MF->CreateMachineBasicBlock(BB);
     MBB->addSuccessor(NewMBB);
     return NewMBB;
   };
 
-  auto EmitCondJump = [&](unsigned Opcode, MachineBasicBlock *ThenMBB) {
-    BuildMI(*MBB, MBBI, DL, TII->get(Opcode)).addMBB(ThenMBB);
+  auto EmitCondJump = [&](unsigned CC, MachineBasicBlock *ThenMBB) {
+    BuildMI(*MBB, MBBI, DL, TII->get(X86::JCC_1)).addMBB(ThenMBB).addImm(CC);
 
     auto *ElseMBB = CreateMBB();
     MF->insert(InsPt, ElseMBB);
     MBB = ElseMBB;
     MBBI = MBB->end();
   };
 
-  auto EmitCondJumpTarget = [&](unsigned Opcode, unsigned Target) {
+  auto EmitCondJumpTarget = [&](unsigned CC, unsigned Target) {
     auto *ThenMBB = CreateMBB();
     TargetMBBs.push_back({ThenMBB, Target});
-    EmitCondJump(Opcode, ThenMBB);
+    EmitCondJump(CC, ThenMBB);
   };
 
   auto EmitTailCall = [&](unsigned Target) {
     BuildMI(*MBB, MBBI, DL, TII->get(X86::TAILJMPd64))
         .add(JTInst->getOperand(3 + 2 * Target));
   };
 
   std::function<void(unsigned, unsigned)> EmitBranchFunnel =
       [&](unsigned FirstTarget, unsigned NumTargets) {
     if (NumTargets == 1) {
       EmitTailCall(FirstTarget);
       return;
     }
 
     if (NumTargets == 2) {
       CmpTarget(FirstTarget + 1);
-      EmitCondJumpTarget(X86::JB_1, FirstTarget);
+      EmitCondJumpTarget(X86::COND_B, FirstTarget);
       EmitTailCall(FirstTarget + 1);
       return;
     }
 
     if (NumTargets < 6) {
       CmpTarget(FirstTarget + 1);
-      EmitCondJumpTarget(X86::JB_1, FirstTarget);
-      EmitCondJumpTarget(X86::JE_1, FirstTarget + 1);
+      EmitCondJumpTarget(X86::COND_B, FirstTarget);
+      EmitCondJumpTarget(X86::COND_E, FirstTarget + 1);
       EmitBranchFunnel(FirstTarget + 2, NumTargets - 2);
       return;
     }
 
     auto *ThenMBB = CreateMBB();
     CmpTarget(FirstTarget + (NumTargets / 2));
-    EmitCondJump(X86::JB_1, ThenMBB);
-    EmitCondJumpTarget(X86::JE_1, FirstTarget + (NumTargets / 2));
+    EmitCondJump(X86::COND_B, ThenMBB);
+    EmitCondJumpTarget(X86::COND_E, FirstTarget + (NumTargets / 2));
     EmitBranchFunnel(FirstTarget + (NumTargets / 2) + 1,
                   NumTargets - (NumTargets / 2) - 1);
 
     MF->insert(InsPt, ThenMBB);
     MBB = ThenMBB;
     MBBI = MBB->end();
     EmitBranchFunnel(FirstTarget, NumTargets / 2);
   };

llvm/lib/Target/X86/X86FastISel.cpp

if (CI->hasOneUse() && CI->getParent() == I->getParent()) {
         LLVM_FALLTHROUGH;
       case CmpInst::FCMP_UNE:
         NeedExtraBranch = true;
         Predicate = CmpInst::FCMP_ONE;
         break;
       }
 
       bool SwapArgs;
-      unsigned BranchOpc;
       std::tie(CC, SwapArgs) = X86::getX86ConditionCode(Predicate);
       assert(CC <= X86::LAST_VALID_COND && "Unexpected condition code.");
 
-      BranchOpc = X86::GetCondBranchFromCond(CC);
       if (SwapArgs)
         std::swap(CmpLHS, CmpRHS);
 
       // Emit a compare of the LHS and RHS, setting the flags.
       if (!X86FastEmitCompare(CmpLHS, CmpRHS, VT, CI->getDebugLoc()))
         return false;
 
-      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BranchOpc))
-        .addMBB(TrueMBB);
+      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JCC_1))
+        .addMBB(TrueMBB).addImm(CC);
 
       // X86 requires a second branch to handle UNE (and OEQ, which is mapped
       // to UNE above).
       if (NeedExtraBranch) {
-        BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JP_1))
-          .addMBB(TrueMBB);
+        BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JCC_1))
+          .addMBB(TrueMBB).addImm(X86::COND_P);
       }
 
       finishCondBranch(BI->getParent(), TrueMBB, FalseMBB);
       return true;
     }
   } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
     // Handle things like "%cond = trunc i32 %X to i1 / br i1 %cond", which
     // typically happen for _Bool and C++ bools.
if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
       }
       if (TestOpc) {
         unsigned OpReg = getRegForValue(TI->getOperand(0));
         if (OpReg == 0) return false;
 
         BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TestOpc))
           .addReg(OpReg).addImm(1);
 
-        unsigned JmpOpc = X86::JNE_1;
+        unsigned JmpCond = X86::COND_NE;
         if (FuncInfo.MBB->isLayoutSuccessor(TrueMBB)) {
           std::swap(TrueMBB, FalseMBB);
-          JmpOpc = X86::JE_1;
+          JmpCond = X86::COND_E;
         }
 
-        BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(JmpOpc))
-          .addMBB(TrueMBB);
+        BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JCC_1))
+          .addMBB(TrueMBB).addImm(JmpCond);
 
         finishCondBranch(BI->getParent(), TrueMBB, FalseMBB);
         return true;
       }
     }
   } else if (foldX86XALUIntrinsic(CC, BI, BI->getCondition())) {
     // Fake request the condition, otherwise the intrinsic might be completely
     // optimized away.
     unsigned TmpReg = getRegForValue(BI->getCondition());
     if (TmpReg == 0)
       return false;
 
-    unsigned BranchOpc = X86::GetCondBranchFromCond(CC);
-
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BranchOpc))
-      .addMBB(TrueMBB);
+    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JCC_1))
+      .addMBB(TrueMBB).addImm(CC);
     finishCondBranch(BI->getParent(), TrueMBB, FalseMBB);
     return true;
   }
 
   // Otherwise do a clumsy setcc and re-test it.
   // Note that i1 essentially gets ANY_EXTEND'ed to i8 where it isn't used
   // in an explicit cast, so make sure to handle that correctly.
   unsigned OpReg = getRegForValue(BI->getCondition());
   if (OpReg == 0) return false;
 
   // In case OpReg is a K register, COPY to a GPR
   if (MRI.getRegClass(OpReg) == &X86::VK1RegClass) {
     unsigned KOpReg = OpReg;
     OpReg = createResultReg(&X86::GR32RegClass);
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
             TII.get(TargetOpcode::COPY), OpReg)
         .addReg(KOpReg);
     OpReg = fastEmitInst_extractsubreg(MVT::i8, OpReg, /*Kill=*/true,
                                        X86::sub_8bit);
   }
   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri))
       .addReg(OpReg)
       .addImm(1);
-  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JNE_1))
-    .addMBB(TrueMBB);
+  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JCC_1))
+    .addMBB(TrueMBB).addImm(X86::COND_NE);
   finishCondBranch(BI->getParent(), TrueMBB, FalseMBB);
   return true;
 }
 
 bool X86FastISel::X86SelectShift(const Instruction *I) {
   unsigned CReg = 0, OpReg = 0;
   const TargetRegisterClass *RC = nullptr;
   if (I->getType()->isIntegerTy(8)) {

llvm/lib/Target/X86/X86FlagsCopyLowering.cpp

static MachineBasicBlock &splitBlock(MachineBasicBlock &MBB,
                                      MachineInstr &SplitI,
                                      const X86InstrInfo &TII) {
   MachineFunction &MF = *MBB.getParent();
 
   assert(SplitI.getParent() == &MBB &&
          "Split instruction must be in the split block!");
   assert(SplitI.isBranch() &&
          "Only designed to split a tail of branch instructions!");
-  assert(X86::getCondFromBranchOpc(SplitI.getOpcode()) != X86::COND_INVALID &&
+  assert(X86::getCondFromBranch(SplitI) != X86::COND_INVALID &&
          "Must split on an actual jCC instruction!");
 
   // Dig out the previous instruction to the split point.
   MachineInstr &PrevI = *std::prev(SplitI.getIterator());
   assert(PrevI.isBranch() && "Must split after a branch!");
-  assert(X86::getCondFromBranchOpc(PrevI.getOpcode()) != X86::COND_INVALID &&
+  assert(X86::getCondFromBranch(PrevI) != X86::COND_INVALID &&
          "Must split after an actual jCC instruction!");
   assert(!std::prev(PrevI.getIterator())->isTerminator() &&
          "Must only have this one terminator prior to the split!");
 
   // Grab the one successor edge that will stay in `MBB`.
   MachineBasicBlock &UnsplitSucc = *PrevI.getOperand(0).getMBB();
 
   // Analyze the original block to see if we are actually splitting an edge
do {
         // Once we encounter a branch, the rest of the instructions must also be
         // branches. We can't rewrite in place here, so we handle them below.
         //
         // Note that we don't have to handle tail calls here, even conditional
         // tail calls, as those are not introduced into the X86 MI until post-RA
         // branch folding or black placement. As a consequence, we get to deal
         // with the simpler formulation of conditional branches followed by tail
         // calls.
-        if (X86::getCondFromBranchOpc(MI.getOpcode()) != X86::COND_INVALID) {
+        if (X86::getCondFromBranch(MI) != X86::COND_INVALID) {
           auto JmpIt = MI.getIterator();
           do {
             JmpIs.push_back(&*JmpIt);
             ++JmpIt;
           } while (JmpIt != UseMBB.instr_end() &&
-                   X86::getCondFromBranchOpc(JmpIt->getOpcode()) !=
+                   X86::getCondFromBranch(*JmpIt) !=
                        X86::COND_INVALID);
           break;
         }
 
         // Otherwise we can just rewrite in-place.
         if (X86::getCondFromCMov(MI) != X86::COND_INVALID) {
           rewriteCMov(*TestMBB, TestPos, TestLoc, MI, *FlagUse, CondRegs);
         } else if (X86::getCondFromSETCC(MI) != X86::COND_INVALID) {
void X86FlagsCopyLoweringPass::rewriteCMov(MachineBasicBlock &TestMBB,
   FlagUse.setIsKill(true);
   LLVM_DEBUG(dbgs() << "    fixed cmov: "; CMovI.dump());
 }
 
 void X86FlagsCopyLoweringPass::rewriteCondJmp(
     MachineBasicBlock &TestMBB, MachineBasicBlock::iterator TestPos,
     DebugLoc TestLoc, MachineInstr &JmpI, CondRegArray &CondRegs) {
   // First get the register containing this specific condition.
-  X86::CondCode Cond = X86::getCondFromBranchOpc(JmpI.getOpcode());
+  X86::CondCode Cond = X86::getCondFromBranch(JmpI);
   unsigned CondReg;
   bool Inverted;
   std::tie(CondReg, Inverted) =
       getCondOrInverseInReg(TestMBB, TestPos, TestLoc, Cond, CondRegs);
 
   MachineBasicBlock &JmpMBB = *JmpI.getParent();
 
   // Insert a direct test of the saved register.
   insertTest(JmpMBB, JmpI.getIterator(), JmpI.getDebugLoc(), CondReg);
 
   // Rewrite the jump to use the !ZF flag from the test, and kill its use of
   // flags afterward.
-  JmpI.setDesc(TII->get(
-      X86::GetCondBranchFromCond(Inverted ? X86::COND_E : X86::COND_NE)));
-  const int ImplicitEFLAGSOpIdx = 1;
-  JmpI.getOperand(ImplicitEFLAGSOpIdx).setIsKill(true);
+  JmpI.getOperand(1).setImm(Inverted ? X86::COND_E : X86::COND_NE);
+  JmpI.findRegisterUseOperand(X86::EFLAGS)->setIsKill(true);
   LLVM_DEBUG(dbgs() << "    fixed jCC: "; JmpI.dump());
 }
 
 void X86FlagsCopyLoweringPass::rewriteCopy(MachineInstr &MI,
                                            MachineOperand &FlagUse,
                                            MachineInstr &CopyDefI) {
   // Just replace this copy with the original copy def.
   MRI->replaceRegWith(MI.getOperand(0).getReg(),

llvm/lib/Target/X86/X86FrameLowering.cpp

void X86FrameLowering::emitStackProbeInline(MachineFunction &MF,
   BuildMI(&MBB, DL, TII.get(X86::MOV64rm), LimitReg)
       .addReg(0)
       .addImm(1)
       .addReg(0)
       .addImm(ThreadEnvironmentStackLimit)
       .addReg(X86::GS);
   BuildMI(&MBB, DL, TII.get(X86::CMP64rr)).addReg(FinalReg).addReg(LimitReg);
   // Jump if the desired stack pointer is at or above the stack limit.
-  BuildMI(&MBB, DL, TII.get(X86::JAE_1)).addMBB(ContinueMBB);
+  BuildMI(&MBB, DL, TII.get(X86::JCC_1)).addMBB(ContinueMBB).addImm(X86::COND_AE);
 
   // Add code to roundMBB to round the final stack pointer to a page boundary.
   RoundMBB->addLiveIn(FinalReg);
   BuildMI(RoundMBB, DL, TII.get(X86::AND64ri32), RoundedReg)
       .addReg(FinalReg)
       .addImm(PageMask);
   BuildMI(RoundMBB, DL, TII.get(X86::JMP_1)).addMBB(LoopMBB);
 
BuildMI(LoopMBB, DL, TII.get(X86::MOV8mi))
       .addImm(0)
       .addReg(0)
       .addImm(0);
 
   LoopMBB->addLiveIn(RoundedReg);
   BuildMI(LoopMBB, DL, TII.get(X86::CMP64rr))
       .addReg(RoundedReg)
       .addReg(ProbeReg);
-  BuildMI(LoopMBB, DL, TII.get(X86::JNE_1)).addMBB(LoopMBB);
+  BuildMI(LoopMBB, DL, TII.get(X86::JCC_1)).addMBB(LoopMBB).addImm(X86::COND_NE);
 
   MachineBasicBlock::iterator ContinueMBBI = ContinueMBB->getFirstNonPHI();
 
   // If in prolog, restore RDX and RCX.
   if (InProlog) {
     if (RCXShadowSlot) // It means we spilled RCX in the prologue.
       addRegOffset(BuildMI(*ContinueMBB, ContinueMBBI, DL,
                            TII.get(X86::MOV64rm), X86::RCX),
if (STI.isTargetLinux() || STI.isTargetWin32() || STI.isTargetWin64() ||
 
       if (SaveScratch2)
         BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
     }
   }
 
   // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
   // It jumps to normal execution of the function body.
-  BuildMI(checkMBB, DL, TII.get(X86::JA_1)).addMBB(&PrologueMBB);
+  BuildMI(checkMBB, DL, TII.get(X86::JCC_1)).addMBB(&PrologueMBB).addImm(X86::COND_A);
 
   // On 32 bit we first push the arguments size and then the frame size. On 64
   // bit, we pass the stack frame size in r10 and the argument size in r11.
   if (Is64Bit) {
     // Functions with nested arguments use R10, so it needs to be saved across
     // the call to _morestack
 
     const unsigned RegAX = IsLP64 ? X86::RAX : X86::EAX;
assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
            "HiPE prologue scratch register is live-in");
 
     // Create new MBB for StackCheck:
     addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
                  SPReg, false, -MaxStack);
     // SPLimitOffset is in a fixed heap location (pointed by BP).
     addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
                  .addReg(ScratchReg), PReg, false, SPLimitOffset);
-    BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_1)).addMBB(&PrologueMBB);
+    BuildMI(stackCheckMBB, DL, TII.get(X86::JCC_1)).addMBB(&PrologueMBB).addImm(X86::COND_AE);
 
     // Create new MBB for IncStack:
     BuildMI(incStackMBB, DL, TII.get(CALLop)).
       addExternalSymbol("inc_stack_0");
     addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
                  SPReg, false, -MaxStack);
     addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
                  .addReg(ScratchReg), PReg, false, SPLimitOffset);
-    BuildMI(incStackMBB, DL, TII.get(X86::JLE_1)).addMBB(incStackMBB);
+    BuildMI(incStackMBB, DL, TII.get(X86::JCC_1)).addMBB(incStackMBB).addImm(X86::COND_LE);
 
     stackCheckMBB->addSuccessor(&PrologueMBB, {99, 100});
     stackCheckMBB->addSuccessor(incStackMBB, {1, 100});
     incStackMBB->addSuccessor(&PrologueMBB, {99, 100});
     incStackMBB->addSuccessor(incStackMBB, {1, 100});
   }
 #ifdef EXPENSIVE_CHECKS
   MF.verify();

llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

bool X86DAGToDAGISel::isSExtAbsoluteSymbolRef(unsigned Width, SDNode *N) const {
   Optional<ConstantRange> CR = GA->getGlobal()->getAbsoluteSymbolRange();
   return CR && CR->getSignedMin().sge(-1ull << Width) &&
          CR->getSignedMax().slt(1ull << Width);
 }
 
 static X86::CondCode getCondFromNode(SDNode *N) {
   assert(N->isMachineOpcode() && "Unexpected node");
   X86::CondCode CC = X86::COND_INVALID;
-  if (CC == X86::COND_INVALID)
-    CC = X86::getCondFromBranchOpc(N->getMachineOpcode());
-  if (CC == X86::COND_INVALID) {
-    unsigned Opc = N->getMachineOpcode();
-    if (Opc == X86::SETCCr)
-      CC = static_cast<X86::CondCode>(N->getConstantOperandVal(0));
-    else if (Opc == X86::SETCCm)
-      CC = static_cast<X86::CondCode>(N->getConstantOperandVal(5));
-    else if (Opc == X86::CMOV16rr || Opc == X86::CMOV32rr ||
-             Opc == X86::CMOV64rr)
-      CC = static_cast<X86::CondCode>(N->getConstantOperandVal(2));
-    else if (Opc == X86::CMOV16rm || Opc == X86::CMOV32rm ||
-             Opc == X86::CMOV64rm)
-      CC = static_cast<X86::CondCode>(N->getConstantOperandVal(6));
-  }
+  if (Opc == X86::JCC_1)
+    CC = static_cast<X86::CondCode>(N->getConstantOperandVal(1));
+  else if (Opc == X86::SETCCr)
 
   return CC;
 }
 
 /// Test whether the given X86ISD::CMP node has any users that use a flag
 /// other than ZF.
 bool X86DAGToDAGISel::onlyUsesZeroFlag(SDValue Flags) const {
   // Examine each user of the node.

llvm/lib/Target/X86/X86ISelLowering.cpp

if (!UseGPOffset && !UseFPOffset) {
 
     // Check if there is enough room left to pull this argument.
     BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
       .addReg(OffsetReg)
       .addImm(MaxOffset + 8 - ArgSizeA8);
 
     // Branch to "overflowMBB" if offset >= max
     // Fall through to "offsetMBB" otherwise
-    BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
-      .addMBB(overflowMBB);
+    BuildMI(thisMBB, DL, TII->get(X86::JCC_1))
+      .addMBB(overflowMBB).addImm(X86::COND_AE);
   }
 
   // In offsetMBB, emit code to use the reg_save_area.
   if (offsetMBB) {
     assert(OffsetReg != 0);
 
     // Read the reg_save_area address.
     unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
MachineBasicBlock *X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
 
   unsigned CountReg = MI.getOperand(0).getReg();
   int64_t RegSaveFrameIndex = MI.getOperand(1).getImm();
   int64_t VarArgsFPOffset = MI.getOperand(2).getImm();
 
   if (!Subtarget.isCallingConvWin64(F->getFunction().getCallingConv())) {
     // If %al is 0, branch around the XMM save block.
     BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
-    BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
+    BuildMI(MBB, DL, TII->get(X86::JCC_1)).addMBB(EndMBB).addImm(X86::COND_E);
     MBB->addSuccessor(EndMBB);
   }
 
   // Make sure the last operand is EFLAGS, which gets clobbered by the branch
   // that was just emitted, but clearly shouldn't be "saved".
   assert((MI.getNumOperands() <= 3 ||
           !MI.getOperand(MI.getNumOperands() - 1).isReg() ||
           MI.getOperand(MI.getNumOperands() - 1).getReg() == X86::EFLAGS) &&
X86TargetLowering::EmitLoweredCascadedSelect(MachineInstr &FirstCMOV,
   FirstInsertedMBB->addSuccessor(SecondInsertedMBB);
   // The true block for the branch of FirstInsertedMBB.
   FirstInsertedMBB->addSuccessor(SinkMBB);
   // This is fallthrough.
   SecondInsertedMBB->addSuccessor(SinkMBB);
 
   // Create the conditional branch instructions.
   X86::CondCode FirstCC = X86::CondCode(FirstCMOV.getOperand(3).getImm());
-  unsigned Opc = X86::GetCondBranchFromCond(FirstCC);
-  BuildMI(ThisMBB, DL, TII->get(Opc)).addMBB(SinkMBB);
+  BuildMI(ThisMBB, DL, TII->get(X86::JCC_1)).addMBB(SinkMBB).addImm(FirstCC);
 
   X86::CondCode SecondCC =
       X86::CondCode(SecondCascadedCMOV.getOperand(3).getImm());
-  unsigned Opc2 = X86::GetCondBranchFromCond(SecondCC);
-  BuildMI(FirstInsertedMBB, DL, TII->get(Opc2)).addMBB(SinkMBB);
+  BuildMI(FirstInsertedMBB, DL, TII->get(X86::JCC_1)).addMBB(SinkMBB).addImm(SecondCC);
 
   //  SinkMBB:
   //   %Result = phi [ %FalseValue, SecondInsertedMBB ], [ %TrueValue, ThisMBB ]
   unsigned DestReg = FirstCMOV.getOperand(0).getReg();
   unsigned Op1Reg = FirstCMOV.getOperand(1).getReg();
   unsigned Op2Reg = FirstCMOV.getOperand(2).getReg();
   MachineInstrBuilder MIB =
       BuildMI(*SinkMBB, SinkMBB->begin(), DL, TII->get(X86::PHI), DestReg)
X86TargetLowering::EmitLoweredSelect(MachineInstr &MI,
   // Fallthrough block for ThisMBB.
   ThisMBB->addSuccessor(FalseMBB);
   // The true block target of the first (or only) branch is always a SinkMBB.
   ThisMBB->addSuccessor(SinkMBB);
   // Fallthrough block for FalseMBB.
   FalseMBB->addSuccessor(SinkMBB);
 
   // Create the conditional branch instruction.
-  unsigned Opc = X86::GetCondBranchFromCond(CC);
-  BuildMI(ThisMBB, DL, TII->get(Opc)).addMBB(SinkMBB);
+  BuildMI(ThisMBB, DL, TII->get(X86::JCC_1)).addMBB(SinkMBB).addImm(CC);
 
   //  SinkMBB:
   //   %Result = phi [ %FalseValue, FalseMBB ], [ %TrueValue, ThisMBB ]
   //  ...
   MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
   MachineBasicBlock::iterator MIItEnd =
       std::next(MachineBasicBlock::iterator(LastCMOV));
   createPHIsForCMOVsInSinkBB(MIItBegin, MIItEnd, ThisMBB, FalseMBB, SinkMBB);
X86TargetLowering::EmitLoweredSegAlloca(MachineInstr &MI,
   // Add code to the main basic block to check if the stack limit has been hit,
   // and if so, jump to mallocMBB otherwise to bumpMBB.
   BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
   BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
     .addReg(tmpSPVReg).addReg(sizeVReg);
   BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
     .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
     .addReg(SPLimitVReg);
-  BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
+  BuildMI(BB, DL, TII->get(X86::JCC_1)).addMBB(mallocMBB).addImm(X86::COND_G);
 
   // bumpMBB simply decreases the stack pointer, since we know the current
   // stacklet has enough space.
   BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
     .addReg(SPLimitVReg);
   BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
     .addReg(SPLimitVReg);
   BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
X86TargetLowering::emitLongJmpShadowStackFix(MachineInstr &MI,
   BuildMI(checkSspMBB, DL, TII->get(RdsspOpc), SSPCopyReg).addReg(ZReg);
 
   // Check whether the result of the SSP register is zero and jump directly
   // to the sink.
   unsigned TestRROpc = (PVT == MVT::i64) ? X86::TEST64rr : X86::TEST32rr;
   BuildMI(checkSspMBB, DL, TII->get(TestRROpc))
       .addReg(SSPCopyReg)
       .addReg(SSPCopyReg);
-  BuildMI(checkSspMBB, DL, TII->get(X86::JE_1)).addMBB(sinkMBB);
+  BuildMI(checkSspMBB, DL, TII->get(X86::JCC_1)).addMBB(sinkMBB).addImm(X86::COND_E);
   checkSspMBB->addSuccessor(sinkMBB);
   checkSspMBB->addSuccessor(fallMBB);
 
   // Reload the previously saved SSP register value.
   unsigned PrevSSPReg = MRI.createVirtualRegister(PtrRC);
   unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
   const int64_t SPPOffset = 3 * PVT.getStoreSize();
   MachineInstrBuilder MIB =
X86TargetLowering::emitLongJmpShadowStackFix(MachineInstr &MI,
   // Subtract the current SSP from the previous SSP.
   unsigned SspSubReg = MRI.createVirtualRegister(PtrRC);
   unsigned SubRROpc = (PVT == MVT::i64) ? X86::SUB64rr : X86::SUB32rr;
   BuildMI(fallMBB, DL, TII->get(SubRROpc), SspSubReg)
       .addReg(PrevSSPReg)
       .addReg(SSPCopyReg);
 
   // Jump to sink in case PrevSSPReg <= SSPCopyReg.
-  BuildMI(fallMBB, DL, TII->get(X86::JBE_1)).addMBB(sinkMBB);
+  BuildMI(fallMBB, DL, TII->get(X86::JCC_1)).addMBB(sinkMBB).addImm(X86::COND_BE);
   fallMBB->addSuccessor(sinkMBB);
   fallMBB->addSuccessor(fixShadowMBB);
 
   // Shift right by 2/3 for 32/64 because incssp multiplies the argument by 4/8.
   unsigned ShrRIOpc = (PVT == MVT::i64) ? X86::SHR64ri : X86::SHR32ri;
   unsigned Offset = (PVT == MVT::i64) ? 3 : 2;
   unsigned SspFirstShrReg = MRI.createVirtualRegister(PtrRC);
   BuildMI(fixShadowMBB, DL, TII->get(ShrRIOpc), SspFirstShrReg)
       .addReg(SspSubReg)
       .addImm(Offset);
 
   // Increase SSP when looking only on the lower 8 bits of the delta.
   unsigned IncsspOpc = (PVT == MVT::i64) ? X86::INCSSPQ : X86::INCSSPD;
   BuildMI(fixShadowMBB, DL, TII->get(IncsspOpc)).addReg(SspFirstShrReg);
 
   // Reset the lower 8 bits.
   unsigned SspSecondShrReg = MRI.createVirtualRegister(PtrRC);
   BuildMI(fixShadowMBB, DL, TII->get(ShrRIOpc), SspSecondShrReg)
       .addReg(SspFirstShrReg)
       .addImm(8);
 
   // Jump if the result of the shift is zero.
-  BuildMI(fixShadowMBB, DL, TII->get(X86::JE_1)).addMBB(sinkMBB);
+  BuildMI(fixShadowMBB, DL, TII->get(X86::JCC_1)).addMBB(sinkMBB).addImm(X86::COND_E);
   fixShadowMBB->addSuccessor(sinkMBB);
   fixShadowMBB->addSuccessor(fixShadowLoopPrepareMBB);
 
   // Do a single shift left.
   unsigned ShlR1Opc = (PVT == MVT::i64) ? X86::SHL64r1 : X86::SHL32r1;
   unsigned SspAfterShlReg = MRI.createVirtualRegister(PtrRC);
   BuildMI(fixShadowLoopPrepareMBB, DL, TII->get(ShlR1Opc), SspAfterShlReg)
       .addReg(SspSecondShrReg);
X86TargetLowering::emitLongJmpShadowStackFix(MachineInstr &MI,
   // Every iteration we increase the SSP by 128.
   BuildMI(fixShadowLoopMBB, DL, TII->get(IncsspOpc)).addReg(Value128InReg);
 
   // Every iteration we decrement the counter by 1.
   unsigned DecROpc = (PVT == MVT::i64) ? X86::DEC64r : X86::DEC32r;
   BuildMI(fixShadowLoopMBB, DL, TII->get(DecROpc), DecReg).addReg(CounterReg);
 
   // Jump if the counter is not zero yet.
-  BuildMI(fixShadowLoopMBB, DL, TII->get(X86::JNE_1)).addMBB(fixShadowLoopMBB);
+  BuildMI(fixShadowLoopMBB, DL, TII->get(X86::JCC_1)).addMBB(fixShadowLoopMBB).addImm(X86::COND_NE);
   fixShadowLoopMBB->addSuccessor(sinkMBB);
   fixShadowLoopMBB->addSuccessor(fixShadowLoopMBB);
 
   return sinkMBB;
 }
 
 MachineBasicBlock *
 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr &MI,
X86TargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI,
 
   // IReg is used as an index in a memory operand and therefore can't be SP
   unsigned IReg = MRI->createVirtualRegister(&X86::GR32_NOSPRegClass);
   addFrameReference(BuildMI(DispatchBB, DL, TII->get(X86::MOV32rm), IReg), FI,
                     Subtarget.is64Bit() ? 8 : 4);
   BuildMI(DispatchBB, DL, TII->get(X86::CMP32ri))
       .addReg(IReg)
       .addImm(LPadList.size());
-  BuildMI(DispatchBB, DL, TII->get(X86::JAE_1)).addMBB(TrapBB);
+  BuildMI(DispatchBB, DL, TII->get(X86::JCC_1)).addMBB(TrapBB).addImm(X86::COND_AE);
 
   if (Subtarget.is64Bit()) {
     unsigned BReg = MRI->createVirtualRegister(&X86::GR64RegClass);
     unsigned IReg64 = MRI->createVirtualRegister(&X86::GR64_NOSPRegClass);
 
     // leaq .LJTI0_0(%rip), BReg
     BuildMI(DispContBB, DL, TII->get(X86::LEA64r), BReg)
         .addReg(X86::RIP)

llvm/lib/Target/X86/X86InstrControl.td

let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in {
     def JMP_2 : Ii16PCRel<0xE9, RawFrm, (outs), (ins brtarget16:$dst),
                           "jmp\t$dst", []>, OpSize16;
     def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget32:$dst),
                           "jmp\t$dst", []>, OpSize32;
   }
 }
 
 // Conditional Branches.
-let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump] in {
-  multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
-    def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm,
-                       [(X86brcond bb:$dst, Cond, EFLAGS)]>;
-    let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in {
-      def _2 : Ii16PCRel<opc4, RawFrm, (outs), (ins brtarget16:$dst), asm,
+let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump],
+    isCodeGenOnly = 1, ForceDisassemble = 1 in {
+  def JCC_1 : Ii8PCRel <0x70, AddCCFrm, (outs),
+                        (ins brtarget8:$dst, ccode:$cond),
+                        "j${cond}\t$dst",
+                        [(X86brcond bb:$dst, imm:$cond, EFLAGS)]>;
+  let hasSideEffects = 0 in {
+    def JCC_2 : Ii16PCRel<0x80, AddCCFrm, (outs),
+                          (ins brtarget16:$dst, ccode:$cond),
+                          "j${cond}\t$dst",
                           []>, OpSize16, TB;
-      def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget32:$dst), asm,
+    def JCC_4 : Ii32PCRel<0x80, AddCCFrm, (outs),
+                          (ins brtarget32:$dst, ccode:$cond),
+                          "j${cond}\t$dst",
                           []>, TB, OpSize32;
-    }
-  }
-}
 
-defm JO  : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
-defm JNO : ICBr<0x71, 0x81, "jno\t$dst", X86_COND_NO>;
-defm JB  : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
-defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
-defm JE  : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
-defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
-defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
-defm JA  : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
-defm JS  : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
-defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
-defm JP  : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
-defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
-defm JL  : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
-defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
-defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
-defm JG  : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
+def : InstAlias<"jo\t$dst",  (JCC_1 brtarget8:$dst,  0), 0>;
+def : InstAlias<"jno\t$dst", (JCC_1 brtarget8:$dst,  1), 0>;
+def : InstAlias<"jb\t$dst",  (JCC_1 brtarget8:$dst,  2), 0>;
+def : InstAlias<"jae\t$dst", (JCC_1 brtarget8:$dst,  3), 0>;
+def : InstAlias<"je\t$dst",  (JCC_1 brtarget8:$dst,  4), 0>;
+def : InstAlias<"jne\t$dst", (JCC_1 brtarget8:$dst,  5), 0>;
+def : InstAlias<"jbe\t$dst", (JCC_1 brtarget8:$dst,  6), 0>;
+def : InstAlias<"ja\t$dst",  (JCC_1 brtarget8:$dst,  7), 0>;
+def : InstAlias<"js\t$dst",  (JCC_1 brtarget8:$dst,  8), 0>;
+def : InstAlias<"jns\t$dst", (JCC_1 brtarget8:$dst,  9), 0>;
+def : InstAlias<"jp\t$dst",  (JCC_1 brtarget8:$dst, 10), 0>;
+def : InstAlias<"jnp\t$dst", (JCC_1 brtarget8:$dst, 11), 0>;
+def : InstAlias<"jl\t$dst",  (JCC_1 brtarget8:$dst, 12), 0>;
+def : InstAlias<"jge\t$dst", (JCC_1 brtarget8:$dst, 13), 0>;
+def : InstAlias<"jle\t$dst", (JCC_1 brtarget8:$dst, 14), 0>;
+def : InstAlias<"jg\t$dst",  (JCC_1 brtarget8:$dst, 15), 0>;
 
 // jcx/jecx/jrcx instructions.
 let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in {
   // These are the 32-bit versions of this instruction for the asmparser.  In
   // 32-bit mode, the address size prefix is jcxz and the unprefixed version is
   // jecxz.
   let Uses = [CX] in
     def JCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),

llvm/lib/Target/X86/X86InstrFormats.td

 def RawFrm        : Format<1>;
 def AddRegFrm     : Format<2>;
 def RawFrmMemOffs : Format<3>;
 def RawFrmSrc     : Format<4>;
 def RawFrmDst     : Format<5>;
 def RawFrmDstSrc  : Format<6>;
 def RawFrmImm8    : Format<7>;
 def RawFrmImm16   : Format<8>;
+def AddCCFrm      : Format<9>;
 def MRMDestMem     : Format<32>;
 def MRMSrcMem      : Format<33>;
 def MRMSrcMem4VOp3 : Format<34>;
 def MRMSrcMemOp4   : Format<35>;
 def MRMSrcMemCC    : Format<36>;
 def MRMXmCC: Format<38>;
 def MRMXm  : Format<39>;
 def MRM0m  : Format<40>;  def MRM1m  : Format<41>;  def MRM2m  : Format<42>;

llvm/lib/Target/X86/X86InstrInfo.h

 
 namespace X86 {
 
 enum AsmComments {
   // For instr that was compressed from EVEX to VEX.
   AC_EVEX_2_VEX = MachineInstr::TAsmComments
 };
 
-// Turn condition code into conditional branch opcode.
-unsigned GetCondBranchFromCond(CondCode CC);
-
 /// Return a pair of condition code for the given predicate and whether
 /// the instruction operands should be swaped to match the condition code.
 std::pair<CondCode, bool> getX86ConditionCode(CmpInst::Predicate Predicate);
 
 /// Return a setcc opcode based on whether it has a memory operand.
 unsigned getSETOpc(bool HasMemoryOperand = false);
 
 /// Return a cmov opcode for the given register size in bytes, and operand type.
 unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand = false);
 
-// Turn jCC opcode into condition code.
-CondCode getCondFromBranchOpc(unsigned Opc);
+// Turn jCC instruction into condition code.
+CondCode getCondFromBranch(const MachineInstr &MI);
 
-// Turn setCC opcode into condition code.
+// Turn setCC instruction into condition code.
 CondCode getCondFromSETCC(const MachineInstr &MI);
 
-// Turn CMov opcode into condition code.
+// Turn CMov instruction into condition code.
 CondCode getCondFromCMov(const MachineInstr &MI);
 
 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
 /// e.g. turning COND_E to COND_NE.
 CondCode GetOppositeBranchCondition(CondCode CC);
 
 /// Get the VPCMP immediate for the given condition.
 unsigned getVPCMPImmForCond(ISD::CondCode CC);

llvm/lib/Target/X86/X86InstrInfo.cpp

if (X86II::isKMasked(Desc.TSFlags)) {
       return true;
     }
 
     return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
   }
   return false;
 }
 
-X86::CondCode X86::getCondFromBranchOpc(unsigned BrOpc) {
-  switch (BrOpc) {
+X86::CondCode X86::getCondFromBranch(const MachineInstr &MI) {
+  switch (MI.getOpcode()) {
   default: return X86::COND_INVALID;
-  case X86::JE_1:  return X86::COND_E;
-  case X86::JNE_1: return X86::COND_NE;
-  case X86::JL_1:  return X86::COND_L;
-  case X86::JLE_1: return X86::COND_LE;
-  case X86::JG_1:  return X86::COND_G;
-  case X86::JGE_1: return X86::COND_GE;
-  case X86::JB_1:  return X86::COND_B;
-  case X86::JBE_1: return X86::COND_BE;
-  case X86::JA_1:  return X86::COND_A;
-  case X86::JAE_1: return X86::COND_AE;
-  case X86::JS_1:  return X86::COND_S;
-  case X86::JNS_1: return X86::COND_NS;
-  case X86::JP_1:  return X86::COND_P;
-  case X86::JNP_1: return X86::COND_NP;
-  case X86::JO_1:  return X86::COND_O;
-  case X86::JNO_1: return X86::COND_NO;
+  case X86::JCC_1:
+    return static_cast<X86::CondCode>(
+        MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
   }
 }
 
 /// Return condition code of a SETCC opcode.
 X86::CondCode X86::getCondFromSETCC(const MachineInstr &MI) {
   switch (MI.getOpcode()) {
   default: return X86::COND_INVALID;
   case X86::SETCCr: case X86::SETCCm:
     return static_cast<X86::CondCode>(
         MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
   }
 }
 
 /// Return condition code of a CMov opcode.
 X86::CondCode X86::getCondFromCMov(const MachineInstr &MI) {
   switch (MI.getOpcode()) {
   default: return X86::COND_INVALID;
   case X86::CMOV16rr: case X86::CMOV32rr: case X86::CMOV64rr:
   case X86::CMOV16rm: case X86::CMOV32rm: case X86::CMOV64rm:
     return static_cast<X86::CondCode>(
         MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
   }
 }
 
-unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
-  switch (CC) {
-  default: llvm_unreachable("Illegal condition code!");
-  case X86::COND_E:  return X86::JE_1;
-  case X86::COND_NE: return X86::JNE_1;
-  case X86::COND_L:  return X86::JL_1;
-  case X86::COND_LE: return X86::JLE_1;
-  case X86::COND_G:  return X86::JG_1;
-  case X86::COND_GE: return X86::JGE_1;
-  case X86::COND_B:  return X86::JB_1;
-  case X86::COND_BE: return X86::JBE_1;
-  case X86::COND_A:  return X86::JA_1;
-  case X86::COND_AE: return X86::JAE_1;
-  case X86::COND_S:  return X86::JS_1;
-  case X86::COND_NS: return X86::JNS_1;
-  case X86::COND_P:  return X86::JP_1;
-  case X86::COND_NP: return X86::JNP_1;
-  case X86::COND_O:  return X86::JO_1;
-  case X86::COND_NO: return X86::JNO_1;
-  }
-}
-
 /// Return the inverse of the specified condition,
 /// e.g. turning COND_E to COND_NE.
 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
   switch (CC) {
   default: llvm_unreachable("Illegal condition code!");
   case X86::COND_E:  return X86::COND_NE;
   case X86::COND_NE: return X86::COND_E;
   case X86::COND_L:  return X86::COND_GE;
void X86InstrInfo::replaceBranchWithTailCall(
   MachineBasicBlock::iterator I = MBB.end();
   while (I != MBB.begin()) {
     --I;
     if (I->isDebugInstr())
       continue;
     if (!I->isBranch())
       assert(0 && "Can't find the branch to replace!");
 
-    X86::CondCode CC = X86::getCondFromBranchOpc(I->getOpcode());
+    X86::CondCode CC = X86::getCondFromBranch(*I);
     assert(BranchCond.size() == 1);
     if (CC != BranchCond[0].getImm())
       continue;
 
     break;
   }
 
   unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
if (I->getOpcode() == X86::JMP_1) {
       }
 
       // TBB is used to indicate the unconditional destination.
       TBB = I->getOperand(0).getMBB();
       continue;
     }
 
     // Handle conditional branches.
-    X86::CondCode BranchCode = X86::getCondFromBranchOpc(I->getOpcode());
+    X86::CondCode BranchCode = X86::getCondFromBranch(*I);
     if (BranchCode == X86::COND_INVALID)
       return true;  // Can't handle indirect branch.
 
     // In practice we should never have an undef eflags operand, if we do
     // abort here as we are not prepared to preserve the flag.
-    if (I->getOperand(1).isUndef())
+    if (I->findRegisterUseOperand(X86::EFLAGS)->isUndef())
       return true;
 
     // Working from the bottom, handle the first conditional branch.
     if (Cond.empty()) {
       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
       if (AllowModify && UnCondBrIter != MBB.end() &&
           MBB.isLayoutSuccessor(TargetBB)) {
         // If we can modify the code and it ends in something like:
if (Cond.empty()) {
         //     jnCC L2
         //   L1:
         //     ...
         //   L2:
         //
         // Which is a bit more efficient.
         // We conditionally jump to the fall-through block.
         BranchCode = GetOppositeBranchCondition(BranchCode);
-        unsigned JNCC = GetCondBranchFromCond(BranchCode);
         MachineBasicBlock::iterator OldInst = I;
 
-        BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
-          .addMBB(UnCondBrIter->getOperand(0).getMBB());
+        BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JCC_1))
+          .addMBB(UnCondBrIter->getOperand(0).getMBB())
+          .addImm(BranchCode);
         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
           .addMBB(TargetBB);
 
         OldInst->eraseFromParent();
         UnCondBrIter->eraseFromParent();
 
         // Restart the analysis.
         UnCondBrIter = MBB.end();
unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB,
   MachineBasicBlock::iterator I = MBB.end();
   unsigned Count = 0;
 
   while (I != MBB.begin()) {
     --I;
     if (I->isDebugInstr())
       continue;
     if (I->getOpcode() != X86::JMP_1 &&
-        X86::getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
+        X86::getCondFromBranch(*I) == X86::COND_INVALID)
       break;
     // Remove the branch.
     I->eraseFromParent();
     I = MBB.end();
     ++Count;
   }
 
   return Count;
unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
   bool FallThru = FBB == nullptr;
 
   // Conditional branch.
   unsigned Count = 0;
   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
   switch (CC) {
   case X86::COND_NE_OR_P:
     // Synthesize NE_OR_P with two branches.
-    BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
+    BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NE);
     ++Count;
-    BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
+    BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_P);
     ++Count;
     break;
   case X86::COND_E_AND_NP:
     // Use the next block of MBB as FBB if it is null.
     if (FBB == nullptr) {
       FBB = getFallThroughMBB(&MBB, TBB);
       assert(FBB && "MBB cannot be the last block in function when the false "
                     "body is a fall-through.");
     }
     // Synthesize COND_E_AND_NP with two branches.
-    BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(FBB);
+    BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(FBB).addImm(X86::COND_NE);
     ++Count;
-    BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
+    BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NP);
     ++Count;
     break;
   default: {
-    unsigned Opc = GetCondBranchFromCond(CC);
-    BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
+    BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(CC);
     ++Count;
   }
   }
   if (!FallThru) {
     // Two-way Conditional branch. Insert the second branch.
     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
     ++Count;
   }
for (++I; I != E; ++I) {
     if (!UseEFLAGS && !ModifyEFLAGS)
       continue;
 
     // EFLAGS is used by this instruction.
     X86::CondCode OldCC = X86::COND_INVALID;
     if (IsCmpZero || IsSwapped) {
       // We decode the condition code from opcode.
       if (Instr.isBranch())
-        OldCC = X86::getCondFromBranchOpc(Instr.getOpcode());
+        OldCC = X86::getCondFromBranch(Instr);
       else {
         OldCC = X86::getCondFromSETCC(Instr);
         if (OldCC == X86::COND_INVALID)
           OldCC = X86::getCondFromCMov(Instr);
       }
       if (OldCC == X86::COND_INVALID) return false;
     }
     X86::CondCode ReplacementCC = X86::COND_INVALID;
for (; i != e; ++i) {
     }
   }
   assert(i != e && "Unable to locate a def EFLAGS operand");
 
   CmpInstr.eraseFromParent();
 
   // Modify the condition code of instructions in OpsToUpdate.
   for (auto &Op : OpsToUpdate) {
-    if (Op.first->isBranch())
-      Op.first->setDesc(get(GetCondBranchFromCond(Op.second)));
-    else
-      Op.first->getOperand(Op.first->getDesc().getNumOperands() - 1)
-          .setImm(Op.second);
   }
   return true;
 }
 
 /// Try to remove the load by folding it to a register
 /// operand at the use. We fold the load instructions if load defines a virtual
 /// register, the virtual register is used once in the same BB, and the
 /// instructions in-between do not load or store, and have no side effects.

llvm/lib/Target/X86/X86InstructionSelector.cpp

bool X86InstructionSelector::selectCondBranch(MachineInstr &I,
 
   const unsigned CondReg = I.getOperand(0).getReg();
   MachineBasicBlock *DestMBB = I.getOperand(1).getMBB();
 
   MachineInstr &TestInst =
       *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::TEST8ri))
            .addReg(CondReg)
            .addImm(1);
-  BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::JNE_1))
-      .addMBB(DestMBB);
+  BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::JCC_1))
+      .addMBB(DestMBB).addImm(X86::COND_NE);
 
   constrainSelectedInstRegOperands(TestInst, TII, TRI, RBI);
 
   I.eraseFromParent();
   return true;
 }
 
 bool X86InstructionSelector::materializeFP(MachineInstr &I,

llvm/lib/Target/X86/X86MCInstLower.cpp

// instruction.
       unsigned Opcode;
     case X86::TAILJMPr:
       Opcode = X86::JMP32r;
       goto SetTailJmpOpcode;
     case X86::TAILJMPd:
     case X86::TAILJMPd64:
       Opcode = X86::JMP_1;
       goto SetTailJmpOpcode;
-    case X86::TAILJMPd_CC:
-    case X86::TAILJMPd64_CC:
-      Opcode = X86::GetCondBranchFromCond(
-          static_cast<X86::CondCode>(MI->getOperand(1).getImm()));
-      goto SetTailJmpOpcode;
 
     SetTailJmpOpcode:
       MCOperand Saved = OutMI.getOperand(0);
       OutMI = MCInst();
       OutMI.setOpcode(Opcode);
       OutMI.addOperand(Saved);
       break;
     }
 
+  case X86::TAILJMPd_CC:
+  case X86::TAILJMPd64_CC: {
+    MCOperand Saved = OutMI.getOperand(0);
+    MCOperand Saved2 = OutMI.getOperand(1);
+    OutMI = MCInst();
+    OutMI.setOpcode(X86::JCC_1);
+    OutMI.addOperand(Saved);
+    OutMI.addOperand(Saved2);
+    break;
+  }
+
   case X86::DEC16r:
   case X86::DEC32r:
   case X86::INC16r:
   case X86::INC32r:
     // If we aren't in 64-bit mode we can use the 1-byte inc/dec instructions.
     if (!AsmPrinter.getSubtarget().is64Bit()) {
       unsigned Opcode;
       switch (OutMI.getOpcode()) {

llvm/lib/Target/X86/X86MacroFusion.cpp

static FirstInstrKind classifyFirst(const MachineInstr &MI) {
   case X86::DEC32r:
   case X86::DEC64r:
   case X86::DEC8r:
     return FirstInstrKind::IncDec;
   }
 }
 
 static JumpKind classifySecond(const MachineInstr &MI) {
-  switch (MI.getOpcode()) {
+  X86::CondCode CC = X86::getCondFromBranch(MI);
+  if (CC == X86::COND_INVALID)
+    return JumpKind::Invalid;
+
+  switch (CC) {
   default:
     return JumpKind::Invalid;
-  case X86::JE_1:
-  case X86::JNE_1:
-  case X86::JL_1:
-  case X86::JLE_1:
-  case X86::JG_1:
-  case X86::JGE_1:
+  case X86::COND_E:
+  case X86::COND_NE:
+  case X86::COND_L:
+  case X86::COND_LE:
+  case X86::COND_G:
+  case X86::COND_GE:
     return JumpKind::ELG;
-  case X86::JB_1:
-  case X86::JBE_1:
-  case X86::JA_1:
-  case X86::JAE_1:
+  case X86::COND_B:
+  case X86::COND_BE:
+  case X86::COND_A:
+  case X86::COND_AE:
     return JumpKind::AB;
-  case X86::JS_1:
-  case X86::JNS_1:
-  case X86::JP_1:
-  case X86::JNP_1:
-  case X86::JO_1:
-  case X86::JNO_1:
+  case X86::COND_S:
+  case X86::COND_NS:
+  case X86::COND_P:
+  case X86::COND_NP:
+  case X86::COND_O:
+  case X86::COND_NO:
     return JumpKind::SPO;
   }
 }
 
 /// Check if the instr pair, FirstMI and SecondMI, should be fused
 /// together. Given SecondMI, when FirstMI is unspecified, then check if
 /// SecondMI may be part of a fused pair at all.
 static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,

llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp

for (MachineInstr &MI : llvm::reverse(MBB)) {
       // other unanalyzable "fallthrough" case. We model this as a nullptr for
       // the destination so we can still guard any conditional successors.
       // Consider code sequences like:
       // ```
       //   jCC L1
       //   jmpq *%rax
       // ```
       // We still want to harden the edge to `L1`.
-      if (X86::getCondFromBranchOpc(MI.getOpcode()) == X86::COND_INVALID) {
+      if (X86::getCondFromBranch(MI) == X86::COND_INVALID) {
         Info.CondBrs.clear();
         Info.UncondBr = &MI;
         continue;
       }
 
       // We have a vanilla conditional branch, add it to our list.
       Info.CondBrs.push_back(&MI);
     }
auto BuildCheckingBlockForSuccAndConds =
           PS->SSA.AddAvailableValue(&CheckingMBB, CurStateReg);
         };
 
     std::vector<X86::CondCode> UncondCodeSeq;
     for (auto *CondBr : CondBrs) {
       MachineBasicBlock &Succ = *CondBr->getOperand(0).getMBB();
       int &SuccCount = SuccCounts[&Succ];
 
-      X86::CondCode Cond = X86::getCondFromBranchOpc(CondBr->getOpcode());
+      X86::CondCode Cond = X86::getCondFromBranch(*CondBr);
       X86::CondCode InvCond = X86::GetOppositeBranchCondition(Cond);
       UncondCodeSeq.push_back(Cond);
 
       BuildCheckingBlockForSuccAndConds(MBB, Succ, SuccCount, CondBr, UncondBr,
                                         {InvCond});
 
       // Decrement the successor count now that we've split one of the edges.
       // We need to keep the count of edges to the successor accurate in order

llvm/test/CodeGen/MIR/X86/auto-successor.mir

 # RUN: llc -mtriple=x86_64-- -o - %s -run-pass=none -verify-machineinstrs -simplify-mir | FileCheck %s
 ---
 # We shouldn't need any explicit successor lists in these examples
 # CHECK-LABEL: name: func0
 # CHECK: bb.0:
 # CHECK-NOT: successors
-# CHECK: JE_1 %bb.1, implicit undef $eflags
+# CHECK: JCC_1 %bb.1, 4, implicit undef $eflags
 # CHECK: JMP_1 %bb.3
 # CHECK: bb.1:
 # CHECK-NOT: successors
 # CHECK: bb.2:
 # CHECK-NOT: successors
-# CHECK: JE_1 %bb.1, implicit undef $eflags
+# CHECK: JCC_1 %bb.1, 4, implicit undef $eflags
 # CHECK: bb.3:
 # CHECK: RETQ undef $eax
 name: func0
 body: |
   bb.0:
-    JE_1 %bb.1, implicit undef $eflags
+    JCC_1 %bb.1, 4, implicit undef $eflags
     JMP_1 %bb.3
 
   bb.1:
 
   bb.2:
-    JE_1 %bb.1, implicit undef $eflags
+    JCC_1 %bb.1, 4, implicit undef $eflags
 
   bb.3:
-    JE_1 %bb.4, implicit undef $eflags   ; condjump+fallthrough to same block
+    JCC_1 %bb.4, 4, implicit undef $eflags   ; condjump+fallthrough to same block
 
   bb.4:
     RETQ undef $eax
 ...
 ---
 # Some cases that need explicit successors:
 # CHECK-LABEL: name: func1
 name: func1
 body: |
   bb.0:
     ; CHECK: bb.0:
     ; CHECK: successors: %bb.3, %bb.1
     successors: %bb.3, %bb.1   ; different order than operands
-    JE_1 %bb.1, implicit undef $eflags
+    JCC_1 %bb.1, 4, implicit undef $eflags
     JMP_1 %bb.3
 
   bb.1:
     ; CHECK: bb.1:
     ; CHECK: successors: %bb.2, %bb.1
     successors: %bb.2, %bb.1   ; different order (fallthrough variant)
-    JE_1 %bb.1, implicit undef $eflags
+    JCC_1 %bb.1, 4, implicit undef $eflags
 
   bb.2:
     ; CHECK: bb.2:
     ; CHECK: successors: %bb.1(0x60000000), %bb.3(0x20000000)
     successors: %bb.1(3), %bb.3(1)  ; branch probabilities not normalized
-    JE_1 %bb.1, implicit undef $eflags
+    JCC_1 %bb.1, 4, implicit undef $eflags
 
   bb.3:
     ; CHECK: bb.3:
     ; CHECK: RETQ undef $eax
     RETQ undef $eax
 ...

llvm/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir

 liveins:
   - { reg: '$edi' }
 body: |
   bb.0.entry:
     successors: %bb.1.less, %bb.2.exit
     liveins: $edi 44
 
     CMP32ri8 $edi, 10, implicit-def $eflags
-    JG_1 %bb.2.exit, implicit killed $eflags
+    JCC_1 %bb.2.exit, 15, implicit killed $eflags
 
   ; CHECK: [[@LINE+1]]:8: basic block definition should be located at the start of the line
   less bb.1:
     $eax = MOV32r0 implicit-def dead $eflags
     RETQ killed $eax
 
   bb.2.exit:
     liveins: $edi
 
     $eax = COPY killed $edi
     RETQ killed $eax
 ...

llvm/test/CodeGen/MIR/X86/branch-folder-with-label.mir

bb.0.entry:
   
     frame-setup PUSH64r killed $rbx, implicit-def $rsp, implicit $rsp
     CFI_INSTRUCTION def_cfa_offset 16
     CFI_INSTRUCTION offset $rbx, -16
     renamable $rbx = COPY $rdi
     renamable $edi = MOV32rm $rdi, 1, $noreg, 0, $noreg :: (load 4 from %ir.out)
     CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !9
     TEST32rr renamable $eax, renamable $eax, implicit-def $eflags
-    JNS_1 %bb.2, implicit killed $eflags
-  ; CHECK: JS_1 %bb.2, implicit $eflags
+    JCC_1 %bb.2, 9, implicit killed $eflags
+  ; CHECK: JCC_1 %bb.2, 8, implicit $eflags
   
   bb.1:
     successors: %bb.3(0x80000000)
     liveins: $eax
   
     JMP_1 %bb.3
   
   bb.2.if.then1:
bb.0.entry:
     CFI_INSTRUCTION def_cfa_offset 32
     CFI_INSTRUCTION offset $rbx, -24
     CFI_INSTRUCTION offset $r14, -16
     renamable $rbx = COPY $rdi
     DBG_LABEL !20, debug-location !21
     renamable $rdi = LEA64r $rsp, 1, $noreg, 4, $noreg
     CALL64pcrel32 @baz, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !22
     TEST32rr renamable $eax, renamable $eax, implicit-def $eflags
-    JNS_1 %bb.2, implicit killed $eflags
-  ; CHECK: JS_1 %bb.5, implicit $eflags
+    JCC_1 %bb.2, 9, implicit killed $eflags
+  ; CHECK: JCC_1 %bb.5, 8, implicit $eflags
   
   bb.1:
     successors: %bb.5(0x80000000)
     liveins: $eax
   
     JMP_1 %bb.5
   
   bb.2:
     successors: %bb.6(0x80000000)
     liveins: $rbx
   
     renamable $r14 = LEA64r $rsp, 1, $noreg, 4, $noreg
     JMP_1 %bb.6
   
   bb.3.retry.loopexit:
     successors: %bb.4(0x04000000), %bb.6(0x7c000000)
     liveins: $rbx, $r14
   
     DBG_LABEL !20, debug-location !21
     $rdi = COPY renamable $r14, debug-location !22
     CALL64pcrel32 @baz, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !22
     TEST32rr renamable $eax, renamable $eax, implicit-def $eflags
-    JNS_1 %bb.6, implicit killed $eflags
+    JCC_1 %bb.6, 9, implicit killed $eflags
   
   bb.4:
     successors: %bb.5(0x80000000)
     liveins: $eax
   
   
   bb.5.if.then:
     liveins: $eax
   
     $rsp = frame-destroy ADD64ri8 $rsp, 8, implicit-def dead $eflags
     CFI_INSTRUCTION def_cfa_offset 24
     $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp
     CFI_INSTRUCTION def_cfa_offset 16
     $r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp
     CFI_INSTRUCTION def_cfa_offset 8
     RET 0, $eax
   
   bb.6.do.cond:
     successors: %bb.8(0x30000000), %bb.7(0x50000000)
     liveins: $rbx, $r14
   
     CMP32mi8 $rsp, 1, $noreg, 4, $noreg, 0, implicit-def $eflags :: (dereferenceable load 4 from %ir.idx)
-    JS_1 %bb.8, implicit killed $eflags
+    JCC_1 %bb.8, 8, implicit killed $eflags
     JMP_1 %bb.7
   
   bb.7.lor.rhs:
     successors: %bb.8(0x30000000), %bb.3(0x50000000)
     liveins: $rbx, $r14
   
     CMP32mi8 renamable $rbx, 1, $noreg, 0, $noreg, 0, implicit-def $eflags :: (load 4 from %ir.1)
-    JNE_1 %bb.3, implicit killed $eflags
+    JCC_1 %bb.3, 5, implicit killed $eflags
     JMP_1 %bb.8
   
   bb.8.do.body.backedge:
     successors: %bb.9(0x04000000), %bb.6(0x7c000000)
     liveins: $rbx, $r14
   
     $rdi = COPY renamable $r14, debug-location !22
     CALL64pcrel32 @baz, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !22
     TEST32rr renamable $eax, renamable $eax, implicit-def $eflags
-    JNS_1 %bb.6, implicit killed $eflags
+    JCC_1 %bb.6, 9, implicit killed $eflags
   
   bb.9:
     successors: %bb.5(0x80000000)
     liveins: $eax
   
     JMP_1 %bb.5
 
 ...

llvm/test/CodeGen/MIR/X86/branch-probabilities.mir

 # RUN: llc -o - %s -mtriple=x86_64-- -run-pass=none | FileCheck %s
 ---
 # Check that branch probabilities are printed correctly as hex numbers.
 # CHECK-LABEL: name: test
 # CHECK: bb.0:
 # CHECK-NEXT: successors: %bb.1(0x66666666), %bb.2(0x1999999a)
 name: test
 body: |
   bb.0:
     successors: %bb.1(4), %bb.2(1)
-    JE_1 %bb.2, implicit undef $eflags
+    JCC_1 %bb.2, 4, implicit undef $eflags
 
   bb.1:
     NOOP
 
   bb.2:
     RETQ undef $eax
 ...

llvm/test/CodeGen/MIR/X86/callee-saved-info.mir

bb.0.entry:
     $ebx = COPY $edi
     MOV32mr $rsp, 1, _, 12, _, $ebx
 
   bb.1.check:
     successors: %bb.2.loop, %bb.3.exit
     liveins: $ebx
 
     CMP32ri8 $ebx, 10, implicit-def $eflags
-    JG_1 %bb.3.exit, implicit killed $eflags
+    JCC_1 %bb.3.exit, 15, implicit killed $eflags
     JMP_1 %bb.2.loop
 
   bb.2.loop:
     successors: %bb.1.check
     liveins: $ebx
 
     $edi = MOV32rm $rsp, 1, _, 12, _
     CALL64pcrel32 @compute, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, implicit-def $eax

llvm/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir

 ...
 ---
 name:            foo
 body: |
   bb.0.entry:
     successors: %bb.1.less, %bb.2.exit
 
     CMP32ri8 $edi, 10, implicit-def $eflags
-  ; CHECK: [[@LINE+1]]:31: duplicate 'implicit' register flag
-    JG_1 %bb.2.exit, implicit implicit $eflags
+  ; CHECK: [[@LINE+1]]:36: duplicate 'implicit' register flag
+    JCC_1 %bb.2.exit, 15, implicit implicit $eflags
 
   bb.1.less:
     $eax = MOV32r0 implicit-def $eflags
     RETQ $eax
 
   bb.2.exit:
     $eax = COPY $edi
     RETQ $eax
 ...

llvm/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir

 liveins:
   - { reg: '$edi' }
 body: |
   ; CHECK: [[@LINE+1]]:3: expected a basic block definition before instructions
   successors: %bb.1.less, %bb.2.exit
     liveins: $edi 44
 
     CMP32ri8 $edi, 10, implicit-def $eflags
-    JG_1 %bb.2.exit, implicit killed $eflags
+    JCC_1 %bb.2.exit, 15, implicit killed $eflags
 
   bb.1.less:
     $eax = MOV32r0 implicit-def dead $eflags
     RETQ killed $eax
 
   bb.2.exit:
     liveins: $edi
 
     $eax = COPY killed $edi
     RETQ killed $eax
 ...

llvm/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir

 
 ...
 ---
 name:            foo
 body: |
   bb.0.entry:
     $eax = MOV32rm $rdi, 1, _, 0, _
     CMP32ri8 $eax, 10, implicit-def $eflags
-  ; CHECK: [[@LINE+1]]:35: missing implicit register operand 'implicit $eflags'
-    JG_1 %bb.2.exit, implicit $eax
+  ; CHECK: [[@LINE+1]]:40: missing implicit register operand 'implicit $eflags'
+    JCC_1 %bb.2.exit, 15, implicit $eax
 
   bb.1.less:
     $eax = MOV32r0 implicit-def $eflags
 
   bb.2.exit:
     RETQ $eax
 ...

llvm/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir

 
 ...
 ---
 name:            foo
 body: |
   bb.0.entry:
     $eax = MOV32rm $rdi, 1, _, 0, _
     CMP32ri8 $eax, 10, implicit-def $eflags
-  ; CHECK: [[@LINE+1]]:42: missing implicit register operand 'implicit $eflags'
-    JG_1 %bb.2.exit, implicit-def $eflags
+  ; CHECK: [[@LINE+1]]:47: missing implicit register operand 'implicit $eflags'
+    JCC_1 %bb.2.exit, 15, implicit-def $eflags
 
   bb.1.less:
     $eax = MOV32r0 implicit-def $eflags
 
   bb.2.exit:
     RETQ $eax
 ...

llvm/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir

 name:            foo
 body: |
   bb.0.entry:
   ; CHECK: [[@LINE+1]]:29: expected an integer literal after '('
     successors: %bb.1.less (_), %bb.2.exit(32)
     liveins: $edi
 
     CMP32ri8 $edi, 10, implicit-def $eflags
-    JG_1 %bb.2.exit, implicit killed $eflags
+    JCC_1 %bb.2.exit, 15, implicit killed $eflags
 
   bb.1.less:
     $eax = MOV32r0 implicit-def dead $eflags
     RETQ killed $eax
 
   bb.2.exit:
     liveins: $edi
 
     $eax = COPY killed $edi
     RETQ killed $eax
 ...

llvm/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir

bb.0.entry:
     $ebx = COPY $edi
     MOV32mr $rsp, 1, _, 12, _, $ebx
 
   bb.1.check:
     successors: %bb.2.loop, %bb.3.exit
     liveins: $ebx
 
     CMP32ri8 $ebx, 10, implicit-def $eflags
-    JG_1 %bb.3.exit, implicit killed $eflags
+    JCC_1 %bb.3.exit, 15, implicit killed $eflags
     JMP_1 %bb.2.loop
 
   bb.2.loop:
     successors: %bb.1.check
     liveins: $ebx
 
     $edi = MOV32rm $rsp, 1, _, 12, _
     CALL64pcrel32 @compute, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, implicit-def $eax

llvm/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir

liveins:
   - { reg: '$edi' }
 body: |
   bb.0.entry:
     successors: %bb.1.less, %bb.2.exit
   ; CHECK: [[@LINE+1]]:19: expected line break at the end of a list
     liveins: $edi 44
 
     CMP32ri8 $edi, 10, implicit-def $eflags
-    JG_1 %bb.2.exit, implicit killed $eflags
+    JCC_1 %bb.2.exit, 15, implicit killed $eflags
 
   bb.1.less:
     $eax = MOV32r0 implicit-def dead $eflags
     RETQ killed $eax
 
   bb.2.exit:
     liveins: $edi
 
     $eax = COPY killed $edi
     RETQ killed $eax
 ...

llvm/test/CodeGen/MIR/X86/expected-number-after-bb.mir

 
 ...
 ---
 name:            foo
 body: |
   bb.0.entry:
     $eax = MOV32rm $rdi, 1, _, 0, _
     CMP32ri8 $eax, 10, implicit-def $eflags
-    ; CHECK: [[@LINE+1]]:14: expected a number after '%bb.'
-    JG_1 %bb.nah, implicit $eflags
+    ; CHECK: [[@LINE+1]]:15: expected a number after '%bb.'
+    JCC_1 %bb.nah, 15, implicit $eflags
 
   bb.1.true:
     $eax = MOV32r0 implicit-def $eflags
 
   bb.2.nah:
     RETQ $eax
 ...

llvm/test/CodeGen/MIR/X86/external-symbol-operands.mir

bb.0.entry:
     liveins: $edi
 
     $rsp = SUB64ri32 $rsp, 520, implicit-def $eflags
     $rcx = LOAD_STACK_GUARD
     MOV64mr $rsp, 1, _, 512, _, $rcx
     $rax = MOVSX64rr32 $edi
     $eax = MOV32rm $rsp, 4, $rax, 0, _
     CMP64rm $rcx, $rsp, 1, _, 512, _, implicit-def $eflags
-    JNE_1 %bb.2.entry, implicit $eflags
+    JCC_1 %bb.2.entry, 5, implicit $eflags
 
   bb.1.entry:
     liveins: $eax
 
     $rsp = ADD64ri32 $rsp, 520, implicit-def $eflags
     RETQ $eax
 
   bb.2.entry:

llvm/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir

stack:
   - { id: 0, name: tmp, offset: 0, size: 4, alignment: 4 }
 body: |
   bb.0:
     successors: %bb.2, %bb.1
     liveins: $edi, $esi
 
     $eax = COPY $edi
     CMP32rr $eax, killed $esi, implicit-def $eflags
-    JL_1 %bb.2, implicit killed $eflags
+    JCC_1 %bb.2, 12, implicit killed $eflags
 
   bb.1:
     successors: %bb.3
     liveins: $eax
 
     JMP_1 %bb.3
 
   bb.2.true:

llvm/test/CodeGen/MIR/X86/frame-info-stack-references.mir

bb.0.entry:
     $rbx = LOAD_STACK_GUARD :: (invariant load 8 from @__stack_chk_guard)
     MOV64mr $rsp, 1, _, 24, _, $rbx
     $rsi = LEA64r $rsp, 1, _, 19, _
     MOV64mr $rsp, 1, _, 8, _, $rsi
     $rdi = LEA64r $rip, 1, _, @.str, _
     dead $eax = MOV32r0 implicit-def dead $eflags, implicit-def $al
     CALL64pcrel32 @printf, csr_64, implicit $rsp, implicit $rdi, implicit $rsi, implicit $al, implicit-def $rsp, implicit-def $eax
     CMP64rm killed $rbx, $rsp, 1, _, 24, _, implicit-def $eflags
-    JNE_1 %bb.2.entry, implicit $eflags
+    JCC_1 %bb.2.entry, 5, implicit $eflags
 
   bb.1.entry:
     liveins: $eax
 
     $rsp = ADD64ri8 $rsp, 32, implicit-def dead $eflags
     $rbx = POP64r implicit-def $rsp, implicit $rsp
     RETQ $eax
 
   bb.2.entry:
     CALL64pcrel32 &__stack_chk_fail, csr_64, implicit $rsp, implicit-def $rsp
 ...

llvm/test/CodeGen/MIR/X86/implicit-register-flag.mir

 
 ...
 ---
 name:            foo
 body: |
   bb.0.entry:
     successors: %bb.1, %bb.2
     ; CHECK:      CMP32ri8 $edi, 10, implicit-def $eflags
-    ; CHECK-NEXT: JG_1 %bb.2, implicit $eflags
+    ; CHECK-NEXT: JCC_1 %bb.2, 15, implicit $eflags
     CMP32ri8 $edi, 10, implicit-def $eflags
-    JG_1 %bb.2, implicit $eflags
+    JCC_1 %bb.2, 15, implicit $eflags
 
   bb.1.less:
     ; CHECK: $eax = MOV32r0 implicit-def $eflags
     $eax = MOV32r0 implicit-def $eflags
     RETQ $eax
 
   bb.2.exit:
     $eax = COPY $edi

llvm/test/CodeGen/MIR/X86/jump-table-info.mir

entries:
     - id:        0
       blocks:    [ '%bb.3', '%bb.4', '%bb.5', '%bb.6' ]
 body: |
   bb.0.entry:
     successors: %bb.2, %bb.1
 
     $eax = MOV32rr $edi, implicit-def $rax
     CMP32ri8 $edi, 3, implicit-def $eflags
-    JA_1 %bb.2, implicit $eflags
+    JCC_1 %bb.2, 7, implicit $eflags
 
   bb.1.entry:
     successors: %bb.3, %bb.4, %bb.5, %bb.6
     ; CHECK: $rcx = LEA64r $rip, 1, $noreg, %jump-table.0, $noreg
     $rcx = LEA64r $rip, 1, _, %jump-table.0, _
     $rax = MOVSX64rm32 $rcx, 4, $rax, 0, _
     $rax = ADD64rr $rax, $rcx, implicit-def $eflags
     JMP64r $rax
entries:
     - id:        1
       blocks:    [ '%bb.3', '%bb.4', '%bb.5', '%bb.6' ]
 body: |
   bb.0.entry:
     successors: %bb.2, %bb.1
 
     $eax = MOV32rr $edi, implicit-def $rax
     CMP32ri8 $edi, 3, implicit-def $eflags
-    JA_1 %bb.2, implicit $eflags
+    JCC_1 %bb.2, 7, implicit $eflags
 
   bb.1.entry:
     successors: %bb.3, %bb.4, %bb.5, %bb.6
     ; Verify that the printer will use an id of 0 for this jump table:
     ; CHECK: $rcx = LEA64r $rip, 1, $noreg, %jump-table.0, $noreg
     $rcx = LEA64r $rip, 1, _, %jump-table.1, _
     $rax = MOVSX64rm32 $rcx, 4, $rax, 0, _
     $rax = ADD64rr $rax, $rcx, implicit-def $eflags

llvm/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir

# CHECK: [[@LINE+1]]:18: redefinition of jump table entry '%jump-table.0'
     - id:        0
       blocks:    [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]
 body: |
   bb.0.entry:
     successors: %bb.2.def, %bb.1.entry
 
     $eax = MOV32rr $edi, implicit-def $rax
     CMP32ri8 $edi, 3, implicit-def $eflags
-    JA_1 %bb.2.def, implicit $eflags
+    JCC_1 %bb.2.def, 7, implicit $eflags
 
   bb.1.entry:
     successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4
 
     $rcx = LEA64r $rip, 1, _, %jump-table.0, _
     $rax = MOVSX64rm32 $rcx, 4, $rax, 0, _
     $rax = ADD64rr $rax, $rcx, implicit-def $eflags
     JMP64r $rax

llvm/test/CodeGen/MIR/X86/killed-register-flag.mir

 ...
 ---
 name:            foo
 body: |
   bb.0.entry:
     successors: %bb.1.less, %bb.2.exit
 
     CMP32ri8 $edi, 10, implicit-def $eflags
-    JG_1 %bb.2.exit, implicit $eflags
+    JCC_1 %bb.2.exit, 15, implicit $eflags
 
   bb.1.less:
     ; CHECK:      $eax = MOV32r0
     ; CHECK-NEXT: RETQ killed $eax
     $eax = MOV32r0 implicit-def $eflags
     RETQ killed $eax
 
   bb.2.exit:
     ; CHECK:      $eax = COPY killed $edi
     ; CHECK-NEXT: RETQ killed $eax
     $eax = COPY killed $edi
     RETQ killed $eax
 ...

llvm/test/CodeGen/MIR/X86/large-index-number-error.mir

 
 ...
 ---
 name:            foo
 body: |
   bb.0.entry:
     $eax = MOV32rm $rdi, 1, _, 0, _
     CMP32ri8 $eax, 10, implicit-def $eflags
-    ; CHECK: [[@LINE+1]]:10: expected 32-bit integer (too large)
-    JG_1 %bb.123456789123456, implicit $eflags
+    ; CHECK: [[@LINE+1]]:11: expected 32-bit integer (too large)
+    JCC_1 %bb.123456789123456, 15, implicit $eflags
 
   bb.1:
     $eax = MOV32r0 implicit-def $eflags
 
   bb.2:
     RETQ $eax
 ...

llvm/test/CodeGen/MIR/X86/machine-basic-block-operands.mir

 name:            foo
 body: |
   ; CHECK: bb.0.entry
   bb.0.entry:
     successors: %bb.1, %bb.2
 
     $eax = MOV32rm $rdi, 1, _, 0, _
     ; CHECK:      CMP32ri8 $eax, 10
-    ; CHECK-NEXT: JG_1 %bb.2
+    ; CHECK-NEXT: JCC_1 %bb.2, 15
     CMP32ri8 $eax, 10, implicit-def $eflags
-    JG_1 %bb.2, implicit $eflags
+    JCC_1 %bb.2, 15, implicit $eflags
   ; CHECK: bb.1.less:
 
   bb.1.less:
     $eax = MOV32r0 implicit-def $eflags
 
   bb.2.exit:
     RETQ $eax
 ...
 ---
 # CHECK: name: bar
 name:            bar
 body: |
   ; CHECK: bb.0.entry:
   bb.0.entry:
     successors: %bb.1, %bb.3
 
     $eax = MOV32rm $rdi, 1, _, 0, _
     ; CHECK:      CMP32ri8 $eax, 10
-    ; CHECK-NEXT: JG_1 %bb.2
+    ; CHECK-NEXT: JCC_1 %bb.2, 15
     CMP32ri8 $eax, 10, implicit-def $eflags
-    JG_1 %bb.3, implicit $eflags
+    JCC_1 %bb.3, 15, implicit $eflags
 
   bb.1:
     $eax = MOV32r0 implicit-def $eflags
 
   bb.3:
     RETQ $eax
 ...

llvm/test/CodeGen/MIR/X86/memory-operands.mir

- id:        0
       blocks:    [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]
 body: |
   bb.0.entry:
     successors: %bb.2.def, %bb.1.entry
     liveins: $edi
 
     $eax = MOV32rr $edi, implicit-def $rax
     CMP32ri8 killed $edi, 3, implicit-def $eflags
-    JA_1 %bb.2.def, implicit killed $eflags
+    JCC_1 %bb.2.def, 7, implicit killed $eflags
 
   bb.1.entry:
     successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4
     liveins: $rax
 
     $rcx = LEA64r $rip, 1, _, %jump-table.0, _
   ; CHECK: name: jumptable_psv
   ; CHECK: $rax = MOVSX64rm32 $rcx, 4, killed $rax, 0, $noreg :: (load 4 from jump-table, align 8)

llvm/test/CodeGen/MIR/X86/missing-implicit-operand.mir

 ---
 name:            foo
 body: |
   bb.0.entry:
     successors: %bb.1.less, %bb.2.exit
 
     $eax = MOV32rm $rdi, 1, _, 0, _
     CMP32ri8 $eax, 10, implicit-def $eflags
-  ; CHECK: [[@LINE+1]]:20: missing implicit register operand 'implicit $eflags'
-    JG_1 %bb.2.exit
+  ; CHECK: [[@LINE+1]]:25: missing implicit register operand 'implicit $eflags'
+    JCC_1 %bb.2.exit, 15
 
   bb.1.less:
     $eax = MOV32r0 implicit-def $eflags
 
   bb.2.exit:
     RETQ $eax
 ...

llvm/test/CodeGen/MIR/X86/newline-handling.mir

 liveins:
   - { reg: '$edi' }
 # CHECK-LABEL: name: foo
 # CHECK: body: |
 # CHECK-NEXT: bb.0.entry:
 # CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
 # CHECK-NEXT: liveins: $edi
 # CHECK:      CMP32ri8 $edi, 10, implicit-def $eflags
-# CHECK-NEXT: JG_1 %bb.2, implicit killed $eflags
+# CHECK-NEXT: JCC_1 %bb.2, 15, implicit killed $eflags
 
 # CHECK:      bb.1.less:
 # CHECK-NEXT: $eax = MOV32r0 implicit-def dead $eflags
 # CHECK-NEXT: RETQ killed $eax
 
 # CHECK:      bb.2.exit:
 # CHECK-NEXT: liveins: $edi
 # CHECK:      $eax = COPY killed $edi
 # CHECK-NEXT: RETQ killed $eax
 body: |
   bb.0.entry:
     successors: %bb.1, %bb.2
 
     liveins: $edi
 
     CMP32ri8 $edi, 10, implicit-def $eflags
 
-    JG_1 %bb.2, implicit killed $eflags
+    JCC_1 %bb.2, 15, implicit killed $eflags
 
   bb.1.less:
 
 
     $eax = MOV32r0 implicit-def dead $eflags
     RETQ killed $eax
   bb.2.exit:
 

 liveins:
   - { reg: '$edi' }
 # CHECK-LABEL: name: bar
 # CHECK: body: |
 # CHECK-NEXT: bb.0.entry:
 # CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
 # CHECK-NEXT: liveins: $edi
 # CHECK:      CMP32ri8 $edi, 10, implicit-def $eflags
-# CHECK-NEXT: JG_1 %bb.2, implicit killed $eflags
+# CHECK-NEXT: JCC_1 %bb.2, 15, implicit killed $eflags
 
 # CHECK:      bb.1.less:
 # CHECK-NEXT: $eax = MOV32r0 implicit-def dead $eflags
 # CHECK-NEXT: RETQ killed $eax
 
 # CHECK:      bb.2.exit:
 # CHECK-NEXT: liveins: $edi
 # CHECK:      $eax = COPY killed $edi
 # CHECK-NEXT: RETQ killed $eax
 body: |
 
   bb.0.entry:
     successors: %bb.1, %bb.2
     liveins: $edi
     CMP32ri8 $edi, 10, implicit-def $eflags
-    JG_1 %bb.2, implicit killed $eflags
+    JCC_1 %bb.2, 15, implicit killed $eflags
   bb.1.less:  $eax = MOV32r0 implicit-def dead $eflags
               RETQ killed $eax
 
   bb.2.exit:  liveins: $edi
     $eax = COPY killed $edi
     RETQ killed $eax
 
 ...

llvm/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir

body: |
   ; CHECK-LABEL: bb.0.entry:
   ; CHECK:         successors: %bb.1(0x2a3d70a4), %bb.2(0x55c28f5c)
   ; CHECK-LABEL: bb.1.less:
   bb.0.entry:
     successors: %bb.1 (33), %bb.2(67)
     liveins: $edi
 
     CMP32ri8 $edi, 10, implicit-def $eflags
-    JG_1 %bb.2, implicit killed $eflags
+    JCC_1 %bb.2, 15, implicit killed $eflags
 
   bb.1.less:
     $eax = MOV32r0 implicit-def dead $eflags
     RETQ killed $eax
 
   bb.2.exit:
     liveins: $edi
 
     $eax = COPY killed $edi
     RETQ killed $eax
 ...

llvm/test/CodeGen/MIR/X86/successor-basic-blocks.mir

 body: |
   ; CHECK-LABEL: bb.0.entry:
   ; CHECK-LABEL: bb.1.less:
   bb.0.entry:
     successors: %bb.1.less, %bb.2.exit
     liveins: $edi
 
     CMP32ri8 $edi, 10, implicit-def $eflags
-    JG_1 %bb.2.exit, implicit killed $eflags
+    JCC_1 %bb.2.exit, 15, implicit killed $eflags
 
   bb.1.less:
     $eax = MOV32r0 implicit-def dead $eflags
     RETQ killed $eax
 
   bb.2.exit:
     liveins: $edi
 
body: |
   ; CHECK-LABEL: bb.0.entry:
   ; CHECK:         successors: %bb.1(0x80000000), %bb.2(0x00000000)
   bb.0.entry:
     liveins: $edi
     successors: %bb.1
     successors: %bb.2
 
     CMP32ri8 $edi, 10, implicit-def $eflags
-    JG_1 %bb.2, implicit killed $eflags
+    JCC_1 %bb.2, 15, implicit killed $eflags
 
   ; Verify that we can have an empty list of successors.
   ; CHECK-LABEL: bb.1:
   ; CHECK-NEXT:  $eax = MOV32r0 implicit-def dead $eflags
   bb.1:
     successors:
     $eax = MOV32r0 implicit-def dead $eflags
     RETQ killed $eax
 
   bb.2:
     liveins: $edi
 
     $eax = COPY killed $edi
     RETQ killed $eax
 ...

llvm/test/CodeGen/MIR/X86/undefined-jump-table-id.mir

entries:
     - id:        0
       blocks:    [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]
 body: |
   bb.0.entry:
     successors: %bb.2.def, %bb.1.entry
 
     $eax = MOV32rr $edi, implicit-def $rax
     CMP32ri8 $edi, 3, implicit-def $eflags
-    JA_1 %bb.2.def, implicit $eflags
+    JCC_1 %bb.2.def, 7, implicit $eflags
 
   bb.1.entry:
     successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4
     ; CHECK: [[@LINE+1]]:31: use of undefined jump table '%jump-table.2'
     $rcx = LEA64r $rip, 1, _, %jump-table.2, _
     $rax = MOVSX64rm32 $rcx, 4, $rax, 0, _
     $rax = ADD64rr $rax, $rcx, implicit-def $eflags
     JMP64r $rax

llvm/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir

 
 ...
 ---
 name:            foo
 body: |
   bb.0.entry:
     $eax = MOV32rm $rdi, 1, _, 0, _
     CMP32ri8 $eax, 10, implicit-def $eflags
-    ; CHECK: [[@LINE+1]]:10: use of undefined machine basic block #4
-    JG_1 %bb.4, implicit $eflags
+    ; CHECK: [[@LINE+1]]:11: use of undefined machine basic block #4
+    JCC_1 %bb.4, 15, implicit $eflags
 
   bb.1:
     $eax = MOV32r0 implicit-def $eflags
 
   bb.2:
     RETQ $eax
 ...

llvm/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir

 
 ...
 ---
 name:            foo
 body: |
   bb.0.entry:
     $eax = MOV32rm $rdi, 1, _, 0, _
     CMP32ri8 $eax, 10, implicit-def $eflags
-    ; CHECK: [[@LINE+1]]:10: the name of machine basic block #2 isn't 'hit'
-    JG_1 %bb.2.hit, implicit $eflags
+    ; CHECK: [[@LINE+1]]:11: the name of machine basic block #2 isn't 'hit'
+    JCC_1 %bb.2.hit, 15, implicit $eflags
 
   bb.1.less:
     $eax = MOV32r0 implicit-def $eflags
 
   bb.2.exit:
     RETQ $eax
 ...

llvm/test/CodeGen/MIR/X86/virtual-registers.mir

 body: |
   bb.0.entry:
     successors: %bb.2.exit, %bb.1.less
     liveins: $edi
     ; CHECK:      %0:gr32 = COPY $edi
     ; CHECK-NEXT: %1:gr32 = SUB32ri8 %0, 10
     %0 = COPY $edi
     %1 = SUB32ri8 %0, 10, implicit-def $eflags
-    JG_1 %bb.2.exit, implicit $eflags
+    JCC_1 %bb.2.exit, 15, implicit $eflags
     JMP_1 %bb.1.less
 
   bb.1.less:
     ; CHECK:      %2:gr32 = MOV32r0
     ; CHECK-NEXT: $eax = COPY %2
     %2 = MOV32r0 implicit-def $eflags
     $eax = COPY %2
     RETQ $eax

 body: |
   bb.0.entry:
     successors: %bb.2.exit, %bb.1.less
     liveins: $edi
     ; CHECK:      %0:gr32 = COPY $edi
     ; CHECK-NEXT: %1:gr32 = SUB32ri8 %0, 10
     %2 = COPY $edi
     %0 = SUB32ri8 %2, 10, implicit-def $eflags
-    JG_1 %bb.2.exit, implicit $eflags
+    JCC_1 %bb.2.exit, 15, implicit $eflags
     JMP_1 %bb.1.less
 
   bb.1.less:
     ; CHECK:      %2:gr32 = MOV32r0
     ; CHECK-NEXT: $eax = COPY %2
     %10 = MOV32r0 implicit-def $eflags
     $eax = COPY %10
     RETQ $eax
 
   bb.2.exit:
     ; CHECK: $eax = COPY %0
     $eax = COPY %2
     RETQ $eax
 ...

llvm/test/CodeGen/X86/GlobalISel/select-brcond.mir

registers:
   - { id: 2, class: gpr, preferred-register: '' }
   - { id: 3, class: gpr, preferred-register: '' }
 # X64:           %0:gr32 = COPY $edi
 # X32:           %0:gr32_abcd = COPY $edi
 # CHECK-NEXT:    %2:gr32 = MOV32r0 implicit-def $eflags
 # CHECK-NEXT:    %3:gr32 = MOV32ri 1
 # CHECK-NEXT:    %1:gr8 = COPY %0.sub_8bit
 # CHECK-NEXT:    TEST8ri %1, 1, implicit-def $eflags
-# CHECK-NEXT:    JNE_1 %[[TRUE:bb.[0-9]+]], implicit $eflags
+# CHECK-NEXT:    JCC_1 %[[TRUE:bb.[0-9]+]], 5, implicit $eflags
 # CHECK-NEXT:    JMP_1 %[[FALSE:bb.[0-9]+]]
 # CHECK:      [[TRUE]].{{[a-zA-Z0-9]+}}:
 # CHECK-NEXT:    $eax = COPY %2
 # CHECK-NEXT:    RET 0, implicit $eax
 # CHECK:      [[FALSE]].{{[a-zA-Z0-9]+}}:
 # CHECK-NEXT:    $eax = COPY %3
 # CHECK-NEXT:    RET 0, implicit $eax
 

llvm/test/CodeGen/X86/GlobalISel/select-phi.mir

body:             |
   ; ALL:   [[COPY1:%[0-9]+]]:gr32 = COPY $esi
   ; ALL:   [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
   ; ALL:   [[COPY3:%[0-9]+]]:gr32 = COPY $edx
   ; ALL:   [[COPY4:%[0-9]+]]:gr8 = COPY [[COPY3]].sub_8bit
   ; ALL:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
   ; ALL:   CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
   ; ALL:   [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
   ; ALL:   TEST8ri [[SETCCr]], 1, implicit-def $eflags
-  ; ALL:   JNE_1 %bb.2, implicit $eflags
+  ; ALL:   JCC_1 %bb.2, 5, implicit $eflags
   ; ALL: bb.1.cond.false:
   ; ALL:   successors: %bb.2(0x80000000)
   ; ALL: bb.2.cond.end:
   ; ALL:   [[PHI:%[0-9]+]]:gr8 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0
   ; ALL:   $al = COPY [[PHI]]
   ; ALL:   RET 0, implicit $al
   bb.1.entry:
     successors: %bb.3(0x40000000), %bb.2(0x40000000)
body:             |
   ; ALL:   [[COPY1:%[0-9]+]]:gr32 = COPY $esi
   ; ALL:   [[COPY2:%[0-9]+]]:gr16 = COPY [[COPY1]].sub_16bit
   ; ALL:   [[COPY3:%[0-9]+]]:gr32 = COPY $edx
   ; ALL:   [[COPY4:%[0-9]+]]:gr16 = COPY [[COPY3]].sub_16bit
   ; ALL:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
   ; ALL:   CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
   ; ALL:   [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
   ; ALL:   TEST8ri [[SETCCr]], 1, implicit-def $eflags
-  ; ALL:   JNE_1 %bb.2, implicit $eflags
+  ; ALL:   JCC_1 %bb.2, 5, implicit $eflags
   ; ALL: bb.1.cond.false:
   ; ALL:   successors: %bb.2(0x80000000)
   ; ALL: bb.2.cond.end:
   ; ALL:   [[PHI:%[0-9]+]]:gr16 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0
   ; ALL:   $ax = COPY [[PHI]]
   ; ALL:   RET 0, implicit $ax
   bb.1.entry:
     successors: %bb.3(0x40000000), %bb.2(0x40000000)
body:             |
   ; ALL:   liveins: $edi, $edx, $esi
   ; ALL:   [[COPY:%[0-9]+]]:gr32 = COPY $edi
   ; ALL:   [[COPY1:%[0-9]+]]:gr32 = COPY $esi
   ; ALL:   [[COPY2:%[0-9]+]]:gr32 = COPY $edx
   ; ALL:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
   ; ALL:   CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
   ; ALL:   [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
   ; ALL:   TEST8ri [[SETCCr]], 1, implicit-def $eflags
-  ; ALL:   JNE_1 %bb.1, implicit $eflags
+  ; ALL:   JCC_1 %bb.1, 5, implicit $eflags
   ; ALL:   JMP_1 %bb.2
   ; ALL: bb.1.cond.true:
   ; ALL:   successors: %bb.3(0x80000000)
   ; ALL:   JMP_1 %bb.3
   ; ALL: bb.2.cond.false:
   ; ALL:   successors: %bb.3(0x80000000)
   ; ALL: bb.3.cond.end:
   ; ALL:   [[PHI:%[0-9]+]]:gr32 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2
body:             |
   ; ALL:   liveins: $edi, $rdx, $rsi
   ; ALL:   [[COPY:%[0-9]+]]:gr32 = COPY $edi
   ; ALL:   [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
   ; ALL:   [[COPY2:%[0-9]+]]:gr64 = COPY $rdx
   ; ALL:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
   ; ALL:   CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
   ; ALL:   [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
   ; ALL:   TEST8ri [[SETCCr]], 1, implicit-def $eflags
-  ; ALL:   JNE_1 %bb.1, implicit $eflags
+  ; ALL:   JCC_1 %bb.1, 5, implicit $eflags
   ; ALL:   JMP_1 %bb.2
   ; ALL: bb.1.cond.true:
   ; ALL:   successors: %bb.3(0x80000000)
   ; ALL:   JMP_1 %bb.3
   ; ALL: bb.2.cond.false:
   ; ALL:   successors: %bb.3(0x80000000)
   ; ALL: bb.3.cond.end:
   ; ALL:   [[PHI:%[0-9]+]]:gr64 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2
body:             |
   ; ALL:   [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
   ; ALL:   [[COPY2:%[0-9]+]]:fr32 = COPY [[COPY1]]
   ; ALL:   [[COPY3:%[0-9]+]]:vr128 = COPY $xmm1
   ; ALL:   [[COPY4:%[0-9]+]]:fr32 = COPY [[COPY3]]
   ; ALL:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
   ; ALL:   CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
   ; ALL:   [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
   ; ALL:   TEST8ri [[SETCCr]], 1, implicit-def $eflags
-  ; ALL:   JNE_1 %bb.2, implicit $eflags
+  ; ALL:   JCC_1 %bb.2, 5, implicit $eflags
   ; ALL: bb.1.cond.false:
   ; ALL:   successors: %bb.2(0x80000000)
   ; ALL: bb.2.cond.end:
   ; ALL:   [[PHI:%[0-9]+]]:fr32 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0
   ; ALL:   [[COPY5:%[0-9]+]]:vr128 = COPY [[PHI]]
   ; ALL:   $xmm0 = COPY [[COPY5]]
   ; ALL:   RET 0, implicit $xmm0
   bb.1.entry:
body:             |
   ; ALL:   [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
   ; ALL:   [[COPY2:%[0-9]+]]:fr64 = COPY [[COPY1]]
   ; ALL:   [[COPY3:%[0-9]+]]:vr128 = COPY $xmm1
   ; ALL:   [[COPY4:%[0-9]+]]:fr64 = COPY [[COPY3]]
   ; ALL:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
   ; ALL:   CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
   ; ALL:   [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
   ; ALL:   TEST8ri [[SETCCr]], 1, implicit-def $eflags
-  ; ALL:   JNE_1 %bb.2, implicit $eflags
+  ; ALL:   JCC_1 %bb.2, 5, implicit $eflags
   ; ALL: bb.1.cond.false:
   ; ALL:   successors: %bb.2(0x80000000)
   ; ALL: bb.2.cond.end:
   ; ALL:   [[PHI:%[0-9]+]]:fr64 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0
   ; ALL:   [[COPY5:%[0-9]+]]:vr128 = COPY [[PHI]]
   ; ALL:   $xmm0 = COPY [[COPY5]]
   ; ALL:   RET 0, implicit $xmm0
   bb.1.entry:

llvm/test/CodeGen/X86/PR37310.mir

 constants:       
 body:             |
   bb.0.entry:
     successors: %bb.3(0x40000000), %bb.1(0x40000000)
     liveins: $edi
   
     %0:gr32 = COPY $edi
     %1:gr32 = SUB32ri8 %0, 3, implicit-def $eflags
-    JE_1 %bb.3, implicit $eflags
+    JCC_1 %bb.3, 4, implicit $eflags
     JMP_1 %bb.1
   
   bb.1.if.then:
     successors: %bb.4(0x80000000)
   
     LIFETIME_START %stack.0.q
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
     %2:gr64 = LEA64r %stack.0.q, 1, $noreg, 0, $noreg

llvm/test/CodeGen/X86/block-placement.mir

 body:             |
   bb.0.entry:
     successors: %bb.1(0x7ffff800), %bb.3(0x00000800)
     liveins: $esi, $rdi
   
     frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp
     CFI_INSTRUCTION def_cfa_offset 16
     TEST8ri $sil, 1, implicit-def $eflags, implicit killed $esi
-    JE_1 %bb.3, implicit killed $eflags
+    JCC_1 %bb.3, 4, implicit killed $eflags
   
   bb.1.left:
     successors: %bb.2(0x7ffff800), %bb.4(0x00000800)
     liveins: $rdi
   
     $eax = FAULTING_OP 1, %bb.2, 1684, killed $rdi, 1, $noreg, 0, $noreg :: (load 4 from %ir.ptr)
     JMP_1 %bb.4
   

llvm/test/CodeGen/X86/branchfolding-undef.mir

 # CHECK-NOT: RET
 # CHECK: bb.2:
 # CHECK-NOT: RET 0, undef $eax
 # CHECK: RET 0, $eax
 name: func
 tracksRegLiveness: true
 body: |
   bb.0:
-    JE_1 %bb.1, implicit undef $eflags
+    JCC_1 %bb.1, 4, implicit undef $eflags
     JMP_1 %bb.2
 
   bb.1:
     $eax = MOV32ri 2
     RET 0, $eax
 
   bb.2:
     RET 0, undef $eax
 ...

llvm/test/CodeGen/X86/cfi-inserter-cfg-with-merge.mir

 # RUN: llc -o - %s -mtriple=x86_64-- -verify-cfiinstrs -run-pass=cfi-instr-inserter
 
 --- |
   define void @foo() { ret void }
 ...
 ---
 name: foo
 body: |
   bb.0:
-    JE_1 %bb.3, implicit $eflags
+    JCC_1 %bb.3, 4, implicit $eflags
   bb.1:
     CFI_INSTRUCTION def_cfa_offset 24
   bb.2:
     CFI_INSTRUCTION def_cfa_offset 8
   bb.3:
     RET 0
 ...

llvm/test/CodeGen/X86/cfi-inserter-noreturnblock.mir

 # RUN: llc -o - %s -mtriple=x86_64-- -verify-cfiinstrs \
 # RUN:     -run-pass=cfi-instr-inserter
 
 # Test that CFI verifier does not report inconsistent offset for the
 # 'noreturn' block.
 ---
 name: testNoreturnBlock
 body: |
   bb.0:
     CFI_INSTRUCTION def_cfa_offset 24
-    JNE_1 %bb.2, implicit undef $eflags
+    JCC_1 %bb.2, 5, implicit undef $eflags
 
   bb.1:
     CFI_INSTRUCTION def_cfa_offset 32
 
   bb.2:
     TRAP
 ...
 

llvm/test/CodeGen/X86/cfi-inserter-verify-inconsistent-offset.mir

 ---
 # CHECK: *** Inconsistent CFA register and/or offset between pred and succ ***
 # CHECK: Succ: bb.end
 # CHECK: LLVM ERROR: Found 1 in/out CFI information errors.
 name: inconsistentOffset
 body: |
   bb.0:
     CFI_INSTRUCTION def_cfa_offset 24
-    JNE_1 %bb.2, implicit undef $eflags
+    JCC_1 %bb.2, 5, implicit undef $eflags
 
   bb.1:
     CFI_INSTRUCTION def_cfa_offset 32
 
   bb.2.bb.end:
     RET 0
 ...

llvm/test/CodeGen/X86/cfi-inserter-verify-inconsistent-register.mir

 ---
 # CHECK: *** Inconsistent CFA register and/or offset between pred and succ ***
 # CHECK: Succ: bb.end
 # CHECK: LLVM ERROR: Found 1 in/out CFI information errors.
 name: inconsistentRegister
 body: |
   bb.0:
     CFI_INSTRUCTION def_cfa_register $rbp
-    JNE_1 %bb.2, implicit undef $eflags
+    JCC_1 %bb.2, 5, implicit undef $eflags
 
   bb.1:
     CFI_INSTRUCTION def_cfa $rsp, 8
 
   bb.2.bb.end:
     RET 0
 ...

llvm/test/CodeGen/X86/cmovcmov.ll

 ;
 ; %12 = CMOV_GR8 %7, %11 ... (lt)
 ; %13 = CMOV_GR8 %12, %11 ... (gt)
 ;
 ; was lowered to:
 ;
 ; The first two cmovs got expanded to:
 ; %bb.0:
-;   JL_1 %bb.9
+;   JCC_1 %bb.9, 12
 ; %bb.7:
-;   JG_1 %bb.9
+;   JCC_1 %bb.9, 15
 ; %bb.8:
 ; %bb.9:
 ;   %12 = phi(%7, %bb.8, %11, %bb.0, %12, %bb.7)
 ;   %13 = COPY %12
 ; Which was invalid as %12 is not the same value as %13
 
 define void @no_cascade_opt(i32 %v0, i32 %v1, i32 %v2, i32 %v3) nounwind {
 ; CMOV-LABEL: no_cascade_opt:

llvm/test/CodeGen/X86/conditional-tailcall-samedest.mir

 stack:           
 constants:       
 body:             |
   bb.0.entry:
     successors: %bb.2(0x40000000), %bb.1(0x40000000)
     liveins: $edi
   
     CMP32ri8 killed $edi, 2, implicit-def $eflags
-    JB_1 %bb.2, implicit $eflags
+    JCC_1 %bb.2, 2, implicit $eflags
     JMP_1 %bb.1
   
   bb.1.entry:
     successors: %bb.4(0x40000000), %bb.5(0x40000000)
     liveins: $eflags
   
-    JE_1 %bb.4, implicit killed $eflags
+    JCC_1 %bb.4, 4, implicit killed $eflags
     JMP_1 %bb.5
   
   bb.2.sw.bb:
     successors: %bb.3(0x00000800), %bb.6(0x7ffff800)
   
     $al = MOV8rm $rip, 1, $noreg, @static_local_guard, $noreg :: (volatile load acquire 1 from `i8* bitcast (i64* @static_local_guard to i8*)`, align 8)
     TEST8rr killed $al, $al, implicit-def $eflags
-    JNE_1 %bb.6, implicit killed $eflags
+    JCC_1 %bb.6, 5, implicit killed $eflags
     JMP_1 %bb.3
   
   bb.3.init.check.i:
     dead $edi = MOV32ri @static_local_guard, implicit-def $rdi
     TCRETURNdi64 @initialize_static_local, 0, csr_64, implicit $rsp, implicit $rdi
   
   bb.4.sw.bb2:
     TCRETURNdi64 @mergeable_conditional_tailcall, 0, csr_64, implicit $rsp
   
   bb.5.sw.epilog:
     TCRETURNdi64 @mergeable_conditional_tailcall, 0, csr_64, implicit $rsp
   
   bb.6.return:
     RET 0
 
 ...

llvm/test/CodeGen/X86/dbg-changes-codegen-branch-folding2.mir

--- |
   !19 = !DILocation(line: 6, column: 17, scope: !6)
 
 ...
 ---
 # CHECK: name: _Z3fn1v
 # CHECK: bb.10.for.body.9
 # CHECK: renamable $al
 # CHECK-NEXT: TEST8rr killed renamable $al
-# CHECK-NEXT: JNE_1
+# CHECK-NEXT: JCC_1
 # CHECK-NOT: $al = IMPLICIT_DEF
 # CHECK: bb.12.for.body.10
 
 name:            _Z3fn1v
 alignment:       4
 tracksRegLiveness: true
 constants:       
 body:             |
   bb.0.entry:
     successors: %bb.1, %bb.4
     liveins: $rdi, $rbp, $r15, $r14, $r13, $r12, $rbx
   
     renamable $al = MOV8ri 1
     TEST8rr renamable $al, renamable $al, implicit-def $eflags
-    JNE_1 %bb.4, implicit killed $eflags
+    JCC_1 %bb.4, 5, implicit killed $eflags
   
   bb.1.for.cond.cleanup:
     successors: %bb.3, %bb.2
     liveins: $ecx, $rdi
   
     renamable $eax = MOV32rm $rsp, 1, $noreg, -16, $noreg 
     CMP32rm killed renamable $eax, $rip, 1, $noreg, $noreg, $noreg, implicit-def $eflags 
-    JBE_1 %bb.3, implicit $eflags
+    JCC_1 %bb.3, 6, implicit $eflags
   
   bb.2:
     successors: %bb.3
     liveins: $ebp, $ebx, $edx, $esi, $rdi, $r8d, $r9d, $r10d, $r11d, $r12d, $r13d, $r14d, $r15d
   
   bb.3.for.cond.cleanup:
     liveins: $rdi, $xmm3, $xmm4, $xmm5, $xmm6, $xmm7, $xmm9, $xmm13, $xmm14
     RETQ
   
   bb.4.for.body:
     successors: %bb.1, %bb.5
     liveins: $al, $rdi
   
     renamable $ecx = XOR32rr undef $ecx, undef $ecx, implicit-def dead $eflags
     TEST8rr killed renamable $al, renamable $al, implicit-def $eflags
-    JNE_1 %bb.1, implicit $eflags
+    JCC_1 %bb.1, 5, implicit $eflags
   
   bb.5.for.body.1:
     successors: %bb.1, %bb.6
     liveins: $ecx, $rdi
   
     renamable $al = MOV8ri 1
     TEST8rr killed renamable $al, renamable $al, implicit-def $eflags
-    JNE_1 %bb.1, implicit $eflags
+    JCC_1 %bb.1, 5, implicit $eflags
   
   bb.6.for.body.2:
     successors: %bb.1, %bb.7
     liveins: $ecx, $eflags, $rdi
   
-    JNE_1 %bb.1, implicit $eflags
+    JCC_1 %bb.1, 5, implicit $eflags
   
   bb.7.for.body.3:
     successors: %bb.1, %bb.8
     liveins: $ecx, $rdi
   
     renamable $al = MOV8ri 1
     TEST8rr killed renamable $al, renamable $al, implicit-def $eflags
-    JNE_1 %bb.1, implicit $eflags
+    JCC_1 %bb.1, 5, implicit $eflags
   
   bb.8.for.body.4:
     successors: %bb.1, %bb.9
     liveins: $ecx, $eflags, $rdi
   
-    JNE_1 %bb.1, implicit $eflags
+    JCC_1 %bb.1, 5, implicit $eflags
   
   bb.9.for.body.5:
     successors: %bb.1, %bb.10
     liveins: $ecx, $rdi
   
     renamable $al = MOV8ri 1
     TEST8rr killed renamable $al, renamable $al, implicit-def $eflags
-    JNE_1 %bb.1, implicit $eflags
+    JCC_1 %bb.1, 5, implicit $eflags
   
   bb.10.for.body.6:
     successors: %bb.1, %bb.11
     liveins: $ecx, $eflags, $rdi
   
-    JNE_1 %bb.1, implicit $eflags
+    JCC_1 %bb.1, 5, implicit $eflags
   
   bb.11.for.body.7:
     successors: %bb.1, %bb.12
     liveins: $ecx, $rdi
   
     renamable $al = MOV8ri 1
     TEST8rr killed renamable $al, renamable $al, implicit-def $eflags
-    JNE_1 %bb.1, implicit $eflags
+    JCC_1 %bb.1, 5, implicit $eflags
   
   bb.12.for.body.8:
     successors: %bb.1, %bb.13
     liveins: $ecx, $eflags, $rdi
   
-    JNE_1 %bb.1, implicit $eflags
+    JCC_1 %bb.1, 5, implicit $eflags
   
   bb.13.for.body.9:
     successors: %bb.14, %bb.15
     liveins: $rdi
   
     renamable $al = MOV8ri 1
     TEST8rr killed renamable $al, renamable $al, implicit-def $eflags
-    JE_1 %bb.15, implicit $eflags
+    JCC_1 %bb.15, 4, implicit $eflags
   
   bb.14:
     successors: %bb.1
     liveins: $rdi
   
     renamable $ecx = XOR32rr undef $ecx, undef $ecx, implicit-def dead $eflags
     JMP_1 %bb.1
   
   bb.15.for.body.10:
     successors: %bb.16, %bb.17
     liveins: $eflags, $rdi
   
-    JE_1 %bb.17, implicit killed $eflags
+    JCC_1 %bb.17, 4, implicit killed $eflags
   
   bb.16:
     successors: %bb.1
     liveins: $rdi
   
     JMP_1 %bb.1
   
   bb.17.for.body.11:
     successors: %bb.1
     liveins: $rdi
   
     dead renamable $al = MOV8rm $rsp, 1, $noreg, -121, $noreg 
     DBG_VALUE $al, $noreg, !16, !DIExpression(), debug-location !19
     renamable $ecx = XOR32rr undef $ecx, undef $ecx, implicit-def dead $eflags
     JMP_1 %bb.1
 ...

llvm/test/CodeGen/X86/debugloc-no-line-0.ll

 ; RUN: llc -O0 -mtriple=x86_64-unknown-linux-gnu -stop-before="regallocfast" -o - %s | FileCheck %s
 ;
 ; We check that all the instructions in bb4 now have a debug-location
 ; annotation, and that the annotation is identical to the one on e.g.,
 ; the jmp to bb4.
 ;
 ; CHECK: JMP{{.*}}%bb.4, debug-location ![[JUMPLOC:[0-9]+]]
 ; CHECK: bb.4.entry:
 ; CHECK: successors:
-; CHECK: JE{{.*}}debug-location ![[JUMPLOC]]
+; CHECK: JCC{{.*}}debug-location ![[JUMPLOC]]
 ; CHECK: JMP{{.*}}debug-location ![[JUMPLOC]]
 
 define i32 @main() !dbg !12 {
 entry:
   %add = add nsw i32 undef, 1, !dbg !16
   switch i32 %add, label %sw.epilog [
     i32 1, label %sw.bb
     i32 2, label %sw.bb2

llvm/test/CodeGen/X86/domain-reassignment.mir

body:             |
   ; CHECK:   [[COPY2:%[0-9]+]]:fr32x = COPY $xmm3
   ; CHECK:   [[COPY3:%[0-9]+]]:fr32x = COPY $xmm2
   ; CHECK:   [[COPY4:%[0-9]+]]:fr32x = COPY $xmm1
   ; CHECK:   [[COPY5:%[0-9]+]]:vr128x = COPY $xmm0
   ; CHECK:   [[COPY6:%[0-9]+]]:gr64 = COPY $rsi
   ; CHECK:   [[COPY7:%[0-9]+]]:gr32 = COPY $edi
   ; CHECK:   [[COPY8:%[0-9]+]]:gr8 = COPY [[COPY7]].sub_8bit
   ; CHECK:   TEST8ri killed [[COPY8]], 1, implicit-def $eflags
-  ; CHECK:   JE_1 %bb.2, implicit $eflags
+  ; CHECK:   JCC_1 %bb.2, 4, implicit $eflags
   ; CHECK:   JMP_1 %bb.1
   ; CHECK: bb.1.if:
   ; CHECK:   successors: %bb.3(0x80000000)
   ; CHECK:   [[VCMPSSZrr:%[0-9]+]]:vk1 = VCMPSSZrr [[COPY3]], [[COPY2]], 0
   ; CHECK:   [[COPY9:%[0-9]+]]:vk32 = COPY [[VCMPSSZrr]]
   ; CHECK:   [[COPY10:%[0-9]+]]:vk8 = COPY [[COPY9]]
   ; CHECK:   JMP_1 %bb.3
   ; CHECK: bb.2.else:
bb.0.entry:
     %8 = COPY $xmm3
     %7 = COPY $xmm2
     %6 = COPY $xmm1
     %5 = COPY $xmm0
     %4 = COPY $rsi
     %3 = COPY $edi
     %11 = COPY %3.sub_8bit
     TEST8ri killed %11, 1, implicit-def $eflags
-    JE_1 %bb.2, implicit $eflags
+    JCC_1 %bb.2, 4, implicit $eflags
     JMP_1 %bb.1
 
   bb.1.if:
     successors: %bb.3(0x80000000)
 
     %14 = VCMPSSZrr %7, %8, 0
 
     ; check that cross domain copies are replaced with same domain copies.
bb.0:
     %8 = IMPLICIT_DEF
     %9 = INSERT_SUBREG %8, %18, 1
     %10 = COPY %9
     %11 = VMOVAPDZrrk %2, killed %10, %1
     VMOVAPDZmr %0, 1, $noreg, 0, $noreg, killed %11
 
     ; FIXME We can't replace TEST with KTEST due to flag differences
     ; TEST8rr %18, %18, implicit-def $eflags
-    ; JE_1 %bb.1, implicit $eflags
+    ; JCC_1 %bb.1, 4, implicit $eflags
     ; JMP_1 %bb.2
 
   bb.1:
 
   bb.2:
     RET 0
 
 ...
bb.0:
     %8 = IMPLICIT_DEF
     %9 = INSERT_SUBREG %8, %17, 3
     %10 = COPY %9
     %11 = VMOVAPSZrrk %2, killed %10, %1
     VMOVAPSZmr %0, 1, $noreg, 0, $noreg, killed %11
 
     ; FIXME We can't replace TEST with KTEST due to flag differences
     ; FIXME TEST16rr %17, %17, implicit-def $eflags
-    ; FIXME JE_1 %bb.1, implicit $eflags
+    ; FIXME JCC_1 %bb.1, 4, implicit $eflags
     ; FIXME JMP_1 %bb.2
 
   bb.1:
 
   bb.2:
     RET 0
 
 ...
bb.0:
     %13 = ADD32rr %12, %11, implicit-def dead $eflags
 
     %3 = COPY %13
     %4 = VMOVDQU16Zrrk %2, killed %3, %1
     VMOVDQA32Zmr %0, 1, $noreg, 0, $noreg, killed %4
 
     ; FIXME We can't replace TEST with KTEST due to flag differences
     ; FIXME TEST32rr %13, %13, implicit-def $eflags
-    ; FIXME JE_1 %bb.1, implicit $eflags
+    ; FIXME JCC_1 %bb.1, 4, implicit $eflags
     ; FIXME JMP_1 %bb.2
 
   bb.1:
 
   bb.2:
     RET 0
 
 ...
bb.0:
     %13 = ADD64rr %12, %11, implicit-def dead $eflags
 
     %3 = COPY %13
     %4 = VMOVDQU8Zrrk %2, killed %3, %1
     VMOVDQA32Zmr %0, 1, $noreg, 0, $noreg, killed %4
 
     ; FIXME We can't replace TEST with KTEST due to flag differences
     ; FIXME TEST64rr %13, %13, implicit-def $eflags
-    ; FIXME JE_1 %bb.1, implicit $eflags
+    ; FIXME JCC_1 %bb.1, 4, implicit $eflags
     ; FIXME JMP_1 %bb.2
 
   bb.1:
 
   bb.2:
     RET 0
 
 ...

llvm/test/CodeGen/X86/fixup-bw-inst.mir

 # See the comment near the original IR on what preceding decisions can
 # lead to that.
 body:             |
   bb.0.entry:
     successors: %bb.1(0x30000000), %bb.2.if.then(0x50000000)
     liveins: $rdi
 
     TEST64rr $rdi, $rdi, implicit-def $eflags
-    JE_1 %bb.1, implicit $eflags
+    JCC_1 %bb.1, 4, implicit $eflags
 
   bb.2.if.then:
     liveins: $rdi
 
     $ax = MOV16rm killed $rdi, 1, $noreg, 0, $noreg, implicit-def $eax :: (load 2 from %ir.p)
     ; CHECK: $eax = MOVZX32rm16 killed $rdi, 1, $noreg, 0, $noreg, implicit-def $eax :: (load 2 from %ir.p)
     $ax = KILL $ax, implicit killed $eax
     RETQ $ax

llvm/test/CodeGen/X86/flags-copy-lowering.mir

body:             |
   ; CHECK-NEXT: %[[B_REG:[^:]*]]:gr8 = SETCCr 2, implicit $eflags
   ; CHECK-NOT:  COPY{{( killed)?}} $eflags
 
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
     CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax
     ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
 
     $eflags = COPY %2
-    JA_1 %bb.1, implicit $eflags
-    JB_1 %bb.2, implicit $eflags
+    JCC_1 %bb.1, 7, implicit $eflags
+    JCC_1 %bb.2, 2, implicit $eflags
     JMP_1 %bb.3
   ; CHECK-NOT: $eflags =
   ;
   ; CHECK:        TEST8rr %[[A_REG]], %[[A_REG]], implicit-def $eflags
-  ; CHECK-NEXT:   JNE_1 %bb.1, implicit killed $eflags
+  ; CHECK-NEXT:   JCC_1 %bb.1, 5, implicit killed $eflags
   ; CHECK-SAME: {{$[[:space:]]}}
   ; CHECK-NEXT: bb.4:
   ; CHECK-NEXT:   successors: {{.*$}}
   ; CHECK-SAME: {{$[[:space:]]}}
   ; CHECK-NEXT:   TEST8rr %[[B_REG]], %[[B_REG]], implicit-def $eflags
-  ; CHECK-NEXT:   JNE_1 %bb.2, implicit killed $eflags
+  ; CHECK-NEXT:   JCC_1 %bb.2, 5, implicit killed $eflags
   ; CHECK-NEXT:   JMP_1 %bb.3
   
   bb.1:
     %3:gr32 = MOV32ri 42
     $eax = COPY %3
     RET 0, $eax
   
   bb.2:
body:             |
   ; CHECK-NEXT: %[[B_REG:[^:]*]]:gr8 = SETCCr 2, implicit $eflags
   ; CHECK-NOT:  COPY{{( killed)?}} $eflags
 
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
     CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax
     ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
 
     $eflags = COPY %2
-    JA_1 %bb.2, implicit $eflags
-    JB_1 %bb.3, implicit $eflags
+    JCC_1 %bb.2, 7, implicit $eflags
+    JCC_1 %bb.3, 2, implicit $eflags
   ; CHECK-NOT: $eflags =
   ;
   ; CHECK:        TEST8rr %[[A_REG]], %[[A_REG]], implicit-def $eflags
-  ; CHECK-NEXT:   JNE_1 %bb.2, implicit killed $eflags
+  ; CHECK-NEXT:   JCC_1 %bb.2, 5, implicit killed $eflags
   ; CHECK-SAME: {{$[[:space:]]}}
   ; CHECK-NEXT: bb.4:
   ; CHECK-NEXT:   successors: {{.*$}}
   ; CHECK-SAME: {{$[[:space:]]}}
   ; CHECK-NEXT:   TEST8rr %[[B_REG]], %[[B_REG]], implicit-def $eflags
-  ; CHECK-NEXT:   JNE_1 %bb.3, implicit killed $eflags
+  ; CHECK-NEXT:   JCC_1 %bb.3, 5, implicit killed $eflags
   ; CHECK-SAME: {{$[[:space:]]}}
   ; CHECK-NEXT:   bb.1:
 
   bb.1:
     %5:gr32 = MOV32r0 implicit-def dead $eflags
     $eax = COPY %5
     RET 0, $eax
   
body:             |
   ; CHECK-NEXT: %[[B_REG:[^:]*]]:gr8 = SETCCr 2, implicit $eflags
   ; CHECK-NOT:  COPY{{( killed)?}} $eflags
 
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
     CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax
     ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
 
     $eflags = COPY %2
-    JA_1 %bb.1, implicit $eflags
-    JB_1 %bb.2, implicit $eflags
+    JCC_1 %bb.1, 7, implicit $eflags
+    JCC_1 %bb.2, 2, implicit $eflags
     JMP_1 %bb.3
   ; CHECK-NOT: $eflags =
   ;
   ; CHECK:        TEST8rr %[[A_REG]], %[[A_REG]], implicit-def $eflags
-  ; CHECK-NEXT:   JNE_1 %bb.1, implicit killed $eflags
+  ; CHECK-NEXT:   JCC_1 %bb.1, 5, implicit killed $eflags
   ; CHECK-SAME: {{$[[:space:]]}}
   ; CHECK-NEXT: bb.4:
   ; CHECK-NEXT:   successors: {{.*$}}
   ; CHECK-SAME: {{$[[:space:]]}}
   ; CHECK-NEXT:   TEST8rr %[[B_REG]], %[[B_REG]], implicit-def $eflags
-  ; CHECK-NEXT:   JNE_1 %bb.2, implicit killed $eflags
+  ; CHECK-NEXT:   JCC_1 %bb.2, 5, implicit killed $eflags
   ; CHECK-NEXT:   JMP_1 %bb.3
 
   bb.1:
     liveins: $eflags
 
     %3:gr64 = CMOV64rr %0, %1, 4, implicit killed $eflags
   ; CHECK-NOT:     $eflags =
   ; CHECK:         TEST8rr %[[NE_REG]], %[[NE_REG]], implicit-def $eflags
body:             |
   ; CHECK-NEXT: %[[O_REG:[^:]*]]:gr8 = SETCCr 0, implicit $eflags
   ; CHECK-NOT:  COPY{{( killed)?}} $eflags
 
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
     CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax
     ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
 
     $eflags = COPY %2
-    JA_1 %bb.1, implicit $eflags
-    JB_1 %bb.2, implicit $eflags
+    JCC_1 %bb.1, 7, implicit $eflags
+    JCC_1 %bb.2, 2, implicit $eflags
     JMP_1 %bb.5
   ; CHECK-NOT: $eflags =
   ;
   ; CHECK:        TEST8rr %[[A_REG]], %[[A_REG]], implicit-def $eflags
-  ; CHECK-NEXT:   JNE_1 %bb.1, implicit killed $eflags
+  ; CHECK-NEXT:   JCC_1 %bb.1, 5, implicit killed $eflags
   ; CHECK-SAME: {{$[[:space:]]}}
   ; CHECK-NEXT: bb.6:
   ; CHECK-NEXT:   successors: {{.*$}}
   ; CHECK-SAME: {{$[[:space:]]}}
   ; CHECK-NEXT:   TEST8rr %[[B_REG]], %[[B_REG]], implicit-def $eflags
-  ; CHECK-NEXT:   JNE_1 %bb.2, implicit killed $eflags
+  ; CHECK-NEXT:   JCC_1 %bb.2, 5, implicit killed $eflags
   ; CHECK-NEXT:   JMP_1 %bb.5
 
   bb.1:
     liveins: $eflags
 
     %3:gr64 = CMOV64rr %0, %1, 4, implicit killed $eflags
   ; CHECK-NOT:     $eflags =
   ; CHECK:         TEST8rr %[[NE_REG]], %[[NE_REG]], implicit-def $eflags
   ; CHECK-NEXT:    %3:gr64 = CMOV64rr %0, %1, 4, implicit killed $eflags
     $rax = COPY %3
     RET 0, $rax
 
   bb.2:
     ; The goal is to have another batch of successors discovered in a block
     ; between two successors which kill $eflags. This ensures that neither of
     ; the surrounding kills impact recursing through this block.
     successors: %bb.3, %bb.4
     liveins: $eflags
 
-    JO_1 %bb.3, implicit $eflags
+    JCC_1 %bb.3, 0, implicit $eflags
     JMP_1 %bb.4
   ; CHECK-NOT: $eflags =
   ;
   ; CHECK:        TEST8rr %[[O_REG]], %[[O_REG]], implicit-def $eflags
-  ; CHECK-NEXT:   JNE_1 %bb.3, implicit killed $eflags
+  ; CHECK-NEXT:   JCC_1 %bb.3, 5, implicit killed $eflags
   ; CHECK-NEXT:   JMP_1 %bb.4
 
   bb.3:
     liveins: $eflags
 
     %4:gr64 = CMOV64rr %0, %1, 5, implicit $eflags
   ; CHECK-NOT:     $eflags =
   ; CHECK:         TEST8rr %[[NE_REG]], %[[NE_REG]], implicit-def $eflags
body:             |
   ; CHECK-NOT:    COPY{{( killed)?}} $eflags
     JMP_1 %bb.1
 
   bb.1:
     successors: %bb.2, %bb.4
     liveins: $eflags
 
     ; Outer loop header, target for one set of hoisting.
-    JE_1 %bb.2, implicit $eflags
+    JCC_1 %bb.2, 4, implicit $eflags
     JMP_1 %bb.4
   ; CHECK:      bb.1:
   ; CHECK-NOT:    COPY{{( killed)?}} $eflags
   ; CHECK:        %[[A_REG:[^:]*]]:gr8 = SETCCr 7, implicit $eflags
   ; CHECK-NEXT:   %[[E_REG:[^:]*]]:gr8 = SETCCr 4, implicit $eflags
   ; CHECK-NEXT:   %[[B_REG:[^:]*]]:gr8 = SETCCr 2, implicit $eflags
   ; CHECK-NOT:    COPY{{( killed)?}} $eflags
 
   bb.2:
     successors: %bb.2, %bb.3
     liveins: $eflags
 
     ; Inner loop with a local copy. We should eliminate this but can't hoist.
     %2:gr64 = COPY $eflags
     $eflags = COPY %2
-    JE_1 %bb.2, implicit $eflags
+    JCC_1 %bb.2, 4, implicit $eflags
     JMP_1 %bb.3
   ; CHECK:      bb.2:
   ; CHECK-NOT:    COPY{{( killed)?}} $eflags
   ; CHECK:        TEST8rr %[[E_REG]], %[[E_REG]], implicit-def $eflags
-  ; CHECK-NEXT:   JNE_1 %bb.2, implicit killed $eflags
+  ; CHECK-NEXT:   JCC_1 %bb.2, 5, implicit killed $eflags
   ; CHECK-NOT:    COPY{{( killed)?}} $eflags
 
   bb.3:
     successors: %bb.8
     liveins: $eflags
 
     ; Use and then clobber $eflags. Then hop to the outer loop latch.
     %3:gr64 = ADC64ri32 %0, 42, implicit-def dead $eflags, implicit $eflags
   ; CHECK:      bb.3:
   ; CHECK-NOT:    COPY{{( killed)?}} $eflags
   ; CHECK:        dead %{{[^:]*}}:gr8 = ADD8ri %[[B_REG]], 255, implicit-def $eflags
   ; CHECK-NEXT:   %3:gr64 = ADC64ri32 %0, 42, implicit-def{{( dead)?}} $eflags, implicit{{( killed)?}} $eflags
   ; CHECK-NOT:    COPY{{( killed)?}} $eflags
     MOV64mr $rsp, 1, $noreg, -16, $noreg, killed %3
     JMP_1 %bb.8
 
   bb.4:
     successors: %bb.5, %bb.6
     liveins: $eflags
 
     ; Another inner loop, this one with a diamond.
-    JE_1 %bb.5, implicit $eflags
+    JCC_1 %bb.5, 4, implicit $eflags
     JMP_1 %bb.6
   ; CHECK:      bb.4:
   ; CHECK-NOT:    COPY{{( killed)?}} $eflags
   ; CHECK:        TEST8rr %[[E_REG]], %[[E_REG]], implicit-def $eflags
-  ; CHECK-NEXT:   JNE_1 %bb.5, implicit killed $eflags
+  ; CHECK-NEXT:   JCC_1 %bb.5, 5, implicit killed $eflags
   ; CHECK-NOT:    COPY{{( killed)?}} $eflags
 
   bb.5:
     successors: %bb.7
     liveins: $eflags
 
     ; Just use $eflags on this side of the diamond.
     %4:gr64 = CMOV64rr %0, %1, 7, implicit $eflags
; CHECK-NOT:    COPY{{( killed)?}} $eflags
     MOV64mr $rsp, 1, $noreg, -16, $noreg, killed %7
     JMP_1 %bb.7
 
   bb.7:
     successors: %bb.4, %bb.8
     liveins: $eflags
 
     ; Inner loop latch.
-    JE_1 %bb.4, implicit $eflags
+    JCC_1 %bb.4, 4, implicit $eflags
     JMP_1 %bb.8
   ; CHECK:      bb.7:
   ; CHECK-NOT:    COPY{{( killed)?}} $eflags
   ; CHECK:        TEST8rr %[[E_REG]], %[[E_REG]], implicit-def $eflags
-  ; CHECK-NEXT:   JNE_1 %bb.4, implicit killed $eflags
+  ; CHECK-NEXT:   JCC_1 %bb.4, 5, implicit killed $eflags
   ; CHECK-NOT:    COPY{{( killed)?}} $eflags
 
   bb.8:
     successors: %bb.1, %bb.9
 
     ; Outer loop latch. Note that we cannot have EFLAGS live-in here as that
     ; immediately require PHIs.
     CMP64rr %0, %1, implicit-def $eflags
-    JE_1 %bb.1, implicit $eflags
+    JCC_1 %bb.1, 4, implicit $eflags
     JMP_1 %bb.9
   ; CHECK:      bb.8:
   ; CHECK-NOT:    COPY{{( killed)?}} $eflags
   ; CHECK:        CMP64rr %0, %1, implicit-def $eflags
-  ; CHECK-NEXT:   JE_1 %bb.1, implicit $eflags
+  ; CHECK-NEXT:   JCC_1 %bb.1, 4, implicit $eflags
   ; CHECK-NOT:    COPY{{( killed)?}} $eflags
 
   bb.9:
     liveins: $eflags
 
     ; And we're done.
     %8:gr64 = CMOV64rr %0, %1, 4, implicit killed $eflags
     $rax = COPY %8
body:             |
   ; CHECK-NEXT: %[[AE_REG:[^:]*]]:gr8 = SETCCr 3, implicit $eflags
   ; CHECK-NOT:  COPY{{( killed)?}} $eflags
 
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
     CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax
     ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
 
     $eflags = COPY %4
-    JA_1 %bb.1, implicit $eflags
-    JB_1 %bb.2, implicit $eflags
+    JCC_1 %bb.1, 7, implicit $eflags
+    JCC_1 %bb.2, 2, implicit $eflags
     JMP_1 %bb.3
   ; CHECK-NOT: $eflags =
   ;
   ; CHECK:        TEST8rr %[[A_REG]], %[[A_REG]], implicit-def $eflags
-  ; CHECK-NEXT:   JNE_1 %bb.1, implicit killed $eflags
+  ; CHECK-NEXT:   JCC_1 %bb.1, 5, implicit killed $eflags
   ; CHECK-SAME: {{$[[:space:]]}}
   ; CHECK-NEXT: bb.4:
   ; CHECK-NEXT:   successors: {{.*$}}
   ; CHECK-SAME: {{$[[:space:]]}}
   ; CHECK-NEXT:   TEST8rr %[[AE_REG]], %[[AE_REG]], implicit-def $eflags
-  ; CHECK-NEXT:   JE_1 %bb.2, implicit killed $eflags
+  ; CHECK-NEXT:   JCC_1 %bb.2, 4, implicit killed $eflags
   ; CHECK-NEXT:   JMP_1 %bb.3
 
   bb.1:
     %5:gr32 = MOV32ri 42
     $eax = COPY %5
     RET 0, $eax
 
   bb.2:
body:             |
   ; CHECK-NEXT: %[[E_REG:[^:]*]]:gr8 = SETCCr 4, implicit $eflags
   ; CHECK-NOT:  COPY{{( killed)?}} $eflags
 
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
     CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax
     ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
 
     $eflags = COPY %2
-    JE_1 %bb.1, implicit $eflags
+    JCC_1 %bb.1, 4, implicit $eflags
     JMP_1 %bb.2
   ; CHECK-NOT: $eflags =
   ;
   ; CHECK:        TEST8rr %[[E_REG]], %[[E_REG]], implicit-def $eflags
-  ; CHECK-NEXT:   JNE_1 %bb.1, implicit killed $eflags
+  ; CHECK-NEXT:   JCC_1 %bb.1, 5, implicit killed $eflags
   ; CHECK-NEXT:   JMP_1 %bb.2
 
   bb.1:
     %3:gr32 = MOV32ri 42
     $eax = COPY %3
     RET 0, $eax
 
   bb.2:
     %4:gr32 = MOV32ri 43
     $eax = COPY %4
     RET 0, $eax
 
 ...

llvm/test/CodeGen/X86/implicit-null-checks.mir

 # CHECK-NEXT:    $eax = FAULTING_OP 1, %bb.3, {{[0-9]+}}, $eax, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags :: (load 4 from %ir.x)
 # CHECK-NEXT:    JMP_1 %bb.1
 
 body:             |
   bb.0.entry:
     liveins: $esi, $rdi
 
     TEST64rr $rdi, $rdi, implicit-def $eflags
-    JE_1 %bb.3, implicit $eflags
+    JCC_1 %bb.3, 4, implicit $eflags
 
   bb.1.not_null:
     liveins: $esi, $rdi
 
     $eax = MOV32ri 2200000
     $eax = AND32rm killed $eax, killed $rdi, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load 4 from %ir.x)
     CMP32rr killed $eax, killed $esi, implicit-def $eflags
-    JE_1 %bb.4, implicit $eflags
+    JCC_1 %bb.4, 4, implicit $eflags
 
   bb.2.ret_200:
     $eax = MOV32ri 200
     RETQ $eax
 
   bb.3.is_null:
     $eax = MOV32ri 42
     RETQ $eax

 tracksRegLiveness: true
 liveins:
   - { reg: '$rdi' }
   - { reg: '$esi' }
   - { reg: '$rdx' }
 # CHECK: bb.0.entry:
 # CHECK:    $eax = MOV32rm killed $rdx, 1, $noreg, 0, $noreg :: (volatile load 4 from %ir.ptr)
 # CHECK-NEXT:    TEST64rr $rdi, $rdi, implicit-def $eflags
-# CHECK-NEXT:    JE_1 %bb.3, implicit $eflags
+# CHECK-NEXT:    JCC_1 %bb.3, 4, implicit $eflags
 
 body:             |
   bb.0.entry:
     liveins: $esi, $rdi, $rdx
 
     $eax = MOV32rm killed $rdx, 1, $noreg, 0, $noreg :: (volatile load 4 from %ir.ptr)
     TEST64rr $rdi, $rdi, implicit-def $eflags
-    JE_1 %bb.3, implicit $eflags
+    JCC_1 %bb.3, 4, implicit $eflags
 
   bb.1.not_null:
     liveins: $esi, $rdi
 
     $eax = MOV32ri 2200000
     $eax = AND32rm killed $eax, killed $rdi, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load 4 from %ir.x)
     CMP32rr killed $eax, killed $esi, implicit-def $eflags
-    JE_1 %bb.4, implicit $eflags
+    JCC_1 %bb.4, 4, implicit $eflags
 
   bb.2.ret_200:
 
     $eax = MOV32ri 200
 
   bb.3.is_null:
     liveins: $eax, $ah, $al, $ax, $bh, $bl, $bp, $bpl, $bx, $eax, $ebp, $ebx, $rax, $rbp, $rbx, $r12, $r13, $r14, $r15, $r12b, $r13b, $r14b, $r15b, $r12d, $r13d, $r14d, $r15d, $r12w, $r13w, $r14w, $r15w
 

 # CHECK-LABEL: name:            imp_null_check_with_bitwise_op_2
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '$rdi' }
   - { reg: '$esi' }
 # CHECK:  bb.0.entry:
 # CHECK:    TEST64rr $rdi, $rdi, implicit-def $eflags
-# CHECK-NEXT:    JE_1 %bb.3, implicit $eflags
+# CHECK-NEXT:    JCC_1 %bb.3, 4, implicit $eflags
 
 body:             |
   bb.0.entry:
     liveins: $esi, $rdi
 
     TEST64rr $rdi, $rdi, implicit-def $eflags
-    JE_1 %bb.3, implicit $eflags
+    JCC_1 %bb.3, 4, implicit $eflags
 
   bb.1.not_null:
     liveins: $esi, $rdi
 
     $eax = MOV32ri 2200000
     $eax = ADD32ri killed $eax, 100, implicit-def dead $eflags
     $eax = AND32rm killed $eax, killed $rdi, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load 4 from %ir.x)
     CMP32rr killed $eax, killed $esi, implicit-def $eflags
-    JE_1 %bb.4, implicit $eflags
+    JCC_1 %bb.4, 4, implicit $eflags
 
   bb.2.ret_200:
     $eax = MOV32ri 200
     RETQ $eax
 
   bb.3.is_null:
     $eax = MOV32ri 42
     RETQ $eax
 
   bb.4.ret_100:
     $eax = MOV32ri 100
     RETQ $eax
 
 ...
 ---
 name:            imp_null_check_with_bitwise_op_3
 # CHECK-LABEL: name:            imp_null_check_with_bitwise_op_3
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '$rdi' }
   - { reg: '$rsi' }
 # CHECK:  bb.0.entry:
 # CHECK:    TEST64rr $rdi, $rdi, implicit-def $eflags
-# CHECK-NEXT:    JE_1 %bb.3, implicit $eflags
+# CHECK-NEXT:    JCC_1 %bb.3, 4, implicit $eflags
 
 body:             |
   bb.0.entry:
     liveins: $rsi, $rdi
 
     TEST64rr $rdi, $rdi, implicit-def $eflags
-    JE_1 %bb.3, implicit $eflags
+    JCC_1 %bb.3, 4, implicit $eflags
 
   bb.1.not_null:
     liveins: $rsi, $rdi
 
     $rdi  = MOV64ri 5000
     $rdi = AND64rm killed $rdi, killed $rdi, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load 4 from %ir.x)
     CMP64rr killed $rdi, killed $rsi, implicit-def $eflags
-    JE_1 %bb.4, implicit $eflags
+    JCC_1 %bb.4, 4, implicit $eflags
 
   bb.2.ret_200:
     $eax = MOV32ri 200
     RETQ $eax
 
   bb.3.is_null:
     $eax = MOV32ri 42
     RETQ $eax

 # CHECK:  $rbx = MOV64rr $rdx
 # CHECK-NEXT:  $rbx = FAULTING_OP 1, %bb.3, {{[0-9]+}}, $rbx, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags :: (load 4 from %ir.x)
 
 body:             |
   bb.0.entry:
     liveins: $rsi, $rdi, $rdx
 
     TEST64rr $rdi, $rdi, implicit-def $eflags
-    JE_1 %bb.3, implicit $eflags
+    JCC_1 %bb.3, 4, implicit $eflags
 
   bb.1.not_null:
     liveins: $rsi, $rdi, $rdx
 
     $rbx  = MOV64rr $rdx
     $rbx = AND64rm killed $rbx, killed $rdi, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load 4 from %ir.x)
     $rdx = MOV64ri 0
     CMP64rr killed $rbx, killed $rsi, implicit-def $eflags
-    JE_1 %bb.4, implicit $eflags
+    JCC_1 %bb.4, 4, implicit $eflags
 
   bb.2.ret_200:
     $eax = MOV32ri 200
     RETQ $eax
 
   bb.3.is_null:
     $eax = MOV32ri 42
     RETQ $eax
body:             |
   bb.0.entry:
     liveins: $rdi, $rbx
 
     frame-setup PUSH64r killed $rbx, implicit-def $rsp, implicit $rsp
     CFI_INSTRUCTION def_cfa_offset 16
     CFI_INSTRUCTION offset $rbx, -16
     $rbx = MOV64rr $rdi
     TEST64rr $rbx, $rbx, implicit-def $eflags
-    JE_1 %bb.2, implicit killed $eflags
+    JCC_1 %bb.2, 4, implicit killed $eflags
 
   bb.1.stay:
     liveins: $rbx
 
     CALL64pcrel32 @f, csr_64, implicit $rsp, implicit-def $rsp
     $eax = MOV32rm killed $rbx, 1, $noreg, 0, $noreg :: (load 4 from %ir.ptr)
     $rbx = POP64r implicit-def $rsp, implicit $rsp
     RETQ $eax

 liveins:
   - { reg: '$rdi' }
   - { reg: '$rsi' }
 body:             |
   bb.0.entry:
     liveins: $rdi, $rsi
 
     TEST64rr $rdi, $rdi, implicit-def $eflags
-    JE_1 %bb.2, implicit killed $eflags
+    JCC_1 %bb.2, 4, implicit killed $eflags
 
   bb.1.not_null:
     liveins: $rdi, $rsi
 
     $rcx = MOV64rm killed $rsi, 1, $noreg, 0, $noreg :: (load 8 from %ir.ptr2)
     $esi = MOV32ri 3076
     $eax = BEXTR32rm killed $rdi, 1, $noreg, 0, $noreg, killed $esi, implicit-def dead $eflags :: (load 4 from %ir.ptr)
     $eax = ADD32rm killed $eax, killed $rcx, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load 4 from %ir.val)

 liveins:
   - { reg: '$rdi' }
   - { reg: '$rsi' }
 body:             |
   bb.0.entry:
     liveins: $rdi, $rsi
 
     TEST64rr $rdi, $rdi, implicit-def $eflags
-    JE_1 %bb.2, implicit killed $eflags
+    JCC_1 %bb.2, 4, implicit killed $eflags
 
   bb.1.not_null:
     liveins: $rdi, $rsi
 
     $rcx = MOV64rm killed $rsi, 1, $noreg, 0, $noreg
     $rcx = AND64rm killed $rcx, $rdi, 1, $noreg, 0, $noreg, implicit-def dead $eflags
     $rax = MOV64rm killed $rdi, 1, $noreg, 0, $noreg
     RETQ $eax

 liveins:         
   - { reg: '$rdi' }
   - { reg: '$rsi' }
 body:             |
   bb.0.entry:
     liveins: $rsi, $rdi
   
     TEST64rr $rdi, $rdi, implicit-def $eflags
-    JE_1 %bb.1, implicit $eflags
+    JCC_1 %bb.1, 4, implicit $eflags
   
   bb.2.not_null:
     liveins: $rdi, $rsi
   
     $rsi = ADD64rr $rsi, $rdi, implicit-def dead $eflags
     $eax = MOV32rm killed $rdi, 1, $noreg, 0, $noreg, implicit-def $rax :: (load 4 from %ir.x)
     $eax = LEA64_32r killed $rax, 1, killed $rsi, 4, $noreg
     RETQ $eax

 liveins:         
   - { reg: '$rdi' }
   - { reg: '$rsi' }
 body:             |
   bb.0.entry:
     liveins: $rsi, $rdi
   
     TEST64rr $rdi, $rdi, implicit-def $eflags
-    JE_1 %bb.1, implicit $eflags
+    JCC_1 %bb.1, 4, implicit $eflags
   
   bb.2.not_null:
     liveins: $rdi, $rsi
   
     $rsi = ADD64rr $rsi, $rdi, implicit-def dead $eflags
     $esi = AND32rm killed $esi, $rdi, 1, $noreg, 0, $noreg, implicit-def dead $eflags
     $eax = MOV32rr $esi
     RETQ $eax

 liveins:
   - { reg: '$rdi' }
   - { reg: '$rsi' }
 body:             |
   bb.0.entry:
     liveins: $rdi, $rsi
 
     TEST64rr $rdi, $rdi, implicit-def $eflags
-    JE_1 %bb.2, implicit killed $eflags
+    JCC_1 %bb.2, 4, implicit killed $eflags
 
   bb.1.not_null:
     liveins: $rdi, $rsi
 
     MOV64mr killed $rdi, 1, $noreg, 0, $noreg, killed $rsi
     RETQ
 
   bb.2.is_null:

 liveins:
   - { reg: '$rdi' }
   - { reg: '$rsi' }
 body:             |
   bb.0.entry:
     liveins: $rdi, $rsi
 
     TEST64rr $rdi, $rdi, implicit-def $eflags
-    JE_1 %bb.2, implicit killed $eflags
+    JCC_1 %bb.2, 4, implicit killed $eflags
 
   bb.1.not_null:
     liveins: $rdi, $rsi
 
     MOV64mr killed $rdi, 1, $noreg, 16, $noreg, killed $rsi
     RETQ
 
   bb.2.is_null:

 liveins:
   - { reg: '$rdi' }
   - { reg: '$rsi' }
 body:             |
   bb.0.entry:
     liveins: $rdi, $rsi
 
     TEST64rr $rdi, $rdi, implicit-def $eflags
-    JE_1 %bb.2, implicit killed $eflags
+    JCC_1 %bb.2, 4, implicit killed $eflags
 
   bb.1.not_null:
     liveins: $rdi, $rsi
 
     $esi = ADD32rr killed $esi, killed $esi, implicit-def dead $eflags
     MOV32mr killed $rdi, 1, $noreg, 16, $noreg, killed $esi
     RETQ
 
   bb.2.is_null:
     RETQ
 
 ...
 ---
 name:            inc_store_with_dep_in_null
 # CHECK-LABEL: inc_store_with_dep_in_null
 # CHECK: bb.0.entry:
 # CHECK:    TEST64rr $rdi, $rdi, implicit-def $eflags
-# CHECK-NEXT:    JE_1 %bb.2, implicit killed $eflags
+# CHECK-NEXT:    JCC_1 %bb.2, 4, implicit killed $eflags
 # CHECK: bb.1.not_null
 
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '$rdi' }
   - { reg: '$rsi' }
 body:             |
   bb.0.entry:
     liveins: $rdi, $rsi
 
     TEST64rr $rdi, $rdi, implicit-def $eflags
-    JE_1 %bb.2, implicit killed $eflags
+    JCC_1 %bb.2, 4, implicit killed $eflags
 
   bb.1.not_null:
     liveins: $rdi, $rsi
 
     $esi = ADD32rr $esi, $esi, implicit-def dead $eflags
     MOV32mr killed $rdi, 1, $noreg, 0, $noreg, $esi
     $eax = MOV32rr killed $esi
     RETQ $eax
 
   bb.2.is_null:
     liveins: $rsi
     
     $eax = MOV32rr killed $esi
     RETQ $eax
 
 ...
 ---
 name:            inc_store_with_volatile
 # CHECK-LABEL: inc_store_with_volatile
 # CHECK: bb.0.entry:
 # CHECK:    TEST64rr $rdi, $rdi, implicit-def $eflags
-# CHECK-NEXT:    JE_1 %bb.2, implicit killed $eflags
+# CHECK-NEXT:    JCC_1 %bb.2, 4, implicit killed $eflags
 # CHECK: bb.1.not_null
 
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '$rdi' }
   - { reg: '$rsi' }
 body:             |
   bb.0.entry:
     liveins: $rdi, $rsi
 
     TEST64rr $rdi, $rdi, implicit-def $eflags
-    JE_1 %bb.2, implicit killed $eflags
+    JCC_1 %bb.2, 4, implicit killed $eflags
 
   bb.1.not_null:
     liveins: $rdi, $rsi
 
     MOV32mr killed $rdi, 1, $noreg, 0, $noreg, killed $esi :: (volatile store 4 into %ir.ptr)
     RETQ
 
   bb.2.is_null:
     RETQ
 
 ...
 ---
 name:            inc_store_with_two_dep
 # CHECK-LABEL: inc_store_with_two_dep
 # CHECK: bb.0.entry:
 # CHECK:    TEST64rr $rdi, $rdi, implicit-def $eflags
-# CHECK-NEXT:    JE_1 %bb.2, implicit killed $eflags
+# CHECK-NEXT:    JCC_1 %bb.2, 4, implicit killed $eflags
 # CHECK: bb.1.not_null
 
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '$rdi' }
   - { reg: '$rsi' }
 body:             |
   bb.0.entry:
     liveins: $rdi, $rsi
 
     TEST64rr $rdi, $rdi, implicit-def $eflags
-    JE_1 %bb.2, implicit killed $eflags
+    JCC_1 %bb.2, 4, implicit killed $eflags
 
   bb.1.not_null:
     liveins: $rdi, $rsi
 
     $esi = ADD32rr killed $esi, killed $esi, implicit-def dead $eflags
     $esi = ADD32ri killed $esi, 15, implicit-def dead $eflags
     MOV32mr killed $rdi, 1, $noreg, 16, $noreg, killed $esi
     RETQ
 
   bb.2.is_null:
     RETQ
 
 ...
 ---
 name:            inc_store_with_redefined_base
 # CHECK-LABEL: inc_store_with_redefined_base
 # CHECK: bb.0.entry:
 # CHECK:    TEST64rr $rdi, $rdi, implicit-def $eflags
-# CHECK-NEXT:    JE_1 %bb.2, implicit killed $eflags
+# CHECK-NEXT:    JCC_1 %bb.2, 4, implicit killed $eflags
 # CHECK: bb.1.not_null
 
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '$rdi' }
   - { reg: '$rsi' }
 body:             |
   bb.0.entry:
     liveins: $rdi, $rsi
 
     TEST64rr $rdi, $rdi, implicit-def $eflags
-    JE_1 %bb.2, implicit killed $eflags
+    JCC_1 %bb.2, 4, implicit killed $eflags
 
   bb.1.not_null:
     liveins: $rdi, $rsi
 
     $rdi = ADD64rr killed $rdi, killed $rdi, implicit-def dead $eflags
     MOV32mr killed $rdi, 1, $noreg, 16, $noreg, killed $esi
     RETQ
 

 liveins:
   - { reg: '$rdi' }
   - { reg: '$rsi' }
 body:             |
   bb.0.entry:
     liveins: $rdi, $rsi
 
     TEST64rr $rdi, $rdi, implicit-def $eflags
-    JE_1 %bb.2, implicit killed $eflags
+    JCC_1 %bb.2, 4, implicit killed $eflags
 
   bb.1.not_null:
     liveins: $rdi, $rsi
 
     $rax = MOV64rr $rdi
     MOV32mr killed $rdi, 1, $noreg, 16, $noreg, killed $esi
     RETQ $eax
 
   bb.2.is_null:
     $rax = XOR64rr undef $rax, undef $rax, implicit-def dead $eflags
     RETQ $eax
 
 ...
 ---
 name:            inc_store_across_call
 # CHECK-LABEL: inc_store_across_call
 # CHECK: bb.0.entry:
 # CHECK:    TEST64rr $rbx, $rbx, implicit-def $eflags
-# CHECK-NEXT:    JE_1 %bb.2, implicit killed $eflags
+# CHECK-NEXT:    JCC_1 %bb.2, 4, implicit killed $eflags
 # CHECK: bb.1.not_null
 
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '$rdi' }
 calleeSavedRegisters: [ '$bh', '$bl', '$bp', '$bpl', '$bx', '$ebp', '$ebx',
                         '$rbp', '$rbx', '$r12', '$r13', '$r14', '$r15',
                         '$r12b', '$r13b', '$r14b', '$r15b', '$r12d', '$r13d',
                         '$r14d', '$r15d', '$r12w', '$r13w', '$r14w', '$r15w' ]
 body:             |
   bb.0.entry:
     liveins: $rdi, $rbx
 
     frame-setup PUSH64r killed $rbx, implicit-def $rsp, implicit $rsp
     CFI_INSTRUCTION def_cfa_offset 16
     CFI_INSTRUCTION offset $rbx, -16
     $rbx = MOV64rr killed $rdi
     TEST64rr $rbx, $rbx, implicit-def $eflags
-    JE_1 %bb.2, implicit killed $eflags
+    JCC_1 %bb.2, 4, implicit killed $eflags
 
   bb.1.not_null:
     liveins: $rbx
 
     CALL64pcrel32 @f, csr_64, implicit $rsp, implicit-def $rsp
     MOV32mi $rbx, 1, $noreg, 0, $noreg, 20
     $rax = MOV64rr killed $rbx
     $rbx = POP64r implicit-def $rsp, implicit $rsp
     RETQ $eax
 
   bb.2.is_null:
     $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags
     $rbx = POP64r implicit-def $rsp, implicit $rsp
     RETQ $eax
 
 ...
 ---
 name:            inc_store_with_dep_in_dep
 # CHECK-LABEL: inc_store_with_dep_in_dep
 # CHECK: bb.0.entry:
 # CHECK:    TEST64rr $rdi, $rdi, implicit-def $eflags
-# CHECK-NEXT:    JE_1 %bb.2, implicit killed $eflags
+# CHECK-NEXT:    JCC_1 %bb.2, 4, implicit killed $eflags
 # CHECK: bb.1.not_null
 
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '$rdi' }
   - { reg: '$rsi' }
 body:             |
   bb.0.entry:
     liveins: $rdi, $rsi
 
     TEST64rr $rdi, $rdi, implicit-def $eflags
-    JE_1 %bb.2, implicit killed $eflags
+    JCC_1 %bb.2, 4, implicit killed $eflags
 
   bb.1.not_null:
     liveins: $rdi, $rsi
 
     $eax = MOV32rr $esi
     $esi = ADD32ri killed $esi, 15, implicit-def dead $eflags
     MOV32mr killed $rdi, 1, $noreg, 0, $noreg, killed $esi
     RETQ $eax
 
   bb.2.is_null:
     $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags
     RETQ $eax
 
 ...
 ---
 name:            inc_store_with_load_over_store
 # CHECK-LABEL: inc_store_with_load_over_store
 # CHECK: bb.0.entry:
 # CHECK:    TEST64rr $rdi, $rdi, implicit-def $eflags
-# CHECK-NEXT:    JE_1 %bb.2, implicit killed $eflags
+# CHECK-NEXT:    JCC_1 %bb.2, 4, implicit killed $eflags
 # CHECK: bb.1.not_null
 
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '$rdi' }
   - { reg: '$rsi' }
 body:             |
   bb.0.entry:
     liveins: $rdi, $rsi
 
     TEST64rr $rdi, $rdi, implicit-def $eflags
-    JE_1 %bb.2, implicit killed $eflags
+    JCC_1 %bb.2, 4, implicit killed $eflags
 
   bb.1.not_null:
     liveins: $rdi, $rsi
 
     MOV32mi killed $rsi, 1, $noreg, 0, $noreg, 2
     $eax = MOV32rm killed $rdi, 1, $noreg, 0, $noreg 
     RETQ $eax
 
   bb.2.is_null:
     $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags
     RETQ $eax
 
 ...
 ---
 name:            inc_store_with_store_over_load
 # CHECK-LABEL: inc_store_with_store_over_load
 # CHECK: bb.0.entry:
 # CHECK:    TEST64rr $rdi, $rdi, implicit-def $eflags
-# CHECK-NEXT:    JE_1 %bb.2, implicit killed $eflags
+# CHECK-NEXT:    JCC_1 %bb.2, 4, implicit killed $eflags
 # CHECK: bb.1.not_null
 
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '$rdi' }
   - { reg: '$rsi' }
 body:             |
   bb.0.entry:
     liveins: $rdi, $rsi
 
     TEST64rr $rdi, $rdi, implicit-def $eflags
-    JE_1 %bb.2, implicit killed $eflags
+    JCC_1 %bb.2, 4, implicit killed $eflags
 
   bb.1.not_null:
     liveins: $rdi, $rsi
 
     $eax = MOV32rm killed $rsi, 1, $noreg, 0, $noreg 
     MOV32mi killed $rdi, 1, $noreg, 0, $noreg, 2
     RETQ $eax
 
   bb.2.is_null:
     $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags
     RETQ $eax
 
 ...
 ---
 name:            inc_store_with_store_over_store
 # CHECK-LABEL: inc_store_with_store_over_store
 # CHECK: bb.0.entry:
 # CHECK:    TEST64rr $rdi, $rdi, implicit-def $eflags
-# CHECK-NEXT:    JE_1 %bb.2, implicit killed $eflags
+# CHECK-NEXT:    JCC_1 %bb.2, 4, implicit killed $eflags
 # CHECK: bb.1.not_null
 
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '$rdi' }
   - { reg: '$rsi' }
 body:             |
   bb.0.entry:
     liveins: $rdi, $rsi
 
     TEST64rr $rdi, $rdi, implicit-def $eflags
-    JE_1 %bb.2, implicit killed $eflags
+    JCC_1 %bb.2, 4, implicit killed $eflags
 
   bb.1.not_null:
     liveins: $rdi, $rsi
 
     MOV32mi killed $rsi, 1, $noreg, 0, $noreg, 3 
     MOV32mi killed $rdi, 1, $noreg, 0, $noreg, 2
     RETQ
 

 liveins:
   - { reg: '$rdi' }
   - { reg: '$rsi' }
 body:             |
   bb.0.entry:
     liveins: $rdi, $rsi
 
     TEST64rr $rdi, $rdi, implicit-def $eflags
-    JE_1 %bb.2, implicit killed $eflags
+    JCC_1 %bb.2, 4, implicit killed $eflags
 
   bb.1.not_null:
     liveins: $rdi, $rsi
 
     $esi = ADD32rr $esi, $esi, implicit-def dead $eflags
     ADD32mr killed $rdi, 1, $noreg, 0, $noreg, killed $esi, implicit-def dead $eflags
     RETQ
 

 liveins:
   - { reg: '$rdi' }
   - { reg: '$rsi' }
 body:             |
   bb.0.entry:
     liveins: $rdi, $rsi
 
     TEST64rr $rdi, $rdi, implicit-def $eflags
-    JE_1 %bb.2, implicit killed $eflags
+    JCC_1 %bb.2, 4, implicit killed $eflags
 
   bb.1.not_null:
     liveins: $rdi, $rsi
 
     MOV32mi killed $rsi, 1, $noreg, 0, $noreg, 3 :: (store 4 into %ir.ptr2)
     $eax = MOV32rm killed $rdi, 1, $noreg, 0, $noreg :: (load 4 from %ir.ptr)
     RETQ $eax
 
   bb.2.is_null:
     $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags
     RETQ $eax
 
 ...
 ---
 name:            inc_store_and_load_alias
 # CHECK-LABEL: inc_store_and_load_alias
 # CHECK: bb.0.entry:
 # CHECK:    TEST64rr $rdi, $rdi, implicit-def $eflags
-# CHECK-NEXT:    JE_1 %bb.2, implicit killed $eflags
+# CHECK-NEXT:    JCC_1 %bb.2, 4, implicit killed $eflags
 # CHECK: bb.1.not_null
 
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '$rdi' }
   - { reg: '$rsi' }
 body:             |
   bb.0.entry:
     liveins: $rdi, $rsi
 
     TEST64rr $rdi, $rdi, implicit-def $eflags
-    JE_1 %bb.2, implicit killed $eflags
+    JCC_1 %bb.2, 4, implicit killed $eflags
 
   bb.1.not_null:
     liveins: $rdi, $rsi
 
     MOV32mi killed $rsi, 1, $noreg, 0, $noreg, 3 :: (store 4 into %ir.ptr2)
     $eax = MOV32rm killed $rdi, 1, $noreg, 0, $noreg :: (load 4 from %ir.ptr)
     RETQ $eax
 
   bb.2.is_null:
     $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags
     RETQ $eax
 
 ...
 ---
 name:            inc_spill_dep
 # CHECK-LABEL: inc_spill_dep
 # CHECK: bb.0.entry:
 # CHECK:    TEST64rr $rdi, $rdi, implicit-def $eflags
-# CHECK-NEXT:    JE_1 %bb.2, implicit killed $eflags
+# CHECK-NEXT:    JCC_1 %bb.2, 4, implicit killed $eflags
 # CHECK: bb.1.not_null
 
 alignment:       4
 tracksRegLiveness: true
 stack:
   - { id: 0, type: spill-slot, offset: -8, size: 8, alignment: 8}
 liveins:
   - { reg: '$rdi' }
   - { reg: '$rsi' }
 body:             |
   bb.0.entry:
     liveins: $rdi, $rsi
 
     $rsp = frame-setup SUB64ri8 $rsp, 8, implicit-def dead $eflags
     MOV32mr $rsp, 1, $noreg, 0, $noreg, $esi :: (store 4 into %stack.0)
     TEST64rr $rdi, $rdi, implicit-def $eflags
-    JE_1 %bb.2, implicit killed $eflags
+    JCC_1 %bb.2, 4, implicit killed $eflags
 
   bb.1.not_null:
     liveins: $rdi, $rsi
 
     $r14d = MOV32rm $rsp, 1, $noreg, 0, $noreg :: (load 4 from %stack.0)
     MOV64mr $rsp, 1, $noreg, 0, $noreg, $rdi :: (store 8 into %stack.0)
     $edi = MOV32rm $rdi, 1, $noreg, 8, $noreg :: (load 4 from %ir.ptr)
     $eax = MOV32rr $edi
     RETQ $eax
 
   bb.2.is_null:
     $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags
     RETQ $eax
 
 ...

llvm/test/CodeGen/X86/implicit-null-chk-reg-rewrite.mir

 body:             |
   bb.0.entry:
     liveins: $rdi
 
     TEST64rr $rdi, $rdi, implicit-def $eflags
     ; CHECK-LABEL: bb.0.entry
     ; CHECK-NOT: FAULTING_OP
     renamable $rdi = MOV64ri 5000
-    JE_1 %bb.2, implicit $eflags
+    JCC_1 %bb.2, 4, implicit $eflags
 
   bb.1.not_null:
     liveins: $rdi, $rsi
     
     $rax = MOV64rm renamable $rdi, 1, $noreg, 4, $noreg
     RETQ $eax
 
   bb.2.is_null:
     $eax = MOV32ri 200
     RETQ $eax
 ...

llvm/test/CodeGen/X86/invalid-liveness.mir

 #
 # CHECK: Use of %0 does not have a corresponding definition on every path
 # CHECK: ERROR: Use not jointly dominated by defs.
 name: func
 registers:
   - { id: 0, class: gr32 }
 body: |
   bb.0:
-    JG_1 %bb.2, implicit $eflags
+    JCC_1 %bb.2, 15, implicit $eflags
     JMP_1 %bb.3
 
   bb.2:
     %0 = IMPLICIT_DEF
     JMP_1 %bb.3
 
   bb.3:
     $eax = COPY %0
     RETQ $eax
 ...

llvm/test/CodeGen/X86/late-remat-update-2.mir

 ---
 name:            foo
 body:             |
   bb.0.entry:
     successors: %bb.1(0x15555555), %bb.2(0x6aaaaaab)
 
     %t1:gr64 = MOV64ri32 -11
     CMP64ri8 %t1, 1, implicit-def $eflags
-    JE_1 %bb.2, implicit killed $eflags
+    JCC_1 %bb.2, 4, implicit killed $eflags
     JMP_1 %bb.1
 
   bb.1:
     successors: %bb.1(0x80000000)
 
     %t2:gr64 = COPY %t1
     %t2:gr64 = ADD64ri8 %t2, 5, implicit-def $eflags
     $rax = COPY %t2
     CMP64ri8 %t2, 1, implicit-def $eflags
-    JE_1 %bb.1, implicit killed $eflags
+    JCC_1 %bb.1, 4, implicit killed $eflags
     RET 0, $rax
 
   bb.2:
     successors: %bb.3(0x80000000)
     %t3:gr64 = COPY %t1
     %t3:gr64 = ADD64ri8 %t3, 10, implicit-def $eflags
 
   bb.3:
     $rax = COPY %t3
     RET 0, $rax
 
 ...

llvm/test/CodeGen/X86/late-remat-update.mir

bb.0.entry:
     %0:gr32 = COPY killed $edi
     %5:gr32 = MOV32ri 2122
   
   bb.1.do.body:
     successors: %bb.6(0x15555555), %bb.2(0x6aaaaaab)
   
     INLINEASM &"", 1, 12, implicit-def dead early-clobber $r10, 12, implicit-def dead early-clobber $r11, 12, implicit-def dead early-clobber $r12, 12, implicit-def dead early-clobber $r13, 12, implicit-def dead early-clobber $r14, 12, implicit-def dead early-clobber $r15, 12, implicit-def dead early-clobber $eflags, !3
     CMP32ri8 %0, 2, implicit-def $eflags
-    JE_1 %bb.6, implicit killed $eflags
+    JCC_1 %bb.6, 4, implicit killed $eflags
     JMP_1 %bb.2
   
   bb.2.do.body:
     successors: %bb.5(0x19999999), %bb.3(0x66666667)
   
     CMP32ri8 %0, 1, implicit-def $eflags
-    JE_1 %bb.5, implicit killed $eflags
+    JCC_1 %bb.5, 4, implicit killed $eflags
     JMP_1 %bb.3
   
   bb.3.do.body:
     successors: %bb.4(0x20000000), %bb.1(0x60000000)
   
     TEST32rr %0, %0, implicit-def $eflags
-    JNE_1 %bb.1, implicit killed $eflags
+    JCC_1 %bb.1, 5, implicit killed $eflags
     JMP_1 %bb.4
   
   bb.4.sw.bb:
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
     $edi = COPY %5
     CALL64pcrel32 @_Z3gooi, csr_64, implicit $rsp, implicit $ssp, implicit killed $edi, implicit-def $rsp, implicit-def $ssp
     ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
   

llvm/test/CodeGen/X86/leaFixup32.mir

body:             |
   bb.0 (%ir-block.0):
     liveins: $eax, $ebp, $ebx
     ; CHECK: $ebx = LEA32r killed $eax, 4, killed $eax, 5, $noreg
     ; CHECK: $ebp = LEA32r killed $ebx, 4, killed $ebx, 0, $noreg
     ; CHECK: $ebp = ADD32ri8 $ebp, 5
    
     CMP32rr   $eax, killed $ebx, implicit-def $eflags
     $ebx = LEA32r killed $eax, 4, killed $eax, 5, $noreg
-    JE_1 %bb.1, implicit $eflags
+    JCC_1 %bb.1, 4, implicit $eflags
     RETQ $ebx
   bb.1:
     liveins: $eax, $ebp, $ebx
     $ebp = LEA32r killed $ebx, 4, killed $ebx, 5, $noreg
     RETQ $ebp
 
 ...
 
 
 

llvm/test/CodeGen/X86/leaFixup64.mir

body:             |
   bb.0 (%ir-block.0):
     liveins: $rax, $rbp, $rbx
     ; CHECK: $rbx = LEA64r killed $rax, 4, killed $rax, 5, $noreg
     ; CHECK: $rbp = LEA64r killed $rbx, 4, killed $rbx, 0, $noreg
     ; CHECK: $rbp = ADD64ri8 $rbp, 5
    
     CMP64rr   $rax, killed $rbx, implicit-def $eflags
     $rbx = LEA64r killed $rax, 4, killed $rax, 5, $noreg
-    JE_1 %bb.1, implicit $eflags
+    JCC_1 %bb.1, 4, implicit $eflags
     RETQ $ebx
   bb.1:
     liveins: $rax, $rbp, $rbx
     $rbp = LEA64r killed $rbx, 4, killed $rbx, 5, $noreg
     RETQ $ebp
 
 ...
 ---
body:             |
   bb.0 (%ir-block.0):
     liveins: $rax, $rbp, $rbx
     ; CHECK: $ebx = LEA64_32r killed $rax, 4, killed $rax, 5, $noreg
     ; CHECK: $ebp = LEA64_32r killed $rbx, 4, killed $rbx, 0, $noreg
     ; CHECK: $ebp = ADD32ri8 $ebp, 5
    
     CMP64rr   $rax, killed $rbx, implicit-def $eflags
     $ebx = LEA64_32r killed $rax, 4, killed $rax, 5, $noreg
-    JE_1 %bb.1, implicit $eflags
+    JCC_1 %bb.1, 4, implicit $eflags
     RETQ $ebx
   bb.1:
     liveins: $rax, $rbp, $rbx
     $ebp = LEA64_32r killed $rbx, 4, killed $rbx, 5, $noreg
     RETQ $ebp
 
 ...
 
 
 

llvm/test/CodeGen/X86/limit-split-cost.mir

bb.0.entry:
     %4:gr64 = LEA64r $rip, 1, $noreg, @.str.1, $noreg
     %3:gr64 = LEA64r $rip, 1, $noreg, @.str, $noreg
   
   bb.1.do.body:
     successors: %bb.6(0x20000000), %bb.2(0x60000000)
   
     INLINEASM &"", 1, 12, implicit-def dead early-clobber $r10, 12, implicit-def dead early-clobber $r11, 12, implicit-def dead early-clobber $r12, 12, implicit-def dead early-clobber $r13, 12, implicit-def dead early-clobber $r14, 12, implicit-def dead early-clobber $r15, 12, implicit-def dead early-clobber $eflags, !3
     CMP32ri8 %0, 2, implicit-def $eflags
-    JE_1 %bb.6, implicit killed $eflags
+    JCC_1 %bb.6, 4, implicit killed $eflags
     JMP_1 %bb.2
   
   bb.2.do.body:
     successors: %bb.5(0x2aaaaaab), %bb.3(0x55555555)
   
     CMP32ri8 %0, 1, implicit-def $eflags
-    JE_1 %bb.5, implicit killed $eflags
+    JCC_1 %bb.5, 4, implicit killed $eflags
     JMP_1 %bb.3
   
   bb.3.do.body:
     successors: %bb.4, %bb.7
   
     TEST32rr %0, %0, implicit-def $eflags
-    JNE_1 %bb.7, implicit killed $eflags
+    JCC_1 %bb.7, 5, implicit killed $eflags
     JMP_1 %bb.4
   
   bb.4.sw.bb:
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
     $rdi = COPY %3
     CALL64pcrel32 target-flags(x86-plt) @_Z3gooPKc, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp
     ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
   
   bb.5.sw.bb1:
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
     $rdi = COPY %4
     CALL64pcrel32 target-flags(x86-plt) @_Z3gooPKc, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp
     ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
   
   bb.6.sw.bb2:
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
     $rdi = COPY %5
     CALL64pcrel32 target-flags(x86-plt) @_Z3gooPKc, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp
     ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
   
   bb.7.do.cond:
     successors: %bb.8(0x04000000), %bb.1(0x7c000000)
   
     CMP32mi8 %6, 1, $noreg, 0, $noreg, 5, implicit-def $eflags :: (dereferenceable load 4 from @m, !tbaa !4)
-    JNE_1 %bb.1, implicit killed $eflags
+    JCC_1 %bb.1, 5, implicit killed $eflags
     JMP_1 %bb.8
   
   bb.8.do.end:
     RET 0
 
 ...

llvm/test/CodeGen/X86/machine-region-info.mir

 # RUN: llc -mtriple=x86_64-- -run-pass=machine-region-info %s -debug-only=machine-region-info -o /dev/null 2>&1 | FileCheck %s
 # REQUIRES: asserts
 ---
 name:            fun
 body:             |
   bb.0:
     CMP32ri8 $edi, 40, implicit-def $eflags
-    JNE_1 %bb.7, implicit killed $eflags
+    JCC_1 %bb.7, 5, implicit killed $eflags
     JMP_1 %bb.1
 
   bb.1:
     CMP32ri8 $edi, 1, implicit-def $eflags
-    JNE_1 %bb.11, implicit killed $eflags
+    JCC_1 %bb.11, 5, implicit killed $eflags
     JMP_1 %bb.2
 
   bb.2:
     CMP32ri8 $edi, 2, implicit-def $eflags
-    JNE_1 %bb.5, implicit killed $eflags
+    JCC_1 %bb.5, 5, implicit killed $eflags
     JMP_1 %bb.3
 
   bb.3:
     CMP32ri8 $edi, 90, implicit-def $eflags
-    JNE_1 %bb.5, implicit killed $eflags
+    JCC_1 %bb.5, 5, implicit killed $eflags
     JMP_1 %bb.4
 
   bb.4:
 
   bb.5:
     CMP32ri8 $edi, 4, implicit-def $eflags
-    JNE_1 %bb.11, implicit killed $eflags
+    JCC_1 %bb.11, 5, implicit killed $eflags
     JMP_1 %bb.6
 
   bb.6:
     JMP_1 %bb.11
 
   bb.7:
     CMP32ri8 $edi, 5, implicit-def $eflags
-    JE_1 %bb.9, implicit killed $eflags
+    JCC_1 %bb.9, 4, implicit killed $eflags
     JMP_1 %bb.8
 
   bb.8:
 
   bb.9:
     CMP32ri8 $edi, 6, implicit-def $eflags
-    JE_1 %bb.11, implicit killed $eflags
+    JCC_1 %bb.11, 4, implicit killed $eflags
     JMP_1 %bb.10
 
   bb.10:
 
   bb.11:
     RET 0
 
 ...

llvm/test/CodeGen/X86/non-value-mem-operand.mir

bb.0.bb:
     frame-setup PUSH64r killed $r15, implicit-def $rsp, implicit $rsp
     frame-setup PUSH64r killed $r14, implicit-def $rsp, implicit $rsp
     frame-setup PUSH64r killed $r13, implicit-def $rsp, implicit $rsp
     frame-setup PUSH64r killed $r12, implicit-def $rsp, implicit $rsp
     frame-setup PUSH64r killed $rbx, implicit-def $rsp, implicit $rsp
     $rsp = frame-setup SUB64ri8 $rsp, 56, implicit-def dead $eflags
     CALL64r undef $rax, csr_64, implicit $rsp, implicit undef $rdi, implicit undef $rsi, implicit-def $rsp, implicit-def $rax
     TEST64rr $rax, $rax, implicit-def $eflags
-    JNE_1 %bb.3.bb3, implicit killed $eflags
+    JCC_1 %bb.3.bb3, 5, implicit killed $eflags
   
   bb.1.bb2:
     successors: %bb.2(0x40000000), %bb.13.bb59(0x40000000)
   
     $ebp = XOR32rr undef $ebp, undef $ebp, implicit-def dead $eflags
     TEST8rr $bpl, $bpl, implicit-def $eflags
-    JE_1 %bb.13.bb59, implicit killed $eflags
+    JCC_1 %bb.13.bb59, 4, implicit killed $eflags
   
   bb.2:
     successors: %bb.12.bb51(0x80000000)
     liveins: $ebp
   
     $xmm0 = XORPSrr undef $xmm0, undef $xmm0
     $ebx = IMPLICIT_DEF implicit-def $rbx
     JMP_1 %bb.12.bb51
body:             |
   bb.4.bb7:
     successors: %bb.6.bb26(0x40000000), %bb.5.bb15(0x40000000)
     liveins: $eax, $ecx, $esi, $r12, $xmm0
   
     $ebp = MOV32rr killed $ecx
     $ebx = MOV32rr killed $eax, implicit-def $rbx
     $r14d = MOV32rr $ebx, implicit-def $r14
     TEST8rr $sil, $sil, implicit-def $eflags
-    JNE_1 %bb.6.bb26, implicit $eflags
+    JCC_1 %bb.6.bb26, 5, implicit $eflags
   
   bb.5.bb15:
     successors: %bb.6.bb26(0x80000000)
     liveins: $ebp, $rbx, $r14, $xmm0
   
     MOV32mr $rsp, 1, $noreg, 24, $noreg, $ebx :: (store 4 into %stack.0, align 8)
     MOV32mr $rsp, 1, $noreg, 16, $noreg, $ebp :: (store 4 into %stack.1, align 8)
     MOVSDmr $rsp, 1, $noreg, 8, $noreg, killed $xmm0 :: (store 8 into %stack.2)
bb.6.bb26:
     $rdx = MOV64rm $r12, 8, $r14, 0, $noreg :: (load 8 from %ir.tmp3)
     $r15 = LEA64r $rdx, 1, $noreg, 1, _
     MOV64mr $r12, 8, $r14, 0, $noreg, $r15 :: (store 8 into %ir.tmp3)
     $ecx = SUB32rr killed $ecx, $edx, implicit-def dead $eflags, implicit killed $rdx
     MOV32mr undef $rax, 1, $noreg, 0, $noreg, killed $ecx :: (store 4 into `i32* undef`)
     $r13 = MOV64rm killed $rax, 1, $noreg, 768, $noreg :: (load 8 from %ir.tmp33)
     TEST8rr $sil, $sil, implicit-def $eflags
     $rax = IMPLICIT_DEF
-    JNE_1 %bb.8.bb37, implicit $eflags
+    JCC_1 %bb.8.bb37, 5, implicit $eflags
   
   bb.7.bb35:
     successors: %bb.8.bb37(0x80000000)
     liveins: $ebp, $rbx, $r12, $r13, $r14, $r15
   
     $rsi = MOV64ri @global
     $rax = MOV64ri @ham
     CALL64r killed $rax, csr_64, implicit $rsp, implicit undef $rdi, implicit $rsi, implicit-def $rsp, implicit-def $rax
     $esi = XOR32rr undef $esi, undef $esi, implicit-def dead $eflags
   
   bb.8.bb37:
     successors: %bb.9.bb37(0x40000000), %bb.10.bb37(0x40000000)
     liveins: $ebp, $esi, $rax, $rbx, $r12, $r13, $r14, $r15
   
     $rcx = MOV64rm killed $rax, 1, $noreg, 760, $noreg :: (load 8 from %ir.tmp40)
     CMP64rr $r13, $rcx, implicit-def $eflags
-    JL_1 %bb.10.bb37, implicit $eflags
+    JCC_1 %bb.10.bb37, 12, implicit $eflags
   
   bb.9.bb37:
     successors: %bb.10.bb37(0x80000000)
     liveins: $ebp, $esi, $rbx, $r12, $r13, $r14, $r15
   
     $cl = MOV8rr $r13b, implicit killed $r13, implicit-def $rcx
   
   bb.10.bb37:
     successors: %bb.11.bb51.loopexit(0x00000800), %bb.4.bb7(0x7ffff800)
     liveins: $ebp, $esi, $rbx, $rcx, $r12, $r14, $r15
   
     $cl = KILL $cl, implicit killed $rcx
     $r15 = SAR64rCL killed $r15, implicit-def dead $eflags, implicit $cl
     MOV64mr $r12, 8, killed $r14, 0, $noreg, killed $r15 :: (store 8 into %ir.tmp7)
     MOV64mi32 undef $rax, 1, $noreg, 0, $noreg, 0 :: (store 8 into `i64* undef`)
     $eax = LEA64_32r $rbx, 1, $noreg, 1, _
     $ecx = MOV32ri 6
     CMP32ri $eax, 15141, implicit-def $eflags
     $xmm0 = MOVSDrm $rsp, 1, $noreg, 40, $noreg :: (load 8 from %stack.4)
-    JL_1 %bb.4.bb7, implicit $eflags
+    JCC_1 %bb.4.bb7, 12, implicit $eflags
   
   bb.11.bb51.loopexit:
     successors: %bb.12.bb51(0x80000000)
     liveins: $ebp, $rbx
   
     $ebp = INC32r killed $ebp, implicit-def dead $eflags
     $ebx = INC32r $ebx, implicit-def dead $eflags, implicit killed $rbx, implicit-def $rbx
     $rax = MOV64ri %const.0

llvm/test/CodeGen/X86/opt_phis2.mir

bb.0:
     %7:gr32 = COPY $edi
     %11:gr32 = SAR32ri %7, 31, implicit-def dead $eflags
     %12:gr32 = SHR32ri %11, 30, implicit-def dead $eflags
     %13:gr32 = ADD32rr %7, killed %12, implicit-def dead $eflags
     %14:gr32 = AND32ri8 %13, -4, implicit-def dead $eflags
     %15:gr32 = SUB32rr %7, %14, implicit-def dead $eflags
     %10:gr64_nosp = SUBREG_TO_REG 0, %15, %subreg.sub_32bit
     %16:gr32 = SUB32ri8 %15, 3, implicit-def $eflags
-    JA_1 %bb.8, implicit $eflags
+    JCC_1 %bb.8, 7, implicit $eflags
 
   bb.9:
     JMP64m $noreg, 8, %10, %jump-table.0, $noreg :: (load 8 from jump-table)
 
   bb.1:
     %0:vr256 = COPY %8
     JMP_1 %bb.5
 

llvm/test/CodeGen/X86/peephole-recurrence.mir

body:             |
 
   bb.1.bb1:
     successors: %bb.3(0x30000000), %bb.2(0x50000000)
 
     ; CHECK: %0:gr32 = PHI %5, %bb.0, %3, %bb.5
     %0 = PHI %5, %bb.0, %3, %bb.5
     %6 = MOV32ri 1
     TEST32rr %4, %4, implicit-def $eflags
-    JE_1 %bb.3, implicit $eflags
+    JCC_1 %bb.3, 4, implicit $eflags
     JMP_1 %bb.2
 
   bb.2.bb3:
     successors: %bb.3(0x80000000)
 
     %7 = MOV32ri 2
 
   bb.3.bb4:
     successors: %bb.5(0x30000000), %bb.4(0x50000000)
 
     %1 = PHI %6, %bb.1, %7, %bb.2
     TEST32rr %1, %1, implicit-def $eflags
-    JE_1 %bb.5, implicit $eflags
+    JCC_1 %bb.5, 4, implicit $eflags
     JMP_1 %bb.4
 
   bb.4.bb6:
     successors: %bb.5(0x80000000)
 
     %9 = MOV32ri 2
 
   bb.5.bb7:
     successors: %bb.1(0x7c000000), %bb.6(0x04000000)
 
     %2 = PHI %6, %bb.3, %9, %bb.4
     %10 = ADD32rr %1, %0, implicit-def dead $eflags
     ; CHECK: %10:gr32 = ADD32rr
     ; CHECK-SAME: %0,
     ; CHECK-SAME: %1,
     %3 = ADD32rr %2, killed %10, implicit-def dead $eflags
     ; CHECK: %3:gr32 = ADD32rr
     ; CHECK-SAME: %10,
     ; CHECK-SAME: %2,
     %11 = SUB32ri8 %3, 10, implicit-def $eflags
-    JL_1 %bb.1, implicit $eflags
+    JCC_1 %bb.1, 12, implicit $eflags
     JMP_1 %bb.6
 
   bb.6.bb8:
     %12 = MOV32r0 implicit-def dead $eflags
     $eax = COPY %12
     RET 0, $eax
 
 ...
body:             |
 
   bb.1.bb1:
     successors: %bb.3(0x30000000), %bb.2(0x50000000)
 
     %0 = PHI %6, %bb.0, %3, %bb.5
     ; CHECK: %0:gr32 = PHI %6, %bb.0, %3, %bb.5
     %7 = MOV32ri 1
     TEST32rr %4, %4, implicit-def $eflags
-    JE_1 %bb.3, implicit $eflags
+    JCC_1 %bb.3, 4, implicit $eflags
     JMP_1 %bb.2
 
   bb.2.bb3:
     successors: %bb.3(0x80000000)
 
     %8 = MOV32ri 2
 
   bb.3.bb4:
     successors: %bb.5(0x30000000), %bb.4(0x50000000)
 
     %1 = PHI %7, %bb.1, %8, %bb.2
     TEST32rr %1, %1, implicit-def $eflags
-    JE_1 %bb.5, implicit $eflags
+    JCC_1 %bb.5, 4, implicit $eflags
     JMP_1 %bb.4
 
   bb.4.bb6:
     successors: %bb.5(0x80000000)
 
     %10 = MOV32ri 2
 
   bb.5.bb7:
     successors: %bb.1(0x7c000000), %bb.6(0x04000000)
 
     %2 = PHI %7, %bb.3, %10, %bb.4
     %11 = ADD32rr %1, %0, implicit-def dead $eflags
     ; CHECK: %11:gr32 = ADD32rr
     ; CHECK-SAME: %1,
     ; CHECK-SAME: %0,
     MOV32mr %5, 1, $noreg, 0, $noreg, %0 :: (store 4 into %ir.p)
     %3 = ADD32rr %2, killed %11, implicit-def dead $eflags
     ; CHECK: %3:gr32 = ADD32rr
     ; CHECK-SAME: %2,
     ; CHECK-SAME: %11,
     %12 = SUB32ri8 %3, 10, implicit-def $eflags
-    JL_1 %bb.1, implicit $eflags
+    JCC_1 %bb.1, 12, implicit $eflags
     JMP_1 %bb.6
 
   bb.6.bb8:
     %13 = MOV32r0 implicit-def dead $eflags
     $eax = COPY %13
     RET 0, $eax
 
 ...

llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir

bb.0:
     $rcx = LEA64r $rbp, 1, $noreg, -20, $noreg
     DBG_VALUE $rcx, $noreg, !46, !17, debug-location !48
     DBG_VALUE $rcx, $noreg, !39, !17, debug-location !44
     DBG_VALUE $rbp, -20, !29, !17, debug-location !36
     $rcx = CMOV64rr killed $rcx, killed $rdx, 5, implicit killed $eflags
     $rcx = OR64rr killed $rcx, killed $rsi, implicit-def dead $eflags
     $rdx = MOVSX64rm32 $rbx, 1, $noreg, 0, $noreg :: (load 4, align 8)
     TEST32mr killed $rcx, 4, killed $rdx, 0, $noreg, killed $eax, implicit-def $eflags :: (load 4)
-    JNE_1 %bb.2, implicit $eflags
+    JCC_1 %bb.2, 5, implicit $eflags
     JMP_1 %bb.3
 
   bb.1:
     successors: %bb.2
     liveins: $rbx, $rbp
 
     $rdi = MOV64rm $rbx, 1, $noreg, 24, $noreg :: (load 8)
 
   bb.2:
     successors: %bb.1, %bb.3
     liveins: $rbx, $rbp, $rsp, $rdi
 
     CALL64pcrel32 @_ZN1p2aaEv, csr_64, implicit $rsp, implicit $rdi, implicit-def $rsp, implicit-def $eax
     $eax = KILL $eax, implicit-def $rax
     $ecx = LEA64_32r $rax, 1, $noreg, -1, $noreg, implicit-def $rcx
     $ecx = SHR32ri $ecx, 31, implicit-def dead $eflags, implicit killed $rcx, implicit-def $rcx
     $eax = LEA64_32r killed $rax, 1, killed $rcx, -1, $noreg
     $eax = SAR32r1 killed $eax, implicit-def dead $eflags
     CMP32mr $rbx, 1, $noreg, 0, $noreg, killed $eax, implicit-def $eflags :: (load 4, align 8), (load 4, align 8)
-    JG_1 %bb.1, implicit killed $eflags
+    JCC_1 %bb.1, 15, implicit killed $eflags
 
   bb.3:
     liveins: $rbp
 
     $rsp = ADD64ri8 $rsp, 16, implicit-def dead $eflags
     $rbx = POP64r implicit-def $rsp, implicit $rsp
     $r14 = POP64r implicit-def $rsp, implicit $rsp
     $rbp = POP64r implicit-def $rsp, implicit $rsp
     RETQ
 
 ...

llvm/test/CodeGen/X86/postra-ignore-dbg-instrs.mir

 body: |
   bb.0:
     successors: %bb.2, %bb.1; %bb.2, %bb.1
     liveins: $edi
     DBG_VALUE $edi, $noreg, !14, !DIExpression(), debug-location !16
     renamable $eax = COPY $edi
     DBG_VALUE $eax, $noreg, !14, !DIExpression(), debug-location !16
     CMP32mi8 $rip, 1, $noreg, @x0, $noreg, 0, implicit-def $eflags, debug-location !16
-    JE_1 %bb.2, implicit killed $eflags, debug-location !16
+    JCC_1 %bb.2, 4, implicit killed $eflags, debug-location !16
     JMP_1 %bb.1, debug-location !16
 
   bb.1:
     liveins: $eax
     $edi = MOV32r0 implicit-def dead $eflags, debug-location !16
     $esi = COPY killed renamable $eax, debug-location !16
 
   bb.2:
     RET 0, debug-location !16
 ...

llvm/test/CodeGen/X86/pr27681.mir

bb.1:
     TEST32rr killed $edx, $edx, implicit-def $eflags
     $cl = SETCCr 5, implicit $eflags
     ; Verify that removal of the $bl antidependence does not use $ch
     ; as a replacement register.
     ; CHECK: $cl = AND8rr killed $cl, killed $b
     $cl = AND8rr killed $cl, killed $bl, implicit-def dead $eflags
     CMP32ri8 $ebp, -1, implicit-def $eflags
     $edx = MOV32ri 0
-    JE_1 %bb.3, implicit $eflags
+    JCC_1 %bb.3, 4, implicit $eflags
 
   bb.2:
     liveins: $cl, $eax, $ebp, $esi
 
     OR32mr $esp, 1, $noreg, 8, $noreg, killed $eax, implicit-def $eflags ; :: (store 4 into %stack.1)
     $dl = SETCCr 5, implicit $eflags, implicit-def $edx
 
   bb.3:

llvm/test/CodeGen/X86/pr38952.mir

body:             |
   ; Test that the DBG_VALUE on ebx below is sunk with the def of ebx, despite
   ; not being adjacent to the def, see PR38952
 
     DBG_VALUE $edi, $noreg, !21, !DIExpression()
     renamable $ebx = COPY $edi
     renamable $eax = MOV32r0 implicit-def dead $eflags
     DBG_VALUE $ebx, $noreg, !21, !DIExpression()
     CMP32ri $edi, 255, implicit-def $eflags
-    JG_1 %bb.2, implicit killed $eflags
+    JCC_1 %bb.2, 15, implicit killed $eflags
     JMP_1 %bb.1
   
   bb.1.if.end:
   ; CHECK-LABEL: bb.1.if.end
     successors: %bb.2(0x80000000)
     liveins: $ebx
   
   ; CHECK: $ebx = COPY $edi

llvm/test/CodeGen/X86/pre-coalesce.mir

 
 ...
 ---
 # Check A = B and B = A copies will not exist in the loop at the same time.
 # CHECK: name: foo
 # CHECK: [[L1:bb.3]].{{[a-zA-Z0-9.]+}}:
 # CHECK: %[[REGA:.*]] = COPY %[[REGB:.*]]
 # CHECK-NOT: %[[REGB]] = COPY %[[REGA]]
-# CHECK: JNE_1 %[[L1]]
+# CHECK: JCC_1 %[[L1]], 5
 
 name:            foo
 alignment:       4
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
frameInfo:
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
 body:             |
   bb.0.entry:
     %0 = MOV64rm $rip, 1, $noreg, @b, $noreg :: (dereferenceable load 8 from @b)
     %12 = MOV8rm %0, 1, $noreg, 0, $noreg :: (load 1 from %ir.t0)
     TEST8rr %12, %12, implicit-def $eflags
     %11 = MOV32rm $rip, 1, $noreg, @a, $noreg :: (dereferenceable load 4 from @a)
-    JNE_1 %bb.1, implicit killed $eflags
+    JCC_1 %bb.1, 5, implicit killed $eflags
   
   bb.4:
     %10 = COPY %11
     JMP_1 %bb.3
   
   bb.1.while.body.preheader:
 
   bb.2.while.body:
     %8 = MOVSX32rr8 %12
     %10 = COPY %11
     %10 = SHL32ri %10, 5, implicit-def dead $eflags
     %10 = ADD32rr %10, %11, implicit-def dead $eflags
     %10 = ADD32rr %10, %8, implicit-def dead $eflags
     MOV32mr $rip, 1, $noreg, @a, $noreg, %10 :: (store 4 into @a)
     %12 = MOV8rm %0, 1, $noreg, 0, $noreg :: (load 1 from %ir.t0)
     TEST8rr %12, %12, implicit-def $eflags
     %11 = COPY %10
-    JNE_1 %bb.2, implicit killed $eflags
+    JCC_1 %bb.2, 5, implicit killed $eflags
     JMP_1 %bb.3
   
   bb.3.while.end:
     $eax = COPY %10
     RET 0, killed $eax
 
 ...

llvm/test/CodeGen/X86/regalloc-copy-hints.mir

 fixedStack:      
   - { id: 0, size: 4, alignment: 4, stack-id: 0, isImmutable: true }
 body:             |
   bb.0:
     successors: %bb.1(0x00000001), %bb.2(0x7fffffff)
   
     %13:gr32_abcd = MOV32r0 implicit-def dead $eflags
     TEST8rr %13.sub_8bit, %13.sub_8bit, implicit-def $eflags
-    JNE_1 %bb.2, implicit killed $eflags
+    JCC_1 %bb.2, 5, implicit killed $eflags
     JMP_1 %bb.1
   
   bb.1:
     successors: 
   
   
   bb.2:
     successors: %bb.4(0x7fffffff), %bb.3(0x00000001)
   
     %15:gr32_abcd = MOV32r0 implicit-def dead $eflags
     TEST8rr %15.sub_8bit, %15.sub_8bit, implicit-def $eflags
-    JNE_1 %bb.4, implicit killed $eflags
+    JCC_1 %bb.4, 5, implicit killed $eflags
     JMP_1 %bb.3
   
   bb.3:
     successors: 
   
   
   bb.4:
     successors: %bb.6(0x7fffffff), %bb.5(0x00000001)
   
     %12:gr32 = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg
     %1:gr32 = LEA32r %12, 1, $noreg, 144, $noreg
     MOV32mr undef %17:gr32, 1, $noreg, 0, $noreg, %1
     %18:gr32_abcd = MOV32r0 implicit-def dead $eflags
     TEST8rr %18.sub_8bit, %18.sub_8bit, implicit-def $eflags
-    JNE_1 %bb.6, implicit killed $eflags
+    JCC_1 %bb.6, 5, implicit killed $eflags
     JMP_1 %bb.5
   
   bb.5:
     successors: 
   
   
   bb.6:
     successors: %bb.7(0x00000001), %bb.8(0x7fffffff)
   
     %20:gr32_abcd = MOV32r0 implicit-def dead $eflags
     TEST8rr %20.sub_8bit, %20.sub_8bit, implicit-def $eflags
-    JNE_1 %bb.8, implicit killed $eflags
+    JCC_1 %bb.8, 5, implicit killed $eflags
     JMP_1 %bb.7
   
   bb.7:
     successors: 
   
   
   bb.8:
     successors: %bb.10(0x7fffffff), %bb.9(0x00000001)
   
     %22:gr32_abcd = MOV32r0 implicit-def dead $eflags
     TEST8rr %22.sub_8bit, %22.sub_8bit, implicit-def $eflags
-    JNE_1 %bb.10, implicit killed $eflags
+    JCC_1 %bb.10, 5, implicit killed $eflags
     JMP_1 %bb.9
   
   bb.9:
     successors: 
   
   
   bb.10:
     successors: %bb.12(0x7fffffff), %bb.11(0x00000001)
   
     %24:gr32_abcd = MOV32r0 implicit-def dead $eflags
     TEST8rr %24.sub_8bit, %24.sub_8bit, implicit-def $eflags
-    JNE_1 %bb.12, implicit killed $eflags
+    JCC_1 %bb.12, 5, implicit killed $eflags
     JMP_1 %bb.11
   
   bb.11:
     successors: 
   
   
   bb.12:
     successors: %bb.13(0x00000001), %bb.14(0x7fffffff)
   
     %26:gr32_abcd = MOV32r0 implicit-def dead $eflags
     TEST8rr %26.sub_8bit, %26.sub_8bit, implicit-def $eflags
-    JNE_1 %bb.14, implicit killed $eflags
+    JCC_1 %bb.14, 5, implicit killed $eflags
     JMP_1 %bb.13
   
   bb.13:
     successors: 
   
   
   bb.14:
     %0:gr32 = LEA32r %12, 1, $noreg, 80, $noreg
     %28:gr32_abcd = MOV32r0 implicit-def dead $eflags
     TEST8rr %28.sub_8bit, %28.sub_8bit, implicit-def $eflags
-    JNE_1 %bb.20, implicit killed $eflags
+    JCC_1 %bb.20, 5, implicit killed $eflags
     JMP_1 %bb.15
   
   bb.15:
     successors: %bb.16(0x00000001), %bb.17(0x7fffffff)
   
     %78:gr32_abcd = MOV32r0 implicit-def dead $eflags
     TEST8rr %78.sub_8bit, %78.sub_8bit, implicit-def $eflags
-    JNE_1 %bb.17, implicit killed $eflags
+    JCC_1 %bb.17, 5, implicit killed $eflags
     JMP_1 %bb.16
   
   bb.16:
     successors: 
   
   
   bb.17:
     successors: %bb.18(0x7fffffff), %bb.19(0x00000001)
   
     TEST8rr %78.sub_8bit, %78.sub_8bit, implicit-def $eflags
-    JE_1 %bb.19, implicit killed $eflags
+    JCC_1 %bb.19, 4, implicit killed $eflags
   
   bb.18:
     %79:gr32 = LEA32r %12, 1, $noreg, 80, $noreg
     JMP_1 %bb.21
   
   bb.19:
     successors: 
   
   
   bb.20:
     %78:gr32_abcd = COPY %0
     %79:gr32 = COPY %0
   
   bb.21:
     successors: %bb.22, %bb.23
   
     %35:gr32_abcd = MOV32r0 implicit-def dead $eflags
     TEST8rr %35.sub_8bit, %35.sub_8bit, implicit-def $eflags
     %80:gr32 = IMPLICIT_DEF
-    JNE_1 %bb.23, implicit killed $eflags
+    JCC_1 %bb.23, 5, implicit killed $eflags
     JMP_1 %bb.22
   
   bb.22:
     ADJCALLSTACKDOWN32 0, 0, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp
     CALLpcrel32 @_Znwj, csr_32, implicit $esp, implicit $ssp, implicit-def $esp, implicit-def $ssp, implicit-def $eax
     ADJCALLSTACKUP32 0, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp
     %80:gr32 = COPY killed $eax
     MOV32mr undef %38:gr32, 1, $noreg, 0, $noreg, %78
     MOV32mr %79, 1, $noreg, 0, $noreg, %80
     ADJCALLSTACKDOWN32 0, 0, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp
     CALLpcrel32 @_ZNSt3__127__tree_balance_after_insertIPNS_16__tree_node_baseIPvEEEEvT_S5_, csr_32, implicit $esp, implicit $ssp, implicit-def $esp, implicit-def $ssp
     ADJCALLSTACKUP32 0, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp
   
   bb.23:
     successors: %bb.24(0x00000001), %bb.25(0x7fffffff)
   
     MOV32mi %80, 1, $noreg, 52, $noreg, @_ZN15COLLADASaxFWL1429ColladaParserAutoGen14Private15_preEnd__authorEv
     %39:gr32_abcd = MOV32r0 implicit-def dead $eflags
     TEST8rr %39.sub_8bit, %39.sub_8bit, implicit-def $eflags
-    JNE_1 %bb.25, implicit killed $eflags
+    JCC_1 %bb.25, 5, implicit killed $eflags
     JMP_1 %bb.24
   
   bb.24:
     successors: 
   
   
   bb.25:
     successors: %bb.27(0x7fffffff), %bb.26(0x00000001)
   
     %41:gr32_abcd = MOV32r0 implicit-def dead $eflags
     TEST8rr %41.sub_8bit, %41.sub_8bit, implicit-def $eflags
-    JNE_1 %bb.27, implicit killed $eflags
+    JCC_1 %bb.27, 5, implicit killed $eflags
     JMP_1 %bb.26
   
   bb.26:
     successors: 
   
   
   bb.27:
     successors: %bb.29(0x7fffffff), %bb.28(0x00000001)
   
     %43:gr32_abcd = MOV32r0 implicit-def dead $eflags
     TEST8rr %43.sub_8bit, %43.sub_8bit, implicit-def $eflags
-    JNE_1 %bb.29, implicit killed $eflags
+    JCC_1 %bb.29, 5, implicit killed $eflags
     JMP_1 %bb.28
   
   bb.28:
     successors: 
   
   
   bb.29:
     successors: %bb.31(0x7fffffff), %bb.30(0x00000001)
   
     %45:gr32_abcd = MOV32r0 implicit-def dead $eflags
     TEST8rr %45.sub_8bit, %45.sub_8bit, implicit-def $eflags
-    JNE_1 %bb.31, implicit killed $eflags
+    JCC_1 %bb.31, 5, implicit killed $eflags
     JMP_1 %bb.30
   
   bb.30:
     successors: 
   
   
   bb.31:
     successors: %bb.32(0x00000001), %bb.33(0x7fffffff)
   
     %47:gr32_abcd = MOV32r0 implicit-def dead $eflags
     TEST8rr %47.sub_8bit, %47.sub_8bit, implicit-def $eflags
-    JNE_1 %bb.33, implicit killed $eflags
+    JCC_1 %bb.33, 5, implicit killed $eflags
     JMP_1 %bb.32
   
   bb.32:
     successors: 
   
   
   bb.33:
     successors: %bb.37(0x30000000), %bb.34(0x50000000)
   
     %49:gr8 = MOV8ri 1
     TEST8rr %49, %49, implicit-def $eflags
-    JNE_1 %bb.37, implicit killed $eflags
+    JCC_1 %bb.37, 5, implicit killed $eflags
     JMP_1 %bb.34
   
   bb.34:
     successors: %bb.36(0x00000001), %bb.35(0x7fffffff)
   
     %81:gr32_abcd = MOV32r0 implicit-def dead $eflags
     TEST8rr %81.sub_8bit, %81.sub_8bit, implicit-def $eflags
-    JE_1 %bb.36, implicit killed $eflags
+    JCC_1 %bb.36, 4, implicit killed $eflags
   
   bb.35:
     %82:gr32 = LEA32r %12, 1, $noreg, 80, $noreg
     JMP_1 %bb.38
   
   bb.36:
     successors: 
   
bb.38:
     MOV32mr %82, 1, $noreg, 0, $noreg, %52
     ADJCALLSTACKDOWN32 0, 0, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp
     CALLpcrel32 @_ZNSt3__127__tree_balance_after_insertIPNS_16__tree_node_baseIPvEEEEvT_S5_, csr_32, implicit $esp, implicit $ssp, implicit-def $esp, implicit-def $ssp
     ADJCALLSTACKUP32 0, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp
     MOV32mi %52, 1, $noreg, 36, $noreg, @_ZN15COLLADASaxFWL1429ColladaParserAutoGen14Private14_end__commentsEv
     MOV32mr undef %54:gr32, 1, $noreg, 0, $noreg, %1
     %55:gr32 = MOV32rm %12, 1, $noreg, 140, $noreg
     CMP32mi8 %55, 1, $noreg, 0, $noreg, 0, implicit-def $eflags
-    JE_1 %bb.40, implicit killed $eflags
+    JCC_1 %bb.40, 4, implicit killed $eflags
     JMP_1 %bb.39
   
   bb.39:
     successors: 
   
   
   bb.40:
     successors: %bb.42(0x00000001), %bb.41(0x7fffffff)
   
     %56:gr32_abcd = MOV32r0 implicit-def dead $eflags
     TEST8rr %56.sub_8bit, %56.sub_8bit, implicit-def $eflags
-    JNE_1 %bb.42, implicit killed $eflags
+    JCC_1 %bb.42, 5, implicit killed $eflags
     JMP_1 %bb.41
   
   bb.41:
     successors: %bb.43(0x00000001), %bb.44(0x7fffffff)
   
     %58:gr32_abcd = MOV32r0 implicit-def dead $eflags
     TEST8rr %58.sub_8bit, %58.sub_8bit, implicit-def $eflags
-    JNE_1 %bb.43, implicit killed $eflags
+    JCC_1 %bb.43, 5, implicit killed $eflags
     JMP_1 %bb.44
   
   bb.42:
     successors: 
   
   
   bb.43:
     successors: 
   
   
   bb.44:
     successors: %bb.45(0x00000001), %bb.46(0x7fffffff)
   
     %60:gr32_abcd = MOV32r0 implicit-def dead $eflags
     TEST8rr %60.sub_8bit, %60.sub_8bit, implicit-def $eflags
-    JNE_1 %bb.46, implicit killed $eflags
+    JCC_1 %bb.46, 5, implicit killed $eflags
     JMP_1 %bb.45
   
   bb.45:
     successors: 
   
   
   bb.46:
     successors: %bb.48(0x7fffffff), %bb.47(0x00000001)
   
     %62:gr32_abcd = MOV32r0 implicit-def dead $eflags
     TEST8rr %62.sub_8bit, %62.sub_8bit, implicit-def $eflags
-    JNE_1 %bb.48, implicit killed $eflags
+    JCC_1 %bb.48, 5, implicit killed $eflags
     JMP_1 %bb.47
   
   bb.47:
     successors: 
   
   
   bb.48:
     successors: %bb.50(0x7fffffff), %bb.49(0x00000001)
   
     %64:gr32_abcd = MOV32r0 implicit-def dead $eflags
     TEST8rr %64.sub_8bit, %64.sub_8bit, implicit-def $eflags
-    JNE_1 %bb.50, implicit killed $eflags
+    JCC_1 %bb.50, 5, implicit killed $eflags
     JMP_1 %bb.49
   
   bb.49:
     successors: 
   
   
   bb.50:
     successors: %bb.51(0x00000001), %bb.52(0x7fffffff)
   
     %66:gr32_abcd = MOV32r0 implicit-def dead $eflags
     TEST8rr %66.sub_8bit, %66.sub_8bit, implicit-def $eflags
-    JNE_1 %bb.52, implicit killed $eflags
+    JCC_1 %bb.52, 5, implicit killed $eflags
     JMP_1 %bb.51
   
   bb.51:
     successors: 
   
   
   bb.52:
     successors: %bb.54(0x7fffffff), %bb.53(0x00000001)
   
     %68:gr32_abcd = MOV32r0 implicit-def dead $eflags
     TEST8rr %68.sub_8bit, %68.sub_8bit, implicit-def $eflags
-    JNE_1 %bb.54, implicit killed $eflags
+    JCC_1 %bb.54, 5, implicit killed $eflags
     JMP_1 %bb.53
   
   bb.53:
     successors: 
   
   
   bb.54:
     successors: %bb.55(0x00000001), %bb.56(0x7fffffff)
   
     %70:gr32_abcd = MOV32r0 implicit-def dead $eflags
     TEST8rr %70.sub_8bit, %70.sub_8bit, implicit-def $eflags
-    JNE_1 %bb.56, implicit killed $eflags
+    JCC_1 %bb.56, 5, implicit killed $eflags
     JMP_1 %bb.55
   
   bb.55:
     successors: 
   
   
   bb.56:
     successors: %bb.57(0x00000001), %bb.58(0x7fffffff)
   
     %72:gr32_abcd = MOV32r0 implicit-def dead $eflags
     TEST8rr %72.sub_8bit, %72.sub_8bit, implicit-def $eflags
-    JNE_1 %bb.58, implicit killed $eflags
+    JCC_1 %bb.58, 5, implicit killed $eflags
     JMP_1 %bb.57
   
   bb.57:
     successors: 
   
   
   bb.58:
     successors: %bb.62(0x00000001), %bb.59(0x7fffffff)
   
     CMP32mi8 %0, 1, $noreg, 0, $noreg, 0, implicit-def $eflags
-    JE_1 %bb.62, implicit killed $eflags
+    JCC_1 %bb.62, 4, implicit killed $eflags
     JMP_1 %bb.59
   
   bb.59:
   
   bb.60:
     successors: %bb.60(0x7fffffff), %bb.61(0x00000001)
   
     CMP32ri undef %75:gr32, 95406325, implicit-def $eflags
-    JB_1 %bb.61, implicit killed $eflags
+    JCC_1 %bb.61, 2, implicit killed $eflags
     JMP_1 %bb.60
   
   bb.61:
     successors: 
   
   
   bb.62:
     successors: %bb.63, %bb.64
   
     %76:gr32_abcd = MOV32r0 implicit-def dead $eflags
     TEST8rr %76.sub_8bit, %76.sub_8bit, implicit-def $eflags
-    JNE_1 %bb.64, implicit killed $eflags
+    JCC_1 %bb.64, 5, implicit killed $eflags
     JMP_1 %bb.63
   
   bb.63:
     successors: 
   
   
   bb.64:
 
 ...

llvm/test/CodeGen/X86/shrink_wrap_dbg_value.mir

bb.0.entry:
     liveins: $ecx, $edx
   
     DBG_VALUE $edx, $noreg, !15, !DIExpression(), debug-location !25
     DBG_VALUE $ecx, $noreg, !16, !DIExpression(), debug-location !26
     $eax = COPY $ecx
     DBG_VALUE %fixed-stack.0, 0, !16, !DIExpression(), debug-location !26
     DBG_VALUE %fixed-stack.1, 0, !15, !DIExpression(), debug-location !25
     CMP32rr $eax, killed $edx, implicit-def $eflags, debug-location !27
-    JL_1 %bb.4, implicit killed $eflags, debug-location !29
+    JCC_1 %bb.4, 12, implicit killed $eflags, debug-location !29
     JMP_1 %bb.1, debug-location !29
   
   bb.1.for.cond.preheader:
     successors: %bb.2(0x80000000)
   
     $esi = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (load 4 from %fixed-stack.0)
     DBG_VALUE $esi, $noreg, !13, !DIExpression(), debug-location !19
     $edi = MOV32rm %fixed-stack.1, 1, $noreg, 0, $noreg :: (load 4 from %fixed-stack.1)
     DBG_VALUE $edi, $noreg, !14, !DIExpression(), debug-location !20
     $edi = DEC32r killed $edi, implicit-def dead $eflags, debug-location !30
     $ebx = LEA32r %fixed-stack.1, 1, $noreg, 0, $noreg
   
   bb.2.for.cond:
     successors: %bb.2(0x7c000000), %bb.3(0x04000000)
     liveins: $ebx, $edi, $esi
   
     ADJCALLSTACKDOWN32 4, 0, 4, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp, debug-location !33
     DBG_VALUE %fixed-stack.1, 0, !14, !DIExpression(), debug-location !20
     PUSH32r $ebx, implicit-def $esp, implicit $esp, debug-location !33
     CFI_INSTRUCTION adjust_cfa_offset 4, debug-location !33
     CALLpcrel32 @doSomething, csr_32, implicit $esp, implicit $ssp, implicit-def $esp, implicit-def $ssp, implicit-def $eax, debug-location !33
     ADJCALLSTACKUP32 4, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp, debug-location !33
     $edi = INC32r killed $edi, implicit-def dead $eflags, debug-location !30
     CMP32rr $edi, $esi, implicit-def $eflags, debug-location !30
-    JL_1 %bb.2, implicit killed $eflags, debug-location !34
+    JCC_1 %bb.2, 12, implicit killed $eflags, debug-location !34
   
   bb.3:
     successors: %bb.4(0x80000000)
     liveins: $eax
   
   
   bb.4.return:
     liveins: $eax
   
     RET 8, $eax, debug-location !37
 
 ...

llvm/test/CodeGen/X86/simple-register-allocation-read-undef.mir

 # RUN: llc < %s -x=mir -mtriple=x86_64-- -run-pass=simple-register-coalescing | FileCheck %s
 ---
 name: f
 body: |
   bb.0:
-    JB_1 %bb.2, undef implicit killed $eflags
+    JCC_1 %bb.2, 2, undef implicit killed $eflags
     JMP_1 %bb.1
 
   bb.1:
     %0 : gr64 = IMPLICIT_DEF
     NOOP implicit-def undef %1.sub_32bit : gr64
     NOOP implicit-def %1.sub_16bit : gr64
     JMP_1 %bb.3
 

llvm/test/CodeGen/X86/switch-lower-peel-top-case.ll

 ; RUN: llc -mtriple=x86_64-linux-gnu -stop-after=expand-isel-pseudos < %s  | FileCheck %s
 
 define i32 @foo(i32 %n) !prof !1 {
 entry:
   switch i32 %n, label %bb_default [
     i32 8, label %bb1
     i32 -8826, label %bb2
     i32 18312, label %bb3
     i32 18568, label %bb4
     i32 129, label %bb5
   ], !prof !2
 
 ; CHECK: successors: %[[PEELED_CASE_LABEL:.*]](0x5999999a), %[[PEELED_SWITCH_LABEL:.*]](0x26666666)
 ; CHECK:    %[[VAL:[0-9]+]]:gr32 = COPY $edi
 ; CHECK:    %{{[0-9]+}}:gr32 = SUB32ri %[[VAL]], 18568, implicit-def $eflags
-; CHECK:    JE_1 %[[PEELED_CASE_LABEL]], implicit $eflags
+; CHECK:    JCC_1 %[[PEELED_CASE_LABEL]], 4, implicit $eflags
 ; CHECK:    JMP_1 %[[PEELED_SWITCH_LABEL]]
 ; CHECK:  [[PEELED_SWITCH_LABEL]].{{[a-zA-Z0-9.]+}}:
 ; CHECK:    successors: %[[BB1_LABEL:.*]](0x0206d3a0), %[[BB2_LABEL:.*]](0x7df92c60)
 ; CHECK:    %{{[0-9]+}}:gr32 = SUB32ri %[[VAL]], 18311, implicit-def $eflags
-; CHECK:    JG_1 %[[BB2_LABEL]], implicit $eflags
+; CHECK:    JCC_1 %[[BB2_LABEL]], 15, implicit $eflags
 ; CHECK:    JMP_1 %[[BB1_LABEL]]
 ; CHECK:  [[BB1_LABEL]].{{[a-zA-Z0-9.]+}}:
 ; CHECK:    successors: %[[CASE2_LABEL:.*]](0x35e50d5b), %[[BB3_LABEL:.*]](0x4a1af2a5)
 ; CHECK:    %{{[0-9]+}}:gr32 = SUB32ri %[[VAL]], -8826, implicit-def $eflags
-; CHECK:    JE_1 %[[CASE2_LABEL]], implicit $eflags
+; CHECK:    JCC_1 %[[CASE2_LABEL]], 4, implicit $eflags
 ; CHECK:    JMP_1 %[[BB3_LABEL]]
 ; CHECK:  [[BB3_LABEL]]
 ; CHECK:    successors: %[[CASE5_LABEL:.*]](0x45d173c8), %[[BB4_LABEL:.*]](0x3a2e8c38)
 ; CHECK:    %{{[0-9]+}}:gr32 = SUB32ri %[[VAL]], 129, implicit-def $eflags
-; CHECK:    JE_1 %[[CASE5_LABEL]], implicit $eflags
+; CHECK:    JCC_1 %[[CASE5_LABEL]], 4, implicit $eflags
 ; CHECK:    JMP_1 %[[BB4_LABEL]]
 ; CHECK:  [[BB4_LABEL:.*]].{{[a-zA-Z0-9.]+}}:
 ; CHECK:    successors: %[[CASE1_LABEL:.*]](0x66666666), %[[DEFAULT_BB_LABEL:.*]](0x1999999a)
 ; CHECK:    %{{[0-9]+}}:gr32 = SUB32ri8 %[[VAL]], 8, implicit-def $eflags
-; CHECK:    JE_1 %[[CASE1_LABEL]], implicit $eflags
+; CHECK:    JCC_1 %[[CASE1_LABEL]], 4, implicit $eflags
 ; CHECK:    JMP_1 %[[DEFAULT_BB_LABEL]]
 ; CHECK:  [[BB2_LABEL]].{{[a-zA-Z0-9.]+}}:
 ; CHECK:    successors: %[[CASE3_LABEL:.*]](0x7fe44107), %[[DEFAULT_BB_LABEL]](0x001bbef9)
 ; CHECK:    %{{[0-9]+}}:gr32 = SUB32ri %[[VAL]], 18312, implicit-def $eflags
-; CHECK:    JE_1 %[[CASE3_LABEL]], implicit $eflags
+; CHECK:    JCC_1 %[[CASE3_LABEL]], 4, implicit $eflags
 ; CHECK:    JMP_1 %[[DEFAULT_BB_LABEL]]
 
 bb1:
   br label %return
 bb2:
   br label %return
 bb3:
   br label %return
switch i32 %n, label %bb_default [
     i32 7, label %bb5
     i32 49, label %bb6
   ], !prof !3
 
 ; CHECK:   successors: %[[PEELED_CASE_LABEL:.*]](0x59999999), %[[PEELED_SWITCH_LABEL:.*]](0x26666667)
 ; CHECK:   %[[VAL:[0-9]+]]:gr32 = COPY $edi
 ; CHECK:   %{{[0-9]+}}:gr32 = ADD32ri8 %{{[0-9]+}}, -85, implicit-def dead $eflags
 ; CHECK:   %{{[0-9]+}}:gr32 = SUB32ri8 %{{[0-9]+}}, 2, implicit-def $eflags
-; CHECK:   JB_1 %[[PEELED_CASE_LABEL]], implicit $eflags
+; CHECK:   JCC_1 %[[PEELED_CASE_LABEL]], 2, implicit $eflags
 ; CHECK:   JMP_1 %[[PEELED_SWITCH_LABEL]]
 ; CHECK: [[PEELED_SWITCH_LABEL]].{{[a-zA-Z0-9.]+}}:
 ; CHECK:    successors: %[[BB1_LABEL:.*]](0x0088888a), %[[BB2_LABEL:.*]](0x7f777776)
 ; CHECK:    %{{[0-9]+}}:gr32 = SUB32ri8 %[[VAL]], 4, implicit-def $eflags
-; CHECK:    JG_1 %[[BB2_LABEL]], implicit $eflags
+; CHECK:    JCC_1 %[[BB2_LABEL]], 15, implicit $eflags
 ; CHECK:    JMP_1 %[[BB1_LABEL]]
 ; CHECK:  [[BB1_LABEL]].{{[a-zA-Z0-9.]+}}:
 ; CHECK:    successors: %[[CASE4_LABEL:.*]](0x7f775a4f), %[[BB3_LABEL:.*]](0x0088a5b1)
 ; CHECK:    %{{[0-9]+}}:gr32 = SUB32ri8 %[[VAL]], 1, implicit-def $eflags
-; CHECK:    JE_1 %[[CASE4_LABEL]], implicit $eflags
+; CHECK:    JCC_1 %[[CASE4_LABEL]], 4, implicit $eflags
 ; CHECK:    JMP_1 %[[BB3_LABEL]]
 ; CHECK:  [[BB3_LABEL]].{{[a-zA-Z0-9.]+}}:
 ; CHECK:    successors: %[[CASE1_LABEL:.*]](0x66666666), %[[DEFAULT_BB_LABEL:.*]](0x1999999a)
 ; CHECK:    %{{[0-9]+}}:gr32 = SUB32ri8 %[[VAL]], -40, implicit-def $eflags
-; CHECK:    JE_1 %[[CASE1_LABEL]], implicit $eflags
+; CHECK:    JCC_1 %[[CASE1_LABEL]], 4, implicit $eflags
 ; CHECK:    JMP_1 %[[DEFAULT_BB_LABEL]]
 ; CHECK:  [[BB2_LABEL]].{{[a-zA-Z0-9.]+}}:
 ; CHECK:    successors: %[[CASE5_LABEL:.*]](0x00000000), %[[BB4_LABEL:.*]](0x80000000)
 ; CHECK:    %{{[0-9]+}}:gr32 = SUB32ri8 %[[VAL]], 5, implicit-def $eflags
-; CHECK:    JE_1 %[[CASE5_LABEL]], implicit $eflags
+; CHECK:    JCC_1 %[[CASE5_LABEL]], 4, implicit $eflags
 ; CHECK:    JMP_1 %[[BB4_LABEL]]
 ; CHECK:  [[BB4_LABEL]].{{[a-zA-Z0-9.]+}}:
 ; CHECK:    successors: %[[CASE6_LABEL:.*]](0x00000000), %[[BB5_LABEL:.*]](0x80000000)
 ; CHECK:    %{{[0-9]+}}:gr32 = SUB32ri8 %[[VAL]], 7, implicit-def $eflags
-; CHECK:    JE_1 %[[CASE6_LABEL]], implicit $eflags
+; CHECK:    JCC_1 %[[CASE6_LABEL]], 4, implicit $eflags
 ; CHECK:    JMP_1 %[[BB5_LABEL]]
 ; CHECK:  [[BB5_LABEL]].{{[a-zA-Z0-9.]+}}:
 ; CHECK:    successors: %[[CASE7_LABEL:.*]](0x00000000), %[[DEFAULT_BB_LABEL]](0x80000000)
 ; CHECK:    %{{[0-9]+}}:gr32 = SUB32ri8 %[[VAL]], 49, implicit-def $eflags
-; CHECK:    JE_1 %[[CASE7_LABEL]], implicit $eflags
+; CHECK:    JCC_1 %[[CASE7_LABEL]], 4, implicit $eflags
 ; CHECK:    JMP_1 %[[DEFAULT_BB_LABEL]]
 
 
 bb1:
   br label %return
 bb2:
   br label %return
 bb3:

llvm/test/CodeGen/X86/tail-call-conditional.mir

liveins:
   - { reg: '$rsi' }
 body:             |
   bb.0:
     successors: %bb.1, %bb.4
     liveins: $rdi, $rsi
 
     $rax = COPY $rdi
     CMP64ri8 $rax, 99, implicit-def $eflags
-    JA_1 %bb.4, implicit $eflags
+    JCC_1 %bb.4, 7, implicit $eflags
     JMP_1 %bb.1
 
   ; CHECK: bb.1:
   ; CHECK-NEXT: successors: %bb.2({{[^)]+}}){{$}}
   ; CHECK-NEXT: liveins: $rax, $rsi
   ; CHECK-NEXT: {{^  $}}
   ; CHECK-NEXT: $rdi = COPY $rsi
   ; CHECK-NEXT: $rsi = COPY $rax
   ; CHECK-NEXT: CMP64ri8 $rax, 9, implicit-def $eflags
   ; CHECK-NEXT: TCRETURNdi64cc @f1, 0, 6, csr_64, implicit $rsp, implicit $eflags, implicit $ssp, implicit $rsp, implicit $rdi, implicit $rsi, implicit $rdi, implicit-def $rdi, implicit $hsi, implicit-def $hsi, implicit $sih, implicit-def $sih, implicit $sil, implicit-def $sil, implicit $si, implicit-def $si, implicit $esi, implicit-def $esi, implicit $rsi, implicit-def $rsi, implicit $hdi, implicit-def $hdi, implicit $dih, implicit-def $dih, implicit $dil, implicit-def $dil, implicit $di, implicit-def $di, implicit $edi, implicit-def $edi
 
   bb.1:
     successors: %bb.2, %bb.3
     liveins: $rax, $rsi
 
     CMP64ri8 $rax, 9, implicit-def $eflags
-    JA_1 %bb.3, implicit $eflags
+    JCC_1 %bb.3, 7, implicit $eflags
     JMP_1 %bb.2
 
   bb.2:
     liveins: $rax, $rsi
 
     $rdi = COPY $rsi
     $rsi = COPY $rax
 

llvm/test/CodeGen/X86/tail-dup-debugloc.ll

 ; RUN: llc -stop-after=early-tailduplication < %s | FileCheck %s
 ;
 ; Check that DebugLoc attached to the branch instruction of
 ; 'while.cond1.preheader.lr.ph' survives after tailduplication pass.
 ;
 ; CHECK: [[DLOC:![0-9]+]] = !DILocation(line: 9, column: 5, scope: !{{[0-9]+}})
 ; CHECK: [[VREG:%[^ ]+]]:gr64 = COPY $rdi
 ; CHECK: TEST64rr [[VREG]], [[VREG]]
-; CHECK-NEXT: JE_1 {{.+}}, debug-location [[DLOC]]
+; CHECK-NEXT: JCC_1 {{.+}}, debug-location [[DLOC]]
 ; CHECK-NEXT: JMP_1 {{.+}}, debug-location [[DLOC]]
 
 target triple = "x86_64-unknown-linux-gnu"
 
 %struct.Node = type { %struct.Node* }
 
 define i32 @foo(%struct.Node* readonly %node, %struct.Node* readnone %root) !dbg !6 {
 entry:

llvm/test/CodeGen/X86/tail-merge-after-mbp.mir

 # RUN: llc -mtriple=x86_64-linux -run-pass=block-placement -o - %s | FileCheck %s
 
 ---
 # check loop bb.7 is not merged with bb.10, bb.13
 # check loop bb.9 is not merged with bb.12
 # CHECK:  bb.2:
 # CHECK-NEXT:    successors: %bb.3(0x30000000), %bb.4(0x50000000)
 # CHECK:    $rax = MOV64rm $r14, 1, $noreg, 0, $noreg
 # CHECK-NEXT:    TEST64rr $rax, $rax
-# CHECK-NEXT:    JE_1 %bb.3
+# CHECK-NEXT:    JCC_1 %bb.3, 4
 # CHECK:  bb.4:
 # CHECK-NEXT:    successors: %bb.5(0x30000000), %bb.10(0x50000000)
 # CHECK:    CMP64mi8 killed $rax, 1, $noreg, 8, $noreg, 0
-# CHECK-NEXT:    JNE_1 %bb.10
+# CHECK-NEXT:    JCC_1 %bb.10, 5
 # CHECK:  bb.5:
 # CHECK-NEXT:    successors: %bb.6(0x30000000), %bb.7(0x50000000)
 # CHECK:    $rax = MOV64rm $r14, 1, $noreg, 0, $noreg
 # CHECK-NEXT:    TEST64rr $rax, $rax
-# CHECK-NEXT:    JE_1 %bb.6
+# CHECK-NEXT:    JCC_1 %bb.6, 4
 # CHECK:  bb.7
 # CHECK-NEXT:    successors: %bb.8(0x71555555), %bb.10(0x0eaaaaab)
 # CHECK:    CMP64mi8 killed $rax, 1, $noreg, 8, $noreg, 0
-# CHECK-NEXT:    JNE_1 %bb.10
+# CHECK-NEXT:    JCC_1 %bb.10, 5
 # CHECK:  bb.8:
 # CHECK-NEXT:    successors: %bb.9(0x04000000), %bb.7(0x7c000000)
 # CHECK:    $rax = MOV64rm $r14, 1, $noreg, 0, $noreg
 # CHECK-NEXT:    TEST64rr $rax, $rax
-# CHECK-NEXT:    JNE_1 %bb.7
+# CHECK-NEXT:    JCC_1 %bb.7, 5
 
 name:            foo
 body:             |
   bb.0:
     successors: %bb.1(0x40000000), %bb.7(0x40000000)
 
     TEST8ri $dl, 1, implicit-def $eflags, implicit killed $edx
-    JE_1 %bb.7, implicit $eflags
+    JCC_1 %bb.7, 4, implicit $eflags
 
   bb.1:
     successors: %bb.16(0x80000000)
 
     $ebp = XOR32rr undef $ebp, undef $ebp, implicit-def dead $eflags
     JMP_1 %bb.16
 
   bb.7:
     successors: %bb.8(0x30000000), %bb.9(0x50000000)
 
     $rax = MOV64rm $r14, 1, $noreg, 0, $noreg :: (load 8)
     TEST64rr $rax, $rax, implicit-def $eflags
-    JNE_1 %bb.9, implicit killed $eflags
+    JCC_1 %bb.9, 5, implicit killed $eflags
 
   bb.8:
     successors: %bb.16(0x80000000)
 
     $ebp = XOR32rr undef $ebp, undef $ebp, implicit-def dead $eflags
     JMP_1 %bb.16
 
   bb.9:
     successors: %bb.10(0x30000000), %bb.15(0x50000000)
 
     CMP64mi8 killed $rax, 1, $noreg, 8, $noreg, 0, implicit-def $eflags :: (load 8)
-    JNE_1 %bb.15, implicit $eflags
+    JCC_1 %bb.15, 5, implicit $eflags
 
   bb.10:
     successors: %bb.11(0x30000000), %bb.12(0x50000000)
 
     $rax = MOV64rm $r14, 1, $noreg, 0, $noreg :: (load 8)
     TEST64rr $rax, $rax, implicit-def $eflags
-    JNE_1 %bb.12, implicit $eflags
+    JCC_1 %bb.12, 5, implicit $eflags
 
   bb.11:
     successors: %bb.16(0x80000000)
 
     $ebp = XOR32rr undef $ebp, undef $ebp, implicit-def dead $eflags
     JMP_1 %bb.16
 
   bb.12:
     successors: %bb.13(0x71555555), %bb.15(0x0eaaaaab)
 
     CMP64mi8 killed $rax, 1, $noreg, 8, $noreg, 0, implicit-def $eflags :: (load 8), (load 8)
-    JNE_1 %bb.15, implicit $eflags
+    JCC_1 %bb.15, 5, implicit $eflags
 
   bb.13:
     successors: %bb.14(0x04000000), %bb.12(0x7c000000)
 
     $rax = MOV64rm $r14, 1, $noreg, 0, $noreg :: (load 8)
     TEST64rr $rax, $rax, implicit-def $eflags
-    JNE_1 %bb.12, implicit $eflags
+    JCC_1 %bb.12, 5, implicit $eflags
 
   bb.14:
     successors: %bb.16(0x80000000)
 
     $ebp = XOR32rr undef $ebp, undef $ebp, implicit-def dead $eflags
     JMP_1 %bb.16
 
   bb.15:

llvm/test/CodeGen/X86/tail-merge-debugloc.ll

 ; RUN: llc -stop-after=branch-folder < %s | FileCheck %s
 ;
 ; bb2 and bb3 in the IR below will be tail-merged into a single basic block.
 ; As br instructions in bb2 and bb3 have the same debug location, make sure that
 ; the branch instruction in the merged basic block still maintains the debug 
 ; location info.
 ; 
 ; CHECK:      [[DLOC:![0-9]+]] = !DILocation(line: 2, column: 2, scope: !{{[0-9]+}})
 ; CHECK:      TEST64rr{{.*}}$rsi, renamable $rsi, implicit-def $eflags
-; CHECK-NEXT: JNE_1{{.*}}, debug-location [[DLOC]]
+; CHECK-NEXT: JCC_1{{.*}}, debug-location [[DLOC]]
 
 target triple = "x86_64-unknown-linux-gnu"
 
 define i32 @foo(i1 %b, i8* %p) {
 bb1: 
   br i1 %b, label %bb2, label %bb3
 
 bb2:

llvm/test/CodeGen/X86/test_x86condbr_globaladdr.mir

 name: func
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $edx
     %1:gr32 = COPY $edx
     %2:gr32 = MOV32rm %1:gr32, 1, $noreg, 850256, $noreg
     %3:gr32 = SUB32ri %2:gr32, @img2buf_normal, implicit-def $eflags
-    JE_1 %bb.2, implicit $eflags
+    JCC_1 %bb.2, 4, implicit $eflags
     JMP_1 %bb.3
 
   bb.2:
     RET 0, undef $eax
 
   bb.3:
     $eax = MOV32rr %3:gr32
     RET 0, $eax
 ...

llvm/test/CodeGen/X86/undef-eflags.mir

 # RUN: llc -o - %s -mtriple=x86_64-- -verify-machineinstrs -run-pass branch-folder | FileCheck %s
 # Check that we do not generate invalid MIR when optimizing condjumps with undef
 # flags on the eflags input (currently we should just bail out).
 ---
 # CHECK-LABEL: name: fallundef
 name: fallundef
 tracksRegLiveness: true
 body: |
   bb.0:
-    JE_1 %bb.1, implicit undef $eflags
-    ; CHECK: JE_1 %bb.1, implicit undef $eflags
+    JCC_1 %bb.1, 4, implicit undef $eflags
+    ; CHECK: JCC_1 %bb.1, 4, implicit undef $eflags
     JMP_1 %bb.2
   bb.1:
     RET 2, undef $eax
 
   bb.2:
     RET 0, undef $eax
 ...

llvm/test/CodeGen/X86/update-terminator-debugloc.ll

 ; With the test code, LLVM-IR below shows that loop-control branches have a
 ; debug location of line 6 (branches in entry and for.body block). Make sure that
 ; these debug locations are propaged correctly to lowered instructions.
 ;
 ; CHECK: [[DLOC:![0-9]+]] = !DILocation(line: 6
 ; CHECK-DAG: [[VREG1:%[^ ]+]]:gr64 = COPY $rsi
 ; CHECK-DAG: [[VREG2:%[^ ]+]]:gr64 = COPY $rdi
 ; CHECK: SUB64rr [[VREG2]], [[VREG1]]
-; CHECK-NEXT: JNE_1 {{.*}}, debug-location [[DLOC]]{{$}}
+; CHECK-NEXT: JCC_1 {{.*}}, debug-location [[DLOC]]{{$}}
 ; CHECK: [[VREG3:%[^ ]+]]:gr64 = PHI [[VREG2]]
 ; CHECK: [[VREG4:%[^ ]+]]:gr64 = nuw ADD64ri8 [[VREG3]], 4
 ; CHECK: SUB64rr [[VREG1]], [[VREG4]]
-; CHECK-NEXT: JNE_1 {{.*}}, debug-location [[DLOC]]{{$}}
+; CHECK-NEXT: JCC_1 {{.*}}, debug-location [[DLOC]]{{$}}
 ; CHECK-NEXT: JMP_1 {{.*}}, debug-location [[DLOC]]{{$}}
 
 target triple = "x86_64-unknown-linux-gnu"
 
 define i32 @foo(i32* readonly %begin, i32* readnone %end) !dbg !4 {
 entry:
   %cmp6 = icmp eq i32* %begin, %end, !dbg !9
   br i1 %cmp6, label %for.end, label %for.body.preheader, !dbg !12

llvm/test/CodeGen/X86/update-terminator.mir

 # CHECK: JMP_1 %bb.2
 # CHECK: bb.3:
 # CHECK: bb.2:
 name:            f2
 body:             |
   bb.0 (%ir-block.0):
     successors: %bb.1(50), %bb.3(50)
 
-    JNE_1 %bb.1, implicit $eflags
+    JCC_1 %bb.1, 2, implicit $eflags
     JMP_1 %bb.3
   bb.1:
     successors: %bb.2(100)
 
     CALL64pcrel32 @dummy1, csr_64, implicit $rsp, implicit-def $rsp
     CALL64pcrel32 @dummy1, csr_64, implicit $rsp, implicit-def $rsp
     CALL64pcrel32 @dummy1, csr_64, implicit $rsp, implicit-def $rsp
-    JNE_1 %bb.2, implicit $eflags
+    JCC_1 %bb.2, 5, implicit $eflags
 
   bb.2:
     successors: %bb.4(100)
 
     CALL64pcrel32 @dummy2, csr_64, implicit $rsp, implicit-def $rsp
     CALL64pcrel32 @dummy2, csr_64, implicit $rsp, implicit-def $rsp
     CALL64pcrel32 @dummy2, csr_64, implicit $rsp, implicit-def $rsp
     JMP_1 %bb.4

llvm/test/CodeGen/X86/xor-combine-debugloc.ll

 ; RUN: llc -stop-after=expand-isel-pseudos < %s | FileCheck %s
 ;
 ; Make sure that when the entry block of IR below is lowered, an instruction
 ; that implictly defines $eflags has a same debug location with the icmp
 ; instruction, and the branch instructions have a same debug location with the
 ; br instruction.
 ;
 ; CHECK:      [[DLOC1:![0-9]+]] = !DILocation(line: 5, column: 9, scope: !{{[0-9]+}})
 ; CHECK:      [[DLOC2:![0-9]+]] = !DILocation(line: 5, column: 7, scope: !{{[0-9]+}})
 ; CHECK-DAG:  [[VREG1:%[^ ]+]]:gr32 = COPY $esi
 ; CHECK-DAG:  [[VREG2:%[^ ]+]]:gr32 = COPY $edi
 ; CHECK:      SUB32rr [[VREG2]], [[VREG1]], implicit-def $eflags, debug-location [[DLOC1]]
-; CHECK-NEXT: JE_1{{.*}} implicit $eflags, debug-location [[DLOC2]]
+; CHECK-NEXT: JCC_1{{.*}} 4, implicit $eflags, debug-location [[DLOC2]]
 ; CHECK-NEXT: JMP_1{{.*}} debug-location [[DLOC2]]
 
 target triple = "x86_64-unknown-linux-gnu"
 
 ; Function Attrs: nounwind uwtable
 define i32 @foo(i32 %x, i32 %y) !dbg !4 {
 entry:
   tail call void @llvm.dbg.value(metadata i32 %x, i64 0, metadata !9, metadata !11), !dbg !12

llvm/test/DebugInfo/MIR/X86/empty-inline.mir

 #stack:
 #  - { id: 0, name: '<unnamed alloca>', offset: -16, size: 2, alignment: 8 }
 body:             |
   bb.0 (%ir-block.1):
     successors: %bb.1(0x30000000), %bb.2(0x50000000)
     liveins: $rdi
 
     CMP64mi8 $rip, 1, _, @a, _, 0, implicit-def $eflags :: (dereferenceable load 8 from @a, align 4)
-    JE_1 %bb.1, implicit $eflags
+    JCC_1 %bb.1, 4, implicit $eflags
 
   bb.2 (%ir-block.5):
     liveins: $rdi
 
     $rax = MOV64rm $rdi, 1, _, 0, _ :: (load 8 from %ir.6, align 4)
     $al = MOV8rm killed $rax, 1, _, 0, _ :: (load 1 from %ir.8)
     MOV8mr killed $rdi, 1, _, 8, _, killed $al, debug-location !14 :: (store 1 into %ir.12)
     RETQ undef $eax

llvm/test/DebugInfo/MIR/X86/kill-after-spill.mir

bb.0.entry:
     $r15d = MOV32rr $edi
     DBG_VALUE $r15d, $noreg, !36, !DIExpression(), debug-location !57
     renamable $r14 = MOV64ri -9223372036854775808
     $edi = MOV32rr $ebx
     CALL64pcrel32 @func1, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit-def $rsp, implicit-def $ssp, implicit-def $rax
     $r13 = MOV64rr $rax
     renamable $ecx = XOR32rr undef $ecx, undef $ecx, implicit-def dead $eflags
     renamable $r13 = AND64rr killed renamable $r13, renamable $r14, implicit-def $eflags
-    JE_1 %bb.9, implicit $eflags
+    JCC_1 %bb.9, 4, implicit $eflags
 
   bb.1.if.end:
     successors: %bb.2(0x30000000), %bb.3(0x50000000)
     liveins: $ebx, $r13, $r14, $r15d
 
     ; The instruction below is inserted additionally in order to test part of the code.
     $r12d = MOV32rr $r15d
     MOV32mr $rbp, 1, $noreg, -48, $noreg, renamable $r15d :: (store 4 into %stack.0)
     ; The instruction below is altered ($r15d -> $r12d) in order to test part of the code.
     ; The original instruction "$edi = MOV32rr killed $r15d
     $edi = MOV32rr killed $r12d
     MOV32mr $rbp, 1, $noreg, -44, $noreg, renamable $ebx :: (store 4 into %stack.1)
     $esi = MOV32rr killed $ebx
     CALL64pcrel32 @func2, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit $esi, implicit-def $rsp, implicit-def $ssp, implicit-def $rax
     $r12 = MOV64rr $rax
     $r15 = MOV64rr $r12
     renamable $r15 = AND64ri8 killed renamable $r15, -123, implicit-def $eflags
-    JE_1 %bb.2, implicit $eflags
+    JCC_1 %bb.2, 4, implicit $eflags
 
   bb.3.private.exit:
     successors: %bb.9(0x30000000), %bb.4(0x50000000)
     liveins: $r12, $r13, $r14, $r15
 
     renamable $r14 = OR64rr killed renamable $r14, renamable $r12, implicit-def dead $eflags
     $esi = XOR32rr undef $esi, undef $esi, implicit-def dead $eflags
     dead $edx = MOV32ri 16, implicit-def $rdx
     $rdi = MOV64rr killed $r14
     CALL64pcrel32 @memset, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $esi, implicit $rdx, implicit-def $rsp, implicit-def $ssp, implicit-def dead $rax
     $rdi = MOV64rr $r12
     CALL64pcrel32 @func4, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax
     renamable $ecx = MOV32ri 1
     TEST32rr killed renamable $eax, renamable $eax, implicit-def $eflags
-    JE_1 %bb.9, implicit $eflags
+    JCC_1 %bb.9, 4, implicit $eflags
 
   bb.4.if.then8:
     successors: %bb.8(0x30000000), %bb.5(0x50000000)
     liveins: $r12, $r13, $r15
 
     $esi = XOR32rr undef $esi, undef $esi, implicit-def dead $eflags
     $rdi = MOV64rr $r12
     CALL64pcrel32 @func5, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $esi, implicit-def $rsp, implicit-def $ssp
     renamable $rax = MOV64rm killed renamable $r13, 1, $noreg, 8, $noreg :: (load 8 from %ir.13)
     TEST64rr renamable $rax, renamable $rax, implicit-def $eflags
-    JE_1 %bb.8, implicit $eflags
+    JCC_1 %bb.8, 4, implicit $eflags
 
   bb.5.land.lhs.true:
     successors: %bb.6(0x30000000), %bb.7(0x50000000)
     liveins: $rax, $r12, $r15
 
     CMP32mi8 renamable $r15, 1, $noreg, 0, $noreg, 0, implicit-def $eflags :: (load 4 from %ir.tot_perf2, align 8)
-    JNE_1 %bb.7, implicit $eflags
+    JCC_1 %bb.7, 5, implicit $eflags
 
   bb.6.lor.lhs.false:
     successors: %bb.8(0x30000000), %bb.7(0x50000000)
     liveins: $rax, $r12, $r15
 
     CMP32mi8 killed renamable $r15, 1, $noreg, 4, $noreg, 0, implicit-def $eflags :: (load 4 from %ir.tot_bw)
-    JE_1 %bb.8, implicit $eflags
+    JCC_1 %bb.8, 4, implicit $eflags
 
   bb.7.if.then14:
     successors: %bb.8(0x80000000)
     liveins: $rax, $r12
 
     renamable $rdx = MOV64rm killed renamable $rax, 1, $noreg, 8, $noreg :: (load 8 from %ir.20)
     $rdi = MOV64rr killed $r12
     $esi = MOV32rm $rbp, 1, $noreg, -44, $noreg :: (load 4 from %stack.1)

llvm/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir

bb.0.entry:
     DBG_VALUE $edi, _, !9, !17, debug-location !18
     DBG_VALUE $esi, _, !10, !17, debug-location !19
     DBG_VALUE $edx, _, !11, !17, debug-location !21
     DBG_VALUE $ecx, _, !12, !17, debug-location !23
     DBG_VALUE 0, 0, !13, !17, debug-location !25
     $r8d = MOV32rr $esi, debug-location !26
     $r8d = IMUL32rr killed $r8d, $edi, implicit-def dead $eflags, debug-location !26
     TEST32rr $r8d, $r8d, implicit-def $eflags, debug-location !31
-    JLE_1 %bb.9.for.end, implicit $eflags
+    JCC_1 %bb.9.for.end, 14, implicit $eflags
   
   bb.1.for.body.preheader:
     successors: %bb.3.for.body(0)
     liveins: $ecx, $edi, $edx, $esi, $r8d
   
     DBG_VALUE $edi, _, !9, !17, debug-location !18
     DBG_VALUE $esi, _, !10, !17, debug-location !19
     DBG_VALUE $edx, _, !11, !17, debug-location !21
     DBG_VALUE $ecx, _, !12, !17, debug-location !23
     DBG_VALUE 0, 0, !13, !17, debug-location !25
     $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags
   
   bb.3.for.body (align 4):
     successors: %bb.4.if.then(4), %bb.5.if.end(124)
     liveins: $eax, $ecx, $edi, $edx, $esi, $r8d
   
     DBG_VALUE $edi, _, !9, !17, debug-location !18
     DBG_VALUE $esi, _, !10, !17, debug-location !19
     DBG_VALUE $edx, _, !11, !17, debug-location !21
     DBG_VALUE $ecx, _, !12, !17, debug-location !23
     DBG_VALUE 0, 0, !13, !17, debug-location !25
     TEST32rr $edi, $edi, implicit-def $eflags, debug-location !35
-    JG_1 %bb.4.if.then, implicit $eflags
+    JCC_1 %bb.4.if.then, 15, implicit $eflags
   
   bb.5.if.end:
     successors: %bb.6.if.then.4(4), %bb.7.if.end.6(124)
     liveins: $eax, $ecx, $edi, $edx, $esi, $r8d
   
     DBG_VALUE $edi, _, !9, !17, debug-location !18
     DBG_VALUE $esi, _, !10, !17, debug-location !19
     DBG_VALUE $edx, _, !11, !17, debug-location !21
     DBG_VALUE $ecx, _, !12, !17, debug-location !23
     DBG_VALUE 0, 0, !13, !17, debug-location !25
     TEST32rr $esi, $esi, implicit-def $eflags, debug-location !39
-    JG_1 %bb.6.if.then.4, implicit $eflags
+    JCC_1 %bb.6.if.then.4, 15, implicit $eflags
   
   bb.7.if.end.6:
     successors: %bb.8.if.then.8(4), %bb.2.for.cond(124)
     liveins: $eax, $ecx, $edi, $edx, $esi, $r8d
   
     DBG_VALUE $edi, _, !9, !17, debug-location !18
     DBG_VALUE $esi, _, !10, !17, debug-location !19
     DBG_VALUE $edx, _, !11, !17, debug-location !21
     DBG_VALUE $ecx, _, !12, !17, debug-location !23
     DBG_VALUE 0, 0, !13, !17, debug-location !25
     TEST32rr $edx, $edx, implicit-def $eflags, debug-location !45
-    JG_1 %bb.8.if.then.8, implicit $eflags
+    JCC_1 %bb.8.if.then.8, 15, implicit $eflags
   
   bb.2.for.cond:
     successors: %bb.3.for.body(124), %bb.9.for.end(4)
     liveins: $eax, $ecx, $edi, $edx, $esi, $r8d
   
     DBG_VALUE $edi, _, !9, !17, debug-location !18
     DBG_VALUE $esi, _, !10, !17, debug-location !19
     DBG_VALUE $edx, _, !11, !17, debug-location !21
     DBG_VALUE $ecx, _, !12, !17, debug-location !23
     DBG_VALUE 0, 0, !13, !17, debug-location !25
     $eax = INC32r killed $eax, implicit-def dead $eflags, debug-location !44
     DBG_VALUE $eax, _, !13, !17, debug-location !25
     CMP32rr $eax, $r8d, implicit-def $eflags, debug-location !31
-    JL_1 %bb.3.for.body, implicit $eflags
+    JCC_1 %bb.3.for.body, 12, implicit $eflags
     JMP_1 %bb.9.for.end
   
   bb.4.if.then:
     liveins: $ecx, $edi
   
     DBG_VALUE $edi, _, !9, !17, debug-location !18
     DBG_VALUE $ecx, _, !12, !17, debug-location !23
     DBG_VALUE 0, 0, !13, !17, debug-location !25

llvm/test/DebugInfo/MIR/X86/live-debug-values-reg-copy.mir

bb.0.entry:
     renamable $rdi = LEA64r $rsp, 1, $noreg, 4, $noreg
     CALL64pcrel32 @init, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, debug-location !15
     renamable $edi = MOV32rm $rsp, 1, $noreg, 4, $noreg :: (dereferenceable load 4 from %ir.local1, !tbaa !20)
     renamable $edi = ADD32rr killed renamable $edi, renamable $ebx, implicit-def dead $eflags, debug-location !15
     CALL64pcrel32 @coeficient, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !15
     $ebp = MOV32rr $eax, debug-location !15
     $edi = MOV32rr $ebx, debug-location !15
     CMP32ri8 renamable $ebp, 33, implicit-def $eflags, debug-location !15
-    JL_1 %bb.2, implicit killed $eflags, debug-location !15
+    JCC_1 %bb.2, 12, implicit killed $eflags, debug-location !15
 
   bb.1.if.then:
     successors: %bb.3(0x80000000)
     liveins: $ebp, $edi
 
     CALL64pcrel32 @externFunc, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !15
     JMP_1 %bb.3
 

llvm/test/DebugInfo/MIR/X86/live-debug-values-restore.mir

 body:             |
   bb.0.entry:
     successors: %bb.2(0x30000000), %bb.1(0x50000000)
     liveins: $rdi, $rbx, $r12, $r13, $r14, $r15, $rbp
   
     DBG_VALUE $rdi, $noreg, !13, !DIExpression(), debug-location !14
     DBG_VALUE $rdi, $noreg, !13, !DIExpression(), debug-location !14
     TEST64rr renamable $rdi, renamable $rdi, implicit-def $eflags, debug-location !15
-    JE_1 %bb.2, implicit $eflags, debug-location !17
+    JCC_1 %bb.2, 4, implicit $eflags, debug-location !17
   
   bb.1.if.then:
     successors: %bb.2(0x80000000)
     liveins: $rdi, $rbp, $r15, $r14, $r13, $r12, $rbx
   
     frame-setup PUSH64r killed $rbp, implicit-def $rsp, implicit $rsp
     CFI_INSTRUCTION def_cfa_offset 16
     frame-setup PUSH64r killed $r15, implicit-def $rsp, implicit $rsp

llvm/test/DebugInfo/MIR/X86/live-debug-values-spill.mir

bb.0.entry:
     DBG_VALUE $esi, _, !34, !38, debug-location !57
     $ebx = MOV32rm $rip, 1, _, @glob4, _, debug-location !59 :: (dereferenceable load 4 from @glob4, !tbaa !47)
     DBG_VALUE $ebx, _, !35, !38, debug-location !60
     MOV32mr $rbp, 1, _, -44, _, $ebx, debug-location !60 :: (store 4 into %ir.inte, !tbaa !47)
     $edi = MOV32rm $rip, 1, _, @glob5, _, debug-location !62 :: (dereferenceable load 4 from @glob5, !tbaa !47)
     DBG_VALUE $edi, _, !36, !38, debug-location !63
     MOV32mr $rbp, 1, _, -60, _, $edi, debug-location !63 :: (store 4 into %ir.intf, !tbaa !47)
     TEST32rr killed $eax, $eax, implicit-def $eflags, debug-location !67
-    JNE_1 %bb.5.cleanup, implicit $eflags
+    JCC_1 %bb.5.cleanup, 5, implicit $eflags
   
   bb.1.if.end:
     successors: %bb.2(0x30000000), %bb.3.if.then4(0x50000000)
     liveins: $ebx, $ecx, $edi, $edx, $esi, $r8d, $r9d, $r12d, $r13d, $r14d, $r15d, $rbp
   
     MOV32mr $rbp, 1, _, -48, _, killed $edx :: (store 4 into %stack.5)
     MOV32mr $rbp, 1, _, -52, _, killed $r8d :: (store 4 into %stack.4)
     MOV32mr $rbp, 1, _, -56, _, killed $esi :: (store 4 into %stack.3)
     DBG_VALUE _, _, !30, !38, debug-location !45
     $r14d = ADD32rr killed $r14d, killed $ecx, implicit-def dead $eflags, debug-location !68
     $r14d = ADD32rr killed $r14d, killed $r9d, implicit-def dead $eflags, debug-location !69
     $r14d = IMUL32rm killed $r14d, $rbp, 1, _, 16, _, implicit-def dead $eflags, debug-location !70 :: (load 4 from %fixed-stack.6, align 16)
     DBG_VALUE $r14d, _, !26, !38, debug-location !41
     CALL64pcrel32 @use, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, debug-location !72
     $edi = MOV32rr killed $ebx, debug-location !73
     CALL64pcrel32 @use, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, debug-location !73
     TEST32rr killed $r12d, $r12d, implicit-def $eflags, debug-location !74
-    JE_1 %bb.2, implicit $eflags
+    JCC_1 %bb.2, 4, implicit $eflags
   
   bb.3.if.then4:
     successors: %bb.4.if.end13(0x80000000)
     liveins: $r14d, $r15d, $rbp
   
     $rdi = LEA64r $rbp, 1, _, -44, _
     DBG_VALUE $rbp, -44, !35, !38, debug-location !60
     $rsi = LEA64r $rbp, 1, _, -60, _

llvm/test/DebugInfo/MIR/X86/live-debug-values.mir

bb.0.entry:
     CFI_INSTRUCTION def_cfa_offset 16
     CFI_INSTRUCTION offset $rbx, -16
     DBG_VALUE $edi, _, !12, !20, debug-location !21
     DBG_VALUE $rsi, _, !13, !20, debug-location !22
     $eax = MOV32rr $edi
     DBG_VALUE $eax, _, !12, !20, debug-location !21
     $edi = MOV32ri 2
     CMP32ri8 killed $eax, 2, implicit-def $eflags, debug-location !26
-    JNE_1 %bb.2.if.end, implicit $eflags
+    JCC_1 %bb.2.if.end, 5, implicit $eflags
   
   bb.1.if.else:
     successors: %bb.2.if.end(0)
     liveins: $rsi
   
     DBG_VALUE $rsi, _, !13, !20, debug-location !22
     $rdi = MOV64rm killed $rsi, 1, _, 8, _, debug-location !27 :: (load 8 from %ir.arrayidx, !tbaa !28)
     dead $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, implicit-def $al, debug-location !32
     CALL64pcrel32 @atoi, csr_64, implicit $rsp, implicit $rdi, implicit $al, implicit-def $rsp, implicit-def $eax, debug-location !32
     $edi = MOV32rr $eax, debug-location !32
     DBG_VALUE $edi, _, !14, !20, debug-location !33
   
   bb.2.if.end:
     successors: %bb.3.if.then.3(16), %bb.4.if.else.5(16)
     liveins: $edi
   
     CALL64pcrel32 @change, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, implicit-def $eax, debug-location !34
     $ebx = MOV32rr $eax, debug-location !34
     DBG_VALUE $ebx, _, !14, !20, debug-location !33
     CMP32ri8 $ebx, 11, implicit-def $eflags, debug-location !37
-    JL_1 %bb.4.if.else.5, implicit killed $eflags, debug-location !37
+    JCC_1 %bb.4.if.else.5, 12, implicit killed $eflags, debug-location !37
   
   bb.3.if.then.3:
     successors: %bb.5.if.end.7(0)
     liveins: $ebx
   
     DBG_VALUE $ebx, _, !14, !20, debug-location !33
     $edi = MOV32rr $ebx, debug-location !38
     CALL64pcrel32 @modify, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, implicit-def $eax, debug-location !38

llvm/test/DebugInfo/MIR/X86/livedebugvalues-limit.mir

bb.0.entry:
     frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp
     CFI_INSTRUCTION offset $rbx, -24
     DBG_VALUE $edi, _, !19, !13, debug-location !20
     $ebx = MOV32rr $edi
     DBG_VALUE $ebx, _, !12, !13, debug-location !21
     DBG_VALUE $ebx, _, !19, !13, debug-location !20
     CALL64pcrel32 @sink, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, debug-location !23
     TEST32rr $ebx, $ebx, implicit-def $eflags, debug-location !24
-    JE_1 %bb.2.if.end, implicit $eflags
+    JCC_1 %bb.2.if.end, 4, implicit $eflags
   
   bb.1.if.then:
     successors: %bb.2.if.end
     liveins: $ebx, $rbp
   
     DBG_VALUE $ebx, _, !19, !13, debug-location !20
     DBG_VALUE $ebx, _, !12, !13, debug-location !27
     $edi = MOV32rr $ebx, debug-location !29

llvm/test/DebugInfo/X86/debug-loc-asan.mir

bb.0.entry:
     $rsp = frame-setup AND64ri8 $rsp, -32, implicit-def dead $eflags
     $rsp = frame-setup SUB64ri32 $rsp, 160, implicit-def dead $eflags
     renamable $rax = LEA64r $rsp, 1, $noreg, 64, $noreg
     CMP32mi8 $noreg, 1, $noreg, @__asan_option_detect_stack_use_after_return, $noreg, 0, implicit-def $eflags :: (load 4 from @__asan_option_detect_stack_use_after_return)
     $rcx = MOV64rr $rax
     MOV32mr $rsp, 1, $noreg, 60, $noreg, killed $edi :: (store 4 into %stack.1)
     MOV64mr $rsp, 1, $noreg, 48, $noreg, killed $rax :: (store 8 into %stack.2)
     MOV64mr $rsp, 1, $noreg, 40, $noreg, killed $rcx :: (store 8 into %stack.3)
-    JE_1 %bb.2, implicit $eflags
+    JCC_1 %bb.2, 4, implicit $eflags
   
   bb.1 (%ir-block.3):
     $edi = MOV32ri 64, implicit-def $rdi
     $rsi = MOV64rm $rsp, 1, $noreg, 48, $noreg :: (load 8 from %stack.2)
     CALL64pcrel32 @__asan_stack_malloc_0, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit killed $rsi, implicit-def $rax
     MOV64mr $rsp, 1, $noreg, 40, $noreg, killed $rax :: (store 8 into %stack.3)
   
   bb.2 (%ir-block.5):
bb.2 (%ir-block.5):
     renamable $r8b = MOV8rm killed renamable $rdx, 1, $noreg, 2147450880, $noreg :: (load 1 from %ir.21)
     DBG_VALUE renamable $rcx, 0, !10, !DIExpression(DW_OP_deref), debug-location !11
     CMP8ri renamable $r8b, 0, implicit-def $eflags
     MOV64mr $rsp, 1, $noreg, 32, $noreg, killed $rax :: (store 8 into %stack.4)
     MOV64mr $rsp, 1, $noreg, 24, $noreg, killed $rcx :: (store 8 into %stack.5)
     DBG_VALUE $rsp, 0, !10, !DIExpression(DW_OP_plus_uconst, 24, DW_OP_deref, DW_OP_deref), debug-location !11
     MOV64mr $rsp, 1, $noreg, 16, $noreg, killed $rsi :: (store 8 into %stack.6)
     MOV8mr $rsp, 1, $noreg, 15, $noreg, killed $r8b :: (store 1 into %stack.7)
-    JE_1 %bb.5, implicit $eflags
+    JCC_1 %bb.5, 4, implicit $eflags
   
   bb.3 (%ir-block.24):
     DBG_VALUE $rsp, 0, !10, !DIExpression(DW_OP_plus_uconst, 24, DW_OP_deref, DW_OP_deref), debug-location !11
     $rax = MOV64rm $rsp, 1, $noreg, 24, $noreg :: (load 8 from %stack.5)
     renamable $rax = AND64ri8 renamable $rax, 7, implicit-def $eflags
     renamable $rax = ADD64ri8 renamable $rax, 3, implicit-def $eflags
     $cl = MOV8rr $al, implicit killed $rax
     $dl = MOV8rm $rsp, 1, $noreg, 15, $noreg :: (load 1 from %stack.7)
     CMP8rr killed renamable $cl, killed renamable $dl, implicit-def $eflags
-    JL_1 %bb.5, implicit $eflags
+    JCC_1 %bb.5, 12, implicit $eflags
   
   bb.4 (%ir-block.29):
     successors: 
   
     DBG_VALUE $rsp, 0, !10, !DIExpression(DW_OP_plus_uconst, 24, DW_OP_deref, DW_OP_deref), debug-location !11
     $rdi = MOV64rm $rsp, 1, $noreg, 24, $noreg :: (load 8 from %stack.5)
     CALL64pcrel32 @__asan_report_store4, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi
     INLINEASM &"", 1
   
   bb.5 (%ir-block.30):
     DBG_VALUE $rsp, 0, !10, !DIExpression(DW_OP_plus_uconst, 24, DW_OP_deref, DW_OP_deref), debug-location !11
     $rax = MOV64rm $rsp, 1, $noreg, 24, $noreg :: (load 8 from %stack.5)
     $ecx = MOV32rm $rsp, 1, $noreg, 60, $noreg :: (load 4 from %stack.1)
     MOV32mr renamable $rax, 1, $noreg, 0, $noreg, killed renamable $ecx :: (store 4 into %ir.8)
     renamable $rax = SHR64ri renamable $rax, 3, implicit-def $eflags, debug-location !12
     renamable $dl = MOV8rm killed renamable $rax, 1, $noreg, 2147450880, $noreg, debug-location !12 :: (load 1 from %ir.34)
     CMP8ri renamable $dl, 0, implicit-def $eflags, debug-location !12
     MOV8mr $rsp, 1, $noreg, 14, $noreg, killed $dl :: (store 1 into %stack.8)
-    JE_1 %bb.8, implicit $eflags, debug-location !12
+    JCC_1 %bb.8, 4, implicit $eflags, debug-location !12
   
   bb.6 (%ir-block.37):
     DBG_VALUE $rsp, 0, !10, !DIExpression(DW_OP_plus_uconst, 24, DW_OP_deref, DW_OP_deref), debug-location !11
     $rax = MOV64rm $rsp, 1, $noreg, 24, $noreg :: (load 8 from %stack.5)
     renamable $rax = AND64ri8 renamable $rax, 7, implicit-def $eflags, debug-location !12
     renamable $rax = ADD64ri8 renamable $rax, 3, implicit-def $eflags, debug-location !12
     $cl = MOV8rr $al, implicit killed $rax, debug-location !12
     $dl = MOV8rm $rsp, 1, $noreg, 14, $noreg :: (load 1 from %stack.8)
     CMP8rr killed renamable $cl, killed renamable $dl, implicit-def $eflags, debug-location !12
-    JL_1 %bb.8, implicit $eflags
+    JCC_1 %bb.8, 12, implicit $eflags
   
   bb.7 (%ir-block.42):
     successors: 
   
     DBG_VALUE $rsp, 0, !10, !DIExpression(DW_OP_plus_uconst, 24, DW_OP_deref, DW_OP_deref), debug-location !11
     $rdi = MOV64rm $rsp, 1, $noreg, 24, $noreg :: (load 8 from %stack.5)
     CALL64pcrel32 @__asan_report_load4, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, debug-location !12
     INLINEASM &"", 1
   
   bb.8 (%ir-block.43):
     DBG_VALUE $rsp, 0, !10, !DIExpression(DW_OP_plus_uconst, 24, DW_OP_deref, DW_OP_deref), debug-location !11
     $rax = MOV64rm $rsp, 1, $noreg, 24, $noreg :: (load 8 from %stack.5)
     renamable $ecx = MOV32rm killed renamable $rax, 1, $noreg, 0, $noreg, debug-location !12 :: (load 4 from %ir.8)
     renamable $ecx = ADD32ri8 renamable $ecx, 2, implicit-def $eflags, debug-location !12
     $rdx = MOV64rm $rsp, 1, $noreg, 32, $noreg :: (load 8 from %stack.4)
     MOV64mi32 renamable $rdx, 1, $noreg, 0, $noreg, 1172321806, debug-location !12 :: (store 8 into %ir.9)
     $rsi = MOV64rm $rsp, 1, $noreg, 48, $noreg :: (load 8 from %stack.2)
     CMP64rr killed renamable $rdx, killed renamable $rsi, implicit-def $eflags, debug-location !12
     MOV32mr $rsp, 1, $noreg, 8, $noreg, killed $ecx :: (store 4 into %stack.9)
-    JE_1 %bb.10, implicit $eflags, debug-location !12
+    JCC_1 %bb.10, 4, implicit $eflags, debug-location !12
   
   bb.9 (%ir-block.46):
     DBG_VALUE $rsp, 0, !10, !DIExpression(DW_OP_plus_uconst, 24, DW_OP_deref, DW_OP_deref), debug-location !11
     renamable $rax = MOV64ri -723401728380766731, debug-location !12
     $rcx = MOV64rm $rsp, 1, $noreg, 16, $noreg :: (load 8 from %stack.6)
     MOV64mr killed renamable $rcx, 1, $noreg, 0, $noreg, killed renamable $rax, debug-location !12 :: (store 8 into %ir.48)
     $rax = MOV64rm $rsp, 1, $noreg, 32, $noreg :: (load 8 from %stack.4)
     renamable $rdx = MOV64rm killed renamable $rax, 1, $noreg, 56, $noreg, debug-location !12 :: (load 8 from %ir.50)

llvm/test/DebugInfo/X86/debug-loc-offset.mir

bb.0.entry:
     CFI_INSTRUCTION def_cfa_register $ebp
     $esp = frame-setup SUB32ri8 $esp, 24, implicit-def dead $eflags
     renamable $eax = MOV32rm $ebp, 1, $noreg, 8, $noreg :: (load 4 from %fixed-stack.1)
     DBG_VALUE renamable $eax, 0, !20, !DIExpression(DW_OP_deref), debug-location !21
     MOV32mi $ebp, 1, $noreg, -4, $noreg, 2, debug-location !23 :: (store 4 into %ir.z)
     CMP32mi8 renamable $eax, 1, $noreg, 4, $noreg, 2, implicit-def $eflags, debug-location !24 :: (load 4 from %ir.var)
     MOV32mr $ebp, 1, $noreg, -8, $noreg, killed $eax :: (store 4 into %stack.1)
     DBG_VALUE $ebp, 0, !20, !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref, DW_OP_deref), debug-location !21
-    JLE_1 %bb.2, implicit $eflags, debug-location !24
+    JCC_1 %bb.2, 14, implicit $eflags, debug-location !24
   
   bb.1.if.then:
     DBG_VALUE $ebp, 0, !20, !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref, DW_OP_deref), debug-location !21
     renamable $eax = MOV32rm $ebp, 1, $noreg, -4, $noreg, debug-location !26 :: (load 4 from %ir.z)
     renamable $eax = ADD32ri8 renamable $eax, 1, implicit-def $eflags, debug-location !26
     MOV32mr $ebp, 1, $noreg, -4, $noreg, killed renamable $eax, debug-location !26 :: (store 4 into %ir.z)
   
   bb.2.if.end:
     DBG_VALUE $ebp, 0, !20, !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref, DW_OP_deref), debug-location !21
     $eax = MOV32rm $ebp, 1, $noreg, -8, $noreg :: (load 4 from %stack.1)
     MOV32mr $esp, 1, $noreg, 0, $noreg, killed renamable $eax, debug-location !27 :: (store 4 into stack)
     CALLpcrel32 @_ZN1A3fooEv, csr_32, implicit $esp, implicit $ssp, implicit-def $al, debug-location !27
     renamable $ecx = MOVSX32rr8 killed renamable $al, debug-location !27
     CMP32ri8 killed renamable $ecx, 97, implicit-def $eflags, debug-location !27
-    JNE_1 %bb.4, implicit $eflags, debug-location !27
+    JCC_1 %bb.4, 5, implicit $eflags, debug-location !27
   
   bb.3.if.then2:
     DBG_VALUE $ebp, 0, !20, !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref, DW_OP_deref), debug-location !21
     renamable $eax = MOV32rm $ebp, 1, $noreg, -4, $noreg, debug-location !29 :: (load 4 from %ir.z)
     renamable $eax = ADD32ri8 renamable $eax, 1, implicit-def $eflags, debug-location !29
     MOV32mr $ebp, 1, $noreg, -4, $noreg, killed renamable $eax, debug-location !29 :: (store 4 into %ir.z)
   
   bb.4.if.end4:
     DBG_VALUE $ebp, 0, !20, !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref, DW_OP_deref), debug-location !21
     $esp = frame-destroy ADD32ri8 $esp, 24, implicit-def dead $eflags, debug-location !30
     $ebp = frame-destroy POP32r implicit-def $esp, implicit $esp, debug-location !30
     CFI_INSTRUCTION def_cfa $esp, 4, debug-location !30
     RETL debug-location !30
 
 ...

llvm/test/DebugInfo/X86/pr19307.mir

bb.0.entry:
     $rsi = MOV64rr killed $rax, debug-location !46
     $eax = MOV32ri 6, implicit-def $rax, debug-location !46
     MOV64mr $rbp, 1, $noreg, -24, $noreg, killed $rdx :: (store 8 into %stack.2)
     DBG_VALUE $rbp, 0, !44, !DIExpression(DW_OP_constu, 24, DW_OP_minus, DW_OP_deref, DW_OP_deref), debug-location !45
     $rdx = MOV64rr killed $rax, debug-location !46
     renamable $rcx = MOV64ri @.str, debug-location !46
     CALL64pcrel32 @_ZNKSs7compareEmmPKc, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit killed $rsi, implicit killed $rdx, implicit killed $rcx, implicit-def $eax, debug-location !46
     CMP32ri8 killed renamable $eax, 0, implicit-def $eflags, debug-location !46
-    JNE_1 %bb.2, implicit $eflags, debug-location !46
+    JCC_1 %bb.2, 5, implicit $eflags, debug-location !46
   
   bb.1.lor.lhs.false:
     DBG_VALUE $rbp, 0, !44, !DIExpression(DW_OP_constu, 24, DW_OP_minus, DW_OP_deref, DW_OP_deref), debug-location !45
     $rdi = MOV64rm $rbp, 1, $noreg, -24, $noreg :: (load 8 from %stack.2)
     $esi = MOV32ri 6, implicit-def $rsi, debug-location !48
     CALL64pcrel32 @_ZNSsixEm, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit killed $rsi, implicit-def $rax, debug-location !48
     renamable $ecx = MOVSX32rm8 killed renamable $rax, 1, $noreg, 0, $noreg, debug-location !48 :: (load 1 from %ir.call1)
     CMP32ri8 killed renamable $ecx, 45, implicit-def $eflags, debug-location !48
-    JNE_1 %bb.3, implicit $eflags, debug-location !48
+    JCC_1 %bb.3, 5, implicit $eflags, debug-location !48
   
   bb.2.if.then:
     DBG_VALUE $rbp, 0, !44, !DIExpression(DW_OP_constu, 24, DW_OP_minus, DW_OP_deref, DW_OP_deref), debug-location !45
     renamable $rax = MOV64rm $rbp, 1, $noreg, -8, $noreg, debug-location !50 :: (load 8 from %ir.offset.addr)
     MOV64mi32 killed renamable $rax, 1, $noreg, 0, $noreg, 1, debug-location !50 :: (store 8 into %ir.1)
   
   bb.3.if.end:
     DBG_VALUE $rbp, 0, !44, !DIExpression(DW_OP_constu, 24, DW_OP_minus, DW_OP_deref, DW_OP_deref), debug-location !45

llvm/test/MachineVerifier/verifier-phi-fail0.mir

 # CHECK: - function:    func0
 # CHECK: - basic block: %bb.3
 # CHECK: - instruction: %0:gr32 = PHI
 # CHECK: - operand 3:   %0
 name: func0
 tracksRegLiveness: true
 body: |
   bb.0:
-    JE_1 %bb.1, implicit undef $eflags
+    JCC_1 %bb.1, 4, implicit undef $eflags
     JMP_1 %bb.2
 
   bb.1:
     %0:gr32 = IMPLICIT_DEF
     JMP_1 %bb.3
 
   bb.2:
     %1:gr32 = IMPLICIT_DEF
 
   bb.3:
     %0:gr32 = PHI %1, %bb.1, %0, %bb.2
 ...

llvm/test/MachineVerifier/verifier-phi.mir

 # RUN: llc -o - %s -mtriple=x86_64-- -verify-machineinstrs -run-pass=none | FileCheck %s
 # REQUIRES: x86-registered-target
 
 # This should cleanly pass the machine verifier
 ---
 # CHECK-LABEL: name: func0
 # CHECK: %0:gr32 = PHI undef %1:gr32, %bb.0, undef %1:gr32, %bb.1
 name: func0
 tracksRegLiveness: true
 body: |
   bb.0:
-    JE_1 %bb.1, implicit undef $eflags
+    JCC_1 %bb.1, 4, implicit undef $eflags
     JMP_1 %bb.2
 
   bb.1:
 
   bb.2:
     %0 : gr32 = PHI undef %1 : gr32, %bb.0, undef %1 : gr32, %bb.1
 ...
 ---
 # CHECK-LABEL: name: func1
 # CHECK: %2:gr32 = PHI %0, %bb.0, %1, %bb.1
 name: func1
 tracksRegLiveness: true
 body: |
   bb.0:
     %0 : gr32 = IMPLICIT_DEF
-    JE_1 %bb.1, implicit undef $eflags
+    JCC_1 %bb.1, 4, implicit undef $eflags
     JMP_1 %bb.2
 
   bb.1:
     %1 : gr32 = IMPLICIT_DEF
 
   bb.2:
     %2 : gr32 = PHI %0, %bb.0, %1, %bb.1
 ...

llvm/tools/llvm-exegesis/lib/X86/Target.cpp

 // instruction.
 static Error isInvalidMemoryInstr(const Instruction &Instr) {
   switch (Instr.Description->TSFlags & X86II::FormMask) {
   default:
     llvm_unreachable("Unknown FormMask value");
   // These have no memory access.
   case X86II::Pseudo:
   case X86II::RawFrm:
+  case X86II::AddCCFrm:
   case X86II::MRMDestReg:
   case X86II::MRMSrcReg:
   case X86II::MRMSrcReg4VOp3:
   case X86II::MRMSrcRegOp4:
   case X86II::MRMSrcRegCC:
   case X86II::MRMXrCC:
   case X86II::MRMXr:
   case X86II::MRM0r:

llvm/utils/TableGen/X86RecognizableInstr.h

enum {
     RawFrm        = 1,
     AddRegFrm     = 2,
     RawFrmMemOffs = 3,
     RawFrmSrc     = 4,
     RawFrmDst     = 5,
     RawFrmDstSrc  = 6,
     RawFrmImm8    = 7,
     RawFrmImm16   = 8,
+    AddCCFrm      = 9,
     MRMDestMem     = 32,
     MRMSrcMem      = 33,
     MRMSrcMem4VOp3 = 34,
     MRMSrcMemOp4   = 35,
     MRMSrcMemCC    = 36,
     MRMXmCC = 38, MRMXm = 39,
     MRM0m = 40, MRM1m = 41, MRM2m = 42, MRM3m = 43,
     MRM4m = 44, MRM5m = 45, MRM6m = 46, MRM7m = 47,

llvm/utils/TableGen/X86RecognizableInstr.cpp

#endif
   case X86Local::AddRegFrm:
     // Operand 1 is added to the opcode.
     // Operand 2 (optional) is an address.
     assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
            "Unexpected number of operands for AddRegFrm");
     HANDLE_OPERAND(opcodeModifier)
     HANDLE_OPTIONAL(relocation)
     break;
+  case X86Local::AddCCFrm:
+    // Operand 1 (optional) is an address or immediate.
+    assert(numPhysicalOperands == 2 &&
+           "Unexpected number of operands for AddCCFrm");
+    HANDLE_OPERAND(relocation)
+    HANDLE_OPERAND(opcodeModifier)
+    break;
   case X86Local::MRMDestReg:
     // Operand 1 is a register operand in the R/M field.
     // - In AVX512 there may be a mask operand here -
     // Operand 2 is a register operand in the Reg/Opcode field.
     // - In AVX, there is a register operand in the VEX.vvvv field here -
     // Operand 3 (optional) is an immediate.
     assert(numPhysicalOperands >= 2 + additionalOperands &&
            numPhysicalOperands <= 3 + additionalOperands &&
#define MAP(from, to)                     \
   case X86Local::RawFrm:
   case X86Local::AddRegFrm:
   case X86Local::RawFrmMemOffs:
   case X86Local::RawFrmSrc:
   case X86Local::RawFrmDst:
   case X86Local::RawFrmDstSrc:
   case X86Local::RawFrmImm8:
   case X86Local::RawFrmImm16:
+  case X86Local::AddCCFrm:
     filter = llvm::make_unique<DumbFilter>();
     break;
   case X86Local::MRMDestReg:
   case X86Local::MRMSrcReg:
   case X86Local::MRMSrcReg4VOp3:
   case X86Local::MRMSrcRegOp4:
   case X86Local::MRMSrcRegCC:
   case X86Local::MRMXrCC:
#define MAP(from, to)                     \
   case X86Local::AdSize64: AddressSize = 64; break;
   }
 
   assert(opcodeType && "Opcode type not set");
   assert(filter && "Filter not set");
 
   if (Form == X86Local::AddRegFrm || Form == X86Local::MRMSrcRegCC ||
       Form == X86Local::MRMSrcMemCC || Form == X86Local::MRMXrCC ||
-      Form == X86Local::MRMXmCC) {
+      Form == X86Local::MRMXmCC || Form == X86Local::AddCCFrm) {
     unsigned Count = Form == X86Local::AddRegFrm ? 8 : 16;
     assert(((opcodeToSet % Count) == 0) && "ADDREG_FRM opcode not aligned");
 
     uint8_t currentOpcode;
 
     for (currentOpcode = opcodeToSet; currentOpcode < opcodeToSet + Count;
          ++currentOpcode)
       tables.setTableFields(*opcodeType, insnContext(), currentOpcode, *filter,