[X86] Extend boolean arguments to inline-asm according to getBooleanType

[nickdesaulniers]

Note that with:

1. https://reviews.llvm.org/D60208 ("[X86] Extend boolean arguments to

inline-asm according to getBooleanType")

2. https://reviews.llvm.org/D58260 ("[INLINER] allow inlining of

blockaddresses if sole uses are callbrs")

3. https://reviews.llvm.org/D56571 ("[RFC prototype] Implementation of

asm-goto support in clang")

I can compile a mainline x86 defconfig Linux kernel and boot it in QEMU.

[craig.topper]

LGTM

[jyknight]

This looks like the same bug is present in the generic code in llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp as well.

E.g.,

$ echo 'void f() { asm("# TEST: %0" : : "i"((_Bool)255)); }' | arm-none-eabi-gcc -S -o - -xc - | grep TEST
        # TEST: #1
$ echo 'void f() { asm("# TEST: %0" : : "i"((_Bool)255)); }' | build/bin/clang -target arm-none-eabi -S -o - -xc - | grep TEST
        @ TEST: #-1

[kees]

What other target have their own lowering code? (Or, restated, is x86 the only target not using the generic lowering code?)

[kees]

For the non-X86 case: https://reviews.llvm.org/D60224

llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

case 'Z': {
     }
     // FIXME gcc accepts some relocatable values here too, but only in certain
     // memory models; it's complicated.
     return;
   }
   case 'i': {
     // Literal immediates are always ok.
     if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
-      // Widen to 64 bits here to get it sign extended.
-      Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
+      bool IsBool = CST->getConstantIntValue()->getBitWidth() == 1;
+      BooleanContent BCont = getBooleanContents(MVT::i64);
+      ISD::NodeType ExtOpc = IsBool ? getExtendForContent(BCont)
+                                    : ISD::SIGN_EXTEND;
+      int64_t ExtVal = ExtOpc == ISD::ZERO_EXTEND ? CST->getZExtValue()
+                                                  : CST->getSExtValue();
+      Result = DAG.getTargetConstant(ExtVal, SDLoc(Op), MVT::i64);
       break;
     }
 
     // In any sort of PIC mode addresses need to be computed at runtime by
     // adding in a register or some sort of table lookup.  These can't
     // be used as immediates.
     if (Subtarget.isPICStyleGOT() || Subtarget.isPICStyleStubPIC())
       return;

llvm/trunk/test/CodeGen/X86/inline-asm-i-constraint-i1.ll

+; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+
+; Make sure that boolean immediates are properly (zero) extended.
+; CHECK: .Ltmp[[N:[0-9]+]]:
+; CHECK-NEXT: .quad (42+1)-.Ltmp[[N]]
+
+target triple = "x86_64-unknown-linux-gnu"
+
+define i32 @foo() #0 {
+entry:
+  tail call void asm sideeffect ".quad 42 + ${0:c} - .\0A\09", "i,~{dirflag},~{fpsr},~{flags}"(i1 true) #0
+  ret i32 1
+}
+
+attributes #0 = { nounwind }