The PPC vector cost model values for insert/extract element reflect older processors that lacked vector insert/extract instructions and move-to/move-from VSR instructions. Update getVectorInstrCost to give appropriate values for when the newer instructions are present.
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Some comments related to testcases.
llvm/test/Analysis/CostModel/PowerPC/p9.ll | ||
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2 | Can we have another NFC patch to rename the check-prefixes to avoid confusion. Now CHECK default to P7, while CHECK-P8 is for P8 LE, CHECK-P9 is for P9 BE, CHECK-LE is for P9 LE. Maybe CHECK-P7, CHECK-P8LE, CHECK-P9BE, CHECK-P9LE would be better? Also maybe use multiple prefixes to check common ones, so that we don't need too many duplicates. | |
45 | Maybe it would be better to move all insert/extract to insert_extract.ll? And also rename this file to something like vector_unit.ll other than p9.ll? |
llvm/test/Analysis/CostModel/PowerPC/p9.ll | ||
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2 | Not sure if you're interested, but you can use llvm\utils\update_analyze_test_checks.py to automatically generate cost checks to reduce manual labour. |
llvm/test/Analysis/CostModel/PowerPC/p9.ll | ||
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2 | Good suggestion, Thanks Simon! |
The logic LGTM. Please address the test case updates requested by Jinsong. I don't think this requires another revision though.
Can we have another NFC patch to rename the check-prefixes to avoid confusion.
Now CHECK default to P7, while CHECK-P8 is for P8 LE, CHECK-P9 is for P9 BE, CHECK-LE is for P9 LE.
Maybe CHECK-P7, CHECK-P8LE, CHECK-P9BE, CHECK-P9LE would be better?
Also maybe use multiple prefixes to check common ones, so that we don't need too many duplicates.
eg: --check-prefixes=CHECK,CHECK-P7 for P7,
--check-prefixes=CHECK,CHECK-P8LE for P8 LE.