[mips] MIPS-I Branch on Coprocessor 0 Instructions

[sdardis]

Summary

This patch adds support for the BC0F and BC0T MIPS-I instructions. Besides the
support, corresponding assembler and disassembler tests are also added.

Patch by: Igor Petkovic

Contributions from: Simon Dardis

[dsanders]

LGTM with a few nits.

lib/Target/Mips/MipsInstrFPU.td

270

Nit: Op isn't used

lib/Target/Mips/MipsInstrFormats.td

781

Nit: It's not very clear what 'nd' means (no-delay?). Could we use 'BranchLikely' or 'HasDelaySlot' instead?

lib/Target/Mips/MipsInstrInfo.td

228

This is just a comment, no change required: I agree with the use of ISA_MIPS1_ONLY but it's worth noting that GAS will accept it on MIPS-II and above as well. Also interesting is that, GAS appears to have bc0[tf]l instructions from MIPS-II onwards which have never existed as far as I can tell from the documentation available to me.

229

Nit: NotMips2 already implies NotMips32r6 and NotMips64r6

test/MC/Mips/mips2/invalid-mips1.s

11

Nit: Missing newline at EOF

[ipetkovic]

Nits fixed.

[seanbruno]

This looks like it needs to be refreshed to a more current Trunk if possible.

[sdardis]

Commandeering this patch to rebase to trunk.

[sdardis]

Rebase to trunk, update predicates to reflect GAS exclusions.

[sdardis]

Rebased to trunk. I've changed the instruction predicates to match GAS, for the sake of compatibility.

lib/Target/Mips/MipsInstrFPU.td

class SWXC1_FT<string opstr, RegisterOperand DRC,
                InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
   InstSE<(outs), (ins DRC:$fs, PtrRC:$base, PtrRC:$index),
          !strconcat(opstr, "\t$fs, ${index}(${base})"),
          [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin,
          FrmFI, opstr> {
   let AddedComplexity = 20;
 }
 
+class BC0F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin,
+             bit DelaySlot = 1> :
+  InstSE<(outs), (ins opnd:$offset),
+         !strconcat(opstr, "\t$offset"),
+         [], Itin,
+         FrmFI, opstr> {
+  let isBranch = 1;
+  let isTerminator = 1;
+  let hasDelaySlot = DelaySlot;
+  let Defs = [AT];
+}
+
 class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin,
               SDPatternOperator Op = null_frag, bit DelaySlot = 1> :
   InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),
          !strconcat(opstr, "\t$fcc, $offset"),
          [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin,
          FrmFI, opstr> {
   let isBranch = 1;
   let isTerminator = 1;
   let hasDelaySlot = DelaySlot;
   let Defs = [AT];
 }
 
 class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin,
               SDPatternOperator OpNode = null_frag>  :
   InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond),
          !strconcat("c.$cond.", typestr, "\t$fs, $ft"),
          [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR,
          !strconcat("c.$cond.", typestr)> {
   let Defs = [FCC0];
   let isCodeGenOnly = 1;
 }
 

 //===----------------------------------------------------------------------===//
 // Floating Point Branch Codes
 //===----------------------------------------------------------------------===//
 // Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
 // They must be kept in synch.
 def MIPS_BRANCH_F  : PatLeaf<(i32 0)>;
 def MIPS_BRANCH_T  : PatLeaf<(i32 1)>;
 
+def BC0F : MMRel, BC0F_FT<"bc0f", brtarget, IIBranch>,
+           BC0F_FM<0, 0>, ISA_MIPS1_ONLY;
+def BC0T : MMRel, BC0F_FT<"bc0t", brtarget, IIBranch>,
+           BC0F_FM<0, 1>, ISA_MIPS1_ONLY;
 def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, IIBranch, MIPS_BRANCH_F>,
            BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6;
 def BC1FL : MMRel, BC1F_FT<"bc1fl", brtarget, IIBranch, MIPS_BRANCH_F, 0>,
             BC1F_FM<1, 0>, ISA_MIPS2_NOT_32R6_64R6;
 def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, IIBranch, MIPS_BRANCH_T>,
            BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6;
 def BC1TL : MMRel, BC1F_FT<"bc1tl", brtarget, IIBranch, MIPS_BRANCH_T, 0>,
             BC1F_FM<1, 1>, ISA_MIPS2_NOT_32R6_64R6;

lib/Target/Mips/MipsInstrFormats.td

class SWXC1_FM<bits<6> funct> : StdArch {
   let Inst{31-26} = 0x13;
   let Inst{25-21} = base;
   let Inst{20-16} = index;
   let Inst{15-11} = fs;
   let Inst{10-6}  = 0;
   let Inst{5-0}   = funct;
 }
 
+class BC0F_FM<bit HasDelaySlot, bit tf> : StdArch {
+  bits<3>  fcc;
+  bits<16> offset;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0x10;
+  let Inst{25-21} = 0x8;
+  let Inst{20-18} = 0x0;
+  let Inst{17} = HasDelaySlot;
+  let Inst{16} = tf;
+  let Inst{15-0} = offset;
+}
+
 class BC1F_FM<bit nd, bit tf> : StdArch {
   bits<3>  fcc;
   bits<16> offset;
 
   bits<32> Inst;
 
   let Inst{31-26} = 0x11;
   let Inst{25-21} = 0x8;
   let Inst{20-18} = fcc;
   let Inst{17} = nd;
   let Inst{16} = tf;
   let Inst{15-0} = offset;
 }
 
 class CEQS_FM<bits<5> fmt> : StdArch {
   bits<5> fs;
   bits<5> ft;
   bits<4> cond;
 
   bits<32> Inst;
 
   let Inst{31-26} = 0x11;
   let Inst{25-21} = fmt;

lib/Target/Mips/MipsInstrInfo.td

 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
                      [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 
 //===----------------------------------------------------------------------===//
 // Mips Instruction Predicate Definitions.
 //===----------------------------------------------------------------------===//
 def HasMips2     :    Predicate<"Subtarget->hasMips2()">,
                       AssemblerPredicate<"FeatureMips2">;
+def NotMips2     :    Predicate<"!Subtarget->hasMips2()">,
+                      AssemblerPredicate<"!FeatureMips2">;
 def HasMips3_32  :    Predicate<"Subtarget->hasMips3_32()">,
                       AssemblerPredicate<"FeatureMips3_32">;
 def HasMips3_32r2 :   Predicate<"Subtarget->hasMips3_32r2()">,
                       AssemblerPredicate<"FeatureMips3_32r2">;
 def HasMips3     :    Predicate<"Subtarget->hasMips3()">,
                       AssemblerPredicate<"FeatureMips3">;
 def HasMips4_32  :    Predicate<"Subtarget->hasMips4_32()">,
                       AssemblerPredicate<"FeatureMips4_32">;

 // FIXME: I'd prefer to use additive predicates to build the instruction sets
 //        but we are short on assembler feature bits at the moment. Using a
 //        subtractive predicate will hopefully keep us under the 32 predicate
 //        limit long enough to develop an alternative way to handle P1||P2
 //        predicates.
 class ISA_MIPS1_NOT_32R6_64R6 {
   list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6];
 }
+class ISA_MIPS1_ONLY {
+  list<Predicate> InsnPredicates = [NotMips2];
+}
 class ISA_MIPS2    { list<Predicate> InsnPredicates = [HasMips2]; }
 class ISA_MIPS2_NOT_32R6_64R6 {
   list<Predicate> InsnPredicates = [HasMips2, NotMips32r6, NotMips64r6];
 }
 class ISA_MIPS3    { list<Predicate> InsnPredicates = [HasMips3]; }
 class ISA_MIPS3_NOT_32R6_64R6 {
   list<Predicate> InsnPredicates = [HasMips3, NotMips32r6, NotMips64r6];
 }

test/MC/Disassembler/Mips/mips1.txt

+# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips1 | FileCheck %s
+
+# CHECK: bc0f 1332
+0x41 0x00 0x01 0x4d
+
+# CHECK: bc0t 1332
+0x41 0x01 0x01 0x4d
+

test/MC/Mips/mips1/valid.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 | FileCheck %s
         addi      $13,$9,26322
         addi      $8,$8,~1             # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe]
         add       $9,$14,15176         # CHECK: addi $9, $14, 15176   # encoding: [0x21,0xc9,0x3b,0x48]
         add       $24,-7193            # CHECK: addi $24, $24, -7193  # encoding: [0x23,0x18,0xe3,0xe7]
         addu      $9,$a0,$a2
         addu      $9,10                # CHECK: addiu $9, $9, 10    # encoding: [0x25,0x29,0x00,0x0a]
         and       $s7,$v0,$12
         and       $2,4                 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
+        bc0f      4                    # CHECK: bc0f 4        # encoding: [0x41,0x00,0x00,0x01]
+        bc0t      4                    # CHECK: bc0t 4        # encoding: [0x41,0x01,0x00,0x01]
         bc1f      $fcc0, 4             # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
         bc1f      4                    # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
         bc1t      $fcc0, 4             # CHECK: bc1t 4        # encoding: [0x45,0x01,0x00,0x01]
         bc1t      4                    # CHECK: bc1t 4        # encoding: [0x45,0x01,0x00,0x01]
         bal       21100                # CHECK: bal 21100     # encoding: [0x04,0x11,0x14,0x9b]
         bgezal    $0, 21100            # CHECK: bal 21100     # encoding: [0x04,0x11,0x14,0x9b]
         bgezal    $6, 21100            # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b]
         bltzal    $6, 21100            # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b]

test/MC/Mips/mips2/invalid-mips1.s

+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 \
+# RUN:     2>%t1
+# RUN: FileCheck %s < %t1
+
+        .set noat
+        bc0f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        bc0t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+

test/MC/Mips/mips32/invalid-mips1.s

+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 \
+# RUN:     2>%t1
+# RUN: FileCheck %s < %t1
+
+        .set noat
+        bc0f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        bc0t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+