[X86] Add CMPXCHG8B feature flag. Set it for all CPUs except i386/i486 including 'generic'. Disable use of CMPXCHG8B when this flag isn't set.

[craig.topper]

Summary

CMPXCHG8B was introduced on i586/pentium generation.

If its not enabled, limit the atomic width to 32 bits so the AtomicExpandPass will expand to lib calls. Unclear if we should be using a different limit for other configs. The default is 1024 and experimentation shows that using an i256 atomic will cause a crash in SelectionDAG.

[efriedma]

lib/Support/Host.cpp

1267 ↗

(On Diff #191435)

If someone were to actually try running LLVM on certain 486 models, it would crash because it doesn't actually support CPUID, but I guess that's orthogonal. :)

lib/Target/X86/X86.td

1118 ↗

(On Diff #191435)

This looks a little weird; c3-2 but not c3? Are you sure that's right?

lib/Target/X86/X86ISelLowering.cpp

480 ↗

(On Diff #191435)

?

[craig.topper]

lib/Target/X86/X86.td

1118 ↗

(On Diff #191435)

I think its consistent with gcc. It's also consistent with the CPU enum in clang. c3 is below i586 but c3-2 is above i586.

lib/Target/X86/X86ISelLowering.cpp

480 ↗

(On Diff #191435)

Oops. Leftover from before I changed the AtomicSizeInBits to 32 above.

[craig.topper]

Remove commented out code

[efriedma]

Does this affect the assembler? If so, should we also have an assembler testcase?

[craig.topper]

In D59576#1437153, @efriedma wrote:

Does this affect the assembler? If so, should we also have an assembler testcase?

I shouldn't. We don't do fine grained feature control in the X86 assembler. The only AssemblerPredicates we have have are for 16/32/64 bit mode. We do block cmpxchg16b in 64-bit mode, but we shouldn't have to block cmpxchg8b anywhere.

[efriedma]

LGTM

llvm/lib/Support/Host.cpp

bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
   } text;
 
   if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) ||
       MaxLevel < 1)
     return false;
 
   getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
 
+  Features["cx8"]    = (EDX >>  8) & 1;
   Features["cmov"]   = (EDX >> 15) & 1;
   Features["mmx"]    = (EDX >> 23) & 1;
   Features["fxsr"]   = (EDX >> 24) & 1;
   Features["sse"]    = (EDX >> 25) & 1;
   Features["sse2"]   = (EDX >> 26) & 1;
 
   Features["sse3"]   = (ECX >>  0) & 1;
   Features["pclmul"] = (ECX >>  1) & 1;

llvm/lib/Target/X86/X86.td

def FeatureX87     : SubtargetFeature<"x87","HasX87", "true",
                                       "Enable X87 float instructions">;
 
 def FeatureNOPL    : SubtargetFeature<"nopl", "HasNOPL", "true",
                                       "Enable NOPL instruction">;
 
 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
                                       "Enable conditional move instructions">;
 
+def FeatureCMPXCHG8B : SubtargetFeature<"cx8", "HasCmpxchg8b", "true",
+                                        "Support CMPXCHG8B instructions">;
+
 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
                                        "Support POPCNT instruction">;
 
 def FeatureFXSR    : SubtargetFeature<"fxsr", "HasFXSR", "true",
                                       "Support fxsave/fxrestore instructions">;
 
 def FeatureXSAVE   : SubtargetFeature<"xsave", "HasXSAVE", "true",
                                        "Support xsave instructions">;

 
 //===----------------------------------------------------------------------===//
 // X86 Processor Feature Lists
 //===----------------------------------------------------------------------===//
 
 def ProcessorFeatures {
   // Nehalem
   list<SubtargetFeature> NHMInheritableFeatures = [FeatureX87,
+                                                   FeatureCMPXCHG8B,
                                                    FeatureCMOV,
                                                    FeatureMMX,
                                                    FeatureSSE42,
                                                    FeatureFXSR,
                                                    FeatureNOPL,
                                                    Feature64Bit,
                                                    FeatureCMPXCHG16B,
                                                    FeaturePOPCNT,
def ProcessorFeatures {
   list<SubtargetFeature> ICXSpecificFeatures = [FeaturePCONFIG,
                                                 FeatureWBNOINVD,
                                                 FeatureHasFastGather];
   list<SubtargetFeature> ICXFeatures =
     !listconcat(ICLInheritableFeatures, ICXSpecificFeatures);
 
   // Atom
   list<SubtargetFeature> AtomInheritableFeatures = [FeatureX87,
+                                                    FeatureCMPXCHG8B,
                                                     FeatureCMOV,
                                                     FeatureMMX,
                                                     FeatureSSSE3,
                                                     FeatureFXSR,
                                                     FeatureNOPL,
                                                     Feature64Bit,
                                                     FeatureCMPXCHG16B,
                                                     FeatureMOVBE,
list<SubtargetFeature> TRMAdditionalFeatures = [FeatureCLDEMOTE,
                                                   FeatureWAITPKG];
   list<SubtargetFeature> TRMSpecificFeatures = [ProcIntelTRM];
   list<SubtargetFeature> TRMFeatures =
     !listconcat(GLPInheritableFeatures, TRMAdditionalFeatures,
                 TRMSpecificFeatures);
 
   // Knights Landing
   list<SubtargetFeature> KNLFeatures = [FeatureX87,
+                                        FeatureCMPXCHG8B,
                                         FeatureCMOV,
                                         FeatureMMX,
                                         FeatureFXSR,
                                         FeatureNOPL,
                                         Feature64Bit,
                                         FeatureCMPXCHG16B,
                                         FeaturePOPCNT,
                                         FeatureSlowDivide64,
list<SubtargetFeature> KNLFeatures = [FeatureX87,
                                         FeatureSlowPMADDWD];
   // TODO Add AVX5124FMAPS/AVX5124VNNIW features
   list<SubtargetFeature> KNMFeatures =
     !listconcat(KNLFeatures, [FeatureVPOPCNTDQ]);
 
 
   // Bobcat
   list<SubtargetFeature> BtVer1InheritableFeatures = [FeatureX87,
+                                                      FeatureCMPXCHG8B,
                                                       FeatureCMOV,
                                                       FeatureMMX,
                                                       FeatureSSSE3,
                                                       FeatureSSE4A,
                                                       FeatureFXSR,
                                                       FeatureNOPL,
                                                       Feature64Bit,
                                                       FeatureCMPXCHG16B,
list<SubtargetFeature> BtVer2SpecificFeatures = [FeatureFastLZCNT,
                                                    FeatureFastHorizontalOps];
   list<SubtargetFeature> BtVer2InheritableFeatures =
     !listconcat(BtVer1InheritableFeatures, BtVer2AdditionalFeatures);
   list<SubtargetFeature> BtVer2Features =
     !listconcat(BtVer2InheritableFeatures, BtVer2SpecificFeatures);
 
   // Bulldozer
   list<SubtargetFeature> BdVer1InheritableFeatures = [FeatureX87,
+                                                      FeatureCMPXCHG8B,
                                                       FeatureCMOV,
                                                       FeatureXOP,
                                                       Feature64Bit,
                                                       FeatureCMPXCHG16B,
                                                       FeatureAES,
                                                       FeaturePRFCHW,
                                                       FeaturePCLMUL,
                                                       FeatureMMX,

 
 //===----------------------------------------------------------------------===//
 // X86 processors supported.
 //===----------------------------------------------------------------------===//
 
 class Proc<string Name, list<SubtargetFeature> Features>
  : ProcessorModel<Name, GenericModel, Features>;
 
-def : Proc<"generic",         [FeatureX87, FeatureSlowUAMem16]>;
+// NOTE: CMPXCHG8B is here for legacy compatbility so that it is only disabled
+// if i386/i486 is specifically requested.
+def : Proc<"generic",         [FeatureX87, FeatureSlowUAMem16,
+                               FeatureCMPXCHG8B]>;
 def : Proc<"i386",            [FeatureX87, FeatureSlowUAMem16]>;
 def : Proc<"i486",            [FeatureX87, FeatureSlowUAMem16]>;
-def : Proc<"i586",            [FeatureX87, FeatureSlowUAMem16]>;
-def : Proc<"pentium",         [FeatureX87, FeatureSlowUAMem16]>;
-def : Proc<"pentium-mmx",     [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
+def : Proc<"i586",            [FeatureX87, FeatureSlowUAMem16,
+                               FeatureCMPXCHG8B]>;
+def : Proc<"pentium",         [FeatureX87, FeatureSlowUAMem16,
+                               FeatureCMPXCHG8B]>;
+def : Proc<"pentium-mmx",     [FeatureX87, FeatureSlowUAMem16,
+                               FeatureCMPXCHG8B, FeatureMMX]>;
 
-def : Proc<"i686", [FeatureX87, FeatureSlowUAMem16, FeatureCMOV]>;
-def : Proc<"pentiumpro", [FeatureX87, FeatureSlowUAMem16, FeatureCMOV,
-                          FeatureNOPL]>;
+def : Proc<"i686", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
+                    FeatureCMOV]>;
+def : Proc<"pentiumpro", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
+                          FeatureCMOV, FeatureNOPL]>;
 
-def : Proc<"pentium2",        [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
-                               FeatureCMOV, FeatureFXSR, FeatureNOPL]>;
+def : Proc<"pentium2",        [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
+                               FeatureMMX, FeatureCMOV, FeatureFXSR,
+                               FeatureNOPL]>;
 
 foreach P = ["pentium3", "pentium3m"] in {
-  def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE1,
-                 FeatureFXSR, FeatureNOPL, FeatureCMOV]>;
+  def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,FeatureMMX,
+                 FeatureSSE1, FeatureFXSR, FeatureNOPL, FeatureCMOV]>;
 }
 
 // Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
 // The intent is to enable it for pentium4 which is the current default
 // processor in a vanilla 32-bit clang compilation when no specific
 // architecture is specified.  This generally gives a nice performance
 // increase on silvermont, with largely neutral behavior on other
 // contemporary large core processors.
 // pentium-m, pentium4m, prescott and nocona are included as a preventative
 // measure to avoid performance surprises, in case clang's default cpu
 // changes slightly.
 
 def : ProcessorModel<"pentium-m", GenericPostRAModel,
-                     [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
-                      FeatureSSE2, FeatureFXSR, FeatureNOPL, FeatureCMOV]>;
+                     [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
+                      FeatureMMX, FeatureSSE2, FeatureFXSR, FeatureNOPL,
+                      FeatureCMOV]>;
 
 foreach P = ["pentium4", "pentium4m"] in {
   def : ProcessorModel<P, GenericPostRAModel,
-                       [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
-                        FeatureSSE2, FeatureFXSR, FeatureNOPL, FeatureCMOV]>;
+                       [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
+                        FeatureMMX, FeatureSSE2, FeatureFXSR, FeatureNOPL,
+                        FeatureCMOV]>;
 }
 
 // Intel Quark.
 def : Proc<"lakemont",        []>;
 
 // Intel Core Duo.
 def : ProcessorModel<"yonah", SandyBridgeModel,
-                     [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3,
-                      FeatureFXSR, FeatureNOPL, FeatureCMOV]>;
+                     [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
+                      FeatureMMX, FeatureSSE3, FeatureFXSR, FeatureNOPL,
+                      FeatureCMOV]>;
 
 // NetBurst.
 def : ProcessorModel<"prescott", GenericPostRAModel,
-                     [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3,
-                      FeatureFXSR, FeatureNOPL, FeatureCMOV]>;
+                     [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
+                      FeatureMMX, FeatureSSE3, FeatureFXSR, FeatureNOPL,
+                      FeatureCMOV]>;
 def : ProcessorModel<"nocona", GenericPostRAModel, [
   FeatureX87,
   FeatureSlowUAMem16,
+  FeatureCMPXCHG8B,
   FeatureCMOV,
   FeatureMMX,
   FeatureSSE3,
   FeatureFXSR,
   FeatureNOPL,
   Feature64Bit,
   FeatureCMPXCHG16B
 ]>;
 
 // Intel Core 2 Solo/Duo.
 def : ProcessorModel<"core2", SandyBridgeModel, [
   FeatureX87,
   FeatureSlowUAMem16,
+  FeatureCMPXCHG8B,
   FeatureCMOV,
   FeatureMMX,
   FeatureSSSE3,
   FeatureFXSR,
   FeatureNOPL,
   Feature64Bit,
   FeatureCMPXCHG16B,
   FeatureLAHFSAHF,
   FeatureMacroFusion
 ]>;
 def : ProcessorModel<"penryn", SandyBridgeModel, [
   FeatureX87,
   FeatureSlowUAMem16,
+  FeatureCMPXCHG8B,
   FeatureCMOV,
   FeatureMMX,
   FeatureSSE41,
   FeatureFXSR,
   FeatureNOPL,
   Feature64Bit,
   FeatureCMPXCHG16B,
   FeatureLAHFSAHF,
def : ProcessorModel<"cannonlake", SkylakeServerModel,
                      ProcessorFeatures.CNLFeatures>;
 def : ProcessorModel<"icelake-client", SkylakeServerModel,
                      ProcessorFeatures.ICLFeatures>;
 def : ProcessorModel<"icelake-server", SkylakeServerModel,
                      ProcessorFeatures.ICXFeatures>;
 
 // AMD CPUs.
 
-def : Proc<"k6",              [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
-def : Proc<"k6-2",            [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
-def : Proc<"k6-3",            [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
+def : Proc<"k6",   [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
+                    FeatureMMX]>;
+def : Proc<"k6-2", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
+                    Feature3DNow]>;
+def : Proc<"k6-3", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
+                               Feature3DNow]>;
 
 foreach P = ["athlon", "athlon-tbird"] in {
-  def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMOV, Feature3DNowA,
-                 FeatureNOPL, FeatureSlowSHLD]>;
+  def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureCMOV,
+                 Feature3DNowA, FeatureNOPL, FeatureSlowSHLD]>;
 }
 
 foreach P = ["athlon-4", "athlon-xp", "athlon-mp"] in {
-  def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMOV, FeatureSSE1,
-                 Feature3DNowA, FeatureFXSR, FeatureNOPL, FeatureSlowSHLD]>;
+  def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureCMOV,
+                 FeatureSSE1, Feature3DNowA, FeatureFXSR, FeatureNOPL,
+                 FeatureSlowSHLD]>;
 }
 
 foreach P = ["k8", "opteron", "athlon64", "athlon-fx"] in {
-  def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
-                 FeatureFXSR, FeatureNOPL, Feature64Bit, FeatureSlowSHLD,
-                 FeatureCMOV]>;
+  def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
+                 FeatureSSE2, Feature3DNowA, FeatureFXSR, FeatureNOPL,
+                 Feature64Bit, FeatureSlowSHLD, FeatureCMOV]>;
 }
 
 foreach P = ["k8-sse3", "opteron-sse3", "athlon64-sse3"] in {
-  def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA,
-                 FeatureFXSR, FeatureNOPL, FeatureCMPXCHG16B, FeatureSlowSHLD,
-                 FeatureCMOV, Feature64Bit]>;
+  def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureSSE3,
+                 Feature3DNowA, FeatureFXSR, FeatureNOPL, FeatureCMPXCHG16B,
+                 FeatureSlowSHLD, FeatureCMOV, Feature64Bit]>;
 }
 
 foreach P = ["amdfam10", "barcelona"] in {
-  def : Proc<P, [FeatureX87, FeatureSSE4A, Feature3DNowA, FeatureFXSR,
-                 FeatureNOPL, FeatureCMPXCHG16B, FeatureLZCNT, FeaturePOPCNT,
-                 FeatureSlowSHLD, FeatureLAHFSAHF, FeatureCMOV, Feature64Bit]>;
+  def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureSSE4A, Feature3DNowA,
+                 FeatureFXSR, FeatureNOPL, FeatureCMPXCHG16B, FeatureLZCNT,
+                 FeaturePOPCNT, FeatureSlowSHLD, FeatureLAHFSAHF, FeatureCMOV,
+                 Feature64Bit]>;
 }
 
 // Bobcat
 def : Proc<"btver1", ProcessorFeatures.BtVer1Features>;
 // Jaguar
 def : ProcessorModel<"btver2", BtVer2Model, ProcessorFeatures.BtVer2Features>;
 
 // Bulldozer
 def : ProcessorModel<"bdver1", BdVer2Model, ProcessorFeatures.BdVer1Features>;
 // Piledriver
 def : ProcessorModel<"bdver2", BdVer2Model, ProcessorFeatures.BdVer2Features>;
 // Steamroller
 def : Proc<"bdver3", ProcessorFeatures.BdVer3Features>;
 // Excavator
 def : Proc<"bdver4", ProcessorFeatures.BdVer4Features>;
 
 def : ProcessorModel<"znver1", Znver1Model, ProcessorFeatures.ZNFeatures>;
 def : ProcessorModel<"znver2", Znver1Model, ProcessorFeatures.ZN2Features>;
 
-def : Proc<"geode",           [FeatureX87, FeatureSlowUAMem16, Feature3DNowA]>;
+def : Proc<"geode",           [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
+                               Feature3DNowA]>;
 
 def : Proc<"winchip-c6",      [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
 def : Proc<"winchip2",        [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
 def : Proc<"c3",              [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
-def : Proc<"c3-2",            [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
-                               FeatureSSE1, FeatureFXSR, FeatureCMOV]>;
+def : Proc<"c3-2",            [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
+                               FeatureMMX, FeatureSSE1, FeatureFXSR,
+                               FeatureCMOV]>;
 
 // We also provide a generic 64-bit specific x86 processor model which tries to
 // be good for modern chips without enabling instruction set encodings past the
 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
 // modern 64-bit x86 chip, and enables features that are generally beneficial.
 //
 // We currently use the Sandy Bridge model as the default scheduling model as
 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
 // covers a huge swath of x86 processors. If there are specific scheduling
 // knobs which need to be tuned differently for AMD chips, we might consider
 // forming a common base for them.
 def : ProcessorModel<"x86-64", SandyBridgeModel, [
   FeatureX87,
+  FeatureCMPXCHG8B,
   FeatureCMOV,
   FeatureMMX,
   FeatureSSE2,
   FeatureFXSR,
   FeatureNOPL,
   Feature64Bit,
   FeatureSlow3OpsLEA,
   FeatureSlowIncDec,

llvm/lib/Target/X86/X86ISelLowering.cpp

if (Subtarget.isTargetDarwin()) {
     // MS runtime is weird: it exports _setjmp, but longjmp!
     setUseUnderscoreSetJmp(true);
     setUseUnderscoreLongJmp(false);
   } else {
     setUseUnderscoreSetJmp(true);
     setUseUnderscoreLongJmp(true);
   }
 
+  // If we don't have cmpxchg8b(meaing this is a 386/486), limit atomic size to
+  // 32 bits so the AtomicExpandPass will expand it so we don't need cmpxchg8b.
+  // FIXME: Should we be limitting the atomic size on other configs? Default is
+  // 1024.
+  if (!Subtarget.hasCmpxchg8b())
+    setMaxAtomicSizeInBitsSupported(32);
+
   // Set up the register classes.
   addRegisterClass(MVT::i8, &X86::GR8RegClass);
   addRegisterClass(MVT::i16, &X86::GR16RegClass);
   addRegisterClass(MVT::i32, &X86::GR32RegClass);
   if (Subtarget.is64Bit())
     addRegisterClass(MVT::i64, &X86::GR64RegClass);
 
   for (MVT VT : MVT::integer_valuetypes())

 /// Returns true if the operand type is exactly twice the native width, and
 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
 bool X86TargetLowering::needsCmpXchgNb(Type *MemType) const {
   unsigned OpWidth = MemType->getPrimitiveSizeInBits();
 
   if (OpWidth == 64)
-    return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
-  else if (OpWidth == 128)
+    return Subtarget.hasCmpxchg8b() && !Subtarget.is64Bit();
+  if (OpWidth == 128)
     return Subtarget.hasCmpxchg16b();
-  else
-    return false;
+
 }
 
 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
   return needsCmpXchgNb(SI->getValueOperand()->getType());
 }
 
 // Note: this turns large loads into lock cmpxchg8b/16b.
 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.

llvm/lib/Target/X86/X86InstrCompiler.td

let isCodeGenOnly = 1, SchedRW = [WriteCMPXCHGRMW] in {
   let Defs = [RAX, EFLAGS], Uses = [RAX] in
   def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap),
                    !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"),
                    [(frag addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
 }
 }
 
 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX],
-    SchedRW = [WriteCMPXCHGRMW] in {
+    Predicates = [HasCmpxchg8b], SchedRW = [WriteCMPXCHGRMW] in {
 defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b", X86cas8, i64mem>;
 }
 
 // This pseudo must be used when the frame uses RBX as
 // the base pointer. Indeed, in such situation RBX is a reserved
 // register and the register allocator will ignore any use/def of
 // it. In other words, the register will not fix the clobbering of
 // RBX that will happen when setting the arguments for the instrucion.
 //
 // Unlike the actual related instuction, we mark that this one
 // defines EBX (instead of using EBX).
 // The rationale is that we will define RBX during the expansion of
 // the pseudo. The argument feeding EBX is ebx_input.
 //
 // The additional argument, $ebx_save, is a temporary register used to
 // save the value of RBX across the actual instruction.
 //
 // To make sure the register assigned to $ebx_save does not interfere with
 // the definition of the actual instruction, we use a definition $dst which
 // is tied to $rbx_save. That way, the live-range of $rbx_save spans across
 // the instruction and we are sure we will have a valid register to restore
 // the value of RBX.
 let Defs = [EAX, EDX, EBX, EFLAGS], Uses = [EAX, ECX, EDX],
-    SchedRW = [WriteCMPXCHGRMW], isCodeGenOnly = 1, isPseudo = 1,
-    Constraints = "$ebx_save = $dst", usesCustomInserter = 1 in {
+    Predicates = [HasCmpxchg8b], SchedRW = [WriteCMPXCHGRMW],
+    isCodeGenOnly = 1, isPseudo = 1, Constraints = "$ebx_save = $dst",
+    usesCustomInserter = 1 in {
 def LCMPXCHG8B_SAVE_EBX :
     I<0, Pseudo, (outs GR32:$dst),
       (ins i64mem:$ptr, GR32:$ebx_input, GR32:$ebx_save),
       !strconcat("cmpxchg8b", "\t$ptr"),
       [(set GR32:$dst, (X86cas8save_ebx addr:$ptr, GR32:$ebx_input,
                                         GR32:$ebx_save))]>;
 }
 

llvm/lib/Target/X86/X86InstrInfo.td

 def HasMPX       : Predicate<"Subtarget->hasMPX()">;
 def HasSHSTK     : Predicate<"Subtarget->hasSHSTK()">;
 def HasCLFLUSHOPT : Predicate<"Subtarget->hasCLFLUSHOPT()">;
 def HasCLWB      : Predicate<"Subtarget->hasCLWB()">;
 def HasWBNOINVD  : Predicate<"Subtarget->hasWBNOINVD()">;
 def HasRDPID     : Predicate<"Subtarget->hasRDPID()">;
 def HasWAITPKG   : Predicate<"Subtarget->hasWAITPKG()">;
 def HasINVPCID   : Predicate<"Subtarget->hasINVPCID()">;
+def HasCmpxchg8b : Predicate<"Subtarget->hasCmpxchg8b()">;
 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
 def HasPCONFIG   : Predicate<"Subtarget->hasPCONFIG()">;
 def Not64BitMode : Predicate<"!Subtarget->is64Bit()">,
                              AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">;
 def In64BitMode  : Predicate<"Subtarget->is64Bit()">,
                              AssemblerPredicate<"Mode64Bit", "64-bit mode">;
 def IsLP64  : Predicate<"Subtarget->isTarget64BitLP64()">;
 def NotLP64 : Predicate<"!Subtarget->isTarget64BitLP64()">;
def CMPXCHG32rm  : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
                      NotMemoryFoldable;
 let Defs = [RAX, EFLAGS], Uses = [RAX] in
 def CMPXCHG64rm  : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
                       "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB,
                       NotMemoryFoldable;
 
 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
-                  "cmpxchg8b\t$dst", []>, TB;
+                  "cmpxchg8b\t$dst", []>, TB, Requires<[HasCmpxchg8b]>;
 
 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
 // NOTE: In64BitMode check needed for the AssemblerPredicate.
 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
                     "cmpxchg16b\t$dst", []>,
                     TB, Requires<[HasCmpxchg16b,In64BitMode]>;
 } // SchedRW, mayLoad, mayStore, hasSideEffects
 

llvm/lib/Target/X86/X86Subtarget.h

protected:
   X86SSEEnum X86SSELevel = NoSSE;
 
   /// MMX, 3DNow, 3DNow Athlon, or none supported.
   X863DNowEnum X863DNowLevel = NoThreeDNow;
 
   /// True if the processor supports X87 instructions.
   bool HasX87 = false;
 
+  /// True if the processor supports CMPXCHG8B.
+  bool HasCmpxchg8b = false;
+
   /// True if this processor has NOPL instruction
   /// (generally pentium pro+).
   bool HasNOPL = false;
 
   /// True if this processor has conditional move instructions
   /// (generally pentium pro+).
   bool HasCMov = false;
 
bool isTarget64BitLP64() const {
     return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32 &&
                            !TargetTriple.isOSNaCl());
   }
 
   PICStyles::Style getPICStyle() const { return PICStyle; }
   void setPICStyle(PICStyles::Style Style)  { PICStyle = Style; }
 
   bool hasX87() const { return HasX87; }
+  bool hasCmpxchg8b() const { return HasCmpxchg8b; }
   bool hasNOPL() const { return HasNOPL; }
   // SSE codegen depends on cmovs, and all SSE1+ processors support them.
   // All 64-bit processors support cmov.
   bool hasCMov() const { return HasCMov || X86SSELevel >= SSE1 || is64Bit(); }
   bool hasSSE1() const { return X86SSELevel >= SSE1; }
   bool hasSSE2() const { return X86SSELevel >= SSE2; }
   bool hasSSE3() const { return X86SSELevel >= SSE3; }
   bool hasSSSE3() const { return X86SSELevel >= SSSE3; }

llvm/test/CodeGen/X86/atomic64.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -O0 -mtriple=x86_64-- -mcpu=corei7 -verify-machineinstrs | FileCheck %s --check-prefix X64
+; RUN: llc < %s -O0 -mtriple=i386-- -mcpu=i486 -verify-machineinstrs | FileCheck %s --check-prefix I486
 
 @sc64 = external global i64
 @fsc64 = external global double
 
 define void @atomic_fetch_add64() nounwind {
 ; X64-LABEL: atomic_fetch_add64:
 ; X64:       # %bb.0: # %entry
 ; X64-NEXT:    lock incq {{.*}}(%rip)
 ; X64-NEXT:    lock addq $3, {{.*}}(%rip)
 ; X64-NEXT:    movl $5, %eax
 ; X64-NEXT:    lock xaddq %rax, {{.*}}(%rip)
 ; X64-NEXT:    lock addq %rax, {{.*}}(%rip)
 ; X64-NEXT:    retq
+;
+; I486-LABEL: atomic_fetch_add64:
+; I486:       # %bb.0: # %entry
+; I486-NEXT:    pushl %esi
+; I486-NEXT:    subl $56, %esp
+; I486-NEXT:    leal sc64, %eax
+; I486-NEXT:    movl %esp, %ecx
+; I486-NEXT:    movl $2, 12(%ecx)
+; I486-NEXT:    movl $0, 8(%ecx)
+; I486-NEXT:    movl $1, 4(%ecx)
+; I486-NEXT:    movl $sc64, (%ecx)
+; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    calll __atomic_fetch_add_8
+; I486-NEXT:    leal sc64, %ecx
+; I486-NEXT:    movl %esp, %esi
+; I486-NEXT:    movl $2, 12(%esi)
+; I486-NEXT:    movl $0, 8(%esi)
+; I486-NEXT:    movl $3, 4(%esi)
+; I486-NEXT:    movl $sc64, (%esi)
+; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    calll __atomic_fetch_add_8
+; I486-NEXT:    leal sc64, %ecx
+; I486-NEXT:    movl %esp, %esi
+; I486-NEXT:    movl $2, 12(%esi)
+; I486-NEXT:    movl $0, 8(%esi)
+; I486-NEXT:    movl $5, 4(%esi)
+; I486-NEXT:    movl $sc64, (%esi)
+; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    calll __atomic_fetch_add_8
+; I486-NEXT:    leal sc64, %ecx
+; I486-NEXT:    movl %esp, %esi
+; I486-NEXT:    movl %edx, 8(%esi)
+; I486-NEXT:    movl %eax, 4(%esi)
+; I486-NEXT:    movl $2, 12(%esi)
+; I486-NEXT:    movl $sc64, (%esi)
+; I486-NEXT:    movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    calll __atomic_fetch_add_8
+; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    addl $56, %esp
+; I486-NEXT:    popl %esi
+; I486-NEXT:    retl
 entry:
   %t1 = atomicrmw add  i64* @sc64, i64 1 acquire
   %t2 = atomicrmw add  i64* @sc64, i64 3 acquire
   %t3 = atomicrmw add  i64* @sc64, i64 5 acquire
   %t4 = atomicrmw add  i64* @sc64, i64 %t3 acquire
   ret void
 }
 
 define void @atomic_fetch_sub64() nounwind {
 ; X64-LABEL: atomic_fetch_sub64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    lock decq {{.*}}(%rip)
 ; X64-NEXT:    lock subq $3, {{.*}}(%rip)
 ; X64-NEXT:    movq $-5, %rax
 ; X64-NEXT:    lock xaddq %rax, {{.*}}(%rip)
 ; X64-NEXT:    lock subq %rax, {{.*}}(%rip)
 ; X64-NEXT:    retq
+;
+; I486-LABEL: atomic_fetch_sub64:
+; I486:       # %bb.0:
+; I486-NEXT:    pushl %esi
+; I486-NEXT:    subl $56, %esp
+; I486-NEXT:    leal sc64, %eax
+; I486-NEXT:    movl %esp, %ecx
+; I486-NEXT:    movl $2, 12(%ecx)
+; I486-NEXT:    movl $0, 8(%ecx)
+; I486-NEXT:    movl $1, 4(%ecx)
+; I486-NEXT:    movl $sc64, (%ecx)
+; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    calll __atomic_fetch_sub_8
+; I486-NEXT:    leal sc64, %ecx
+; I486-NEXT:    movl %esp, %esi
+; I486-NEXT:    movl $2, 12(%esi)
+; I486-NEXT:    movl $0, 8(%esi)
+; I486-NEXT:    movl $3, 4(%esi)
+; I486-NEXT:    movl $sc64, (%esi)
+; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    calll __atomic_fetch_sub_8
+; I486-NEXT:    leal sc64, %ecx
+; I486-NEXT:    movl %esp, %esi
+; I486-NEXT:    movl $2, 12(%esi)
+; I486-NEXT:    movl $0, 8(%esi)
+; I486-NEXT:    movl $5, 4(%esi)
+; I486-NEXT:    movl $sc64, (%esi)
+; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    calll __atomic_fetch_sub_8
+; I486-NEXT:    leal sc64, %ecx
+; I486-NEXT:    movl %esp, %esi
+; I486-NEXT:    movl %edx, 8(%esi)
+; I486-NEXT:    movl %eax, 4(%esi)
+; I486-NEXT:    movl $2, 12(%esi)
+; I486-NEXT:    movl $sc64, (%esi)
+; I486-NEXT:    movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    calll __atomic_fetch_sub_8
+; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    addl $56, %esp
+; I486-NEXT:    popl %esi
+; I486-NEXT:    retl
   %t1 = atomicrmw sub  i64* @sc64, i64 1 acquire
   %t2 = atomicrmw sub  i64* @sc64, i64 3 acquire
   %t3 = atomicrmw sub  i64* @sc64, i64 5 acquire
   %t4 = atomicrmw sub  i64* @sc64, i64 %t3 acquire
   ret void
 }
 
 define void @atomic_fetch_and64() nounwind {

 ; X64-NEXT:    movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; X64-NEXT:    movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; X64-NEXT:    jne .LBB2_2
 ; X64-NEXT:    jmp .LBB2_1
 ; X64-NEXT:  .LBB2_2: # %atomicrmw.end
 ; X64-NEXT:    movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
 ; X64-NEXT:    lock andq %rax, {{.*}}(%rip)
 ; X64-NEXT:    retq
+;
+; I486-LABEL: atomic_fetch_and64:
+; I486:       # %bb.0:
+; I486-NEXT:    pushl %esi
+; I486-NEXT:    subl $44, %esp
+; I486-NEXT:    leal sc64, %eax
+; I486-NEXT:    movl %esp, %ecx
+; I486-NEXT:    movl $2, 12(%ecx)
+; I486-NEXT:    movl $0, 8(%ecx)
+; I486-NEXT:    movl $3, 4(%ecx)
+; I486-NEXT:    movl $sc64, (%ecx)
+; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    calll __atomic_fetch_and_8
+; I486-NEXT:    leal sc64, %ecx
+; I486-NEXT:    movl %esp, %esi
+; I486-NEXT:    movl $2, 12(%esi)
+; I486-NEXT:    movl $0, 8(%esi)
+; I486-NEXT:    movl $5, 4(%esi)
+; I486-NEXT:    movl $sc64, (%esi)
+; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    calll __atomic_fetch_and_8
+; I486-NEXT:    leal sc64, %ecx
+; I486-NEXT:    movl %esp, %esi
+; I486-NEXT:    movl %edx, 8(%esi)
+; I486-NEXT:    movl %eax, 4(%esi)
+; I486-NEXT:    movl $2, 12(%esi)
+; I486-NEXT:    movl $sc64, (%esi)
+; I486-NEXT:    movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    calll __atomic_fetch_and_8
+; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    addl $44, %esp
+; I486-NEXT:    popl %esi
+; I486-NEXT:    retl
   %t1 = atomicrmw and  i64* @sc64, i64 3 acquire
   %t2 = atomicrmw and  i64* @sc64, i64 5 acquire
   %t3 = atomicrmw and  i64* @sc64, i64 %t2 acquire
   ret void
 }
 
 define void @atomic_fetch_or64() nounwind {
 ; X64-LABEL: atomic_fetch_or64:

 ; X64-NEXT:    movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; X64-NEXT:    movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; X64-NEXT:    jne .LBB3_2
 ; X64-NEXT:    jmp .LBB3_1
 ; X64-NEXT:  .LBB3_2: # %atomicrmw.end
 ; X64-NEXT:    movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
 ; X64-NEXT:    lock orq %rax, {{.*}}(%rip)
 ; X64-NEXT:    retq
+;
+; I486-LABEL: atomic_fetch_or64:
+; I486:       # %bb.0:
+; I486-NEXT:    pushl %esi
+; I486-NEXT:    subl $44, %esp
+; I486-NEXT:    leal sc64, %eax
+; I486-NEXT:    movl %esp, %ecx
+; I486-NEXT:    movl $2, 12(%ecx)
+; I486-NEXT:    movl $0, 8(%ecx)
+; I486-NEXT:    movl $3, 4(%ecx)
+; I486-NEXT:    movl $sc64, (%ecx)
+; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    calll __atomic_fetch_or_8
+; I486-NEXT:    leal sc64, %ecx
+; I486-NEXT:    movl %esp, %esi
+; I486-NEXT:    movl $2, 12(%esi)
+; I486-NEXT:    movl $0, 8(%esi)
+; I486-NEXT:    movl $5, 4(%esi)
+; I486-NEXT:    movl $sc64, (%esi)
+; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    calll __atomic_fetch_or_8
+; I486-NEXT:    leal sc64, %ecx
+; I486-NEXT:    movl %esp, %esi
+; I486-NEXT:    movl %edx, 8(%esi)
+; I486-NEXT:    movl %eax, 4(%esi)
+; I486-NEXT:    movl $2, 12(%esi)
+; I486-NEXT:    movl $sc64, (%esi)
+; I486-NEXT:    movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    calll __atomic_fetch_or_8
+; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    addl $44, %esp
+; I486-NEXT:    popl %esi
+; I486-NEXT:    retl
   %t1 = atomicrmw or   i64* @sc64, i64 3 acquire
   %t2 = atomicrmw or   i64* @sc64, i64 5 acquire
   %t3 = atomicrmw or   i64* @sc64, i64 %t2 acquire
   ret void
 }
 
 define void @atomic_fetch_xor64() nounwind {
 ; X64-LABEL: atomic_fetch_xor64:

 ; X64-NEXT:    movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; X64-NEXT:    movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; X64-NEXT:    jne .LBB4_2
 ; X64-NEXT:    jmp .LBB4_1
 ; X64-NEXT:  .LBB4_2: # %atomicrmw.end
 ; X64-NEXT:    movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
 ; X64-NEXT:    lock xorq %rax, {{.*}}(%rip)
 ; X64-NEXT:    retq
+;
+; I486-LABEL: atomic_fetch_xor64:
+; I486:       # %bb.0:
+; I486-NEXT:    pushl %esi
+; I486-NEXT:    subl $44, %esp
+; I486-NEXT:    leal sc64, %eax
+; I486-NEXT:    movl %esp, %ecx
+; I486-NEXT:    movl $2, 12(%ecx)
+; I486-NEXT:    movl $0, 8(%ecx)
+; I486-NEXT:    movl $3, 4(%ecx)
+; I486-NEXT:    movl $sc64, (%ecx)
+; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    calll __atomic_fetch_xor_8
+; I486-NEXT:    leal sc64, %ecx
+; I486-NEXT:    movl %esp, %esi
+; I486-NEXT:    movl $2, 12(%esi)
+; I486-NEXT:    movl $0, 8(%esi)
+; I486-NEXT:    movl $5, 4(%esi)
+; I486-NEXT:    movl $sc64, (%esi)
+; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    calll __atomic_fetch_xor_8
+; I486-NEXT:    leal sc64, %ecx
+; I486-NEXT:    movl %esp, %esi
+; I486-NEXT:    movl %edx, 8(%esi)
+; I486-NEXT:    movl %eax, 4(%esi)
+; I486-NEXT:    movl $2, 12(%esi)
+; I486-NEXT:    movl $sc64, (%esi)
+; I486-NEXT:    movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    calll __atomic_fetch_xor_8
+; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    addl $44, %esp
+; I486-NEXT:    popl %esi
+; I486-NEXT:    retl
   %t1 = atomicrmw xor  i64* @sc64, i64 3 acquire
   %t2 = atomicrmw xor  i64* @sc64, i64 5 acquire
   %t3 = atomicrmw xor  i64* @sc64, i64 %t2 acquire
   ret void
 }
 
 define void @atomic_fetch_nand64(i64 %x) nounwind {
 ; X64-LABEL: atomic_fetch_nand64:

 ; X64-NEXT:    lock cmpxchgq %rcx, {{.*}}(%rip)
 ; X64-NEXT:    sete %sil
 ; X64-NEXT:    testb $1, %sil
 ; X64-NEXT:    movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; X64-NEXT:    jne .LBB5_2
 ; X64-NEXT:    jmp .LBB5_1
 ; X64-NEXT:  .LBB5_2: # %atomicrmw.end
 ; X64-NEXT:    retq
+;
+; I486-LABEL: atomic_fetch_nand64:
+; I486:       # %bb.0:
+; I486-NEXT:    pushl %esi
+; I486-NEXT:    subl $28, %esp
+; I486-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; I486-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; I486-NEXT:    leal sc64, %edx
+; I486-NEXT:    movl %esp, %esi
+; I486-NEXT:    movl %eax, 8(%esi)
+; I486-NEXT:    movl %ecx, 4(%esi)
+; I486-NEXT:    movl $2, 12(%esi)
+; I486-NEXT:    movl $sc64, (%esi)
+; I486-NEXT:    movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    calll __atomic_fetch_nand_8
+; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    addl $28, %esp
+; I486-NEXT:    popl %esi
+; I486-NEXT:    retl
   %t1 = atomicrmw nand i64* @sc64, i64 %x acquire
   ret void
 }
 
 define void @atomic_fetch_max64(i64 %x) nounwind {
 ; X64-LABEL: atomic_fetch_max64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq sc64, %rax

 ; X64-NEXT:    sete %sil
 ; X64-NEXT:    testb $1, %sil
 ; X64-NEXT:    movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; X64-NEXT:    movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; X64-NEXT:    jne .LBB6_2
 ; X64-NEXT:    jmp .LBB6_1
 ; X64-NEXT:  .LBB6_2: # %atomicrmw.end
 ; X64-NEXT:    retq
+;
+; I486-LABEL: atomic_fetch_max64:
+; I486:       # %bb.0:
+; I486-NEXT:    pushl %ebp
+; I486-NEXT:    movl %esp, %ebp
+; I486-NEXT:    pushl %ebx
+; I486-NEXT:    pushl %edi
+; I486-NEXT:    pushl %esi
+; I486-NEXT:    andl $-8, %esp
+; I486-NEXT:    subl $80, %esp
+; I486-NEXT:    movl 12(%ebp), %eax
+; I486-NEXT:    movl 8(%ebp), %ecx
+; I486-NEXT:    movl sc64+4, %edx
+; I486-NEXT:    movl sc64, %esi
+; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    jmp .LBB6_1
+; I486-NEXT:  .LBB6_1: # %atomicrmw.start
+; I486-NEXT:    # =>This Inner Loop Header: Depth=1
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; I486-NEXT:    movl %ecx, %edx
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
+; I486-NEXT:    subl %esi, %edx
+; I486-NEXT:    movl %eax, %edi
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
+; I486-NEXT:    sbbl %ebx, %edi
+; I486-NEXT:    movl %ecx, %esi
+; I486-NEXT:    movl %eax, %ebx
+; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    jge .LBB6_4
+; I486-NEXT:  # %bb.3: # %atomicrmw.start
+; I486-NEXT:    # in Loop: Header=BB6_1 Depth=1
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:  .LBB6_4: # %atomicrmw.start
+; I486-NEXT:    # in Loop: Header=BB6_1 Depth=1
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; I486-NEXT:    movl %edx, {{[0-9]+}}(%esp)
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
+; I486-NEXT:    movl %esi, {{[0-9]+}}(%esp)
+; I486-NEXT:    movl %esp, %edi
+; I486-NEXT:    movl %eax, 12(%edi)
+; I486-NEXT:    movl %ecx, 8(%edi)
+; I486-NEXT:    leal {{[0-9]+}}(%esp), %eax
+; I486-NEXT:    movl %eax, 4(%edi)
+; I486-NEXT:    movl $2, 20(%edi)
+; I486-NEXT:    movl $2, 16(%edi)
+; I486-NEXT:    movl $sc64, (%edi)
+; I486-NEXT:    calll __atomic_compare_exchange_8
+; I486-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; I486-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; I486-NEXT:    testb %al, %al
+; I486-NEXT:    movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    je .LBB6_1
+; I486-NEXT:    jmp .LBB6_2
+; I486-NEXT:  .LBB6_2: # %atomicrmw.end
+; I486-NEXT:    leal -12(%ebp), %esp
+; I486-NEXT:    popl %esi
+; I486-NEXT:    popl %edi
+; I486-NEXT:    popl %ebx
+; I486-NEXT:    popl %ebp
+; I486-NEXT:    retl
   %t1 = atomicrmw max  i64* @sc64, i64 %x acquire
 
   ret void
 }
 
 define void @atomic_fetch_min64(i64 %x) nounwind {
 ; X64-LABEL: atomic_fetch_min64:
 ; X64:       # %bb.0:

 ; X64-NEXT:    sete %sil
 ; X64-NEXT:    testb $1, %sil
 ; X64-NEXT:    movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; X64-NEXT:    movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; X64-NEXT:    jne .LBB7_2
 ; X64-NEXT:    jmp .LBB7_1
 ; X64-NEXT:  .LBB7_2: # %atomicrmw.end
 ; X64-NEXT:    retq
+;
+; I486-LABEL: atomic_fetch_min64:
+; I486:       # %bb.0:
+; I486-NEXT:    pushl %ebp
+; I486-NEXT:    movl %esp, %ebp
+; I486-NEXT:    pushl %ebx
+; I486-NEXT:    pushl %edi
+; I486-NEXT:    pushl %esi
+; I486-NEXT:    andl $-8, %esp
+; I486-NEXT:    subl $80, %esp
+; I486-NEXT:    movl 12(%ebp), %eax
+; I486-NEXT:    movl 8(%ebp), %ecx
+; I486-NEXT:    movl sc64+4, %edx
+; I486-NEXT:    movl sc64, %esi
+; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    jmp .LBB7_1
+; I486-NEXT:  .LBB7_1: # %atomicrmw.start
+; I486-NEXT:    # =>This Inner Loop Header: Depth=1
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; I486-NEXT:    subl %ecx, %edx
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
+; I486-NEXT:    sbbl %eax, %esi
+; I486-NEXT:    movl %ecx, %edi
+; I486-NEXT:    movl %eax, %ebx
+; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    jge .LBB7_4
+; I486-NEXT:  # %bb.3: # %atomicrmw.start
+; I486-NEXT:    # in Loop: Header=BB7_1 Depth=1
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:  .LBB7_4: # %atomicrmw.start
+; I486-NEXT:    # in Loop: Header=BB7_1 Depth=1
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; I486-NEXT:    movl %edx, {{[0-9]+}}(%esp)
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
+; I486-NEXT:    movl %esi, {{[0-9]+}}(%esp)
+; I486-NEXT:    movl %esp, %edi
+; I486-NEXT:    movl %eax, 12(%edi)
+; I486-NEXT:    movl %ecx, 8(%edi)
+; I486-NEXT:    leal {{[0-9]+}}(%esp), %eax
+; I486-NEXT:    movl %eax, 4(%edi)
+; I486-NEXT:    movl $2, 20(%edi)
+; I486-NEXT:    movl $2, 16(%edi)
+; I486-NEXT:    movl $sc64, (%edi)
+; I486-NEXT:    calll __atomic_compare_exchange_8
+; I486-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; I486-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; I486-NEXT:    testb %al, %al
+; I486-NEXT:    movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    je .LBB7_1
+; I486-NEXT:    jmp .LBB7_2
+; I486-NEXT:  .LBB7_2: # %atomicrmw.end
+; I486-NEXT:    leal -12(%ebp), %esp
+; I486-NEXT:    popl %esi
+; I486-NEXT:    popl %edi
+; I486-NEXT:    popl %ebx
+; I486-NEXT:    popl %ebp
+; I486-NEXT:    retl
   %t1 = atomicrmw min  i64* @sc64, i64 %x acquire
 
   ret void
 }
 
 define void @atomic_fetch_umax64(i64 %x) nounwind {
 ; X64-LABEL: atomic_fetch_umax64:
 ; X64:       # %bb.0:

 ; X64-NEXT:    sete %sil
 ; X64-NEXT:    testb $1, %sil
 ; X64-NEXT:    movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; X64-NEXT:    movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; X64-NEXT:    jne .LBB8_2
 ; X64-NEXT:    jmp .LBB8_1
 ; X64-NEXT:  .LBB8_2: # %atomicrmw.end
 ; X64-NEXT:    retq
+;
+; I486-LABEL: atomic_fetch_umax64:
+; I486:       # %bb.0:
+; I486-NEXT:    pushl %ebp
+; I486-NEXT:    movl %esp, %ebp
+; I486-NEXT:    pushl %ebx
+; I486-NEXT:    pushl %edi
+; I486-NEXT:    pushl %esi
+; I486-NEXT:    andl $-8, %esp
+; I486-NEXT:    subl $80, %esp
+; I486-NEXT:    movl 12(%ebp), %eax
+; I486-NEXT:    movl 8(%ebp), %ecx
+; I486-NEXT:    movl sc64+4, %edx
+; I486-NEXT:    movl sc64, %esi
+; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    jmp .LBB8_1
+; I486-NEXT:  .LBB8_1: # %atomicrmw.start
+; I486-NEXT:    # =>This Inner Loop Header: Depth=1
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; I486-NEXT:    subl %ecx, %edx
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
+; I486-NEXT:    sbbl %eax, %esi
+; I486-NEXT:    movl %ecx, %edi
+; I486-NEXT:    movl %eax, %ebx
+; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    jb .LBB8_4
+; I486-NEXT:  # %bb.3: # %atomicrmw.start
+; I486-NEXT:    # in Loop: Header=BB8_1 Depth=1
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:  .LBB8_4: # %atomicrmw.start
+; I486-NEXT:    # in Loop: Header=BB8_1 Depth=1
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; I486-NEXT:    movl %edx, {{[0-9]+}}(%esp)
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
+; I486-NEXT:    movl %esi, {{[0-9]+}}(%esp)
+; I486-NEXT:    movl %esp, %edi
+; I486-NEXT:    movl %eax, 12(%edi)
+; I486-NEXT:    movl %ecx, 8(%edi)
+; I486-NEXT:    leal {{[0-9]+}}(%esp), %eax
+; I486-NEXT:    movl %eax, 4(%edi)
+; I486-NEXT:    movl $2, 20(%edi)
+; I486-NEXT:    movl $2, 16(%edi)
+; I486-NEXT:    movl $sc64, (%edi)
+; I486-NEXT:    calll __atomic_compare_exchange_8
+; I486-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; I486-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; I486-NEXT:    testb %al, %al
+; I486-NEXT:    movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    je .LBB8_1
+; I486-NEXT:    jmp .LBB8_2
+; I486-NEXT:  .LBB8_2: # %atomicrmw.end
+; I486-NEXT:    leal -12(%ebp), %esp
+; I486-NEXT:    popl %esi
+; I486-NEXT:    popl %edi
+; I486-NEXT:    popl %ebx
+; I486-NEXT:    popl %ebp
+; I486-NEXT:    retl
   %t1 = atomicrmw umax i64* @sc64, i64 %x acquire
 
   ret void
 }
 
 define void @atomic_fetch_umin64(i64 %x) nounwind {
 ; X64-LABEL: atomic_fetch_umin64:
 ; X64:       # %bb.0:

 ; X64-NEXT:    sete %sil
 ; X64-NEXT:    testb $1, %sil
 ; X64-NEXT:    movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; X64-NEXT:    movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; X64-NEXT:    jne .LBB9_2
 ; X64-NEXT:    jmp .LBB9_1
 ; X64-NEXT:  .LBB9_2: # %atomicrmw.end
 ; X64-NEXT:    retq
+;
+; I486-LABEL: atomic_fetch_umin64:
+; I486:       # %bb.0:
+; I486-NEXT:    pushl %ebp
+; I486-NEXT:    movl %esp, %ebp
+; I486-NEXT:    pushl %ebx
+; I486-NEXT:    pushl %edi
+; I486-NEXT:    pushl %esi
+; I486-NEXT:    andl $-8, %esp
+; I486-NEXT:    subl $80, %esp
+; I486-NEXT:    movl 12(%ebp), %eax
+; I486-NEXT:    movl 8(%ebp), %ecx
+; I486-NEXT:    movl sc64+4, %edx
+; I486-NEXT:    movl sc64, %esi
+; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    jmp .LBB9_1
+; I486-NEXT:  .LBB9_1: # %atomicrmw.start
+; I486-NEXT:    # =>This Inner Loop Header: Depth=1
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; I486-NEXT:    subl %ecx, %edx
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
+; I486-NEXT:    sbbl %eax, %esi
+; I486-NEXT:    movl %ecx, %edi
+; I486-NEXT:    movl %eax, %ebx
+; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    jae .LBB9_4
+; I486-NEXT:  # %bb.3: # %atomicrmw.start
+; I486-NEXT:    # in Loop: Header=BB9_1 Depth=1
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:  .LBB9_4: # %atomicrmw.start
+; I486-NEXT:    # in Loop: Header=BB9_1 Depth=1
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; I486-NEXT:    movl %edx, {{[0-9]+}}(%esp)
+; I486-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
+; I486-NEXT:    movl %esi, {{[0-9]+}}(%esp)
+; I486-NEXT:    movl %esp, %edi
+; I486-NEXT:    movl %eax, 12(%edi)
+; I486-NEXT:    movl %ecx, 8(%edi)
+; I486-NEXT:    leal {{[0-9]+}}(%esp), %eax
+; I486-NEXT:    movl %eax, 4(%edi)
+; I486-NEXT:    movl $2, 20(%edi)
+; I486-NEXT:    movl $2, 16(%edi)
+; I486-NEXT:    movl $sc64, (%edi)
+; I486-NEXT:    calll __atomic_compare_exchange_8
+; I486-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; I486-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; I486-NEXT:    testb %al, %al
+; I486-NEXT:    movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    je .LBB9_1
+; I486-NEXT:    jmp .LBB9_2
+; I486-NEXT:  .LBB9_2: # %atomicrmw.end
+; I486-NEXT:    leal -12(%ebp), %esp
+; I486-NEXT:    popl %esi
+; I486-NEXT:    popl %edi
+; I486-NEXT:    popl %ebx
+; I486-NEXT:    popl %ebp
+; I486-NEXT:    retl
   %t1 = atomicrmw umin i64* @sc64, i64 %x acquire
 
   ret void
 }
 
 define void @atomic_fetch_cmpxchg64() nounwind {
 ; X64-LABEL: atomic_fetch_cmpxchg64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    xorl %eax, %eax
 ; X64-NEXT:    # kill: def $rax killed $eax
 ; X64-NEXT:    movl $1, %ecx
 ; X64-NEXT:    lock cmpxchgq %rcx, {{.*}}(%rip)
 ; X64-NEXT:    movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; X64-NEXT:    retq
+;
+; I486-LABEL: atomic_fetch_cmpxchg64:
+; I486:       # %bb.0:
+; I486-NEXT:    pushl %ebp
+; I486-NEXT:    movl %esp, %ebp
+; I486-NEXT:    andl $-8, %esp
+; I486-NEXT:    subl $40, %esp
+; I486-NEXT:    leal sc64, %eax
+; I486-NEXT:    leal {{[0-9]+}}(%esp), %ecx
+; I486-NEXT:    movl $0, {{[0-9]+}}(%esp)
+; I486-NEXT:    movl $0, {{[0-9]+}}(%esp)
+; I486-NEXT:    movl %esp, %edx
+; I486-NEXT:    movl %ecx, 4(%edx)
+; I486-NEXT:    movl $2, 20(%edx)
+; I486-NEXT:    movl $2, 16(%edx)
+; I486-NEXT:    movl $0, 12(%edx)
+; I486-NEXT:    movl $1, 8(%edx)
+; I486-NEXT:    movl $sc64, (%edx)
+; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    calll __atomic_compare_exchange_8
+; I486-NEXT:    movb %al, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
+; I486-NEXT:    movl %ebp, %esp
+; I486-NEXT:    popl %ebp
+; I486-NEXT:    retl
   %t1 = cmpxchg i64* @sc64, i64 0, i64 1 acquire acquire
   ret void
 }
 
 define void @atomic_fetch_store64(i64 %x) nounwind {
 ; X64-LABEL: atomic_fetch_store64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rdi, {{.*}}(%rip)
 ; X64-NEXT:    retq
+;
+; I486-LABEL: atomic_fetch_store64:
+; I486:       # %bb.0:
+; I486-NEXT:    pushl %esi
+; I486-NEXT:    subl $20, %esp
+; I486-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; I486-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; I486-NEXT:    leal sc64, %edx
+; I486-NEXT:    movl %esp, %esi
+; I486-NEXT:    movl %eax, 8(%esi)
+; I486-NEXT:    movl %ecx, 4(%esi)
+; I486-NEXT:    movl $3, 12(%esi)
+; I486-NEXT:    movl $sc64, (%esi)
+; I486-NEXT:    movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    calll __atomic_store_8
+; I486-NEXT:    addl $20, %esp
+; I486-NEXT:    popl %esi
+; I486-NEXT:    retl
   store atomic i64 %x, i64* @sc64 release, align 8
   ret void
 }
 
 define void @atomic_fetch_swap64(i64 %x) nounwind {
 ; X64-LABEL: atomic_fetch_swap64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    xchgq %rdi, {{.*}}(%rip)
 ; X64-NEXT:    movq %rdi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; X64-NEXT:    retq
+;
+; I486-LABEL: atomic_fetch_swap64:
+; I486:       # %bb.0:
+; I486-NEXT:    pushl %esi
+; I486-NEXT:    subl $28, %esp
+; I486-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; I486-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; I486-NEXT:    leal sc64, %edx
+; I486-NEXT:    movl %esp, %esi
+; I486-NEXT:    movl %eax, 8(%esi)
+; I486-NEXT:    movl %ecx, 4(%esi)
+; I486-NEXT:    movl $2, 12(%esi)
+; I486-NEXT:    movl $sc64, (%esi)
+; I486-NEXT:    movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    calll __atomic_exchange_8
+; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    addl $28, %esp
+; I486-NEXT:    popl %esi
+; I486-NEXT:    retl
   %t1 = atomicrmw xchg i64* @sc64, i64 %x acquire
   ret void
 }
 
 define void @atomic_fetch_swapf64(double %x) nounwind {
 ; X64-LABEL: atomic_fetch_swapf64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %xmm0, %rax
 ; X64-NEXT:    xchgq %rax, {{.*}}(%rip)
 ; X64-NEXT:    movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; X64-NEXT:    retq
+;
+; I486-LABEL: atomic_fetch_swapf64:
+; I486:       # %bb.0:
+; I486-NEXT:    pushl %ebp
+; I486-NEXT:    movl %esp, %ebp
+; I486-NEXT:    pushl %esi
+; I486-NEXT:    andl $-8, %esp
+; I486-NEXT:    subl $48, %esp
+; I486-NEXT:    fldl 8(%ebp)
+; I486-NEXT:    leal fsc64, %eax
+; I486-NEXT:    fstpl {{[0-9]+}}(%esp)
+; I486-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; I486-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; I486-NEXT:    movl %esp, %esi
+; I486-NEXT:    movl %edx, 8(%esi)
+; I486-NEXT:    movl %ecx, 4(%esi)
+; I486-NEXT:    movl $2, 12(%esi)
+; I486-NEXT:    movl $fsc64, (%esi)
+; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    calll __atomic_exchange_8
+; I486-NEXT:    movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT:    leal -4(%ebp), %esp
+; I486-NEXT:    popl %esi
+; I486-NEXT:    popl %ebp
+; I486-NEXT:    retl
   %t1 = atomicrmw xchg double* @fsc64, double %x acquire
   ret void
 }

llvm/test/CodeGen/X86/cmpxchg8b.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-unknown- -mcpu=core2 | FileCheck %s --check-prefixes=CHECK,X86
 ; RUN: llc < %s -mtriple=x86_64-unknown- -mcpu=core2 | FileCheck %s --check-prefixes=CHECK,X64
+; RUN: llc < %s -mtriple=i686-unknown- -mcpu=i486 | FileCheck %s --check-prefixes=I486
 
 ; Basic 64-bit cmpxchg
 define void @t1(i64* nocapture %p) nounwind ssp {
 ; X86-LABEL: t1:
 ; X86:       # %bb.0: # %entry
 ; X86-NEXT:    pushl %ebx
 ; X86-NEXT:    pushl %esi
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %esi
 ; X86-NEXT:    xorl %eax, %eax
 ; X86-NEXT:    xorl %edx, %edx
 ; X86-NEXT:    xorl %ecx, %ecx
 ; X86-NEXT:    movl $1, %ebx
 ; X86-NEXT:    lock cmpxchg8b (%esi)
 ; X86-NEXT:    popl %esi
 ; X86-NEXT:    popl %ebx
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: t1:
 ; X64:       # %bb.0: # %entry
 ; X64-NEXT:    movl $1, %ecx
 ; X64-NEXT:    xorl %eax, %eax
 ; X64-NEXT:    lock cmpxchgq %rcx, (%rdi)
 ; X64-NEXT:    retq
+;
+; I486-LABEL: t1:
+; I486:       # %bb.0: # %entry
+; I486-NEXT:    pushl %ebp
+; I486-NEXT:    movl %esp, %ebp
+; I486-NEXT:    andl $-8, %esp
+; I486-NEXT:    subl $8, %esp
+; I486-NEXT:    movl 8(%ebp), %eax
+; I486-NEXT:    movl $0, {{[0-9]+}}(%esp)
+; I486-NEXT:    movl $0, (%esp)
+; I486-NEXT:    movl %esp, %ecx
+; I486-NEXT:    pushl $5
+; I486-NEXT:    pushl $5
+; I486-NEXT:    pushl $0
+; I486-NEXT:    pushl $1
+; I486-NEXT:    pushl %ecx
+; I486-NEXT:    pushl %eax
+; I486-NEXT:    calll __atomic_compare_exchange_8
+; I486-NEXT:    addl $24, %esp
+; I486-NEXT:    movl %ebp, %esp
+; I486-NEXT:    popl %ebp
+; I486-NEXT:    retl
 entry:
   %r = cmpxchg i64* %p, i64 0, i64 1 seq_cst seq_cst
   ret void
 }