[LLD][ELF][ARM] Redesign of .ARM.exidx handling to use a SyntheticSection

[peter.smith]

Summary

In D58047 Synthesise missing .ARM.exidx sections. Rui made the comment

We used to handle .ARM.exidx sections as regular sections with a sentinel section that is synthesized and added to the end. We later added code to merge contiguous .ARM.exidx sections, and now this patch is adding sentinels at various points. At this point, maybe it is easier to handle .ARM.exidx as a single synthetic section just like MergeInputSection? That synthetic section removes all input section whose name is .ARM.exidx from the input section list and add itself to the input section. That design gives you more flexibility than the current design, as the intermediate data representation doesn't have to be an InputSection.

This is an implementation of the idea to handle .ARM.exidx processing inside a single SyntheticSection. It incorporates the changes in D58047 and reuses the test modifications. There is one additional test change to arm-data-prel.s to account for the single SyntheticSection. I've put what I think the advantages and disadvantages of the approach are below. At this stage I've tested it on the LLD test suite, I'm going to do some more testing on real world programs to make sure I haven't made any mistakes, but I think the approach can be made to work.

Assumptions:

• We can't get rid of SHF_LINK_ORDER as this is used by the sanitizers
• There is at most one .ARM.exidx OutputSection per link unit. This assumption may be broken with pcc's executable split into shared libraries proposal, but I think that this can be expanded to cover that case).

Requirements:

• .ARM.exidx InputSections form a single contiguous table with each entry a pair (Offset to function, Unwind instructions for function).
• The table must be ordered in the OutputSection according to the ascending order of function address.
• The address range of a table entry is [Address of function, Address of next function in table)
• The linker should synthesise table entries for functions that don't have them in order to terminate their address range.
• The linker should synthesise a terminating sentinel entry as some unwinders require it.
• The exidx_start and exidx_end symbols must be defined if referenced at the start and end of the table.
• A PT_ARM_EXIDX program header is created to describe the location of the contiguous range of .arm.exidx sections
• All .ARM.exidx InputSections including any synthetic sections can be DISCARDED

Design:
Instead of working backwards from the .ARM.exidx InputSections to the executable sections, work forwards from the executable sections in the output to find the .ARM.exidx sections in their dependentSections. This permits us to synthesize the EXIDX_CANTUNWIND range terminators and the sentinel in the table without having to create a new type of SyntheticSection to represent the linker created sections.

Changes:

• Writer.cpp: Instead of creating an ARMExidxSentinelSection we create an ARMExidxSyntheticSection that marks all the .ARM.exidx InputSections as not live.
• Writer.cpp: At SHF_LINK_ORDER processing time we call the finalizeContent() member function of ARMExidxSyntheticSection to perform the ordering and table compression.
• SyntheticSections.cpp: The writeTo() member function of the ARMExidxSyntheticSection needs to derive the table contents from the Executable InputSections.

Advantages:

• The vast majority of the ARM specific code is in ARMExidxSyntheticSection.
• We don't need to create multiple range terminating sentinel sections.

Disadvantages:

• To avoid duplicating a lot of the relocation code writeTo() takes advantage of the .ARM.exidx table structure. Modifying it may need more ARM specific knowledge.

I've kept D58047 open as it may be preferable to keep the old design rather than go down this path.

[pcc]

Thanks Peter. I think I prefer this approach.

ELF/SyntheticSections.cpp

3188 ↗

(On Diff #190095)

Should the handling of .ARM.exidx input sections look more like .eh_frame sections, perhaps? You could:

• remove .ARM.exidx sections from the InputSections list in combineEhFrameSections (and maybe rename the function) and add them to a separate list
• arrange for forEachRelSec to visit those sections

Now you should be able to write the sections in the usual way with writeTo.

ELF/Writer.cpp

1438 ↗

(On Diff #190095)

Can/should the ARMExidxSyntheticSection be a field in InStruct? Then it can be finalized with the other synthetic sections.

[ruiu]

Thanks Peter, I think I like this approach than the other one.

ELF/SyntheticSections.cpp

3058 ↗

(On Diff #190095)

Since you are using this variable only in ARMExidxSyntheticSection::writeTo, you can move this to that function.

3066 ↗

(On Diff #190095)

nit: I'd add {} to if if its else if has {}.

3095 ↗

(On Diff #190095)

Could you add a brief function comment?

[peter.smith]

Thanks for the comments, I'll upload another diff with the changes.

ELF/SyntheticSections.cpp

3188 ↗

(On Diff #190095)

Yes I think that is a better approach. I've updated the diff to do that.

[peter.smith]

Updated the diff with the requested changes. I've followed pcc's idea to make the section behave more like the EHFrame section. This gets rid of some of the nastier relocation handling code in writeTo().

[grimar]

Just a few nits about coding style from me.

ELF/SyntheticSections.cpp

3093 ↗

(On Diff #190262)

I think LLD style would be to use {, }:

else {
  Size += 8;
}

3098 ↗

(On Diff #190262)

Will it be better to do Size = 8; from start?

3136 ↗

(On Diff #190262)

No need to use curly bracers.

3217 ↗

(On Diff #190262)

Comments in LLD usually ends with a full stop.

[peter.smith]

Updated to make setSizeAndOffsets() use of Size less confusing, fixed some curly brace nits.

[ruiu]

Overall looking good.

ELF/SyntheticSections.cpp

3111 ↗

(On Diff #190270)

This does not capture anything, so I'd define it as a regular function instead of a lambda.

3121 ↗

(On Diff #190270)

Do you need to cast to ulittle32_t?

3137 ↗

(On Diff #190270)

I don't think you need a cast to ulittle32_t.

3169 ↗

(On Diff #190270)

Why don't you use back?

[pcc]

ELF/Writer.cpp

940 ↗

(On Diff #190270)

This should probably either call Fn or we should change forEachRelSec to not take a function parameter.

[peter.smith]

Thanks for the comments I'll update the diff.

ELF/SyntheticSections.cpp

3098 ↗

(On Diff #190262)

I'm using Size to set the OutSecOff so I need it to start from 0. I'll use a local Offset and derive Size from it to make that a bit clearer.

ELF/Writer.cpp

940 ↗

(On Diff #190270)

I've changed it to call Fn for the moment, a simple followup NFC refactoring change could remove the parameter if we thought there was not likely to be another likely use of forEachRelSec.

[peter.smith]

Updated diff to address review comments.

[peter.smith]

Ping. I think I have addressed all the existing comments. Happy to make any further changes if needed.

[ruiu]

LGTM

ELF/SyntheticSections.cpp

3121 ↗

(On Diff #190270)

I tried this and indeed you need a cast to ulittle32_t.

[peter.smith]

I've discovered 3 problems with this, the first 2 are trivial to fix, the last is not so I think I'll need to send for review when I've fixed rather than just recommit. The trivial problems are:

• When all the .ARM.exidx sections from input files are merged into a synthetic one the getLinkOrderDep() function can't find any .ARM.exidx section and returns nullptr.
  • 1 line fix to just return the front() of the ExecutableSections vector, as that will always exist.
• If the In.ARMexidx is discarded via \DISCARD\ then scanning its relocations adds a dependency to the personality routine (undefined symbol error).
  • 1 line fix to skip the relocation scanning if In.ARM.exidx is not live.

The difficult problem to fix is that --emit-relocs doesn't work with the SyntheticSection.

• The .ARM.exidx InputSections have been removed so there is no way to get the OutputSection
• If table merging is on then we end up with spurious relocations for the removed table. This is true of the existing implementation.

I'm investigating the best way of fixing this. The approach I'm currently favouring is following the example of EhInputSection. The alternative is some special cases for .ARM.exidx, I think that these could prove fragile so I'm tending towards the former even if it is more code.

[peter.smith]

In D59216#1439647, @peter.smith wrote:

I've discovered 3 problems with this, the first 2 are trivial to fix, the last is not so I think I'll need to send for review when I've fixed rather than just recommit. The trivial problems are:

• When all the .ARM.exidx sections from input files are merged into a synthetic one the getLinkOrderDep() function can't find any .ARM.exidx section and returns nullptr.
  • 1 line fix to just return the front() of the ExecutableSections vector, as that will always exist.
• If the In.ARMexidx is discarded via \DISCARD\ then scanning its relocations adds a dependency to the personality routine (undefined symbol error).
  • 1 line fix to skip the relocation scanning if In.ARM.exidx is not live.

The difficult problem to fix is that --emit-relocs doesn't work with the SyntheticSection.

• The .ARM.exidx InputSections have been removed so there is no way to get the OutputSection
• If table merging is on then we end up with spurious relocations for the removed table. This is true of the existing implementation.

I'm investigating the best way of fixing this. The approach I'm currently favouring is following the example of EhInputSection. The alternative is some special cases for .ARM.exidx, I think that these could prove fragile so I'm tending towards the former even if it is more code.

Updated diff with proposed fixes for the three problems found. As mentioned above the first two changes are trivial, I think the last should be looked at in case of disagreement. There are 3 problems caused by --emit-relocs:

• The relocation sections for the .ARM.exidx sections need to find the In.ARMExidx to find their OutputSection in an anlagous way to the EHInputSections need to find the In.EhFrame section.
• The merging of duplicate entries will result in removed .ARM.exidx sections, with --emit-relocs we'll need to remove the associated .rel.ARM.exidx section
• There are no .rel.ARM.exidx sections for linker created table entries.

I've fixed the first two parts with this diff. I don't think that there is an easy fix for --emit-relocs and linker created table entries. I'm not too worried about that as I don't think we do so for other synthetic sections like PLT entries. I'll add some comments to highlight the changes.

[peter.smith]

I've added comments to highlight the changes. I've also added test cases for them.

ELF/InputSection.cpp

198 ↗

(On Diff #192132)

In conjunction with making In.ARMexidx the parent of the input .ARM.exidx sections; this fixes a segfault when --emit-relocs is used.

ELF/OutputSections.cpp

314 ↗

(On Diff #192132)

This removes .rel.ARM.Exidx sections that are associated with merged .ARM.Exidx sections. A simpler but less effective fix would be to disable merging when --emit-relocs is used.

ELF/SyntheticSections.cpp

3180 ↗

(On Diff #192132)

This fixes a segfault when all ExecutableSections with a .ARM.exidx input section are merged as duplicates.

ELF/Writer.cpp

925 ↗

(On Diff #192132)

Added In.ARMExidx->Live to prevent undefined symbol errors caused by the personality routine being relocated against.

[ruiu]

This may be a silly question, but is --emit-reloc for .ARM.exidx important? If we re-create an .ARM.exidx section, we probably have to re-create a relocation section for .ARM.exidx just for --emit-relocs, but I'm wondering if there's an actual user who wants that behavior. Perhaps this is a kind of question no one really knows, though...

[peter.smith]

In D59216#1441965, @ruiu wrote:

This may be a silly question, but is --emit-reloc for .ARM.exidx important? If we re-create an .ARM.exidx section, we probably have to re-create a relocation section for .ARM.exidx just for --emit-relocs, but I'm wondering if there's an actual user who wants that behavior. Perhaps this is a kind of question no one really knows, though...

I think it is a good question. I've only come across two use cases for it, the first is as a form of dynamic linking for OS kernels that want to avoid GOT style PIE/PIC. Examples include x86 and mips linux kernel, and I've also seen it in Fuchsia, which may use Arm. However in the case of an OS kernel I'm not expecting any C++ exceptions. The second use case is binary analysis where some tool such as Facebook's Bolt post-processes the ELF file guided by the relocations, in this particular case I'm guessing that relocations in C++ exception tables aren't that interesting, it would certainly be possible to derive the relocations from the table output.

Given that the relocations for --emit-relocs had been broken when table merging is on for some time (retained relocations for dropped sections) I suspect that no-one cares about it right now. For now I'd be happy to remove all relocation sections from the Input .ARM.exidx sections when --emit-relocs were used. If someone came up with a critical use case then we could add them back. Does that sound like a way forward?

[peter.smith]

Updated the diff to just remove the .rel.ARM.exidx relocation sections when --emit-relocations is used. This is a few lines in the ARMExidxSyntheticSection constructor. This permits us to remove the additional fixup code in InputSections.cpp and OutputSections.cpp. The test remains to make sure we don't crash with --emit-relocs and to check that there are no .rel.ARM.exidx relocation sections.

[ruiu]

LGTM

lld/trunk/ELF/OutputSections.cpp

void OutputSection::finalize() {
   std::vector<InputSection *> V = getInputSections(this);
   InputSection *First = V.empty() ? nullptr : V[0];
 
   if (Flags & SHF_LINK_ORDER) {
     // We must preserve the link order dependency of sections with the
     // SHF_LINK_ORDER flag. The dependency is indicated by the sh_link field. We
     // need to translate the InputSection sh_link to the OutputSection sh_link,
     // all InputSections in the OutputSection have the same dependency.
-    if (auto *D = First->getLinkOrderDep())
+    if (auto *EX = dyn_cast<ARMExidxSyntheticSection>(First))
+      Link = EX->getLinkOrderDep()->getParent()->SectionIndex;
+    else if (auto *D = First->getLinkOrderDep())
       Link = D->getParent()->SectionIndex;
   }
 
   if (Type == SHT_GROUP) {
     finalizeShtGroup(this, First);
     return;
   }
 

lld/trunk/ELF/SyntheticSections.h

 // ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
 class MipsRldMapSection : public SyntheticSection {
 public:
   MipsRldMapSection();
   size_t getSize() const override { return Config->Wordsize; }
   void writeTo(uint8_t *Buf) override {}
 };
 
-class ARMExidxSentinelSection : public SyntheticSection {
+// Representation of the combined .ARM.Exidx input sections. We process these
+// as a SyntheticSection like .eh_frame as we need to merge duplicate entries
+// and add terminating sentinel entries.
+//
+// The .ARM.exidx input sections after SHF_LINK_ORDER processing is done form
+// a table that the unwinder can derive (Addresses are encoded as offsets from
+// table):
+// | Address of function | Unwind instructions for function |
+// where the unwind instructions are either a small number of unwind or the
+// special EXIDX_CANTUNWIND entry representing no unwinding information.
+// When an exception is thrown from an address A, the unwinder searches the
+// table for the closest table entry with Address of function <= A. This means
+// that for two consecutive table entries:
+// | A1 | U1 |
+// | A2 | U2 |
+// The range of addresses described by U1 is [A1, A2)
+//
+// There are two cases where we need a linker generated table entry to fixup
+// the address ranges in the table
+// Case 1:
+// - A sentinel entry added with an address higher than all
+// executable sections. This was needed to work around libunwind bug pr31091.
+// - After address assignment we need to find the highest addressed executable
+// section and use the limit of that section so that the unwinder never
+// matches it.
+// Case 2:
+// - InputSections without a .ARM.exidx section (usually from Assembly)
+// need a table entry so that they terminate the range of the previously
+// function. This is pr40277.
+//
+// Instead of storing pointers to the .ARM.exidx InputSections from
+// InputObjects, we store pointers to the executable sections that need
+// .ARM.exidx sections. We can then use the dependentSections of these to
+// either find the .ARM.exidx section or know that we need to generate one.
+class ARMExidxSyntheticSection : public SyntheticSection {
 public:
-  ARMExidxSentinelSection();
-  size_t getSize() const override { return 8; }
+  ARMExidxSyntheticSection();
+  size_t getSize() const override { return Size; }
   void writeTo(uint8_t *Buf) override;
-  bool empty() const override;
+  bool empty() const override { return Empty; }
+  // Sort and remove duplicate entries.
+  void finalizeContents() override;
+  InputSection *getLinkOrderDep() const;
 
   static bool classof(const SectionBase *D);
 
-  // The last section referenced by a regular .ARM.exidx section.
-  // It is found and filled in Writer<ELFT>::resolveShfLinkOrder().
-  // The sentinel points at the end of that section.
-  InputSection *Highest = nullptr;
+  // Links to the ARMExidxSections so we can transfer the relocations once the
+  // layout is known.
+  std::vector<InputSection *> ExidxSections;
+
+private:
+  // Derive Size from contents of ExecutableSections, including any linker
+  // generated sentinels. Also set the OutSecOff of the ExidxSections.
+  void setSizeAndOffsets();
+  size_t Size;
+
+  // Empty if ExecutableSections contains no dependent .ARM.exidx sections.
+  bool Empty = true;
+
+  // Instead of storing pointers to the .ARM.exidx InputSections from
+  // InputObjects, we store pointers to the executable sections that need
+  // .ARM.exidx sections. We can then use the dependentSections of these to
+  // either find the .ARM.exidx section or know that we need to generate one.
+  std::vector<InputSection *> ExecutableSections;
+
+  // The executable InputSection with the highest address to use for the
+  // sentinel. We store separately from ExecutableSections as merging of
+  // duplicate entries may mean this InputSection is removed from
+  // ExecutableSections.
+  InputSection *Sentinel = nullptr;
 };
 
 // A container for one or more linker generated thunks. Instances of these
 // thunks including ARM interworking and Mips LA25 PI to non-PI thunks.
 class ThunkSection : public SyntheticSection {
 public:
   // ThunkSection in OS, with desired OutSecOff of Off
   ThunkSection(OutputSection *OS, uint64_t Off);

 void mergeSections();
 
 Defined *addSyntheticLocal(StringRef Name, uint8_t Type, uint64_t Value,
                            uint64_t Size, InputSectionBase &Section);
 
 // Linker generated sections which can be used as inputs.
 struct InStruct {
   InputSection *ARMAttributes;
+  ARMExidxSyntheticSection *ARMExidx;
   BssSection *Bss;
   BssSection *BssRelRo;
   BuildIdSection *BuildId;
   EhFrameHeader *EhFrameHdr;
   EhFrameSection *EhFrame;
   SyntheticSection *Dynamic;
   StringTableSection *DynStrTab;
   SymbolTableBaseSection *DynSymTab;

lld/trunk/ELF/SyntheticSections.cpp

void elf::mergeSections() {
   std::vector<InputSectionBase *> &V = InputSections;
   V.erase(std::remove(V.begin(), V.end(), nullptr), V.end());
 }
 
 MipsRldMapSection::MipsRldMapSection()
     : SyntheticSection(SHF_ALLOC | SHF_WRITE, SHT_PROGBITS, Config->Wordsize,
                        ".rld_map") {}
 
-ARMExidxSentinelSection::ARMExidxSentinelSection()
+ARMExidxSyntheticSection::ARMExidxSyntheticSection()
     : SyntheticSection(SHF_ALLOC | SHF_LINK_ORDER, SHT_ARM_EXIDX,
-                       Config->Wordsize, ".ARM.exidx") {}
+                       Config->Wordsize, ".ARM.exidx") {
+  for (InputSectionBase *&IS : InputSections) {
+    if (isa<InputSection>(IS) && IS->Type == SHT_ARM_EXIDX) {
+      ExidxSections.push_back(cast<InputSection>(IS));
+      IS = nullptr;
+    } else if (IS->Live && isa<InputSection>(IS) &&
+               IS->kind() != SectionBase::Synthetic &&
+               (IS->Flags & SHF_ALLOC) && (IS->Flags & SHF_EXECINSTR) &&
+               IS->getSize() > 0) {
+      ExecutableSections.push_back(cast<InputSection>(IS));
+    }
+  }
+  setSizeAndOffsets();
+
+  // FIXME: we do not output a relocation section when --emit-relocs is used
+  // as we do not have relocation sections for linker generated table entries
+  // and we would have to erase at a late stage relocations from merged entries.
+  // Given that exception tables are already position independent and a binary
+  // analyzer could derive the relocations we choose to erase the relocations.
+  if (Config->EmitRelocs)
+    for (InputSectionBase *&IS : InputSections)
+      if (IS && isa<InputSection>(IS) && IS->Type == SHT_REL) {
+        InputSection *RS = cast<InputSection>(IS);
+        if (InputSectionBase *EX = RS->getRelocatedSection())
+          if (isa<InputSection>(EX) && EX->Type == SHT_ARM_EXIDX)
+            IS = nullptr;
+      }
+
+  std::vector<InputSectionBase *> &V = InputSections;
+  V.erase(std::remove(V.begin(), V.end(), nullptr), V.end());
+}
+
+static InputSection *findExidxSection(InputSection *IS) {
+  for (InputSection *D : IS->DependentSections)
+    if (D->Type == SHT_ARM_EXIDX)
+      return D;
+  return nullptr;
+}
+
+void ARMExidxSyntheticSection::setSizeAndOffsets() {
+  size_t Offset = 0;
+  Size = 0;
+  for (InputSection *IS : ExecutableSections) {
+    if (InputSection *D = findExidxSection(IS)) {
+      D->OutSecOff = Offset;
+      D->Parent = getParent();
+      Offset += D->getSize();
+      Empty = false;
+    } else {
+      Offset += 8;
+    }
+  }
+  // Size includes Sentinel.
+  Size = Offset + 8;
+}
+
+// References to .ARM.Extab Sections have bit 31 clear and are not the
+// special EXIDX_CANTUNWIND bit-pattern.
+static bool isExtabRef(uint32_t Unwind) {
+  return (Unwind & 0x80000000) == 0 && Unwind != 0x1;
+}
+
+// Return true if the .ARM.exidx section Cur can be merged into the .ARM.exidx
+// section Prev, where Cur follows Prev in the table. This can be done if the
+// unwinding instructions in Cur are identical to Prev. Linker generated
+// EXIDX_CANTUNWIND entries are represented by nullptr as they do not have an
+// InputSection.
+static bool isDuplicateArmExidxSec(InputSection *Prev, InputSection *Cur) {
 
-// Write a terminating sentinel entry to the end of the .ARM.exidx table.
-// This section will have been sorted last in the .ARM.exidx table.
-// This table entry will have the form:
-// | PREL31 upper bound of code that has exception tables | EXIDX_CANTUNWIND |
-// The sentinel must have the PREL31 value of an address higher than any
-// address described by any other table entry.
-void ARMExidxSentinelSection::writeTo(uint8_t *Buf) {
-  assert(Highest);
-  uint64_t S = Highest->getVA(Highest->getSize());
-  uint64_t P = getVA();
-  Target->relocateOne(Buf, R_ARM_PREL31, S - P);
-  write32le(Buf + 4, 1);
-}
-
-// The sentinel has to be removed if there are no other .ARM.exidx entries.
-bool ARMExidxSentinelSection::empty() const {
-  for (InputSection *IS : getInputSections(getParent()))
-    if (!isa<ARMExidxSentinelSection>(IS))
-      return false;
+  struct ExidxEntry {
+    ulittle32_t Fn;
+    ulittle32_t Unwind;
+  };
+  // Get the last table Entry from the previous .ARM.exidx section. If Prev is
+  // nullptr then it will be a synthesized EXIDX_CANTUNWIND entry.
+  ExidxEntry PrevEntry = {ulittle32_t(0), ulittle32_t(1)};
+  if (Prev)
+    PrevEntry = Prev->getDataAs<ExidxEntry>().back();
+  if (isExtabRef(PrevEntry.Unwind))
+
+  // We consider the unwind instructions of an .ARM.exidx table entry
+  // a duplicate if the previous unwind instructions if:
+  // - Both are the special EXIDX_CANTUNWIND.
+  // - Both are the same inline unwind instructions.
+  // We do not attempt to follow and check links into .ARM.extab tables as
+  // consecutive identical entries are rare and the effort to check that they
+  // are identical is high.
+
+  // If Cur is nullptr then this is synthesized EXIDX_CANTUNWIND entry.
+  if (Cur == nullptr)
+    return PrevEntry.Unwind == 1;
+
+  for (const ExidxEntry Entry : Cur->getDataAs<ExidxEntry>())
+    if (isExtabRef(Entry.Unwind) || Entry.Unwind != PrevEntry.Unwind)
+      return false;
+
+  // All table entries in this .ARM.exidx Section can be merged into the
+  // previous Section.
   return true;
 }
 
-bool ARMExidxSentinelSection::classof(const SectionBase *D) {
+// The .ARM.exidx table must be sorted in ascending order of the address of the
+// functions the table describes. Optionally duplicate adjacent table entries
+// can be removed. At the end of the function the ExecutableSections must be
+// sorted in ascending order of address, Sentinel is set to the InputSection
+// with the highest address and any InputSections that have mergeable
+// .ARM.exidx table entries are removed from it.
+void ARMExidxSyntheticSection::finalizeContents() {
+  // Sort the executable sections that may or may not have associated
+  // .ARM.exidx sections by order of ascending address. This requires the
+  // relative positions of InputSections to be known.
+  auto CompareByFilePosition = [](const InputSection *A,
+                                  const InputSection *B) {
+    OutputSection *AOut = A->getParent();
+    OutputSection *BOut = B->getParent();
+
+    if (AOut != BOut)
+      return AOut->SectionIndex < BOut->SectionIndex;
+    return A->OutSecOff < B->OutSecOff;
+  };
+  std::stable_sort(ExecutableSections.begin(), ExecutableSections.end(),
+                   CompareByFilePosition);
+  Sentinel = ExecutableSections.back();
+  // Optionally merge adjacent duplicate entries.
+  if (Config->MergeArmExidx) {
+    std::vector<InputSection *> SelectedSections;
+    SelectedSections.reserve(ExecutableSections.size());
+    SelectedSections.push_back(ExecutableSections[0]);
+    size_t Prev = 0;
+    for (size_t I = 1; I < ExecutableSections.size(); ++I) {
+      InputSection *EX1 = findExidxSection(ExecutableSections[Prev]);
+      InputSection *EX2 = findExidxSection(ExecutableSections[I]);
+      if (!isDuplicateArmExidxSec(EX1, EX2)) {
+        SelectedSections.push_back(ExecutableSections[I]);
+        Prev = I;
+      }
+    }
+    ExecutableSections = std::move(SelectedSections);
+  }
+  setSizeAndOffsets();
+}
+
+InputSection *ARMExidxSyntheticSection::getLinkOrderDep() const {
+  return ExecutableSections.front();
+}
+
+// To write the .ARM.exidx table from the ExecutableSections we have three cases
+// 1.) The InputSection has a .ARM.exidx InputSection in its dependent sections.
+//     We write the .ARM.exidx section contents and apply its relocations.
+// 2.) The InputSection does not have a dependent .ARM.exidx InputSection. We
+//     must write the contents of an EXIDX_CANTUNWIND directly. We use the
+//     start of the InputSection as the purpose of the linker generated
+//     section is to terminate the address range of the previous entry.
+// 3.) A trailing EXIDX_CANTUNWIND sentinel section is required at the end of
+//     the table to terminate the address range of the final entry.
+void ARMExidxSyntheticSection::writeTo(uint8_t *Buf) {
+
+  const uint8_t CantUnwindData[8] = {0, 0, 0, 0,  // PREL31 to target
+                                     1, 0, 0, 0}; // EXIDX_CANTUNWIND
+
+  uint64_t Offset = 0;
+  for (InputSection *IS : ExecutableSections) {
+    assert(IS->getParent() != nullptr);
+    if (InputSection *D = findExidxSection(IS)) {
+      memcpy(Buf + Offset, D->data().data(), D->data().size());
+      D->relocateAlloc(Buf, Buf + D->getSize());
+      Offset += D->getSize();
+    } else {
+      // A Linker generated CANTUNWIND section.
+      memcpy(Buf + Offset, CantUnwindData, sizeof(CantUnwindData));
+      uint64_t S = IS->getVA();
+      uint64_t P = getVA() + Offset;
+      Target->relocateOne(Buf + Offset, R_ARM_PREL31, S - P);
+      Offset += 8;
+    }
+  }
+  // Write Sentinel.
+  memcpy(Buf + Offset, CantUnwindData, sizeof(CantUnwindData));
+  uint64_t S = Sentinel->getVA(Sentinel->getSize());
+  uint64_t P = getVA() + Offset;
+  Target->relocateOne(Buf + Offset, R_ARM_PREL31, S - P);
+  assert(Size == Offset + 8);
+}
+
+bool ARMExidxSyntheticSection::classof(const SectionBase *D) {
   return D->kind() == InputSectionBase::Synthetic && D->Type == SHT_ARM_EXIDX;
 }
 
 ThunkSection::ThunkSection(OutputSection *OS, uint64_t Off)
     : SyntheticSection(SHF_ALLOC | SHF_EXECINSTR, SHT_PROGBITS,
                        Config->Wordsize, ".text.thunk") {
   this->Parent = OS;
   this->OutSecOff = Off;

lld/trunk/ELF/Writer.cpp

template <class ELFT> static void createSyntheticSections() {
   if (In.SymTab)
     Add(In.SymTab);
   if (In.SymTabShndx)
     Add(In.SymTabShndx);
   Add(In.ShStrTab);
   if (In.StrTab)
     Add(In.StrTab);
 
-  if (Config->EMachine == EM_ARM && !Config->Relocatable)
-    // Add a sentinel to terminate .ARM.exidx. It helps an unwinder
-    // to find the exact address range of the last entry.
-    Add(make<ARMExidxSentinelSection>());
+  if (Config->EMachine == EM_ARM && !Config->Relocatable) {
+    // The ARMExidxsyntheticsection replaces all the individual .ARM.exidx
+    // InputSections.
+    In.ARMExidx = make<ARMExidxSyntheticSection>();
+    Add(In.ARMExidx);
+  }
 }
 
 // The main function of the writer.
 template <class ELFT> void Writer<ELFT>::run() {
   // Create linker-synthesized sections such as .got or .plt.
   // Such sections are of type input section.
   createSyntheticSections<ELFT>();
 
void Writer<ELFT>::forEachRelSec(
   // creating GOT, PLT, copy relocations, etc.
   // Note that relocations for non-alloc sections are directly
   // processed by InputSection::relocateNonAlloc.
   for (InputSectionBase *IS : InputSections)
     if (IS->Live && isa<InputSection>(IS) && (IS->Flags & SHF_ALLOC))
       Fn(*IS);
   for (EhInputSection *ES : In.EhFrame->Sections)
     Fn(*ES);
+  if (In.ARMExidx && In.ARMExidx->Live)
+    for (InputSection *Ex : In.ARMExidx->ExidxSections)
+      Fn(*Ex);
 }
 
 // This function generates assignments for predefined symbols (e.g. _end or
 // _etext) and inserts them into the commands sequence to be processed at the
 // appropriate time. This ensures that the value is going to be correct by the
 // time any references to these symbols are processed and is equivalent to
 // defining these symbols explicitly in the linker script.
 template <class ELFT> void Writer<ELFT>::setReservedSymbolSections() {
while (NonScriptI != E) {
     std::rotate(Pos, NonScriptI, End);
     NonScriptI = End;
   }
 
   Script->adjustSectionsAfterSorting();
 }
 
 static bool compareByFilePosition(InputSection *A, InputSection *B) {
-  // Synthetic, i. e. a sentinel section, should go last.
-  if (A->kind() == InputSectionBase::Synthetic ||
-      B->kind() == InputSectionBase::Synthetic)
-    return A->kind() != InputSectionBase::Synthetic;
-
   InputSection *LA = A->getLinkOrderDep();
   InputSection *LB = B->getLinkOrderDep();
   OutputSection *AOut = LA->getParent();
   OutputSection *BOut = LB->getParent();
 
   if (AOut != BOut)
     return AOut->SectionIndex < BOut->SectionIndex;
   return LA->OutSecOff < LB->OutSecOff;
 }
 
-// This function is used by the --merge-exidx-entries to detect duplicate
-// .ARM.exidx sections. It is Arm only.
-//
-// The .ARM.exidx section is of the form:
-// | PREL31 offset to function | Unwind instructions for function |
-// where the unwind instructions are either a small number of unwind
-// instructions inlined into the table entry, the special CANT_UNWIND value of
-// 0x1 or a PREL31 offset into a .ARM.extab Section that contains unwind
-// instructions.
-//
-// We return true if all the unwind instructions in the .ARM.exidx entries of
-// Cur can be merged into the last entry of Prev.
-static bool isDuplicateArmExidxSec(InputSection *Prev, InputSection *Cur) {
-
-  // References to .ARM.Extab Sections have bit 31 clear and are not the
-  // special EXIDX_CANTUNWIND bit-pattern.
-  auto IsExtabRef = [](uint32_t Unwind) {
-    return (Unwind & 0x80000000) == 0 && Unwind != 0x1;
-  };
-
-  struct ExidxEntry {
-    ulittle32_t Fn;
-    ulittle32_t Unwind;
-  };
-
-  // Get the last table Entry from the previous .ARM.exidx section.
-  const ExidxEntry &PrevEntry = Prev->getDataAs<ExidxEntry>().back();
-  if (IsExtabRef(PrevEntry.Unwind))
-    return false;
-
-  // We consider the unwind instructions of an .ARM.exidx table entry
-  // a duplicate if the previous unwind instructions if:
-  // - Both are the special EXIDX_CANTUNWIND.
-  // - Both are the same inline unwind instructions.
-  // We do not attempt to follow and check links into .ARM.extab tables as
-  // consecutive identical entries are rare and the effort to check that they
-  // are identical is high.
-
-  for (const ExidxEntry Entry : Cur->getDataAs<ExidxEntry>())
-    if (IsExtabRef(Entry.Unwind) || Entry.Unwind != PrevEntry.Unwind)
-      return false;
-
-  // All table entries in this .ARM.exidx Section can be merged into the
-  // previous Section.
-  return true;
-}
-
 template <class ELFT> void Writer<ELFT>::resolveShfLinkOrder() {
   for (OutputSection *Sec : OutputSections) {
     if (!(Sec->Flags & SHF_LINK_ORDER))
       continue;
 
     // Link order may be distributed across several InputSectionDescriptions
     // but sort must consider them all at once.
     std::vector<InputSection **> ScriptSections;
     std::vector<InputSection *> Sections;
     for (BaseCommand *Base : Sec->SectionCommands) {
       if (auto *ISD = dyn_cast<InputSectionDescription>(Base)) {
         for (InputSection *&IS : ISD->Sections) {
           ScriptSections.push_back(&IS);
           Sections.push_back(IS);
         }
       }
     }
-    std::stable_sort(Sections.begin(), Sections.end(), compareByFilePosition);
 
+    // The ARM.exidx section use SHF_LINK_ORDER, but we have consolidated
+    // this processing inside the ARMExidxsyntheticsection::finalizeContents().
     if (!Config->Relocatable && Config->EMachine == EM_ARM &&
-        Sec->Type == SHT_ARM_EXIDX) {
+        Sec->Type == SHT_ARM_EXIDX)
+      continue;
 
-      if (auto *Sentinel = dyn_cast<ARMExidxSentinelSection>(Sections.back())) {
-        assert(Sections.size() >= 2 &&
-               "We should create a sentinel section only if there are "
-               "alive regular exidx sections.");
-
-        // The last executable section is required to fill the sentinel.
-        // Remember it here so that we don't have to find it again.
-        Sentinel->Highest = Sections[Sections.size() - 2]->getLinkOrderDep();
-      }
-
-      // The EHABI for the Arm Architecture permits consecutive identical
-      // table entries to be merged. We use a simple implementation that
-      // removes a .ARM.exidx Input Section if it can be merged into the
-      // previous one. This does not require any rewriting of InputSection
-      // contents but misses opportunities for fine grained deduplication
-      // where only a subset of the InputSection contents can be merged.
-      if (Config->MergeArmExidx) {
-        size_t Prev = 0;
-        // The last one is a sentinel entry which should not be removed.
-        for (size_t I = 1; I < Sections.size() - 1; ++I) {
-          if (isDuplicateArmExidxSec(Sections[Prev], Sections[I]))
-            Sections[I] = nullptr;
-          else
-            Prev = I;
-        }
-      }
-    }
+    std::stable_sort(Sections.begin(), Sections.end(), compareByFilePosition);
 
     for (int I = 0, N = Sections.size(); I < N; ++I)
       *ScriptSections[I] = Sections[I];
-
-    // Remove the Sections we marked as duplicate earlier.
-    for (BaseCommand *Base : Sec->SectionCommands)
-      if (auto *ISD = dyn_cast<InputSectionDescription>(Base))
-        llvm::erase_if(ISD->Sections, [](InputSection *IS) { return !IS; });
   }
 }
 
 // For most RISC ISAs, we need to generate content that depends on the address
 // of InputSections. For example some architectures such as AArch64 use small
 // displacements for jump instructions that is the linker's responsibility for
 // creating range extension thunks for. As the generation of the content may
 // also alter InputSection addresses we must converge to a fixed point.
template <class ELFT> void Writer<ELFT>::finalizeSections() {
 
   // Some symbols are defined in term of program headers. Now that we
   // have the headers, we can find out which sections they point to.
   setReservedSymbolSections();
 
   // Dynamic section must be the last one in this list and dynamic
   // symbol table section (DynSymTab) must be the first one.
   finalizeSynthetic(In.DynSymTab);
+  finalizeSynthetic(In.ARMExidx);
   finalizeSynthetic(In.Bss);
   finalizeSynthetic(In.BssRelRo);
   finalizeSynthetic(In.GnuHashTab);
   finalizeSynthetic(In.HashTab);
   finalizeSynthetic(In.SymTabShndx);
   finalizeSynthetic(In.ShStrTab);
   finalizeSynthetic(In.StrTab);
   finalizeSynthetic(In.VerDef);
template <class ELFT> void Writer<ELFT>::finalizeSections() {
   finalizeSynthetic(In.EhFrameHdr);
   finalizeSynthetic(In.VerSym);
   finalizeSynthetic(In.VerNeed);
   finalizeSynthetic(In.Dynamic);
 
   if (!Script->HasSectionsCommand && !Config->Relocatable)
     fixSectionAlignments();
 
-  // After link order processing .ARM.exidx sections can be deduplicated, which
-  // needs to be resolved before any other address dependent operation.
+  // SHFLinkOrder processing must be processed after relative section placements are
+  // known but before addresses are allocated.
   resolveShfLinkOrder();
 
   // Jump instructions in many ISAs have small displacements, and therefore they
   // cannot jump to arbitrary addresses in memory. For example, RISC-V JAL
   // instruction can target only +-1 MiB from PC. It is a linker's
   // responsibility to create and insert small pieces of code between sections
   // to extend the ranges if jump targets are out of range. Such code pieces are
   // called "thunks".

lld/trunk/test/ELF/arm-data-prel.s

 // REQUIRES: arm
-// RUN: llvm-mc %s -triple=armv7-unknown-linux-gnueabi -filetype=obj -o %t.o
+// RUN: llvm-mc %s -triple=armv7-unknown-linux-gnueabi -filetype=obj --arm-add-build-attributes -o %t.o
 // RUN: echo "SECTIONS { \
 // RUN:          .text : { *(.text) } \
 // RUN:          .prel.test : { *(.ARM.exidx) } \
-// RUN:          .prel.test.TEST1 : { *(.ARM.exidx.TEST1) } \
 // RUN:          .TEST1 : { *(.TEST1) } } " > %t.script
 // RUN: ld.lld --script %t.script %t.o -o %t
 // RUN: llvm-readobj -s -sd %t | FileCheck --check-prefix=CHECK %s
 
 // The R_ARM_PREL31 relocation is used in by the .ARM.exidx exception tables
 // bit31 of the place denotes whether the field is an inline table entry
 // (bit31=1) or relocation (bit31=0)
 // The linker must preserve the value of bit31

 __aeabi_unwind_cpp_pr0:
  .fnstart
  bx lr
  .fnend
 
 // The expected value of the exception table is
 // Word0 0 in bit 31, -4 encoded in 31-bit signed offset
 // Word1 Inline table entry EHT Inline Personality Routine #0
-// CHECK:  Name: .prel.test
-// CHECK:  SectionData (
-// CHECK:     0000: FCFFFF7F B0B0B080
-// CHECK:  )
-
-// The expected value of the exception table is
-// Word0 0 in bit 31, +8 encoded in 31-bit signed offset
-// Word1 Inline table entry EHT Inline Personality Routine #0
+// Word3 0 in bit 31, +10 encoded in 31-bit signed offset
+// Word4 Inline table entry EHT Inline Personality Routine #0
 // set vsp = r11
 // pop r11, r14
-// CHECK:  Name: .prel.test.TEST1
+// Word5 Sentinel +18 EXIDX_CANTUNWIND
+
+// CHECK:  Name: .prel.test
 // CHECK:  SectionData (
-// CHECK:     0000: 08000000 80849B80
+// CHECK:     0000: FCFFFF7F B0B0B080 10000000 80849B80
+// CHECK:     0010: 18000000 01000000
 // CHECK:  )

lld/trunk/test/ELF/arm-exidx-add-missing.s

+// REQUIRES: arm
+// RUN: llvm-mc -filetype=obj -triple=armv7a-none-linux-gnueabi --arm-add-build-attributes %s -o %t
+// RUN: ld-lld %t --no-merge-exidx-entries -o %t2
+// RUN: llvm-objdump -s %t2 | FileCheck %s
+// RUN: ld-lld %t -o %t3
+// RUN: llvm-objdump -s %t3 | FileCheck %s -check-prefix=CHECK-MERGE
+
+// The ARM.exidx section is a table of 8-byte entries of the form:
+// | PREL31 Relocation to start of function | Unwinding information |
+// The range of addresses covered by the table entry is terminated by the
+// next table entry. This means that an executable section without a .ARM.exidx
+// section does not terminate the range of addresses. To fix this the linker
+// synthesises an EXIDX_CANTUNWIND entry for each section wihout a .ARM.exidx
+// section.
+
+        .syntax unified
+
+        // Expect inline unwind instructions
+        .section .text.01, "ax", %progbits
+        .global f1
+f1:
+        .fnstart
+        bx lr
+        .save {r7, lr}
+        .setfp r7, sp, #0
+        .fnend
+
+        // Expect no unwind information from assembler. The linker must
+        // synthesise an EXIDX_CANTUNWIND entry to prevent an exception
+        // thrown through f2 from matching against the unwind instructions
+        // for f1.
+        .section .text.02, "ax", %progbits
+        .global f2
+f2:
+        bx lr
+
+
+        // Expect 1 EXIDX_CANTUNWIND entry that can be merged into the linker
+        // generated EXIDX_CANTUNWIND as if the assembler had generated it.
+        .section .text.03, "ax",%progbits
+        .global f3
+f3:
+        .fnstart
+        bx lr
+        .cantunwind
+        .fnend
+
+        // Dummy implementation of personality routines to satisfy reference
+        // from exception tables, linker will generate EXIDX_CANTUNWIND.
+        .section .text.__aeabi_unwind_cpp_pr0, "ax", %progbits
+        .global __aeabi_unwind_cpp_pr0
+__aeabi_unwind_cpp_pr0:
+        bx lr
+
+// f1, f2
+// CHECK:      100d4 2c0f0000 08849780 280f0000 01000000
+// f3, __aeabi_unwind_cpp_pr0
+// CHECK-NEXT: 100e4 240f0000 01000000 200f0000 01000000
+// sentinel
+// CHECK-NEXT: 100f4 1c0f0000 01000000
+
+// f1, (f2, f3, __aeabi_unwind_cpp_pr0)
+// CHECK-MERGE:      100d4 2c0f0000 08849780 280f0000 01000000
+// sentinel
+// CHECK-MERGE-NEXT: 100e4 2c0f0000 01000000
+

lld/trunk/test/ELF/arm-exidx-canunwind.s

 // REQUIRES: arm
-// RUN: llvm-mc -filetype=obj -triple=armv7a-none-linux-gnueabi %s -o %t
-// RUN: ld.lld %t -o %t2 2>&1
+// RUN: llvm-mc -filetype=obj --arm-add-build-attributes -triple=armv7a-none-linux-gnueabi %s -o %t
+// RUN: ld.lld %t -o %t2
 // RUN: llvm-objdump -d -triple=armv7a-none-linux-gnueabi %t2 | FileCheck %s
 // RUN: llvm-objdump -s -triple=armv7a-none-linux-gnueabi %t2 | FileCheck -check-prefix=CHECK-EXIDX %s
 // RUN: llvm-readobj --program-headers --sections %t2 | FileCheck -check-prefix=CHECK-PT %s
 
 // Test that inline unwinding table entries and references to .ARM.extab
 // entries survive the re-ordering of the .ARM.exidx section
 
  .syntax unified

 // CHECK-NEXT:    1100c:       1e ff 2f e1     bx      lr
 // CHECK:      func2:
 // CHECK-NEXT:    11010:       1e ff 2f e1     bx      lr
 // CHECK:      __gxx_personality_v0:
 // CHECK-NEXT:    11014:       1e ff 2f e1     bx      lr
 // CHECK:      __aeabi_unwind_cpp_pr0:
 // CHECK-NEXT:    11018:       1e ff 2f e1     bx      lr
 
-// CHECK-EXIDX: Contents of section .ARM.exidx:
-// 100d4 + f38 = 1100c = func1 (inline unwinding data)
-// 100dc + f34 = 11010 = func2 (100e0 + c = 100ec = .ARM.extab entry)
-// CHECK-EXIDX-NEXT: 100d4 380f0000 08849780 340f0000 0c000000
-// 100e4 + f30 = 11014 = terminate = func2 + sizeof(func2)
-// CHECK-EXIDX-NEXT: 100e4 300f0000 01000000
-// CHECK-EXIDX-NEXT: Contents of section .ARM.extab:
-// 100ec + f28 = 11014 = __gxx_personality_v0
-// CHECK-EXIDX-NEXT: 100ec 280f0000 b0b0b000 00000000
+// 100d4 + f2c = 11000 = main (linker generated cantunwind)
+// 100dc + f30 = 1100c = func1 (inline unwinding data)
+// CHECK-EXIDX:      100d4 2c0f0000 01000000 300f0000 08849780
+// 100e4 + f2c = 11010 = func2 (100e8 + 14 = 100fc = .ARM.extab entry)
+// 100ec + f28 = 11014 = __gcc_personality_v0 (linker generated cantunwind)
+// CHECK-EXIDX-NEXT: 100e4 2c0f0000 14000000 280f0000 01000000
+// 100f4 + f28 = 1101c = sentinel
+// CHECK-EXIDX-NEXT: 100f4 280f0000 01000000
 
 // CHECK-PT:          Name: .ARM.exidx
 // CHECK-PT-NEXT:     Type: SHT_ARM_EXIDX (0x70000001)
 // CHECK-PT-NEXT:     Flags [
 // CHECK-PT-NEXT:       SHF_ALLOC
 // CHECK-PT-NEXT:       SHF_LINK_ORDER
 // CHECK-PT-NEXT:     ]
 // CHECK-PT-NEXT:     Address: 0x100D4
 // CHECK-PT-NEXT:     Offset: 0xD4
-// CHECK-PT-NEXT:     Size: 24
+// CHECK-PT-NEXT:     Size: 40
 
 // CHECK-PT:          Type: PT_ARM_EXIDX (0x70000001)
 // CHECK-PT-NEXT:     Offset: 0xD4
 // CHECK-PT-NEXT:     VirtualAddress: 0x100D4
 // CHECK-PT-NEXT:     PhysicalAddress: 0x100D4
-// CHECK-PT-NEXT:     FileSize: 24
-// CHECK-PT-NEXT:     MemSize: 24
+// CHECK-PT-NEXT:     FileSize: 40
+// CHECK-PT-NEXT:     MemSize: 40
 // CHECK-PT-NEXT:     Flags [ (0x4)
 // CHECK-PT-NEXT:       PF_R (0x4)
 // CHECK-PT-NEXT:     ]
 // CHECK-PT-NEXT:     Alignment: 4
 // CHECK-PT-NEXT:   }

lld/trunk/test/ELF/arm-exidx-dedup.s

 // REQUIRES: arm
-// RUN: llvm-mc -filetype=obj -triple=armv7a-none-linux-gnueabi %s -o %t
+// RUN: llvm-mc -filetype=obj --arm-add-build-attributes -triple=armv7a-none-linux-gnueabi %s -o %t
 // RUN: ld.lld %t --no-merge-exidx-entries -o %t2
 // RUN: llvm-objdump -s %t2 | FileCheck --check-prefix CHECK-DUPS %s
 // RUN: ld.lld %t -o %t3
 // RUN: llvm-objdump -s %t3 | FileCheck %s
+
 // Test that lld can at least remove duplicate .ARM.exidx sections. A more
 // fine grained implementation will be able to remove duplicate entries within
 // a .ARM.exidx section.
 
 // With duplicate entries
 // CHECK-DUPS: Contents of section .ARM.exidx:
-// CHECK-DUPS-NEXT:  100d4 2c0f0000 01000000 280f0000 01000000
-// CHECK-DUPS-NEXT:  100e4 240f0000 01000000 200f0000 01000000
-// CHECK-DUPS-NEXT:  100f4 1c0f0000 08849780 180f0000 08849780
-// CHECK-DUPS-NEXT:  10104 140f0000 08849780 100f0000 14000000
-// CHECK-DUPS-NEXT:  10114 0c0f0000 18000000 080f0000 01000000
+// CHECK-DUPS-NEXT: 100d4 2c0f0000 01000000 280f0000 01000000
+// CHECK-DUPS-NEXT: 100e4 240f0000 01000000 200f0000 01000000
+// CHECK-DUPS-NEXT: 100f4 1c0f0000 08849780 180f0000 08849780
+// CHECK-DUPS-NEXT: 10104 140f0000 08849780 100f0000 24000000
+// CHECK-DUPS-NEXT: 10114 0c0f0000 28000000 080f0000 01000000
+// CHECK-DUPS-NEXT: 10124 040f0000 01000000 000f0000 01000000
 // CHECK-DUPS-NEXT: Contents of section .ARM.extab:
 
 // After duplicate entry removal
 // CHECK: Contents of section .ARM.exidx:
-// CHECK-NEXT:  100d4 2c0f0000 01000000 340f0000 08849780
-// CHECK-NEXT:  100e4 380f0000 14000000 340f0000 18000000
-// CHECK-NEXT:  100f4 300f0000 01000000
+// CHECK-NEXT: 100d4 2c0f0000 01000000 340f0000 08849780
+// CHECK-NEXT: 100e4 380f0000 1c000000 340f0000 20000000
+// CHECK-NEXT: 100f4 300f0000 01000000 300f0000 01000000
 // CHECK-NEXT: Contents of section .ARM.extab:
         .syntax unified
 
         // Expect 1 EXIDX_CANTUNWIND entry.
         .section .text.00, "ax", %progbits
         .globl _start
 _start:
         .fnstart

 f8:
         .fnstart
         bx lr
         .personality __gxx_personality_v0
         .handlerdata
         .long 0
         .fnend
 
- // Dummy implementation of personality routines to satisfy reference from
- // exception tables
+// Expect Linker generated EXIDX_CANTUNWIND tables
         .section .text.__gcc_personality_v0, "ax", %progbits
         .global __gxx_personality_v0
 __gxx_personality_v0:
         bx lr
 
         .section .text.__aeabi_unwind_cpp_pr0, "ax", %progbits
         .global __aeabi_unwind_cpp_pr0
 __aeabi_unwind_cpp_pr0:
         bx lr

lld/trunk/test/ELF/arm-exidx-discard.s

 // REQUIRES: arm
 // RUN: llvm-mc -filetype=obj -triple arm-gnu-linux-eabi -mcpu cortex-a7 -arm-add-build-attributes %s -o %t.o
 // RUN: echo "ENTRY(__entrypoint) SECTIONS { . = 0x10000; .text : { *(.text .text.*) } /DISCARD/ : { *(.ARM.exidx*) *(.gnu.linkonce.armexidx.*) } }" > %t.script
 // RUN: ld.lld -T %t.script %t.o -o %t.elf 2>&1
 // RUN: llvm-readobj -sections %t.elf | FileCheck %s
 
 .globl  __entrypoint
 __entrypoint:
+.fnstart
     bx  lr
-
+ .save {r7, lr}
+ .setfp r7, sp, #0
+ .fnend
 // Check that .ARM.exidx/.gnu.linkonce.armexidx
 // are correctly removed if they were added.
 // CHECK-NOT: .ARM.exidx
 // CHECK-NOT: .gnu.linkonce.armexidx.

lld/trunk/test/ELF/arm-exidx-emit-relocs.s

+// REQUIRES: arm
+// RUN: llvm-mc -filetype=obj --arm-add-build-attributes -triple=armv7a-none-linux-gnueabi %s -o %t
+// RUN: ld.lld --emit-relocs %t -o %t2
+// RUN: llvm-objdump -s -triple=armv7a-none-linux-gnueabi %t2 | FileCheck %s
+// RUN: llvm-readelf --relocs %t2 | FileCheck -check-prefix=CHECK-RELOCS %s
+
+// LLD does not support --emit-relocs for .ARM.exidx sections as the relocations
+// from synthetic table entries won't be represented. Given the known use cases
+// of --emit-relocs, relocating kernels, and binary analysis, the former doesn't
+// use exceptions and the latter can derive the relocations from the table if
+// they need them.
+ .syntax unified
+ // Will produce an ARM.exidx entry with inline unwinding instructions
+ .section .text.func1, "ax",%progbits
+ .global func1
+func1:
+ .fnstart
+ bx lr
+ .save {r7, lr}
+ .setfp r7, sp, #0
+ .fnend
+
+ .syntax unified
+ .section .text.func2, "ax",%progbits
+// A function with the same inline unwinding instructions, expect merge.
+ .global func2
+func2:
+ .fnstart
+ bx lr
+ .save {r7, lr}
+ .setfp r7, sp, #0
+ .fnend
+
+ .section .text.25, "ax", %progbits
+ .global func25
+func25:
+        .fnstart
+        bx lr
+        .cantunwind
+        .fnend
+
+ .section .text.26, "ax", %progbits
+ .global func26
+func26:
+        .fnstart
+        bx lr
+        .cantunwind
+        .fnend
+
+ .syntax unified
+ .section .text.func3, "ax",%progbits
+// A function with the same inline unwinding instructions, expect merge.
+ .global func3
+func3:
+ .fnstart
+ bx lr
+ .save {r7, lr}
+ .setfp r7, sp, #0
+ .fnend
+
+ .section .text.__aeabi_unwind_cpp_pr0, "ax", %progbits
+ .global __aeabi_unwind_cpp_pr0
+__aeabi_unwind_cpp_pr0:
+ bx lr
+
+// CHECK: Contents of section .ARM.exidx:
+// CHECK-NEXT:  100d4 2c0f0000 08849780 2c0f0000 01000000
+// CHECK-NEXT:  100e4 2c0f0000 08849780 280f0000 01000000
+// CHECK-NEXT:  100f4 240f0000 01000000
+
+// CHECK-RELOCS-NOT: Relocation section '.rel.ARM.exidx'

lld/trunk/test/ELF/arm-exidx-gc.s

 // REQUIRES: arm
-// RUN: llvm-mc -filetype=obj -triple=armv7a-none-linux-gnueabi %s -o %t
+// RUN: llvm-mc -filetype=obj --arm-add-build-attributes -triple=armv7a-none-linux-gnueabi %s -o %t
 // RUN: ld.lld %t --no-merge-exidx-entries -o %t2 --gc-sections 2>&1
 // RUN: llvm-objdump -d -triple=armv7a-none-linux-gnueabi %t2 | FileCheck %s
 // RUN: llvm-objdump -s -triple=armv7a-none-linux-gnueabi %t2 | FileCheck -check-prefix=CHECK-EXIDX %s
 
 // Test the behavior of .ARM.exidx sections under garbage collection
 // A .ARM.exidx section is live if it has a relocation to a live executable
 // section.
 // A .ARM.exidx section may have a relocation to a .ARM.extab section, if the

 
 // GC should have removed table entries for unusedfunc1, unusedfunc2
 // and __gxx_personality_v1
 // CHECK-NOT: unusedfunc1
 // CHECK-NOT: unusedfunc2
 // CHECK-NOT: __gxx_personality_v1
 
 // CHECK-EXIDX: Contents of section .ARM.exidx:
-// 100d4 + f38 = 1100c = func1
-// 100dc + f34 = 11010 = func2 (100e0 + 1c = 100fc = .ARM.extab)
-// CHECK-EXIDX-NEXT: 100d4 380f0000 08849780 340f0000 1c000000
-// 100e4 + f30 = 11014 = __gxx_personality_v0
-// 100ec + f2c = 11018 = __aeabi_unwind_cpp_pr0
-// CHECK-EXIDX-NEXT: 100e4 300f0000 01000000 2c0f0000 01000000
-// 100f4 + f28 = 1101c = __aeabi_unwind_cpp_pr0 + sizeof(__aeabi_unwind_cpp_pr0)
-// CHECK-EXIDX-NEXT: 100f4 280f0000 01000000
+// 100d4 + f2c = 11000
+// 100dc + f30 = 1100c = func1
+// CHECK-EXIDX-NEXT: 100d4 2c0f0000 01000000 300f0000 08849780
+// 100e4 + f2c = 11010 = func2 (100e8 + 1c = 10104 = .ARM.extab)
+// 100ec + f28 = 11014 = __gxx_personality_v0
+// CHECK-EXIDX-NEXT: 100e4 2c0f0000 1c000000 280f0000 01000000
+// 100f4 + f24 = 11018 = __aeabi_unwind_cpp_pr0
+// 100fc + f20 = 1101c = __aeabi_unwind_cpp_pr0 + sizeof(__aeabi_unwind_cpp_pr0)
+// CHECK-EXIDX-NEXT: 100f4 240f0000 01000000 200f0000 01000000
 // CHECK-EXIDX-NEXT: Contents of section .ARM.extab:
-// 100fc + f18 = 11014 = __gxx_personality_v0
-// CHECK-EXIDX-NEXT: 100fc 180f0000 b0b0b000
+// 10104 + f10 = 11014 = __gxx_personality_v0
+// CHECK-EXIDX-NEXT: 10104 100f0000 b0b0b000

lld/trunk/test/ELF/arm-exidx-shared.s

 // REQUIRES: arm
-// RUN: llvm-mc -filetype=obj -triple=armv7a-none-linux-gnueabi %s -o %t
+// RUN: llvm-mc -filetype=obj -arm-add-build-attributes -triple=armv7a-none-linux-gnueabi %s -o %t
 // RUN: ld.lld --hash-style=sysv %t --shared -o %t2 2>&1
 // RUN: llvm-readobj --relocations %t2 | FileCheck %s
-// RUN: llvm-objdump -s -triple=armv7a-none-linux-gnueabi %t2 | FileCheck -check-prefix=CHECK-EXTAB %s
+// RUN: llvm-objdump -s -triple=armv7a-none-linux-gnueabi %t2 | FileCheck --check-prefix=CHECK-EXTAB-NEXT %s
 
 // Check that the relative R_ARM_PREL31 relocation can access a PLT entry
 // for when the personality routine is referenced from a shared library.
 // Also check that the R_ARM_NONE no-op relocation can be used in a shared
 // library.
  .syntax unified
 // Will produce an ARM.exidx entry with an R_ARM_NONE relocation to
 // __aeabi_unwind_cpp_pr0

 __aeabi_unwind_cpp_pr0:
  bx lr
 
 // CHECK: Relocations [
 // CHECK-NEXT:   Section {{.*}} .rel.plt {
 // CHECK-NEXT:     0x300C R_ARM_JUMP_SLOT __gxx_personality_v0
 
 // CHECK-EXTAB: Contents of section .ARM.extab:
-// 0x0210 + 0x0e20 = 0x1030 = __gxx_personality_v0(PLT)
-// CHECK-EXTAB-NEXT:  0230 000e0000 b0b0b000 00000000
+// 0x0238 + 0xdf8 = 0x1030 = __gxx_personality_v0(PLT)      
+// CHECK-EXTAB-NEXT: 0238 f80d0000 b0b0b000 00000000 

lld/trunk/test/ELF/arm-exidx-synthetic-link.s

+// REQUIRES: arm
+// RUN: llvm-mc -filetype=obj  -arm-add-build-attributes -triple=armv7a-none-linux-gnueabi %s -o %t.o
+// RUN: ld.lld %t.o -o %t.so -shared
+// RUN: llvm-readobj -s %t.so | FileCheck %s
+
+// Test that when all the .ARM.exidx sections are merged into a single
+// synthetic EXIDX_CANTUNWIND entry we can still set the SHF_LINK_ORDER
+// link.
+ .syntax unified
+ .section .text.1, "ax", %progbits
+ .globl f1
+ .type f1, %function
+f1:
+ bx lr
+
+ .section .text.2, "ax", %progbits
+ .globl f2
+ .type f2, %function
+f2:
+ .fnstart
+ bx lr
+ .cantunwind
+ .fnend
+
+// CHECK:      Name: .ARM.exidx
+// CHECK-NEXT: Type: SHT_ARM_EXIDX
+// CHECK-NEXT: Flags [
+// CHECK-NEXT:   SHF_ALLOC
+// CHECK-NEXT:   SHF_LINK_ORDER
+// CHECK-NEXT: ]
+// CHECK-NEXT: Address:
+// CHECK-NEXT: Offset:
+// CHECK-NEXT: Size:
+// CHECK-NEXT: Link: [[INDEX:.*]]
+
+// CHECK:      Index: [[INDEX]]
+// CHECK-NEXT: Name: .text