[AMDGPU] Add support for immediate operand for S_ENDPGM

[dstuttard]

Summary

Add support for immediate operand in S_ENDPGM

Change-Id: I0c56a076a10980f719fb2a8f16407e9c301013f6

[rampitec]

LGTM

lib/Target/AMDGPU/AMDGPUCallLowering.cpp

 
 bool AMDGPUCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
                                      const Value *Val,
                                      ArrayRef<unsigned> VRegs) const {
   // FIXME: Add support for non-void returns.
   if (Val)
     return false;
 
-  MIRBuilder.buildInstr(AMDGPU::S_ENDPGM);
+  MIRBuilder.buildInstr(AMDGPU::S_ENDPGM).addImm(0);
   return true;
 }
 
 unsigned AMDGPUCallLowering::lowerParameterPtr(MachineIRBuilder &MIRBuilder,
                                                Type *ParamTy,
                                                uint64_t Offset) const {
 
   MachineFunction &MF = MIRBuilder.getMF();

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

enum ImmTy {
     ImmTyInterpAttr,
     ImmTyAttrChan,
     ImmTyOpSel,
     ImmTyOpSelHi,
     ImmTyNegLo,
     ImmTyNegHi,
     ImmTySwizzle,
     ImmTyGprIdxMode,
+    ImmTyEndpgm,
     ImmTyHigh
   };
 
   struct TokOp {
     const char *Data;
     unsigned Length;
   };
 
public:
   bool isSwizzle() const;
   bool isSMRDOffset8() const;
   bool isSMRDOffset20() const;
   bool isSMRDLiteralOffset() const;
   bool isDPPCtrl() const;
   bool isGPRIdxMode() const;
   bool isS16Imm() const;
   bool isU16Imm() const;
+  bool isEndpgm() const;
 
   StringRef getExpressionAsToken() const {
     assert(isExpr());
     const MCSymbolRefExpr *S = cast<MCSymbolRefExpr>(Expr);
     return S->getSymbol().getName();
   }
 
   StringRef getToken() const {
static void printImmTy(raw_ostream& OS, ImmTy Type) {
     case ImmTyAttrChan: OS << "AttrChan"; break;
     case ImmTyOpSel: OS << "OpSel"; break;
     case ImmTyOpSelHi: OS << "OpSelHi"; break;
     case ImmTyNegLo: OS << "NegLo"; break;
     case ImmTyNegHi: OS << "NegHi"; break;
     case ImmTySwizzle: OS << "Swizzle"; break;
     case ImmTyGprIdxMode: OS << "GprIdxMode"; break;
     case ImmTyHigh: OS << "High"; break;
+    case ImmTyEndpgm:
+      OS << "Endpgm";
+      break;
     }
   }
 
   void print(raw_ostream &OS) const override {
     switch (Kind) {
     case Register:
       OS << "<register " << getReg() << " mods: " << Reg.Mods << '>';
       break;
OperandMatchResultTy parseSDWASel(OperandVector &Operands, StringRef Prefix,
                                     AMDGPUOperand::ImmTy Type);
   OperandMatchResultTy parseSDWADstUnused(OperandVector &Operands);
   void cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands);
   void cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands);
   void cvtSdwaVOP2b(MCInst &Inst, const OperandVector &Operands);
   void cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands);
   void cvtSDWA(MCInst &Inst, const OperandVector &Operands,
                 uint64_t BasicInstType, bool skipVcc = false);
+
+  OperandMatchResultTy parseEndpgmOp(OperandVector &Operands);
+  AMDGPUOperand::Ptr defaultEndpgmImmOperands() const;
 };
 
 struct OptionalOperand {
   const char *Name;
   AMDGPUOperand::ImmTy Type;
   bool IsBit;
   bool (*ConvertResult)(int64_t&);
 };
AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) {
   Operands.push_back(AMDGPUOperand::CreateImm(this, Int, S, AMDGPUOperand::ImmTyDppCtrl));
   return MatchOperand_Success;
 }
 
 AMDGPUOperand::Ptr AMDGPUAsmParser::defaultRowMask() const {
   return AMDGPUOperand::CreateImm(this, 0xf, SMLoc(), AMDGPUOperand::ImmTyDppRowMask);
 }
 
+AMDGPUOperand::Ptr AMDGPUAsmParser::defaultEndpgmImmOperands() const {
+  return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyEndpgm);
+}
+
 AMDGPUOperand::Ptr AMDGPUAsmParser::defaultBankMask() const {
   return AMDGPUOperand::CreateImm(this, 0xf, SMLoc(), AMDGPUOperand::ImmTyDppBankMask);
 }
 
 AMDGPUOperand::Ptr AMDGPUAsmParser::defaultBoundCtrl() const {
   return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyDppBoundCtrl);
 }
 
unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,
   case MCK_Attr:
     return Operand.isInterpAttr() ? Match_Success : Match_InvalidOperand;
   case MCK_AttrChan:
     return Operand.isAttrChan() ? Match_Success : Match_InvalidOperand;
   default:
     return Match_InvalidOperand;
   }
 }
+
+//===----------------------------------------------------------------------===//
+// endpgm
+//===----------------------------------------------------------------------===//
+
+OperandMatchResultTy AMDGPUAsmParser::parseEndpgmOp(OperandVector &Operands) {
+  SMLoc S = Parser.getTok().getLoc();
+  int64_t Imm = 0;
+
+  if (!parseExpr(Imm)) {
+    // The operand is optional, if not present default to 0
+    Imm = 0;
+  }
+
+  if (!isUInt<16>(Imm)) {
+    Error(S, "expected a 16-bit value");
+    return MatchOperand_ParseFail;
+  }
+
+  Operands.push_back(
+      AMDGPUOperand::CreateImm(this, Imm, S, AMDGPUOperand::ImmTyEndpgm));
+  return MatchOperand_Success;
+}
+
+bool AMDGPUOperand::isEndpgm() const { return isImmTy(ImmTyEndpgm); }

lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h

protected:
   void printSendMsg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                     raw_ostream &O);
   void printSwizzle(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                     raw_ostream &O);
   void printWaitFlag(const MCInst *MI, unsigned OpNo,
                      const MCSubtargetInfo &STI, raw_ostream &O);
   void printHwreg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                   raw_ostream &O);
+  void printEndpgm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
+                   raw_ostream &O);
 };
 
 class R600InstPrinter : public MCInstPrinter {
 public:
   R600InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
                   const MCRegisterInfo &MRI)
     : MCInstPrinter(MAI, MII, MRI) {}
 

lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp

if (ID_SYMBOLIC_FIRST_ <= Id && Id < Last && IdSymbolic[Id]) {
     O << Id;
   }
   if (Width != WIDTH_M1_DEFAULT_ + 1 || Offset != OFFSET_DEFAULT_) {
     O << ", " << Offset << ", " << Width;
   }
   O << ')';
 }
 
+void AMDGPUInstPrinter::printEndpgm(const MCInst *MI, unsigned OpNo,
+                                    const MCSubtargetInfo &STI,
+                                    raw_ostream &O) {
+  uint16_t Imm = MI->getOperand(OpNo).getImm();
+  if (Imm == 0) {
+    return;
+  }
+
+  O << formatDec(Imm);
+}
+
 #include "AMDGPUGenAsmWriter.inc"
 
 void R600InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
                     StringRef Annot, const MCSubtargetInfo &STI) {
   O.flush();
   printInstruction(MI, O);
   printAnnotation(O, Annot);
 }

lib/Target/AMDGPU/SIInsertSkips.cpp

BuildMI(*SkipBB, Insert, DL, TII->get(AMDGPU::EXP_DONE))
     .addReg(AMDGPU::VGPR0, RegState::Undef)
     .addReg(AMDGPU::VGPR0, RegState::Undef)
     .addReg(AMDGPU::VGPR0, RegState::Undef)
     .addImm(1)  // vm
     .addImm(0)  // compr
     .addImm(0); // en
 
   // ... and terminate wavefront.
-  BuildMI(*SkipBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM));
+  BuildMI(*SkipBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM)).addImm(0);
 
   return true;
 }
 
 void SIInsertSkips::kill(MachineInstr &MI) {
   MachineBasicBlock &MBB = *MI.getParent();
   DebugLoc DL = MI.getDebugLoc();
 

lib/Target/AMDGPU/SIInstrInfo.cpp

 void SIInstrInfo::insertReturn(MachineBasicBlock &MBB) const {
   auto MF = MBB.getParent();
   SIMachineFunctionInfo *Info = MF->getInfo<SIMachineFunctionInfo>();
 
   assert(Info->isEntryFunction());
 
   if (MBB.succ_empty()) {
     bool HasNoTerminator = MBB.getFirstTerminator() == MBB.end();
-    if (HasNoTerminator)
-      BuildMI(MBB, MBB.end(), DebugLoc(),
-              get(Info->returnsVoid() ? AMDGPU::S_ENDPGM : AMDGPU::SI_RETURN_TO_EPILOG));
+    if (HasNoTerminator) {
+      if (Info->returnsVoid()) {
+        BuildMI(MBB, MBB.end(), DebugLoc(), get(AMDGPU::S_ENDPGM)).addImm(0);
+      } else {
+        BuildMI(MBB, MBB.end(), DebugLoc(), get(AMDGPU::SI_RETURN_TO_EPILOG));
+      }
+    }
   }
 }
 
 unsigned SIInstrInfo::getNumWaitStates(const MachineInstr &MI) {
   switch (MI.getOpcode()) {
   default: return 1; // FIXME: Do wait states equal cycles?
 
   case AMDGPU::S_NOP:

lib/Target/AMDGPU/SIInstrInfo.td

 def SwizzleMatchClass : AsmOperandClass {
   let Name = "Swizzle";
   let PredicateMethod = "isSwizzle";
   let ParserMethod = "parseSwizzleOp";
   let RenderMethod = "addImmOperands";
   let IsOptional = 1;
 }
 
+def EndpgmMatchClass : AsmOperandClass {
+  let Name = "EndpgmImm";
+  let PredicateMethod = "isEndpgm";
+  let ParserMethod = "parseEndpgmOp";
+  let RenderMethod = "addImmOperands";
+  let IsOptional = 1;
+}
+
 def ExpTgtMatchClass : AsmOperandClass {
   let Name = "ExpTgt";
   let PredicateMethod = "isExpTgt";
   let ParserMethod = "parseExpTgt";
   let RenderMethod = "printExpTgt";
 }
 
 def SendMsgImm : Operand<i32> {
   let PrintMethod = "printSendMsg";
   let ParserMatchClass = SendMsgMatchClass;
 }
 
 def SwizzleImm : Operand<i16> {
   let PrintMethod = "printSwizzle";
   let ParserMatchClass = SwizzleMatchClass;
 }
 
+def EndpgmImm : Operand<i16> {
+  let PrintMethod = "printEndpgm";
+  let ParserMatchClass = EndpgmMatchClass;
+}
+
 def SWaitMatchClass : AsmOperandClass {
   let Name = "SWaitCnt";
   let RenderMethod = "addImmOperands";
   let ParserMethod = "parseSWaitCntOps";
 }
 
 def VReg32OrOffClass : AsmOperandClass {
   let Name = "VReg32OrOff";

lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp

for (MachineBasicBlock &MBB : MF) {
 
     // Try to remove unneeded instructions before s_endpgm.
     if (MBB.succ_empty()) {
       if (MBB.empty())
         continue;
 
       // Skip this if the endpgm has any implicit uses, otherwise we would need
       // to be careful to update / remove them.
+      // S_ENDPGM always has a single imm operand that is not used other than to
+      // end up in the encoding
       MachineInstr &Term = MBB.back();
-      if (Term.getOpcode() != AMDGPU::S_ENDPGM ||
-          Term.getNumOperands() != 0)
+      if (Term.getOpcode() != AMDGPU::S_ENDPGM || Term.getNumOperands() != 1)
         continue;
 
       SmallVector<MachineBasicBlock*, 4> Blocks({&MBB});
 
       while (!Blocks.empty()) {
         auto CurBB = Blocks.pop_back_val();
         auto I = CurBB->rbegin(), E = CurBB->rend();
         if (I != E) {

lib/Target/AMDGPU/SOPInstructions.td

class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern = []> :
   let UseNamedOperandTable = 1;
 }
 
 
 def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "s_nop $simm16">;
 
 let isTerminator = 1 in {
 
-def S_ENDPGM : SOPP <0x00000001, (ins), "s_endpgm",
-  [(AMDGPUendpgm)]> {
-  let simm16 = 0;
+def S_ENDPGM : SOPP <0x00000001, (ins EndpgmImm:$simm16), "s_endpgm $simm16"> {
   let isBarrier = 1;
   let isReturn = 1;
 }
 
 let SubtargetPredicate = isVI in {
 def S_ENDPGM_SAVED : SOPP <0x0000001B, (ins), "s_endpgm_saved"> {
   let simm16 = 0;
   let isBarrier = 1;
def : GCNPat <
   (S_GETREG_B32 (as_i16imm $simm16))
 >;
 
 //===----------------------------------------------------------------------===//
 // SOP1 Patterns
 //===----------------------------------------------------------------------===//
 
 def : GCNPat <
+  (AMDGPUendpgm),
+    (S_ENDPGM (i16 0))
+>;
+
+def : GCNPat <
   (i64 (ctpop i64:$src)),
     (i64 (REG_SEQUENCE SReg_64,
      (i32 (COPY_TO_REGCLASS (S_BCNT1_I32_B64 $src), SReg_32)), sub0,
      (S_MOV_B32 (i32 0)), sub1))
 >;
 
 def : GCNPat <
   (i32 (smax i32:$x, (i32 (ineg i32:$x)))),

test/CodeGen/AMDGPU/GlobalISel/legalize-block-addr.mir

 ---
 name:            test_blockaddress
 alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: test_blockaddress
     ; CHECK: [[BLOCK_ADDR:%[0-9]+]]:_(p0) = G_BLOCK_ADDR blockaddress(@test_blockaddress, %ir-block.block)
-    ; CHECK: S_ENDPGM implicit [[BLOCK_ADDR]](p0)
+    ; CHECK: S_ENDPGM 0, implicit [[BLOCK_ADDR]](p0)
     %0:_(p0) = G_BLOCK_ADDR blockaddress(@test_blockaddress, %ir-block.block)
-    S_ENDPGM implicit %0
+    S_ENDPGM 0, implicit %0
 
 ...

test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir

 
 ---
 name:            test_constant_s1
 body: |
   bb.0:
 
     ; CHECK-LABEL: name: test_constant_s1
     ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
-    ; CHECK: S_ENDPGM implicit [[C]](s1)
+    ; CHECK: S_ENDPGM 0, implicit [[C]](s1)
     %1:_(s1) = G_CONSTANT i1 0
-    S_ENDPGM implicit %1
+    S_ENDPGM 0, implicit %1
 ...
 
 ---
 name:            test_constant_s7
 body: |
   bb.0:
 
     ; CHECK-LABEL: name: test_constant_s7

test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir

 ---
 name:            test_blockaddress
 alignment:       4
 legalized: true
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: test_blockaddress
     ; CHECK: [[BLOCK_ADDR:%[0-9]+]]:sgpr(p0) = G_BLOCK_ADDR blockaddress(@test_blockaddress, %ir-block.block)
-    ; CHECK: S_ENDPGM implicit [[BLOCK_ADDR]](p0)
+    ; CHECK: S_ENDPGM 0, implicit [[BLOCK_ADDR]](p0)
     %0:_(p0) = G_BLOCK_ADDR blockaddress(@test_blockaddress, %ir-block.block)
-    S_ENDPGM implicit %0
+    S_ENDPGM 0, implicit %0
 
 ...

test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
 
 ---
 name: merge_s32_s32_s64_s
 legalized: true
 
 body: |
   bb.0:
     liveins: $sgpr0, $sgpr1
     ; CHECK-LABEL: name: merge_s32_s32_s64_s
     ; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
     ; CHECK: [[EXTRACT:%[0-9]+]]:sgpr(s32) = G_EXTRACT [[COPY]](s64), 0
     ; CHECK: [[EXTRACT1:%[0-9]+]]:sgpr(s32) = G_EXTRACT [[COPY]](s64), 32
     ; CHECK: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[EXTRACT]](s32), [[EXTRACT1]](s32)
-    ; CHECK: S_ENDPGM implicit [[MV]](s64)
+    ; CHECK: S_ENDPGM 0, implicit [[MV]](s64)
     %0:_(s64) = COPY $sgpr0_sgpr1
     %1:_(s32) = G_EXTRACT %0, 0
     %2:_(s32) = G_EXTRACT %0, 32
     %3:_(s64) = G_MERGE_VALUES %1, %2
-    S_ENDPGM implicit %3
+    S_ENDPGM 0, implicit %3
 ...
 
 ---
 name: merge_s32_s32_s64_v
 legalized: true
 
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
     ; CHECK-LABEL: name: merge_s32_s32_s64_v
     ; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
     ; CHECK: [[EXTRACT:%[0-9]+]]:vgpr(s32) = G_EXTRACT [[COPY]](s64), 0
     ; CHECK: [[EXTRACT1:%[0-9]+]]:vgpr(s32) = G_EXTRACT [[COPY]](s64), 32
     ; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[EXTRACT]](s32), [[EXTRACT1]](s32)
-    ; CHECK: S_ENDPGM implicit [[MV]](s64)
+    ; CHECK: S_ENDPGM 0, implicit [[MV]](s64)
     %0:_(s64) = COPY $vgpr0_vgpr1
     %1:_(s32) = G_EXTRACT %0, 0
     %2:_(s32) = G_EXTRACT %0, 32
     %3:_(s64) = G_MERGE_VALUES %1, %2
-    S_ENDPGM implicit %3
+    S_ENDPGM 0, implicit %3
 ...
 

test/CodeGen/AMDGPU/break-smem-soft-clauses.mir

 # RUN: llc -march=amdgcn -mcpu=carrizo -verify-machineinstrs -run-pass  post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,XNACK %s
 # RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass  post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,NOXNACK %s
 
 ---
 # Trivial clause at beginning of program
 name: trivial_smem_clause_load_smrd4_x1
 
 body: |
   bb.0:
     ; GCN-LABEL: name: trivial_smem_clause_load_smrd4_x1
     ; GCN: $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
     $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # Trivial clause at beginning of program
 name: trivial_smem_clause_load_smrd4_x2
 
 body: |
   bb.0:
     ; GCN-LABEL: name: trivial_smem_clause_load_smrd4_x2
     ; GCN: $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
     ; GCN-NEXT: $sgpr1 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
     $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
     $sgpr1 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # Trivial clause at beginning of program
 name: trivial_smem_clause_load_smrd4_x3
 
 body: |
   bb.0:
     ; GCN-LABEL: name: trivial_smem_clause_load_smrd4_x3
     ; GCN: $sgpr0 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0
     ; GCN-NEXT: $sgpr1 = S_LOAD_DWORD_IMM $sgpr6_sgpr7, 0, 0
     ; GCN-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr14_sgpr15, 0, 0
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
     $sgpr0 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0
     $sgpr1 = S_LOAD_DWORD_IMM $sgpr6_sgpr7, 0, 0
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr14_sgpr15, 0, 0
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # Trivial clause at beginning of program
 name: trivial_smem_clause_load_smrd4_x4
 
 body: |
   bb.0:
     ; GCN-LABEL: name: trivial_smem_clause_load_smrd4_x4
     ; GCN: $sgpr0 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0
     ; GCN-NEXT: $sgpr1 = S_LOAD_DWORD_IMM $sgpr8_sgpr9, 0, 0
     ; GCN-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr14_sgpr15, 0, 0
     ; GCN-NEXT: $sgpr3 = S_LOAD_DWORD_IMM $sgpr16_sgpr17, 0, 0
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
     $sgpr0 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0
     $sgpr1 = S_LOAD_DWORD_IMM $sgpr8_sgpr9, 0, 0
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr14_sgpr15, 0, 0
     $sgpr3 = S_LOAD_DWORD_IMM $sgpr16_sgpr17, 0, 0
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # Reuse of same input pointer is OK
 name: trivial_smem_clause_load_smrd4_x2_sameptr
 body: |
   bb.0:
     ; GCN-LABEL: name: trivial_smem_clause_load_smrd4_x2_sameptr
     ; GCN: $sgpr12 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
     ; GCN-NEXT: $sgpr13 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
     $sgpr12 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
     $sgpr13 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # 32-bit load partially clobbers its own ptr reg
 name: smrd_load4_overwrite_ptr_lo
 
 body: |
   bb.0:
     ; GCN-LABEL: name: smrd_load4_overwrite_ptr_lo
     ; GCN: $sgpr10 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
     $sgpr10 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # 32-bit load partially clobbers its own ptr reg
 name: smrd_load4_overwrite_ptr_hi
 
 body: |
   bb.0:
     ; GCN-LABEL: name: smrd_load4_overwrite_ptr_hi
     ; GCN: $sgpr11 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
     $sgpr11 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # 64-bit load clobbers its own ptr reg
 name: smrd_load8_overwrite_ptr
 
 body: |
   bb.0:
     ; GCN-LABEL: name: smrd_load8_overwrite_ptr
     ; GCN: $sgpr10_sgpr11 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
     $sgpr10_sgpr11 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # vmcnt has 4 bits, so maximum 16 outstanding loads. The waitcnt
 # breaks the clause.
 
 name: break_smem_clause_at_max_smem_clause_size_smrd_load4
 
 body: |
bb.0:
     ; GCN-NEXT: $sgpr23 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
     ; GCN-NEXT: $sgpr24 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
     ; GCN-NEXT: $sgpr25 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
     ; GCN-NEXT: $sgpr26 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
     ; GCN-NEXT: $sgpr27 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
     ; GCN-NEXT: $sgpr28 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
     ; GCN-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr30_sgpr31, 0, 0
     ; GCN-NEXT: $sgpr0 = S_MOV_B32 $sgpr0, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $sgpr16, implicit $sgpr17, implicit $sgpr18, implicit $sgpr19, implicit $sgpr20, implicit $sgpr21, implicit $sgpr22, implicit $sgpr23, implicit $sgpr24, implicit $sgpr25, implicit $sgpr26, implicit $sgpr27, implicit $sgpr28
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
     $sgpr13 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
     $sgpr14 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
     $sgpr15 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
     $sgpr16 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
 
     $sgpr17 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
     $sgpr18 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
     $sgpr19 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
     $sgpr20 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
 
     $sgpr21 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
     $sgpr22 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
     $sgpr23 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
     $sgpr24 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
 
     $sgpr25 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
     $sgpr26 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
     $sgpr27 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
     $sgpr28 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
 
     $sgpr0 = S_LOAD_DWORD_IMM $sgpr30_sgpr31, 0, 0
     $sgpr0 = S_MOV_B32 $sgpr0, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $sgpr16, implicit $sgpr17, implicit $sgpr18, implicit $sgpr19, implicit $sgpr20, implicit $sgpr21, implicit $sgpr22, implicit $sgpr23, implicit $sgpr24, implicit $sgpr25, implicit $sgpr26, implicit $sgpr27, implicit $sgpr28
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 
 name: break_smem_clause_simple_load_smrd4_lo_ptr
 
 body: |
   bb.0:
     ; GCN-LABEL: name: break_smem_clause_simple_load_smrd4_lo_ptr
     ; GCN: $sgpr10 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
     ; XNACK-NEXT: S_NOP 0
     ; GCN-NEXT: $sgpr12 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
     $sgpr10 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
     $sgpr12 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 
 name: break_smem_clause_simple_load_smrd4_hi_ptr
 
 body: |
   bb.0:
     ; GCN-LABEL: name: break_smem_clause_simple_load_smrd4_hi_ptr
     ; GCN: $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
     ; GCN-NEXT: $sgpr3 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
     $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
     $sgpr3 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 
 name: break_smem_clause_simple_load_smrd8_ptr
 
 body: |
   bb.0:
     ; GCN-LABEL: name: break_smem_clause_simple_load_smrd8_ptr
     ; GCN: $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0
     ; XNACK-NEXT: S_NOP 0
     ; GCN-NEXT: $sgpr10_sgpr11 = S_LOAD_DWORDX2_IMM $sgpr12_sgpr13, 0, 0
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0
     $sgpr10_sgpr11 = S_LOAD_DWORDX2_IMM $sgpr12_sgpr13, 0, 0
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 
 name: break_smem_clause_simple_load_smrd16_ptr
 
 body: |
   bb.0:
     ; GCN-LABEL: name: break_smem_clause_simple_load_smrd16_ptr
     ; GCN: $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0
     ; GCN-NEXT: $sgpr12_sgpr13_sgpr14_sgpr15 = S_LOAD_DWORDX4_IMM $sgpr6_sgpr7, 0, 0
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0
     $sgpr12_sgpr13_sgpr14_sgpr15 = S_LOAD_DWORDX4_IMM $sgpr6_sgpr7, 0, 0
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 
 name: break_smem_clause_block_boundary_load_smrd8_ptr
 
 body: |
   ; GCN-LABEL: name: break_smem_clause_block_boundary_load_smrd8_ptr
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x80000000)
   ; GCN:   $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0
   ; GCN: bb.1:
   ; XNACK-NEXT:   S_NOP 0
   ; GCN-NEXT:   $sgpr10_sgpr11 = S_LOAD_DWORDX2_IMM $sgpr12_sgpr13, 0, 0
-  ; GCN-NEXT:   S_ENDPGM
+  ; GCN-NEXT:   S_ENDPGM 0
   bb.0:
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0
 
   bb.1:
     $sgpr10_sgpr11 = S_LOAD_DWORDX2_IMM $sgpr12_sgpr13, 0, 0
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # The load clobbers the pointer of the store, so it needs to break.
 
 name: break_smem_clause_store_load_into_ptr_smrd4
 
 body: |
   bb.0:
     ; GCN-LABEL: name: break_smem_clause_store_load_into_ptr_smrd4
     ; GCN: S_STORE_DWORD_IMM $sgpr16, $sgpr10_sgpr11, 0, 0
     ; GCN-NEXT: $sgpr12 = S_LOAD_DWORD_IMM $sgpr14_sgpr15, 0, 0
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
     S_STORE_DWORD_IMM $sgpr16, $sgpr10_sgpr11, 0, 0
     $sgpr12 = S_LOAD_DWORD_IMM $sgpr14_sgpr15, 0, 0
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # The load clobbers the data of the store, so it needs to break.
 # FIXME: Would it be better to s_nop and wait later?
 
 name: break_smem_clause_store_load_into_data_smrd4
 
 body: |
   bb.0:
     ; GCN-LABEL: name: break_smem_clause_store_load_into_data_smrd4
     ; GCN: S_STORE_DWORD_IMM $sgpr8, $sgpr10_sgpr11, 0, 0
     ; GCN-NEXT: $sgpr8 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
     S_STORE_DWORD_IMM $sgpr8, $sgpr10_sgpr11, 0, 0
     $sgpr8 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # Regular VALU instruction breaks clause, no nop needed
 name: valu_inst_breaks_smem_clause
 
 body: |
   bb.0:
     ; GCN-LABEL: name: valu_inst_breaks_smem_clause
     ; GCN: $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
     ; GCN-NEXT: $vgpr8 = V_MOV_B32_e32 0, implicit $exec
     ; GCN-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
     $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
     $vgpr8 = V_MOV_B32_e32 0, implicit $exec
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # Regular SALU instruction breaks clause, no nop needed
 name: salu_inst_breaks_smem_clause
 
 body: |
   bb.0:
     ; GCN-LABEL: name: salu_inst_breaks_smem_clause
     ; GCN: $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
     ; GCN-NEXT: $sgpr8 = S_MOV_B32 0
     ; GCN-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
     $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
     $sgpr8 = S_MOV_B32 0
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 name: ds_inst_breaks_smem_clause
 
 body: |
   bb.0:
     ; GCN-LABEL: name: ds_inst_breaks_smem_clause
     ; GCN: $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
     ; GCN-NEXT: $vgpr8 = DS_READ_B32 $vgpr9, 0, 0, implicit $m0, implicit $exec
     ; GCN-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
     $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
     $vgpr8 = DS_READ_B32 $vgpr9, 0, 0, implicit $m0, implicit $exec
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 
 name: flat_inst_breaks_smem_clause
 
 body: |
   bb.0:
     ; GCN-LABEL: name: flat_inst_breaks_smem_clause
     ; GCN: $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
     ; GCN-NEXT: $vgpr0 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; GCN-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
     $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0
     $vgpr0 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # FIXME: Should this be handled?
 name: implicit_use_breaks_smem_clause
 
 body: |
   bb.0:
     ; GCN-LABEL: name: implicit_use_breaks_smem_clause
     ; GCN: $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0, implicit $sgpr12_sgpr13
     ; XNACK-NEXT: S_NOP 0
     ; GCN-NEXT: $sgpr12_sgpr13 = S_LOAD_DWORDX2_IMM $sgpr6_sgpr7, 0, 0
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0, implicit $sgpr12_sgpr13
     $sgpr12_sgpr13 = S_LOAD_DWORDX2_IMM $sgpr6_sgpr7, 0, 0
-    S_ENDPGM
+    S_ENDPGM 0
 ...

test/CodeGen/AMDGPU/break-vmem-soft-clauses.mir

 # RUN: llc -march=amdgcn -mcpu=carrizo -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,XNACK %s
 # RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,NOXNACK %s
 ---
 # Trivial clause at beginning of program
 name: trivial_clause_load_flat4_x1
 
 body: |
   bb.0:
     ; GCN-LABEL: name: trivial_clause_load_flat4_x1
     ; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
 
     $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # Trivial clause at beginning of program
 name: trivial_clause_load_flat4_x2
 
 body: |
   bb.0:
     ; GCN-LABEL: name: trivial_clause_load_flat4_x2
     ; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; GCN-NEXT: $vgpr1 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
 
     $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr1 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # Trivial clause at beginning of program
 name: trivial_clause_load_flat4_x3
 
 body: |
   bb.0:
     ; GCN-LABEL: name: trivial_clause_load_flat4_x3
     ; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr3_vgpr4, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; GCN-NEXT: $vgpr1 = FLAT_LOAD_DWORD $vgpr5_vgpr6, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; GCN-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr7_vgpr8, 0, 0, 0, implicit $exec, implicit $flat_scr
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
 
     $vgpr0 = FLAT_LOAD_DWORD $vgpr3_vgpr4, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr1 = FLAT_LOAD_DWORD $vgpr5_vgpr6, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr2 = FLAT_LOAD_DWORD $vgpr7_vgpr8, 0, 0, 0, implicit $exec, implicit $flat_scr
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # Trivial clause at beginning of program
 name: trivial_clause_load_flat4_x4
 
 body: |
   bb.0:
     ; GCN-LABEL: name: trivial_clause_load_flat4_x4
     ; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; GCN-NEXT: $vgpr1 = FLAT_LOAD_DWORD $vgpr6_vgpr7, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; GCN-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr8_vgpr9, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; GCN-NEXT: $vgpr3 = FLAT_LOAD_DWORD $vgpr10_vgpr11, 0, 0, 0, implicit $exec, implicit $flat_scr
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
 
     $vgpr0 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr1 = FLAT_LOAD_DWORD $vgpr6_vgpr7, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr2 = FLAT_LOAD_DWORD $vgpr8_vgpr9, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr3 = FLAT_LOAD_DWORD $vgpr10_vgpr11, 0, 0, 0, implicit $exec, implicit $flat_scr
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # Reuse of same input pointer is OK
 
 name: trivial_clause_load_flat4_x2_sameptr
 body: |
   bb.0:
     ; GCN-LABEL: name: trivial_clause_load_flat4_x2_sameptr
     ; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; GCN-NEXT: $vgpr1 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
 
     $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr1 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # 32-bit load partially clobbers its own ptr reg
 name: flat_load4_overwrite_ptr_lo
 
 body: |
   bb.0:
     ; GCN-LABEL: name: flat_load4_overwrite_ptr_lo
     ; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
 
     $vgpr0 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # 32-bit load partially clobbers its own ptr reg
 name: flat_load4_overwrite_ptr_hi
 
 body: |
   bb.0:
     ; GCN-LABEL: name: flat_load4_overwrite_ptr_hi
     ; GCN: $vgpr1 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
 
     $vgpr1 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # 64-bit load clobbers its own ptr reg
 name: flat_load8_overwrite_ptr
 
 body: |
   bb.0:
     ; GCN-LABEL: name: flat_load8_overwrite_ptr
     ; GCN: $vgpr2_vgpr3 = FLAT_LOAD_DWORDX2 $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
 
     $vgpr2_vgpr3 = FLAT_LOAD_DWORDX2 $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # vmcnt has 4 bits, so maximum 16 outstanding loads. The waitcnt
 # breaks the clause.
 
 
 name: break_clause_at_max_clause_size_flat_load4
 
bb.0:
     ; GCN-NEXT: $vgpr13 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; GCN-NEXT: $vgpr14 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; GCN-NEXT: $vgpr15 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; GCN-NEXT: $vgpr16 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; GCN-NEXT: $vgpr17 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; XNACK-NEXT: S_NOP 0
     ; GCN-NEXT: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; GCN-NEXT: $sgpr0 = S_MOV_B32 $sgpr0, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
 
     $vgpr2 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr3 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr4 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr5 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr
 
     $vgpr6 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr7 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr8 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr9 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr
 
     $vgpr10 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr11 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr12 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr13 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr
 
     $vgpr14 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr15 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr16 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr17 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr
 
     $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
     $sgpr0 = S_MOV_B32 $sgpr0, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 
 name: break_clause_simple_load_flat4_lo_ptr
 
 body: |
   bb.0:
     ; GCN-LABEL: name: break_clause_simple_load_flat4_lo_ptr
     ; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; XNACK-NEXT: S_NOP 0
     ; GCN-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
 
     $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 
 name: break_clause_simple_load_flat4_hi_ptr
 
 body: |
   bb.0:
     ; GCN-LABEL: name: break_clause_simple_load_flat4_hi_ptr
     ; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; XNACK-NEXT: S_NOP 0
     ; GCN-NEXT: $vgpr3 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
 
     $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr3 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 
 name: break_clause_simple_load_flat8_ptr
 
 body: |
   bb.0:
     ; GCN-LABEL: name: break_clause_simple_load_flat8_ptr
     ; GCN: $vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; XNACK-NEXT: S_NOP 0
     ; GCN-NEXT: $vgpr2_vgpr3 = FLAT_LOAD_DWORDX2 $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
 
     $vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr2_vgpr3 = FLAT_LOAD_DWORDX2 $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 
 
 name: break_clause_simple_load_flat16_ptr
 
 body: |
   bb.0:
     ; GCN-LABEL: name: break_clause_simple_load_flat16_ptr
     ; GCN: $vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; XNACK-NEXT: S_NOP 0
     ; GCN-NEXT: $vgpr2_vgpr3_vgpr4_vgpr5 = FLAT_LOAD_DWORDX4 $vgpr6_vgpr7, 0, 0, 0, implicit $exec, implicit $flat_scr
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
     $vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr2_vgpr3_vgpr4_vgpr5 = FLAT_LOAD_DWORDX4 $vgpr6_vgpr7, 0, 0, 0, implicit $exec, implicit $flat_scr
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 
 # The clause is broken by the waitcnt inserted at the end of the
 # block, so no nop is needed.
 
 
 name: break_clause_block_boundary_load_flat8_ptr
 
 body: |
   ; GCN-LABEL: name: break_clause_block_boundary_load_flat8_ptr
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x80000000)
   ; GCN:   $vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
   ; GCN: bb.1:
   ; XNACK-NEXT:  S_NOP 0
   ; GCN-NEXT:   $vgpr2_vgpr3 = FLAT_LOAD_DWORDX2 $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
-  ; GCN-NEXT:   S_ENDPGM
+  ; GCN-NEXT:   S_ENDPGM 0
 
   bb.0:
     $vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
 
   bb.1:
     $vgpr2_vgpr3 = FLAT_LOAD_DWORDX2 $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # The load clobbers the pointer of the store, so it needs to break.
 
 name: break_clause_store_load_into_ptr_flat4
 
 body: |
   bb.0:
     ; GCN-LABEL: name: break_clause_store_load_into_ptr_flat4
     ; GCN: FLAT_STORE_DWORD $vgpr2_vgpr3, $vgpr0, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; GCN-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
 
     FLAT_STORE_DWORD $vgpr2_vgpr3, $vgpr0, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # The load clobbers the data of the store, so it needs to break.
 # FIXME: Would it be better to s_nop and wait later?
 
 name: break_clause_store_load_into_data_flat4
 
 body: |
   bb.0:
     ; GCN-LABEL: name: break_clause_store_load_into_data_flat4
     ; GCN: FLAT_STORE_DWORD $vgpr2_vgpr3, $vgpr0, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; GCN-NEXT: $vgpr0 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
 
     FLAT_STORE_DWORD $vgpr2_vgpr3, $vgpr0, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr0 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # Regular VALU instruction breaks clause, no nop needed
 
 name: valu_inst_breaks_clause
 
 body: |
   bb.0:
     ; GCN-LABEL: name: valu_inst_breaks_clause
     ; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; GCN-NEXT: $vgpr8 = V_MOV_B32_e32 0, implicit $exec
     ; XNACK-NEXT: S_NOP 0
     ; GCN-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
 
     $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr8 = V_MOV_B32_e32 0, implicit $exec
     $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # Regular SALU instruction breaks clause, no nop needed
 
 name: salu_inst_breaks_clause
 
 body: |
   bb.0:
     ; GCN-LABEL: name: salu_inst_breaks_clause
     ; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; GCN-NEXT: $sgpr8 = S_MOV_B32 0
     ; XNACK-NEXT: S_NOP 0
     ; GCN-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
 
     $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
     $sgpr8 = S_MOV_B32 0
     $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 
 name: ds_inst_breaks_clause
 
 body: |
   bb.0:
     ; GCN-LABEL: name: ds_inst_breaks_clause
     ; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; GCN-NEXT: $vgpr8 = DS_READ_B32 $vgpr9, 0, 0, implicit $m0, implicit $exec
     ; XNACK-NEXT: S_NOP 0
     ; GCN-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
 
     $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr8 = DS_READ_B32 $vgpr9, 0, 0, implicit $m0, implicit $exec
     $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 
 name: smrd_inst_breaks_clause
 
 body: |
   bb.0:
     ; GCN-LABEL: name: smrd_inst_breaks_clause
     ; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; GCN-NEXT: $sgpr8 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
     ; GCN-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
 
     $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
     $sgpr8 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
     $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # FIXME: Should this be handled?
 name: implicit_use_breaks_clause
 
 body: |
   bb.0:
     ; GCN-LABEL: name: implicit_use_breaks_clause
     ; GCN: $vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr, implicit $vgpr4_vgpr5
     ; XNACK-NEXT: S_NOP 0
     ; GCN-NEXT: $vgpr4_vgpr5 = FLAT_LOAD_DWORDX2 $vgpr6_vgpr7, 0, 0, 0, implicit $exec, implicit $flat_scr
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
 
     $vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr, implicit $vgpr4_vgpr5
     $vgpr4_vgpr5 = FLAT_LOAD_DWORDX2 $vgpr6_vgpr7, 0, 0, 0, implicit $exec, implicit $flat_scr
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 name: trivial_clause_load_mubuf4_x2
 
 body: |
   bb.0:
     ; GCN-LABEL: name: trivial_clause_load_mubuf4_x2
     ; GCN: $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec
     ; GCN-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFEN $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
 
     $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec
     $vgpr3 = BUFFER_LOAD_DWORD_OFFEN $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 name: break_clause_simple_load_mubuf_offen_ptr
 
 body: |
   bb.0:
     ; GCN-LABEL: name: break_clause_simple_load_mubuf_offen_ptr
     ; GCN: $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec
     ; XNACK-NEXT: S_NOP 0
     ; GCN-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFEN $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
 
     $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec
     $vgpr2 = BUFFER_LOAD_DWORD_OFFEN $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # BUFFER instructions overwriting their own inputs is supposedly OK.
 
 name: mubuf_load4_overwrite_ptr
 
 body: |
   bb.0:
     ; GCN-LABEL: name: mubuf_load4_overwrite_ptr
     ; GCN: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec
     ; GCN-NEXT: $vgpr1 = V_MOV_B32_e32 0, implicit $exec
     ; GCN-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr0, implicit $exec
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
     $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec
     $vgpr1 = V_MOV_B32_e32 0, implicit $exec
     $vgpr2 = V_MOV_B32_e32 $vgpr0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # Break a clause from interference between mubuf and flat instructions
 
 name: break_clause_flat_load_mubuf_load
 
 body: |
   bb.0:
     ; GCN-LABEL: name: break_clause_flat_load_mubuf_load
     ; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; XNACK-NEXT: S_NOP 0
     ; GCN-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFEN $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
 
     $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr2 = BUFFER_LOAD_DWORD_OFFEN $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 # Break a clause from interference between mubuf and flat instructions
 
 # GCN-LABEL: name: break_clause_mubuf_load_flat_load
 # GCN: bb.0:
 # GCN-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4
 # XNACK-NEXT: S_NOP 0
 # GCN-NEXT: $vgpr1 = FLAT_LOAD_DWORD $vgpr2_vgpr3
-# GCN-NEXT: S_ENDPGM
+# GCN-NEXT: S_ENDPGM 0
 name: break_clause_mubuf_load_flat_load
 
 body: |
   bb.0:
     $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec
     $vgpr1 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
 
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 
 name: break_clause_atomic_rtn_into_ptr_flat4
 
 body: |
   bb.0:
     ; GCN-LABEL: name: break_clause_atomic_rtn_into_ptr_flat4
     ; GCN: $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; XNACK-NEXT: S_NOP 0
     ; GCN-NEXT: $vgpr4 = FLAT_ATOMIC_ADD_RTN $vgpr5_vgpr6, $vgpr7, 0, 0, implicit $exec, implicit $flat_scr
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
 
     $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr4 = FLAT_ATOMIC_ADD_RTN $vgpr5_vgpr6, $vgpr7, 0, 0, implicit $exec, implicit $flat_scr
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 name: break_clause_atomic_nortn_ptr_load_flat4
 
 body: |
   bb.0:
     ; GCN-LABEL: name: break_clause_atomic_nortn_ptr_load_flat4
     ; GCN: FLAT_ATOMIC_ADD $vgpr0_vgpr1, $vgpr2, 0, 0, implicit $exec, implicit $flat_scr
     ; GCN-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr3_vgpr4, 0, 0, 0, implicit $exec, implicit $flat_scr
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
 
     FLAT_ATOMIC_ADD $vgpr0_vgpr1, $vgpr2, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr2 = FLAT_LOAD_DWORD $vgpr3_vgpr4, 0, 0, 0, implicit $exec, implicit $flat_scr
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 
 name: break_clause_atomic_rtn_into_ptr_mubuf4
 
 body: |
   bb.0:
     ; GCN-LABEL: name: break_clause_atomic_rtn_into_ptr_mubuf4
     ; GCN: $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec
     ; XNACK-NEXT: S_NOP 0
     ; GCN-NEXT: $vgpr2 = BUFFER_ATOMIC_ADD_OFFEN_RTN $vgpr2, $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, implicit $exec
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
 
     $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec
     $vgpr2 = BUFFER_ATOMIC_ADD_OFFEN_RTN $vgpr2, $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 
 name: break_clause_atomic_nortn_ptr_load_mubuf4
 
 body: |
   bb.0:
     ; GCN-LABEL: name: break_clause_atomic_nortn_ptr_load_mubuf4
     ; GCN: BUFFER_ATOMIC_ADD_OFFEN $vgpr0, $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, implicit $exec
     ; GCN-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
 
     BUFFER_ATOMIC_ADD_OFFEN $vgpr0, $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, implicit $exec
     $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # Make sure there is no assert on mubuf instructions which do not have
 # vaddr, and don't add register to track.
 name: no_break_clause_mubuf_load_novaddr
 
 body: |
   bb.0:
     ; GCN-LABEL: name: no_break_clause_mubuf_load_novaddr
     ; GCN: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec
     ; GCN-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec
-    ; GCN-NEXT: S_ENDPGM
+    ; GCN-NEXT: S_ENDPGM 0
     $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec
     $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # Loads and stores using different addresses theoretically does not
 # need a nop
 name: mix_load_store_clause
 body: |
   bb.0:
     ; GCN-LABEL: name: mix_load_store_clause
     ; GCN: FLAT_STORE_DWORD $vgpr0_vgpr1, $vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; GCN-NEXT: $vgpr10 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; XNACK-NEXT: S_NOP 0
     ; GCN-NEXT: FLAT_STORE_DWORD $vgpr2_vgpr3, $vgpr6, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; GCN-NEXT: $vgpr11 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
 
     FLAT_STORE_DWORD $vgpr0_vgpr1, $vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr10 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
     FLAT_STORE_DWORD $vgpr2_vgpr3, $vgpr6, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr11 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # Loads and stores using the same address needs a nop.
 
 name: mix_load_store_clause_same_address
 body: |
   bb.0:
     ; GCN-LABEL: name: mix_load_store_clause_same_address
     ; GCN: FLAT_STORE_DWORD $vgpr0_vgpr1, $vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; GCN-NEXT: $vgpr10 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; XNACK-NEXT: S_NOP 0
     ; GCN-NEXT: FLAT_STORE_DWORD $vgpr0_vgpr1, $vgpr6, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; GCN-NEXT: $vgpr11 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
 
     FLAT_STORE_DWORD $vgpr0_vgpr1, $vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr10 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr
     FLAT_STORE_DWORD $vgpr0_vgpr1, $vgpr6, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr11 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
-    S_ENDPGM
+    S_ENDPGM 0
 ...

test/CodeGen/AMDGPU/clamp-omod-special-case.mir

bb.0:
     %14 = S_MOV_B32 2
     %26 = V_LSHL_B64 killed %25, 2, implicit $exec
     %16 = REG_SEQUENCE killed %4, 17, %12, 18
     %18 = COPY %26
     %17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, implicit $exec
     %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec
     %21 = V_MAX_F32_e64 0, killed %20, 0, killed %20, 0, 0, implicit $exec
     BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 # GCN-LABEL: name: v_clamp_omod_already_set_f32
 # GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec
 # GCN: %21:vgpr_32 = V_MAX_F32_e64 0, killed %20, 0, killed %20, 1, 3, implicit $exec
 name:            v_clamp_omod_already_set_f32
 tracksRegLiveness: true
bb.0:
     %14 = S_MOV_B32 2
     %26 = V_LSHL_B64 killed %25, 2, implicit $exec
     %16 = REG_SEQUENCE killed %4, 17, %12, 18
     %18 = COPY %26
     %17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, implicit $exec
     %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec
     %21 = V_MAX_F32_e64 0, killed %20, 0, killed %20, 1, 3, implicit $exec
     BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # Don't fold a mul that looks like an omod if itself has omod set
 
 # GCN-LABEL: name: v_omod_mul_omod_already_set_f32
 # GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec
 # GCN-NEXT: %21:vgpr_32 = V_MUL_F32_e64 0, killed %20, 0, 1056964608, 0, 3, implicit $exec
 name:            v_omod_mul_omod_already_set_f32
bb.0:
     %14 = S_MOV_B32 2
     %26 = V_LSHL_B64 killed %25, 2, implicit $exec
     %16 = REG_SEQUENCE killed %4, 17, %12, 18
     %18 = COPY %26
     %17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, implicit $exec
     %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec
     %21 = V_MUL_F32_e64 0, killed %20, 0, 1056964608, 0, 3, implicit $exec
     BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 # Don't fold a mul that looks like an omod if itself has clamp set
 # This might be OK, but would require folding the clamp at the same time.
 # GCN-LABEL: name: v_omod_mul_clamp_already_set_f32
 # GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec
 # GCN-NEXT: %21:vgpr_32 = V_MUL_F32_e64 0, killed %20, 0, 1056964608, 1, 0, implicit $exec
bb.0:
     %14 = S_MOV_B32 2
     %26 = V_LSHL_B64 killed %25, 2, implicit $exec
     %16 = REG_SEQUENCE killed %4, 17, %12, 18
     %18 = COPY %26
     %17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, implicit $exec
     %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec
     %21 = V_MUL_F32_e64 0, killed %20, 0, 1056964608, 1, 0, implicit $exec
     BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 
 
 
 
 
 
bb.0:
     %14 = S_MOV_B32 2
     %26 = V_LSHL_B64 killed %25, 2, implicit $exec
     %16 = REG_SEQUENCE killed %4, 17, %12, 18
     %18 = COPY %26
     %17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, implicit $exec
     %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec
     %21 = V_ADD_F32_e64 0, killed %20, 0, killed %20, 0, 3, implicit $exec
     BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 # Don't fold a mul that looks like an omod if itself has clamp set
 # This might be OK, but would require folding the clamp at the same time.
 # GCN-LABEL: name: v_omod_add_clamp_already_set_f32
 # GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec
 # GCN-NEXT: %21:vgpr_32 = V_ADD_F32_e64 0, killed %20, 0, killed %20, 1, 0, implicit $exec
bb.0:
     %14 = S_MOV_B32 2
     %26 = V_LSHL_B64 killed %25, 2, implicit $exec
     %16 = REG_SEQUENCE killed %4, 17, %12, 18
     %18 = COPY %26
     %17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, implicit $exec
     %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec
     %21 = V_ADD_F32_e64 0, killed %20, 0, killed %20, 1, 0, implicit $exec
     BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # Pass used to crash with immediate second operand of max
 name:            v_max_reg_imm_f32
 tracksRegLiveness: true
 registers:

test/CodeGen/AMDGPU/cluster-flat-loads-postra.mir

bb.0:
     $vgpr4 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
     $vgpr2 = IMPLICIT_DEF
     $vgpr3 = IMPLICIT_DEF
     $vgpr6 = IMPLICIT_DEF
     $vgpr0 = V_ADD_I32_e32 16, $vgpr2, implicit-def $vcc, implicit $exec
     $vgpr1 = V_ADDC_U32_e32 $vgpr3, killed $vgpr6, implicit-def dead $vcc, implicit $vcc, implicit $exec
     FLAT_STORE_DWORD $vgpr2_vgpr3, killed $vgpr0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)
     FLAT_STORE_DWORD $vgpr0_vgpr1, killed $vgpr4, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...

test/CodeGen/AMDGPU/coalescer-extend-pruned-subrange.mir

body: |
 
   bb.1:
     %11:vgpr_32 = V_OR_B32_e32 %12.sub0, %12.sub1, implicit $exec
     %13:vgpr_32 = V_OR_B32_e32 %11, %12.sub2, implicit $exec
     %14:vgpr_32 = V_AND_B32_e32 1, %13, implicit $exec
     %15:sreg_64_xexec = V_CMP_EQ_U32_e64 0, %14, implicit $exec
     %16:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %15, implicit $exec
     BUFFER_STORE_DWORD_OFFEN_exact %16, undef %17:vgpr_32, undef %18:sreg_128, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into constant-pool, align 1, addrspace 4)
-    S_ENDPGM
+    S_ENDPGM 0
 
   bb.2:
     successors: %bb.3, %bb.4
     %19:sreg_64 = V_CMP_EQ_U32_e64 1, %7, implicit $exec
     %20:sreg_64 = COPY $exec, implicit-def $exec
     %21:sreg_64 = S_AND_B64 %20, %19, implicit-def dead $scc
     $exec = S_MOV_B64_term %21
     SI_MASK_BRANCH %bb.4, implicit $exec

test/CodeGen/AMDGPU/coalescer-subranges-another-copymi-not-live.mir

bb.15:
     %27.sub4:sreg_256 = COPY %26
     %27.sub5:sreg_256 = COPY %26
     %27.sub6:sreg_256 = COPY %26
     %27.sub7:sreg_256 = COPY killed %26
     %28:vgpr_32 = IMAGE_LOAD_V1_V4 killed %25, killed %27, 2, -1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, addrspace 4)
     %29:vgpr_32 = V_ADD_F32_e32 0, killed %28, implicit $exec
     $m0 = S_MOV_B32 -1
     DS_WRITE_B32 undef %30:vgpr_32, killed %29, 0, 0, implicit $m0, implicit $exec :: (store 4 into `i32 addrspace(3)* undef`, addrspace 3)
-    S_ENDPGM
+    S_ENDPGM 0
 ...

test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir

bb.17:
     %109.sub7:sreg_256 = COPY killed %108
     %110:vgpr_32 = IMAGE_SAMPLE_V1_V2 killed %107, killed %109, undef %111:sreg_128, 8, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, addrspace 4)
     %112:vgpr_32 = V_MUL_F32_e32 0, killed %110, implicit $exec
     %113:vgpr_32 = V_MUL_F32_e32 0, killed %112, implicit $exec
     %114:vgpr_32 = V_MAD_F32 0, killed %113, 0, 0, 0, 0, 0, 0, implicit $exec
     %115:vgpr_32 = V_MAX_F32_e32 0, killed %114, implicit $exec
     %116:vgpr_32 = V_CVT_PKRTZ_F16_F32_e64 0, killed %115, 0, 1065353216, 0, 0, implicit $exec
     EXP 0, undef %117:vgpr_32, killed %116, undef %118:vgpr_32, undef %119:vgpr_32, -1, -1, 15, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 ...

test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir

bb.16:
     %50:vgpr_32 = V_MUL_F32_e32 undef %51:vgpr_32, undef %52:vgpr_32, implicit $exec
     undef %53.sub1:vreg_128 = COPY %50
     %38:vreg_128 = COPY killed %53
 
   bb.17:
     %54:vreg_128 = COPY killed %38
     %55:vgpr_32 = V_FMA_F32 0, killed %54.sub1, 0, target-flags(amdgpu-gotprel32-lo) 1056964608, 0, 1056964608, 0, 0, implicit $exec
     EXP 1, undef %56:vgpr_32, killed %55, undef %57:vgpr_32, undef %58:vgpr_32, -1, 0, 15, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
   bb.18:
     successors: %bb.7(0x80000000)
     dead %59:vgpr_32 = V_FMA_F32 0, killed %9.sub2, 0, undef %60:vgpr_32, 0, undef %61:vgpr_32, 0, 0, implicit $exec
     dead %62:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN undef %63:vgpr_32, undef %64:sreg_128, undef %65:sreg_32, 0, 0, 0, 0, implicit $exec
     undef %66.sub1:vreg_128 = COPY %13.sub1
     %66.sub2:vreg_128 = COPY %13.sub2
     %67:sreg_64 = V_CMP_NGT_F32_e64 0, 0, 0, undef %68:vgpr_32, 0, implicit $exec

test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir

body: |
 
   bb.19:
     successors: %bb.20(0x80000000)
 
   bb.20:
     successors: %bb.21(0x80000000)
 
   bb.21:
-    S_ENDPGM
+    S_ENDPGM 0
 ...

test/CodeGen/AMDGPU/coalescing-with-subregs-in-loop-bug.mir

bb.1:
     S_BRANCH %bb.2
 
   bb.2:
     $exec = S_OR_B64 $exec, killed %1, implicit-def $scc
     %33:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
     undef %32.sub0:vreg_128 = COPY killed %31.sub0
     %32.sub2:vreg_128 = COPY %33
     $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %32:vreg_128
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...

test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir

bb.0:
     %4 = S_MOV_B32 61440
     %5 = S_MOV_B32 -1
     %6 = REG_SEQUENCE killed %2, 1, killed %3, 2, killed %4, 3, killed %5, 4
     %7 = S_MOV_B32 1234567
     %8 = S_MOV_B32 9999
     %9 = S_AND_B32 killed %7, killed %8, implicit-def dead $scc
     %10 = COPY %9
     BUFFER_STORE_DWORD_OFFSET killed %10, killed %6, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: v_fold_and_imm_regimm_32{{$}}
 
 # GCN: %9:vgpr_32 = V_MOV_B32_e32 646, implicit $exec
 # GCN: FLAT_STORE_DWORD %19, %9,
bb.0:
     FLAT_STORE_DWORD %37, %29, 0, 0, 0, implicit $exec, implicit $flat_scr
 
     %30 = V_AND_B32_e64 %26, %26, implicit $exec
     FLAT_STORE_DWORD %37, %30, 0, 0, 0, implicit $exec, implicit $flat_scr
 
     %31 = V_AND_B32_e64 %34, %34, implicit $exec
     FLAT_STORE_DWORD %37, %31, 0, 0, 0, implicit $exec, implicit $flat_scr
 
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: s_fold_shl_imm_regimm_32{{$}}
 # GC1: %13 = V_MOV_B32_e32 4096, implicit $exec
 # GCN: BUFFER_STORE_DWORD_OFFSET killed %13,
 
bb.0:
     %6 = COPY %4.sub1
     %7 = COPY %4.sub0
     %8 = S_MOV_B32 61440
     %9 = S_MOV_B32 -1
     %10 = REG_SEQUENCE killed %7, 1, killed %6, 2, killed %9, 3, killed %8, 4
     %12 = S_LSHL_B32 killed %5, 12, implicit-def dead $scc
     %13 = COPY %12
     BUFFER_STORE_DWORD_OFFSET killed %13, killed %10, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 # GCN-LABEL: name: v_fold_shl_imm_regimm_32{{$}}
 
 # GCN: %11:vgpr_32 = V_MOV_B32_e32 40955904, implicit $exec
 # GCN: FLAT_STORE_DWORD %20, %11,
 
bb.0:
     FLAT_STORE_DWORD %20, %25, 0, 0, 0, implicit $exec, implicit $flat_scr
 
     %26 = V_LSHLREV_B32_e32 11, %24, implicit $exec
     FLAT_STORE_DWORD %20, %26, 0, 0, 0, implicit $exec, implicit $flat_scr
 
     %28 = V_LSHL_B32_e32 %27, %6, implicit $exec
     FLAT_STORE_DWORD %20, %28, 0, 0, 0, implicit $exec, implicit $flat_scr
 
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: s_fold_ashr_imm_regimm_32{{$}}
 # GCN: %11:vgpr_32 = V_MOV_B32_e32 243, implicit $exec
 # GCN: BUFFER_STORE_DWORD_OFFSET killed %11, killed %8,
 name:            s_fold_ashr_imm_regimm_32
bb.0:
     %6 = COPY %4.sub1
     %7 = COPY %4.sub0
     %8 = S_MOV_B32 61440
     %9 = S_MOV_B32 -1
     %10 = REG_SEQUENCE killed %7, 1, killed %6, 2, killed %9, 3, killed %8, 4
     %12 = S_ASHR_I32 killed %5, 12, implicit-def dead $scc
     %13 = COPY %12
     BUFFER_STORE_DWORD_OFFSET killed %13, killed %10, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 
 # GCN-LABEL: name: v_fold_ashr_imm_regimm_32{{$}}
 # GCN: %11:vgpr_32 = V_MOV_B32_e32 3903258, implicit $exec
 # GCN: FLAT_STORE_DWORD %20, %11,
 
 # GCN: %12:vgpr_32 = V_MOV_B32_e32 62452139, implicit $exec
bb.0:
     FLAT_STORE_DWORD %20, %25, 0, 0, 0, implicit $exec, implicit $flat_scr
 
     %26 = V_ASHRREV_I32_e32 11, %10, implicit $exec
     FLAT_STORE_DWORD %20, %26, 0, 0, 0, implicit $exec, implicit $flat_scr
 
     %28 = V_ASHR_I32_e32 %27, %35, implicit $exec
     FLAT_STORE_DWORD %20, %28, 0, 0, 0, implicit $exec, implicit $flat_scr
 
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: s_fold_lshr_imm_regimm_32{{$}}
 # GCN: %11:vgpr_32 = V_MOV_B32_e32 1048332, implicit $exec
 # GCN: BUFFER_STORE_DWORD_OFFSET killed %11, killed %8,
 name:            s_fold_lshr_imm_regimm_32
bb.0:
     %6 = COPY %4.sub1
     %7 = COPY %4.sub0
     %8 = S_MOV_B32 61440
     %9 = S_MOV_B32 -1
     %10 = REG_SEQUENCE killed %7, 1, killed %6, 2, killed %9, 3, killed %8, 4
     %12 = S_LSHR_B32 killed %5, 12, implicit-def dead $scc
     %13 = COPY %12
     BUFFER_STORE_DWORD_OFFSET killed %13, killed %10, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: v_fold_lshr_imm_regimm_32{{$}}
 # GCN: %11:vgpr_32 = V_MOV_B32_e32 3903258, implicit $exec
 # GCN: FLAT_STORE_DWORD %20, %11,
 
bb.0:
     FLAT_STORE_DWORD %20, %25, 0, 0, 0, implicit $exec, implicit $flat_scr
 
     %26 = V_LSHRREV_B32_e32 11, %10, implicit $exec
     FLAT_STORE_DWORD %20, %26, 0, 0, 0, implicit $exec, implicit $flat_scr
 
     %28 = V_LSHR_B32_e32 %27, %35, implicit $exec
     FLAT_STORE_DWORD %20, %28, 0, 0, 0, implicit $exec, implicit $flat_scr
 
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 # There is only an undef use operand for %1, so there is no
 # corresponding defining instruction
 
 # GCN-LABEL: name: undefined_vreg_operand{{$}}
 # GCN: bb.0
 # GCN-NEXT: FLAT_STORE_DWORD undef %3:vreg_64, undef %1:vgpr_32,
-# GCN-NEXT: S_ENDPGM
+# GCN-NEXT: S_ENDPGM 0
 name: undefined_vreg_operand
 tracksRegLiveness: true
 registers:
   - { id: 0, class: vgpr_32, preferred-register: '' }
   - { id: 1, class: vgpr_32, preferred-register: '' }
   - { id: 2, class: vgpr_32, preferred-register: '' }
   - { id: 3, class: vreg_64, preferred-register: '' }
 body:             |
   bb.0:
     %0 = V_MOV_B32_e32 0, implicit $exec
     %2 = V_XOR_B32_e64 killed %0, undef %1, implicit $exec
     FLAT_STORE_DWORD undef %3, %2, 0, 0, 0, implicit $exec, implicit $flat_scr
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 # Make sure there is no crash if one of the operands is a physical register
 # GCN-LABEL: name: constant_fold_physreg_op{{$}}
 # GCN: %3:sreg_64 = S_AND_B64 $exec, 0, implicit-def dead $scc
 
 name: constant_fold_physreg_op
body:             |
   bb.1:
     %6:sreg_64 = S_MOV_B64 0
     %7:sreg_64 = S_AND_B64 $exec, killed %6, implicit-def dead $scc
     $vcc = COPY %7
 
   bb.3:
     liveins: $vcc
     SI_END_CF %0, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
-    S_ENDPGM implicit $vcc
+    S_ENDPGM 0, implicit $vcc
 
 ...
 ---
 # GCN-LABEL: name: constant_fold_lshl_or_reg0_immreg_reg{{$}}
 # GCN: %2:vgpr_32 = COPY $vgpr0, implicit $exec
-# GCN-NEXT: S_ENDPGM implicit %2
+# GCN-NEXT: S_ENDPGM 0, implicit %2
 
 name: constant_fold_lshl_or_reg0_immreg_reg
 alignment:       0
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 
 body:             |
   bb.0:
     liveins: $vgpr0
 
   %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
   %1:vgpr_32 = V_MOV_B32_e32 16, implicit $exec
   %2:vgpr_32 = V_LSHL_OR_B32 %0,%1, $vgpr0, implicit $exec
-  S_ENDPGM implicit %2
+  S_ENDPGM 0, implicit %2
 
 ...
 
 ---
 
 # GCN-LABEL: name: constant_fold_lshl_or_reg0_immreg_imm{{$}}
 # GCN: %2:vgpr_32 = V_MOV_B32_e32 10, implicit $exec
-# GCN-NEXT: S_ENDPGM implicit %2
+# GCN-NEXT: S_ENDPGM 0, implicit %2
 
 name: constant_fold_lshl_or_reg0_immreg_imm
 alignment:       0
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 
 body:             |
   bb.0:
 
   %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
   %1:vgpr_32 = V_MOV_B32_e32 16, implicit $exec
   %2:vgpr_32 = V_LSHL_OR_B32 %0, %1, 10, implicit $exec
-  S_ENDPGM implicit %2
+  S_ENDPGM 0, implicit %2
 
 ...
 
 ---
 
 # GCN-LABEL: name: constant_fold_lshl_or_reg0_immreg_immreg{{$}}
 # GCN: %3:vgpr_32 = V_MOV_B32_e32 12345, implicit $exec, implicit $exec
-# GCN-NEXT: S_ENDPGM implicit %3
+# GCN-NEXT: S_ENDPGM 0, implicit %3
 
 name: constant_fold_lshl_or_reg0_immreg_immreg
 alignment:       0
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 
 body:             |
   bb.0:
 
   %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
   %1:vgpr_32 = V_MOV_B32_e32 16, implicit $exec
   %2:vgpr_32 = V_MOV_B32_e32 12345, implicit $exec
   %3:vgpr_32 = V_LSHL_OR_B32 %0, %1, %2, implicit $exec
-  S_ENDPGM implicit %3
+  S_ENDPGM 0, implicit %3
 
 ...

test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir

body:             |
   bb.5.._crit_edge3411:
     %39:vgpr_32 = V_MUL_F32_e32 target-flags(amdgpu-gotprel) 0, killed %55.sub0, implicit $exec
     %41:vgpr_32 = V_MIN_F32_e32 1106771968, killed %39, implicit $exec
     %42:vgpr_32 = nnan arcp contract reassoc V_MAD_F32 0, killed %41, 0, 0, 0, 0, 0, 0, implicit $exec
     %43:vgpr_32 = nnan arcp contract reassoc V_MAD_F32 0, killed %42, 0, 0, 0, 0, 0, 0, implicit $exec
     %44:vgpr_32 = V_MAD_F32 0, killed %43, 0, 0, 0, 0, 0, 0, implicit $exec
     %45:vgpr_32 = V_CVT_PKRTZ_F16_F32_e64 0, killed %44, 0, undef %46:vgpr_32, 0, 0, implicit $exec
     EXP_DONE 0, killed %45, undef %47:vgpr_32, undef %48:vgpr_32, undef %49:vgpr_32, -1, -1, 15, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
   bb.6.DummyReturnBlock:
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...

test/CodeGen/AMDGPU/endpgm-dce.mir

 # RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-optimize-exec-masking-pre-ra %s -o - | FileCheck -check-prefix=GCN %s
 
 # GCN-LABEL: name: kill_all
 # GCN:      bb.0:
-# GCN-NEXT: S_ENDPGM
+# GCN-NEXT: S_ENDPGM 0
 name: kill_all
 tracksRegLiveness: true
 registers:
   - { id: 0, class: vreg_64 }
   - { id: 1, class: vgpr_32 }
   - { id: 2, class: vgpr_32 }
   - { id: 3, class: sgpr_32 }
   - { id: 4, class: sgpr_32 }
 body:             |
   bb.0:
     $vcc = IMPLICIT_DEF
     %0 = IMPLICIT_DEF
     %3 = IMPLICIT_DEF
     $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
     %1 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
     %2 = V_ADD_F32_e64 0, killed %1, 0, 1, 0, 0, implicit $exec
     %4 = S_ADD_U32 %3, 1, implicit-def $scc
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: load_without_memoperand
 # GCN:      $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
 # GCN-NEXT: dead %1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit $exec, implicit $flat_scr
-# GCN-NEXT: S_ENDPGM
+# GCN-NEXT: S_ENDPGM 0
 name: load_without_memoperand
 tracksRegLiveness: true
 registers:
   - { id: 0, class: vreg_64 }
   - { id: 1, class: vgpr_32 }
   - { id: 2, class: vgpr_32 }
   - { id: 3, class: sgpr_32 }
   - { id: 4, class: sgpr_32 }
 body:             |
   bb.0:
     $vcc = IMPLICIT_DEF
     %0 = IMPLICIT_DEF
     %3 = IMPLICIT_DEF
     $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
     %1 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit $exec, implicit $flat_scr
     %2 = V_ADD_F32_e64 0, killed %1, 0, 1, 0, 0, implicit $exec
     %4 = S_ADD_U32 %3, 1, implicit-def $scc
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: load_volatile
 # GCN:      $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
 # GCN-NEXT: dead %1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load 4)
-# GCN-NEXT: S_ENDPGM
+# GCN-NEXT: S_ENDPGM 0
 name: load_volatile
 tracksRegLiveness: true
 registers:
   - { id: 0, class: vreg_64 }
   - { id: 1, class: vgpr_32 }
   - { id: 2, class: vgpr_32 }
   - { id: 3, class: sgpr_32 }
   - { id: 4, class: sgpr_32 }
 body:             |
   bb.0:
     $vcc = IMPLICIT_DEF
     %0 = IMPLICIT_DEF
     %3 = IMPLICIT_DEF
     $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
     %1 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load 4)
     %2 = V_ADD_F32_e64 0, killed %1, 0, 1, 0, 0, implicit $exec
     %4 = S_ADD_U32 %3, 1, implicit-def $scc
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: store
 # GCN:      $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
 # GCN-NEXT: FLAT_STORE_DWORD %0, %1, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)
-# GCN-NEXT: S_ENDPGM
+# GCN-NEXT: S_ENDPGM 0
 name: store
 tracksRegLiveness: true
 registers:
   - { id: 0, class: vreg_64 }
   - { id: 1, class: vgpr_32 }
 body:             |
   bb.0:
     $vcc = IMPLICIT_DEF
     %0 = IMPLICIT_DEF
     %1 = IMPLICIT_DEF
     $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
     FLAT_STORE_DWORD %0, %1, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: barrier
 # GCN:      $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
 # GCN-NEXT: S_BARRIER
-# GCN-NEXT: S_ENDPGM
+# GCN-NEXT: S_ENDPGM 0
 name: barrier
 tracksRegLiveness: true
 body:             |
   bb.0:
     $vcc = IMPLICIT_DEF
     $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
     S_BARRIER
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: call
 # GCN:      $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
 # GCN-NEXT: $sgpr4_sgpr5 = S_SWAPPC_B64 $sgpr2_sgpr3
-# GCN-NEXT: S_ENDPGM
+# GCN-NEXT: S_ENDPGM 0
 name: call
 tracksRegLiveness: true
 body:             |
   bb.0:
     $vcc = IMPLICIT_DEF
     $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
     $sgpr4_sgpr5 = S_SWAPPC_B64 $sgpr2_sgpr3
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: exp
 # GCN:      $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
 # GCN-NEXT: EXP 32, undef %0:vgpr_32, undef %1:vgpr_32, %2, undef %3:vgpr_32, 0, 0, 15, implicit $exec
-# GCN-NEXT: S_ENDPGM
+# GCN-NEXT: S_ENDPGM 0
 name: exp
 tracksRegLiveness: true
 registers:
   - { id: 0, class: vgpr_32 }
   - { id: 1, class: vgpr_32 }
   - { id: 2, class: vgpr_32 }
   - { id: 3, class: vgpr_32 }
 body:             |
   bb.0:
     $vcc = IMPLICIT_DEF
     %2 = IMPLICIT_DEF
     $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
     EXP 32, undef %0, undef %1, killed %2, undef %3, 0, 0, 15, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: return_to_epilog
 # GCN:      $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
 # GCN-NEXT: SI_RETURN_TO_EPILOG killed $vgpr0
 name: return_to_epilog
 tracksRegLiveness: true
 body:             |
   bb.0:
     $vcc = IMPLICIT_DEF
     $vgpr0 = IMPLICIT_DEF
     $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
     SI_RETURN_TO_EPILOG killed $vgpr0
 ...
 ---
 # GCN-LABEL: name: split_block
 # GCN:      bb.0:
 # GCN-NEXT:   successors: %bb.1
 # GCN-NOT:  S_OR_B64
 # GCN:      bb.1:
-# GCN-NEXT:   S_ENDPGM
+# GCN-NEXT:   S_ENDPGM 0
 name: split_block
 tracksRegLiveness: true
 registers:
   - { id: 0, class: vgpr_32 }
   - { id: 1, class: vgpr_32 }
   - { id: 2, class: sgpr_32 }
   - { id: 3, class: sgpr_32 }
 body:             |
   bb.0:
     $vcc = IMPLICIT_DEF
     $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
 
   bb.1:
     %0 = IMPLICIT_DEF
     %2 = IMPLICIT_DEF
     %1 = V_ADD_F32_e64 0, killed %0, 0, 1, 0, 0, implicit $exec
     %3 = S_ADD_U32 %2, 1, implicit-def $scc
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: split_block_empty_block
 # GCN:      bb.0:
 # GCN-NEXT:   successors: %bb.1
 # GCN-NOT:  S_OR_B64
 # GCN:      bb.1:
 # GCN:      bb.2:
-# GCN-NEXT:   S_ENDPGM
+# GCN-NEXT:   S_ENDPGM 0
 name: split_block_empty_block
 tracksRegLiveness: true
 body:             |
   bb.0:
     $vcc = IMPLICIT_DEF
     $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
 
   bb.1:
 
   bb.2:
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: split_block_uncond_branch
 # GCN:      bb.0:
 # GCN-NEXT:   successors: %bb.1
 # GCN:        S_BRANCH %bb.1
 # GCN-NOT:  S_OR_B64
 # GCN:      bb.1:
-# GCN-NEXT:   S_ENDPGM
+# GCN-NEXT:   S_ENDPGM 0
 name: split_block_uncond_branch
 tracksRegLiveness: true
 body:             |
   bb.0:
     $vcc = IMPLICIT_DEF
     $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
     S_BRANCH %bb.1
 
   bb.1:
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: split_block_cond_branch
 # GCN:      bb.0:
 # GCN-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
 # GCN:        $sgpr0_sgpr1 = S_OR_B64 $exec, $vcc, implicit-def $scc
 # GCN:        S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc
 # GCN:      bb.1:
 # GCN:      bb.2:
-# GCN-NEXT:   S_ENDPGM
+# GCN-NEXT:   S_ENDPGM 0
 name: split_block_cond_branch
 tracksRegLiveness: true
 body:             |
   bb.0:
     $vcc = IMPLICIT_DEF
     $sgpr0_sgpr1 = S_OR_B64 $exec, $vcc, implicit-def $scc
     S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc
 
   bb.1:
 
   bb.2:
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: two_preds_both_dead
 # GCN:      bb.0:
 # GCN-NEXT:   successors: %bb.2
 # GCN-NOT:    S_OR
 # GCN:        S_BRANCH %bb.2
 # GCN:      bb.1:
 # GCN-NEXT:   successors: %bb.2
 # GCN-NOT:    S_AND
 # GCN:        S_BRANCH %bb.2
 # GCN:      bb.2:
-# GCN-NEXT:   S_ENDPGM
+# GCN-NEXT:   S_ENDPGM 0
 name: two_preds_both_dead
 tracksRegLiveness: true
 body:             |
   bb.0:
     $vcc = IMPLICIT_DEF
     $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
     S_BRANCH %bb.2
 
   bb.1:
     $vcc = IMPLICIT_DEF
     $sgpr0_sgpr1 = S_AND_B64 $exec, killed $vcc, implicit-def $scc
     S_BRANCH %bb.2
 
   bb.2:
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: two_preds_one_dead
 # GCN:      bb.0:
 # GCN-NEXT:   successors: %bb.2
 # GCN:        $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
 # GCN-NEXT:   S_BARRIER
 # GCN-NEXT:   S_BRANCH %bb.2
 # GCN:      bb.1:
 # GCN-NEXT:   successors: %bb.2
 # GCN-NOT:    S_AND
 # GCN:        S_BRANCH %bb.2
 # GCN:      bb.2:
-# GCN-NEXT:   S_ENDPGM
+# GCN-NEXT:   S_ENDPGM 0
 name: two_preds_one_dead
 tracksRegLiveness: true
 body:             |
   bb.0:
     $vcc = IMPLICIT_DEF
     $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
     S_BARRIER
     S_BRANCH %bb.2
 
   bb.1:
     $vcc = IMPLICIT_DEF
     $sgpr0_sgpr1 = S_AND_B64 $exec, killed $vcc, implicit-def $scc
     S_BRANCH %bb.2
 
   bb.2:
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 # GCN-LABEL: name: implicit_use_on_s_endpgm
 # GCN: V_ADD_I32
 # GCN: COPY
 # GCN: V_ADDC_U32
-# GCN: S_ENDPGM implicit %3
+# GCN: S_ENDPGM 0, implicit %3
 name: implicit_use_on_s_endpgm
 tracksRegLiveness: true
 
 body:             |
   bb.0:
     dead %0:vgpr_32 = V_ADD_I32_e32 12345, undef %1:vgpr_32, implicit-def $vcc, implicit $exec
     %2:sreg_64_xexec = COPY $vcc
     %3:vgpr_32, dead %4:sreg_64_xexec = V_ADDC_U32_e64 undef %5:vgpr_32, undef %6:vgpr_32, %2, implicit $exec
-    S_ENDPGM implicit %3
+    S_ENDPGM 0, implicit %3
 
 ...

test/CodeGen/AMDGPU/flat-load-clustering.mir

bb.0.bb:
     %9.sub1 = V_ADDC_U32_e32 %8, %2, implicit-def dead $vcc, implicit killed $vcc, implicit $exec
     undef %13.sub0 = V_ADD_I32_e32 16, %12.sub0, implicit-def $vcc, implicit $exec
     %13.sub1 = V_ADDC_U32_e32 %12.sub1, %2, implicit-def dead $vcc, implicit killed $vcc, implicit $exec
     %6 = FLAT_LOAD_DWORD %13, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4 from %ir.gep34)
     undef %10.sub0 = V_ADD_I32_e32 16, %9.sub0, implicit-def $vcc, implicit $exec
     %10.sub1 = V_ADDC_U32_e32 %9.sub1, %2, implicit-def dead $vcc, implicit killed $vcc, implicit $exec
     FLAT_STORE_DWORD %9, %5, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into %ir.gep2)
     FLAT_STORE_DWORD %10, %6, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into %ir.gep4)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...

test/CodeGen/AMDGPU/fold-imm-f16-f32.mir

bb.0 (%ir-block.0):
     %7 = COPY %6.sub0
     %8 = S_MOV_B32 61440
     %9 = S_MOV_B32 -1
     %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
     %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)
     %12 = V_MOV_B32_e32 1065353216, implicit $exec
     %13 = V_ADD_F16_e64 0, killed %11, 0, %12, 0, 0, implicit $exec
     BUFFER_STORE_SHORT_OFFSET killed %13, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 # Materialized f32 inline immediate should not be folded into the f16
 # operands
 
 # CHECK-LABEL: name: add_f32_1.0_multi_f16_use
 # CHECK: %13:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
bb.0 (%ir-block.0):
     %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
     %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)
     %12 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
     %13 = V_MOV_B32_e32 1065353216, implicit $exec
     %14 = V_ADD_F16_e64 0, killed %11, 0, %13, 0, 0, implicit $exec
     %15 = V_ADD_F16_e64 0, killed %12, 0, killed %13, 0, 0, implicit $exec
     BUFFER_STORE_SHORT_OFFSET killed %14, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
     BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # f32 1.0 should be folded into the single f32 use as an inline
 #  immediate, and folded into the single f16 use as a literal constant
 
 # CHECK-LABEL: name: add_f32_1.0_one_f32_use_one_f16_use
bb.0 (%ir-block.0):
     %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)
     %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)
     %13 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
     %14 = V_MOV_B32_e32 1065353216, implicit $exec
     %15 = V_ADD_F16_e64 0, %11, 0, %14, 0, 0, implicit $exec
     %16 = V_ADD_F32_e64 0, killed %13, 0, killed %14, 0, 0, implicit $exec
     BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
     BUFFER_STORE_DWORD_OFFSET killed %16, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `float addrspace(1)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # f32 1.0 should be folded for the single f32 use as an inline
 #  constant, and not folded as a multi-use literal for the f16 cases
 
 # CHECK-LABEL: name: add_f32_1.0_one_f32_use_multi_f16_use
bb.0 (%ir-block.0):
     %13 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
     %14 = V_MOV_B32_e32 1065353216, implicit $exec
     %15 = V_ADD_F16_e64 0, %11, 0, %14, 0, 0, implicit $exec
     %16 = V_ADD_F16_e64 0, %12, 0, %14, 0, 0, implicit $exec
     %17 = V_ADD_F32_e64 0, killed %13, 0, killed %14, 0, 0, implicit $exec
     BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
     BUFFER_STORE_SHORT_OFFSET killed %16, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
     BUFFER_STORE_DWORD_OFFSET killed %17, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `float addrspace(1)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 # CHECK-LABEL: name: add_i32_1_multi_f16_use
 # CHECK: %13:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
 # CHECK: %14:vgpr_32 = V_ADD_F16_e32 1, killed %11, implicit $exec
 # CHECK: %15:vgpr_32 = V_ADD_F16_e32 1, killed %12, implicit $exec
 
bb.0 (%ir-block.0):
     %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
     %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)
     %12 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
     %13 = V_MOV_B32_e32 1, implicit $exec
     %14 = V_ADD_F16_e64 0, killed %11, 0, %13, 0, 0, implicit $exec
     %15 = V_ADD_F16_e64 0, killed %12, 0, killed %13, 0, 0, implicit $exec
     BUFFER_STORE_SHORT_OFFSET killed %14, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
     BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # CHECK-LABEL: name: add_i32_m2_one_f32_use_multi_f16_use
 # CHECK: %14:vgpr_32 = V_MOV_B32_e32 -2, implicit $exec
 # CHECK: %15:vgpr_32 = V_ADD_F16_e32 -2, %11, implicit $exec
 # CHECK: %16:vgpr_32 = V_ADD_F16_e32 -2, %12, implicit $exec
bb.0 (%ir-block.0):
     %13 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
     %14 = V_MOV_B32_e32 -2, implicit $exec
     %15 = V_ADD_F16_e64 0, %11, 0, %14, 0, 0, implicit $exec
     %16 = V_ADD_F16_e64 0, %12, 0, %14, 0, 0, implicit $exec
     %17 = V_ADD_F32_e64 0, killed %13, 0, killed %14, 0, 0, implicit $exec
     BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
     BUFFER_STORE_SHORT_OFFSET killed %16, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
     BUFFER_STORE_DWORD_OFFSET killed %17, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `float addrspace(1)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # f32 1.0 should be folded for the single f32 use as an inline
 #  constant, and not folded as a multi-use literal for the f16 cases
 
 # CHECK-LABEL: name: add_f16_1.0_multi_f32_use
bb.0 (%ir-block.0):
     %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
     %11 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
     %12 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
     %13 = V_MOV_B32_e32 15360, implicit $exec
     %14 = V_ADD_F32_e64 0, %11, 0, %13, 0, 0, implicit $exec
     %15 = V_ADD_F32_e64 0, %12, 0, %13, 0, 0, implicit $exec
     BUFFER_STORE_DWORD_OFFSET killed %14, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `float addrspace(1)* undef`)
     BUFFER_STORE_DWORD_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `float addrspace(1)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # The low 16-bits are an inline immediate, but the high bits are junk
 # FIXME: Should be able to fold this
 
 # CHECK-LABEL: name: add_f16_1.0_other_high_bits_multi_f16_use
bb.0 (%ir-block.0):
     %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
     %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)
     %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)
     %13 = V_MOV_B32_e32 80886784, implicit $exec
     %14 = V_ADD_F16_e64 0, %11, 0, %13, 0, 0, implicit $exec
     %15 = V_ADD_F16_e64 0, %12, 0, %13, 0, 0, implicit $exec
     BUFFER_STORE_SHORT_OFFSET killed %14, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
     BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # FIXME: Should fold inline immediate into f16 and literal use into
 # f32 instruction.
 
 # CHECK-LABEL: name: add_f16_1.0_other_high_bits_use_f16_f32
bb.0 (%ir-block.0):
     %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
     %11 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
     %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)
     %13 = V_MOV_B32_e32 305413120, implicit $exec
     %14 = V_ADD_F32_e64 0, %11, 0, %13, 0, 0, implicit $exec
     %15 = V_ADD_F16_e64 0, %12, 0, %13, 0, 0, implicit $exec
     BUFFER_STORE_DWORD_OFFSET killed %14, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `float addrspace(1)* undef`)
     BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...

test/CodeGen/AMDGPU/fold-immediate-operand-shrink-with-carry.mir

 
 body:             |
   bb.0:
     ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_other_carry_out_use
     ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
     ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
     ; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
     ; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY killed $vcc
-    ; GCN: S_ENDPGM implicit [[COPY]]
+    ; GCN: S_ENDPGM 0, implicit [[COPY]]
     %0:sreg_32_xm0 = S_MOV_B32 12345
     %1:vgpr_32 = IMPLICIT_DEF
     %2:vgpr_32 = IMPLICIT_DEF
     %3:vgpr_32 = IMPLICIT_DEF
 
     %4:vgpr_32, %5:sreg_64_xexec = V_ADD_I32_e64 %0, %1, implicit $exec
-    S_ENDPGM implicit %5
+    S_ENDPGM 0, implicit %5
 
 ...
 ---
 
 name: shrink_scalar_imm_multi_use_with_used_carry
 tracksRegLiveness: true
 
 body:             |
   bb.0:
     ; GCN-LABEL: name: shrink_scalar_imm_multi_use_with_used_carry
     ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
     ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
     ; GCN: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
     ; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[S_MOV_B32_]], [[DEF]], implicit $exec
     ; GCN: [[V_ADD_I32_e64_2:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[S_MOV_B32_]], [[DEF1]], implicit $exec
-    ; GCN: S_ENDPGM implicit [[V_ADD_I32_e64_1]], implicit [[V_ADD_I32_e64_2]]
+    ; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e64_1]], implicit [[V_ADD_I32_e64_2]]
     %0:sreg_32_xm0 = S_MOV_B32 12345
     %1:vgpr_32 = IMPLICIT_DEF
     %2:vgpr_32 = IMPLICIT_DEF
     %3:vgpr_32 = IMPLICIT_DEF
     %4:vgpr_32 = IMPLICIT_DEF
 
     %5:vgpr_32, %6:sreg_64_xexec = V_ADD_I32_e64 %0, %1, implicit $exec
     %7:vgpr_32, %8:sreg_64_xexec = V_ADD_I32_e64 %0, %2, implicit $exec
-    S_ENDPGM implicit %6, implicit %7
+    S_ENDPGM 0, implicit %6, implicit %7
 
 ...
 ---
 
 # TODO: Is it OK to leave the broken use around on the DBG_VALUE?
 
 name: shrink_scalar_imm_vgpr_v_add_i32_e64_dbg_only_carry_out_use
 tracksRegLiveness: true
 
 body:             |
   bb.0:
     ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_dbg_only_carry_out_use
     ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
     ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
     ; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
     ; GCN: DBG_VALUE %5:sreg_64_xexec, $noreg
-    ; GCN: S_ENDPGM implicit [[V_ADD_I32_e32_]]
+    ; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e32_]]
     %0:sreg_32_xm0 = S_MOV_B32 12345
     %1:vgpr_32 = IMPLICIT_DEF
     %2:vgpr_32 = IMPLICIT_DEF
     %3:vgpr_32 = IMPLICIT_DEF
 
     %4:vgpr_32, %5:sreg_64_xexec = V_ADD_I32_e64 %0, %1, implicit $exec
     DBG_VALUE %5, $noreg
-    S_ENDPGM implicit %4
+    S_ENDPGM 0, implicit %4
 
 ...
 
 ---
 
 # Uses carry out in a normal pattern
 
 name: shrink_scalar_imm_vgpr_v_add_i32_e64_carry_out_use
 tracksRegLiveness: true
 
 body:             |
   bb.0:
     ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_carry_out_use
     ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
     ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
     ; GCN: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
     ; GCN: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
     ; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
     ; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY killed $vcc
     ; GCN: [[V_ADDC_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADDC_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADDC_U32_e64 [[DEF1]], [[DEF2]], [[COPY]], implicit $exec
-    ; GCN: S_ENDPGM implicit [[V_ADDC_U32_e64_]]
+    ; GCN: S_ENDPGM 0, implicit [[V_ADDC_U32_e64_]]
     %0:sreg_32_xm0 = S_MOV_B32 12345
     %1:vgpr_32 = IMPLICIT_DEF
     %2:vgpr_32 = IMPLICIT_DEF
     %3:vgpr_32 = IMPLICIT_DEF
 
     %4:vgpr_32, %5:sreg_64_xexec = V_ADD_I32_e64 %0, %1, implicit $exec
     %6:vgpr_32, %7:sreg_64_xexec = V_ADDC_U32_e64 %2, %3, %5, implicit $exec
-    S_ENDPGM implicit %6
+    S_ENDPGM 0, implicit %6
 
 ...

test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass si-fold-operands,dead-mi-elimination  %s -o - | FileCheck -check-prefix=GCN %s
 
 ---
 
 name: shrink_scalar_imm_vgpr_v_add_i32_e64_no_carry_out_use
 tracksRegLiveness: true
 
 body:             |
   bb.0:
     ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_no_carry_out_use
     ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
     ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
     ; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
-    ; GCN: S_ENDPGM implicit [[V_ADD_I32_e32_]]
+    ; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e32_]]
     %0:sreg_32_xm0 = S_MOV_B32 12345
     %1:vgpr_32 = IMPLICIT_DEF
     %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, implicit $exec
-    S_ENDPGM implicit %2
+    S_ENDPGM 0, implicit %2
 
 ...
 
 ---
 
 name: shrink_vgpr_scalar_imm_v_add_i32_e64_no_carry_out_use
 tracksRegLiveness: true
 
 body:             |
   bb.0:
     ; GCN-LABEL: name: shrink_vgpr_scalar_imm_v_add_i32_e64_no_carry_out_use
     ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
     ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
     ; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
-    ; GCN: S_ENDPGM implicit [[V_ADD_I32_e32_]]
+    ; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e32_]]
     %0:vgpr_32 = IMPLICIT_DEF
     %1:sreg_32_xm0 = S_MOV_B32 12345
     %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, implicit $exec
-    S_ENDPGM implicit %2
+    S_ENDPGM 0, implicit %2
 
 ...
 ---
 
 name: shrink_scalar_imm_vgpr_v_add_i32_e64_carry_out_use
 tracksRegLiveness: true
 
 body:             |
   bb.0:
     ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_carry_out_use
     ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
     ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
     ; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
-    ; GCN: S_ENDPGM implicit [[V_ADD_I32_e32_]]
+    ; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e32_]]
     %0:sreg_32_xm0 = S_MOV_B32 12345
     %1:vgpr_32 = IMPLICIT_DEF
     %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, implicit $exec
-    S_ENDPGM implicit %2
+    S_ENDPGM 0, implicit %2
 
 ...
 ---
 
 # This does not shrink because it would violate the constant bus
 # restriction. to have an SGPR input and an immediate, so a copy would
 # be required.
 
 name: shrink_vector_imm_sgpr_v_add_i32_e64_no_carry_out_use
 tracksRegLiveness: true
 
 body:             |
   bb.0:
     ; GCN-LABEL: name: shrink_vector_imm_sgpr_v_add_i32_e64_no_carry_out_use
     ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 12345, implicit $exec
     ; GCN: [[DEF:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF
     ; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[DEF]], [[V_MOV_B32_e32_]], implicit $exec
-    ; GCN: S_ENDPGM implicit [[V_ADD_I32_e64_]]
+    ; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]]
     %0:vgpr_32 = V_MOV_B32_e32 12345, implicit $exec
     %1:sreg_32_xm0 = IMPLICIT_DEF
     %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, implicit $exec
-    S_ENDPGM implicit %2
+    S_ENDPGM 0, implicit %2
 
 ...
 
 ---
 
 name: shrink_sgpr_vector_imm_v_add_i32_e64_no_carry_out_use
 tracksRegLiveness: true
 
 body:             |
   bb.0:
     ; GCN-LABEL: name: shrink_sgpr_vector_imm_v_add_i32_e64_no_carry_out_use
     ; GCN: [[DEF:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF
     ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 12345, implicit $exec
     ; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[V_MOV_B32_e32_]], [[DEF]], implicit $exec
-    ; GCN: S_ENDPGM implicit [[V_ADD_I32_e64_]]
+    ; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]]
     %0:sreg_32_xm0 = IMPLICIT_DEF
     %1:vgpr_32 = V_MOV_B32_e32 12345, implicit $exec
     %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, implicit $exec
-    S_ENDPGM implicit %2
+    S_ENDPGM 0, implicit %2
 
 ...
 
 ---
 
 name: shrink_scalar_imm_vgpr_v_add_i32_e64_live_vcc_use
 tracksRegLiveness: true
 
 body:             |
   bb.0:
     ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_live_vcc_use
     ; GCN: $vcc = S_MOV_B64 -1
     ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
     ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
     ; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[S_MOV_B32_]], [[DEF]], implicit $exec
-    ; GCN: S_ENDPGM implicit [[V_ADD_I32_e64_]], implicit $vcc
+    ; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]], implicit $vcc
     $vcc = S_MOV_B64 -1
     %0:sreg_32_xm0 = S_MOV_B32 12345
     %1:vgpr_32 = IMPLICIT_DEF
     %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, implicit $exec
-    S_ENDPGM implicit %2, implicit $vcc
+    S_ENDPGM 0, implicit %2, implicit $vcc
 
 ...
 
 ---
 
 name: shrink_scalar_imm_vgpr_v_add_i32_e64_liveout_vcc_use
 tracksRegLiveness: true
 
 body:             |
   ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_liveout_vcc_use
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x80000000)
   ; GCN:   $vcc = S_MOV_B64 -1
   ; GCN:   [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
   ; GCN:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
   ; GCN:   [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[S_MOV_B32_]], [[DEF]], implicit $exec
   ; GCN: bb.1:
   ; GCN:   liveins: $vcc
-  ; GCN:   S_ENDPGM implicit [[V_ADD_I32_e64_]], implicit $vcc
+  ; GCN:   S_ENDPGM 0, implicit [[V_ADD_I32_e64_]], implicit $vcc
   bb.0:
     successors: %bb.1
     $vcc = S_MOV_B64 -1
     %0:sreg_32_xm0 = S_MOV_B32 12345
     %1:vgpr_32 = IMPLICIT_DEF
     %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, implicit $exec
 
   bb.1:
     liveins: $vcc
-    S_ENDPGM implicit %2, implicit $vcc
+    S_ENDPGM 0, implicit %2, implicit $vcc
 
 ...
 ---
 
 name: shrink_scalar_imm_vgpr_v_add_i32_e64_liveout_vcc_lo_use
 tracksRegLiveness: true
 
 body:             |
   ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_liveout_vcc_lo_use
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x80000000)
   ; GCN:   [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
   ; GCN:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
   ; GCN:   [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[S_MOV_B32_]], [[DEF]], implicit $exec
   ; GCN: bb.1:
   ; GCN:   liveins: $vcc_lo
-  ; GCN:   S_ENDPGM implicit [[V_ADD_I32_e64_]], implicit $vcc_lo
+  ; GCN:   S_ENDPGM 0, implicit [[V_ADD_I32_e64_]], implicit $vcc_lo
   bb.0:
     successors: %bb.1
     $vcc = S_MOV_B64 -1
     %0:sreg_32_xm0 = S_MOV_B32 12345
     %1:vgpr_32 = IMPLICIT_DEF
     %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, implicit $exec
 
   bb.1:
     liveins: $vcc_lo
-    S_ENDPGM implicit %2, implicit $vcc_lo
+    S_ENDPGM 0, implicit %2, implicit $vcc_lo
 
 ...
 ---
 
 # This is not OK to clobber because vcc_lo has a livein use.
 
 name: shrink_scalar_imm_vgpr_v_add_i32_e64_livein_vcc
 tracksRegLiveness: true
 
 body:             |
   ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_livein_vcc
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x80000000)
   ; GCN:   $vcc = S_MOV_B64 -1
   ; GCN: bb.1:
   ; GCN:   liveins: $vcc
   ; GCN:   [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
   ; GCN:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
   ; GCN:   [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[S_MOV_B32_]], [[DEF]], implicit $exec
-  ; GCN:   S_ENDPGM implicit [[V_ADD_I32_e64_]], implicit $vcc_lo
+  ; GCN:   S_ENDPGM 0, implicit [[V_ADD_I32_e64_]], implicit $vcc_lo
   bb.0:
     successors: %bb.1
     $vcc = S_MOV_B64 -1
 
   bb.1:
     liveins: $vcc
     %0:sreg_32_xm0 = S_MOV_B32 12345
     %1:vgpr_32 = IMPLICIT_DEF
     %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, implicit $exec
-    S_ENDPGM implicit %2, implicit $vcc_lo
+    S_ENDPGM 0, implicit %2, implicit $vcc_lo
 
 ...
 ---
 
 name: shrink_scalar_imm_vgpr_v_add_i32_e64_livein_vcc_hi
 tracksRegLiveness: true
 
 body:             |
   ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_livein_vcc_hi
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x80000000)
   ; GCN:   $vcc_hi = S_MOV_B32 -1
   ; GCN: bb.1:
   ; GCN:   successors: %bb.2(0x80000000)
   ; GCN:   liveins: $vcc_hi
   ; GCN:   [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
   ; GCN:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
   ; GCN:   [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[S_MOV_B32_]], [[DEF]], implicit $exec
   ; GCN: bb.2:
   ; GCN:   liveins: $vcc_hi
-  ; GCN:   S_ENDPGM implicit [[V_ADD_I32_e64_]], implicit $vcc_hi
+  ; GCN:   S_ENDPGM 0, implicit [[V_ADD_I32_e64_]], implicit $vcc_hi
   bb.0:
     successors: %bb.1
     $vcc_hi = S_MOV_B32 -1
 
   bb.1:
     liveins: $vcc_hi
     %0:sreg_32_xm0 = S_MOV_B32 12345
     %1:vgpr_32 = IMPLICIT_DEF
     %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, implicit $exec
 
   bb.2:
     liveins: $vcc_hi
 
-    S_ENDPGM implicit %2, implicit $vcc_hi
+    S_ENDPGM 0, implicit %2, implicit $vcc_hi
 
 ...
 
 ---
 
 name: shrink_scalar_imm_vgpr_v_sub_i32_e64_no_carry_out_use
 tracksRegLiveness: true
 
 body:             |
   bb.0:
     ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_sub_i32_e64_no_carry_out_use
     ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
     ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
     ; GCN: [[V_SUBREV_I32_e32_:%[0-9]+]]:vgpr_32 = V_SUBREV_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
-    ; GCN: S_ENDPGM implicit [[V_SUBREV_I32_e32_]]
+    ; GCN: S_ENDPGM 0, implicit [[V_SUBREV_I32_e32_]]
     %0:sreg_32_xm0 = S_MOV_B32 12345
     %1:vgpr_32 = IMPLICIT_DEF
     %2:vgpr_32, %3:sreg_64 = V_SUB_I32_e64 %0, %1, implicit $exec
-    S_ENDPGM implicit %2
+    S_ENDPGM 0, implicit %2
 
 ...
 
 ---
 
 name: shrink_vgpr_scalar_imm_v_sub_i32_e64_no_carry_out_use
 tracksRegLiveness: true
 
 body:             |
   bb.0:
     ; GCN-LABEL: name: shrink_vgpr_scalar_imm_v_sub_i32_e64_no_carry_out_use
     ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
     ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
     ; GCN: [[V_SUB_I32_e32_:%[0-9]+]]:vgpr_32 = V_SUB_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
-    ; GCN: S_ENDPGM implicit [[V_SUB_I32_e32_]]
+    ; GCN: S_ENDPGM 0, implicit [[V_SUB_I32_e32_]]
     %0:vgpr_32 = IMPLICIT_DEF
     %1:sreg_32_xm0 = S_MOV_B32 12345
     %2:vgpr_32, %3:sreg_64 = V_SUB_I32_e64 %0, %1, implicit $exec
-    S_ENDPGM implicit %2
+    S_ENDPGM 0, implicit %2
 
 ...
 
 ---
 
 name: shrink_scalar_imm_vgpr_v_subrev_i32_e64_no_carry_out_use
 tracksRegLiveness: true
 
 body:             |
   bb.0:
     ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_subrev_i32_e64_no_carry_out_use
     ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
     ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
     ; GCN: [[V_SUB_I32_e32_:%[0-9]+]]:vgpr_32 = V_SUB_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
-    ; GCN: S_ENDPGM implicit [[V_SUB_I32_e32_]]
+    ; GCN: S_ENDPGM 0, implicit [[V_SUB_I32_e32_]]
     %0:sreg_32_xm0 = S_MOV_B32 12345
     %1:vgpr_32 = IMPLICIT_DEF
     %2:vgpr_32, %3:sreg_64 = V_SUBREV_I32_e64 %0, %1, implicit $exec
-    S_ENDPGM implicit %2
+    S_ENDPGM 0, implicit %2
 
 ...
 
 ---
 
 name: shrink_vgpr_scalar_imm_v_subrev_i32_e64_no_carry_out_use
 tracksRegLiveness: true
 
 body:             |
   bb.0:
     ; GCN-LABEL: name: shrink_vgpr_scalar_imm_v_subrev_i32_e64_no_carry_out_use
     ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
     ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
     ; GCN: [[V_SUBREV_I32_e32_:%[0-9]+]]:vgpr_32 = V_SUBREV_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
-    ; GCN: S_ENDPGM implicit [[V_SUBREV_I32_e32_]]
+    ; GCN: S_ENDPGM 0, implicit [[V_SUBREV_I32_e32_]]
     %0:vgpr_32 = IMPLICIT_DEF
     %1:sreg_32_xm0 = S_MOV_B32 12345
     %2:vgpr_32, %3:sreg_64 = V_SUBREV_I32_e64 %0, %1, implicit $exec
-    S_ENDPGM implicit %2
+    S_ENDPGM 0, implicit %2
 
 ...
 
 ---
 
 # We know this is OK because vcc isn't live out of the block.
 
 name: shrink_scalar_imm_vgpr_v_add_i32_e64_known_no_liveout
 tracksRegLiveness: true
 
 body:             |
   ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_known_no_liveout
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x80000000)
   ; GCN:   [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
   ; GCN:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
   ; GCN:   [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
   ; GCN: bb.1:
-  ; GCN:   S_ENDPGM implicit [[V_ADD_I32_e32_]]
+  ; GCN:   S_ENDPGM 0, implicit [[V_ADD_I32_e32_]]
   bb.0:
     successors: %bb.1
 
     S_NOP 0
     S_NOP 0
     S_NOP 0
     S_NOP 0
     S_NOP 0
bb.0:
     S_NOP 0
     %0:sreg_32_xm0 = S_MOV_B32 12345
     %1:vgpr_32 = IMPLICIT_DEF
     %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, implicit $exec
     S_NOP 0
     S_NOP 0
 
   bb.1:
-    S_ENDPGM implicit %2
+    S_ENDPGM 0, implicit %2
 
 ...
 
 ---
 
 # We know this is OK because vcc isn't live out of the block, even
 # though it had a defined but unused. value
 
 name: shrink_scalar_imm_vgpr_v_add_i32_e64_known_no_liveout_dead_vcc_def
 tracksRegLiveness: true
 
 body:             |
   ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_known_no_liveout_dead_vcc_def
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x80000000)
   ; GCN:   [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
   ; GCN:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
   ; GCN:   [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
   ; GCN: bb.1:
-  ; GCN:   S_ENDPGM implicit [[V_ADD_I32_e32_]]
+  ; GCN:   S_ENDPGM 0, implicit [[V_ADD_I32_e32_]]
   bb.0:
     successors: %bb.1
 
     S_NOP 0, implicit-def $vcc
     %0:sreg_32_xm0 = S_MOV_B32 12345
     %1:vgpr_32 = IMPLICIT_DEF
     %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, implicit $exec
     S_NOP 0
     S_NOP 0
 
   bb.1:
-    S_ENDPGM implicit %2
+    S_ENDPGM 0, implicit %2
 
 ...
 ---
 
 # This requires searching through many DBG_VALUE instructions before the insert poitn, which
 # should not count against the search limit.
 
 name: vcc_liveness_dbg_value_search_before
bb.0:
     ; GCN: DBG_VALUE $noreg, 0
     ; GCN: DBG_VALUE $noreg, 0
     ; GCN: DBG_VALUE $noreg, 0
     ; GCN: DBG_VALUE $noreg, 0
     ; GCN: DBG_VALUE $noreg, 0
     ; GCN: DBG_VALUE $noreg, 0
     ; GCN: DBG_VALUE $noreg, 0
     ; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
-    ; GCN: S_ENDPGM implicit [[V_ADD_I32_e32_]]
+    ; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e32_]]
     %0:sreg_32_xm0 = S_MOV_B32 12345
     %1:vgpr_32 = IMPLICIT_DEF
     DBG_VALUE $noreg, 0
     DBG_VALUE $noreg, 0
     DBG_VALUE $noreg, 0
     DBG_VALUE $noreg, 0
     DBG_VALUE $noreg, 0
     DBG_VALUE $noreg, 0
bb.0:
     DBG_VALUE $noreg, 0
     DBG_VALUE $noreg, 0
     DBG_VALUE $noreg, 0
     DBG_VALUE $noreg, 0
     DBG_VALUE $noreg, 0
     DBG_VALUE $noreg, 0
     DBG_VALUE $noreg, 0
     %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, implicit $exec
-    S_ENDPGM implicit %2
+    S_ENDPGM 0, implicit %2
 
 ...
 ---
 
 # This requires searching through many DBG_VALUE instructions after the insert point, which
 # should not count against the search limit.
 
 name: vcc_liveness_dbg_value_search_after
bb.0:
     ; GCN: DBG_VALUE $noreg, 0
     ; GCN: DBG_VALUE $noreg, 0
     ; GCN: DBG_VALUE $noreg, 0
     ; GCN: DBG_VALUE $noreg, 0
     ; GCN: DBG_VALUE $noreg, 0
     ; GCN: DBG_VALUE $noreg, 0
     ; GCN: DBG_VALUE $noreg, 0
     ; GCN: DBG_VALUE $noreg, 0
-    ; GCN: S_ENDPGM implicit [[V_ADD_I32_e32_]]
+    ; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e32_]]
     %0:sreg_32_xm0 = S_MOV_B32 12345
     %1:vgpr_32 = IMPLICIT_DEF
     S_NOP 0
     S_NOP 0
     S_NOP 0
     S_NOP 0
     S_NOP 0
     S_NOP 0
bb.0:
     DBG_VALUE $noreg, 0
     DBG_VALUE $noreg, 0
     DBG_VALUE $noreg, 0
     DBG_VALUE $noreg, 0
     DBG_VALUE $noreg, 0
     DBG_VALUE $noreg, 0
     DBG_VALUE $noreg, 0
     $vcc = S_MOV_B64 0
-    S_ENDPGM implicit %2
+    S_ENDPGM 0, implicit %2
 
 ...

test/CodeGen/AMDGPU/fold-immediate-output-mods.mir

bb.0:
     %20 = COPY %29
     %19 = BUFFER_LOAD_DWORD_ADDR64 %20, killed %14, 0, 0, 0, 0, 0, implicit $exec
     %22 = COPY %29
     %21 = BUFFER_LOAD_DWORD_ADDR64 %22, killed %17, 0, 0, 0, 0, 0, implicit $exec
     %23 = V_MOV_B32_e32 1090519040, implicit $exec
     %24 = V_MAC_F32_e64 0, killed %19, 0, killed %21, 0, %23, 1, 0, implicit $exec
     %26 = COPY %29
     BUFFER_STORE_DWORD_ADDR64 killed %24, %26, killed %18, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 # GCN-LABEL: name: no_fold_imm_madak_mac_omod_f32
 # GCN: %23:vgpr_32 = V_MOV_B32_e32 1090519040, implicit $exec
 # GCN: %24:vgpr_32 = V_MAC_F32_e64 0, killed %19, 0, killed %21, 0, %23, 0, 2, implicit $exec
 
 name:            no_fold_imm_madak_mac_omod_f32
bb.0:
     %20 = COPY %29
     %19 = BUFFER_LOAD_DWORD_ADDR64 %20, killed %14, 0, 0, 0, 0, 0, implicit $exec
     %22 = COPY %29
     %21 = BUFFER_LOAD_DWORD_ADDR64 %22, killed %17, 0, 0, 0, 0, 0, implicit $exec
     %23 = V_MOV_B32_e32 1090519040, implicit $exec
     %24 = V_MAC_F32_e64 0, killed %19, 0, killed %21, 0, %23, 0, 2, implicit $exec
     %26 = COPY %29
     BUFFER_STORE_DWORD_ADDR64 killed %24, %26, killed %18, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 # GCN: name: no_fold_imm_madak_mad_clamp_f32
 # GCN: %23:vgpr_32 = V_MOV_B32_e32 1090519040, implicit $exec
 # GCN: %24:vgpr_32 = V_MAD_F32 0, killed %19, 0, killed %21, 0, %23, 1, 0, implicit $exec
 
 name:            no_fold_imm_madak_mad_clamp_f32
bb.0:
     %20 = COPY %29
     %19 = BUFFER_LOAD_DWORD_ADDR64 %20, killed %14, 0, 0, 0, 0, 0, implicit $exec
     %22 = COPY %29
     %21 = BUFFER_LOAD_DWORD_ADDR64 %22, killed %17, 0, 0, 0, 0, 0, implicit $exec
     %23 = V_MOV_B32_e32 1090519040, implicit $exec
     %24 = V_MAD_F32 0, killed %19, 0, killed %21, 0, %23, 1, 0, implicit $exec
     %26 = COPY %29
     BUFFER_STORE_DWORD_ADDR64 killed %24, %26, killed %18, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 # GCN: name: no_fold_imm_madak_mad_omod_f32
 # GCN: %23:vgpr_32 = V_MOV_B32_e32 1090519040, implicit $exec
 # GCN: %24:vgpr_32 = V_MAD_F32 0, killed %19, 0, killed %21, 0, %23, 0, 1, implicit $exec
 
 name:            no_fold_imm_madak_mad_omod_f32
bb.0:
     %20 = COPY %29
     %19 = BUFFER_LOAD_DWORD_ADDR64 %20, killed %14, 0, 0, 0, 0, 0, implicit $exec
     %22 = COPY %29
     %21 = BUFFER_LOAD_DWORD_ADDR64 %22, killed %17, 0, 0, 0, 0, 0, implicit $exec
     %23 = V_MOV_B32_e32 1090519040, implicit $exec
     %24 = V_MAD_F32 0, killed %19, 0, killed %21, 0, %23, 0, 1, implicit $exec
     %26 = COPY %29
     BUFFER_STORE_DWORD_ADDR64 killed %24, %26, killed %18, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...

test/CodeGen/AMDGPU/fold-implicit-operand.mir

 # RUN: llc -march=amdgcn -run-pass si-fold-operands -verify-machineinstrs -o - %s | FileCheck %s
 ---
 # Make sure there is no crash when trying to fold an immediate into an
 # implicit use
 
 # CHECK: %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-# CHECK-NEXT: S_ENDPGM implicit %0
+# CHECK-NEXT: S_ENDPGM 0, implicit %0
 name: fold_imm_implicit_operand
 body:             |
   bb.0:
     %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-    S_ENDPGM implicit %0
+    S_ENDPGM 0, implicit %0
 
 ...

test/CodeGen/AMDGPU/fold-multiple.mir

body:             |
   bb.0 (%ir-block.0):
     %0 = IMPLICIT_DEF
     %1 = S_MOV_B32 2
     %2 = V_LSHLREV_B32_e64 %1, killed %0, implicit $exec
     %3 = S_LSHL_B32 %1, killed %1, implicit-def dead $scc
     %4 = V_AND_B32_e64 killed %2, killed %3, implicit $exec
     %5 = IMPLICIT_DEF
     BUFFER_STORE_DWORD_OFFSET killed %4, killed %5, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...

test/CodeGen/AMDGPU/global-load-store-atomics.mir

bb.0:
 
     %79:sreg_128 = REG_SEQUENCE %4, %subreg.sub0, %4, %subreg.sub1, %4, %subreg.sub2, %4, %subreg.sub3
     %80:vreg_128 = COPY %79
 
     %78:vreg_64 = GLOBAL_ATOMIC_CMPSWAP_X2_RTN %11, %80, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
     GLOBAL_STORE_DWORDX2 %11, %78, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
     GLOBAL_ATOMIC_CMPSWAP_X2 %11, %80, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
 
-    S_ENDPGM
+    S_ENDPGM 0
 ...

test/CodeGen/AMDGPU/hazard-buffer-store-v-interp.mir

 # RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN -check-prefix=VI %s
 # RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
 
 # GCN-LABEL: name: hazard_buffer_store_v_interp
 # GCN:    bb.0.entry:
 # GCN-NEXT:    BUFFER_STORE_DWORDX4_OFFSET_exact
 # GCN-NEXT:    S_NOP
 # GCN-NEXT:    V_INTERP_P1_F32
 
 name:            hazard_buffer_store_v_interp
 body:             |
   bb.0.entry:
     liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr7, $vgpr8, $vgpr9, $vgpr10
   
     BUFFER_STORE_DWORDX4_OFFSET_exact killed $vgpr7_vgpr8_vgpr9_vgpr10, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 96, 0, 0, 0, implicit $exec
     $vgpr7 = V_INTERP_P1_F32 $vgpr0, 0, 0, implicit $m0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...

test/CodeGen/AMDGPU/hazard-inlineasm.mir

 
 ---
 name: hazard-inlineasm
 
 body: |
   bb.0:
    FLAT_STORE_DWORDX4 $vgpr49_vgpr50, $vgpr26_vgpr27_vgpr28_vgpr29, 0, 0, 0, implicit $exec, implicit $flat_scr
    INLINEASM &"v_mad_u64_u32 $0, $1, $2, $3, $4", 0, 2621450, def $vgpr26_vgpr27, 2818058, def dead $sgpr14_sgpr15, 589833, $sgpr12, 327689, killed $vgpr51, 2621449, $vgpr46_vgpr47
-   S_ENDPGM
+   S_ENDPGM 0
 ...
 
 

test/CodeGen/AMDGPU/hazard-kill.mir

bb.0:
   
     $sgpr6 = S_MOV_B32 killed $sgpr3
     renamable $sgpr8_sgpr9_sgpr10_sgpr11 = S_LOAD_DWORDX4_IMM renamable $sgpr6_sgpr7, 16, 0
     $m0 = S_MOV_B32 killed renamable $sgpr4
     dead renamable $sgpr0 = KILL undef renamable $sgpr2
     renamable $vgpr0 = V_INTERP_MOV_F32 2, 0, 0, implicit $m0, implicit $exec
     renamable $sgpr0 = S_MOV_B32 0
 
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...

test/CodeGen/AMDGPU/hazard.mir

bb.0:
     $vgpr0 = IMPLICIT_DEF
     $vgpr1 = IMPLICIT_DEF
     $vgpr2 = IMPLICIT_DEF
     $vgpr3 = IMPLICIT_DEF
     $vgpr4 = IMPLICIT_DEF
     $vgpr5 = IMPLICIT_DEF
     $vgpr6 = IMPLICIT_DEF
     S_SENDMSG 3, implicit $exec, implicit $m0
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 # GCN-LABEL: name: hazard-lookahead-dbg-value
 # GCN: DBG_VALUE 6
 # GFX8-NEXT: S_NOP 0
 # GFX9-NEXT: S_NOP 0
 # GCN: S_SENDMSG 3, implicit $exec, implicit $m0
 ---
 name: hazard-lookahead-dbg-value
 body: |
   bb.0:
     $m0 = S_MOV_B32 killed $sgpr12
     DBG_VALUE 0
     DBG_VALUE 1
     DBG_VALUE 2
     DBG_VALUE 3
     DBG_VALUE 4
     DBG_VALUE 5
     DBG_VALUE 6
     S_SENDMSG 3, implicit $exec, implicit $m0
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 # GCN-LABEL: name: hazard-lookahead-dbg-label
 # GCN: DBG_LABEL 6
 # GFX8-NEXT: S_NOP 0
 # GFX9-NEXT: S_NOP 0
 # GCN: S_SENDMSG 3, implicit $exec, implicit $m0
 ---
 name: hazard-lookahead-dbg-label
 body: |
   bb.0:
     $m0 = S_MOV_B32 killed $sgpr12
     DBG_LABEL 0
     DBG_LABEL 1
     DBG_LABEL 2
     DBG_LABEL 3
     DBG_LABEL 4
     DBG_LABEL 5
     DBG_LABEL 6
     S_SENDMSG 3, implicit $exec, implicit $m0
-    S_ENDPGM
+    S_ENDPGM 0
 ...

test/CodeGen/AMDGPU/insert-skip-from-vcc.mir

body:             |
 
   bb.1:
     S_NOP 0
 
   bb.2:
     $sgpr0_sgpr1 = S_MOV_B64 -1
     $vcc = S_AND_B64 $exec, killed $sgpr0_sgpr1, implicit-def dead $scc
     S_CBRANCH_VCCZ %bb.1, implicit killed $vcc
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: and_execz_imm_vccz
 # GCN-NOT: S_AND_
 # GCN: S_CBRANCH_EXECZ %bb.1, implicit $exec
 name:            and_execz_imm_vccz
 body:             |
   bb.0:
     S_NOP 0
 
   bb.1:
     S_NOP 0
 
   bb.2:
     $vcc = S_AND_B64 $exec, -1, implicit-def dead $scc
     S_CBRANCH_VCCZ %bb.1, implicit killed $vcc
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: and_execnz_imm_vccnz
 # GCN-NOT: S_AND_
 # GCN: S_CBRANCH_EXECNZ %bb.1, implicit $exec
 name:            and_execnz_imm_vccnz
 body:             |
   bb.0:
     S_NOP 0
 
   bb.1:
     S_NOP 0
 
   bb.2:
     $vcc = S_AND_B64 $exec, -1, implicit-def dead $scc
     S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: and_execz_imm_vccz_live_scc
 # GCN: $vcc = S_AND_B64 $exec, -1, implicit-def $scc
 # GCN: S_CBRANCH_EXECZ %bb.1, implicit $exec
 name:            and_execz_imm_vccz_live_scc
 body:             |
   bb.0:
     S_NOP 0
 
   bb.1:
     S_NOP 0
 
   bb.2:
     $vcc = S_AND_B64 $exec, -1, implicit-def $scc
     S_CBRANCH_VCCZ %bb.1, implicit killed $vcc
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: and_execz_mov_vccz_live_scc
 # GCN-NOT: S_MOV_
 # GCN: $vcc = S_AND_B64 $exec, -1, implicit-def $scc
 # GCN: S_CBRANCH_EXECZ %bb.1, implicit $exec
 name:            and_execz_mov_vccz_live_scc
 body:             |
   bb.0:
     S_NOP 0
 
   bb.1:
     S_NOP 0
 
   bb.2:
     $sgpr0_sgpr1 = S_MOV_B64 -1
     $vcc = S_AND_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
     S_CBRANCH_VCCZ %bb.1, implicit killed $vcc
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: and_execz_mov_vccz_live_sreg
 # GCN:      $sgpr0_sgpr1 = S_MOV_B64 -1
 # GCN-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec
 name:            and_execz_mov_vccz_live_sreg
 body:             |
   bb.0:
     S_NOP 0
 
   bb.1:
     S_NOP 0
 
   bb.2:
     $sgpr0_sgpr1 = S_MOV_B64 -1
     $vcc = S_AND_B64 $exec, $sgpr0_sgpr1, implicit-def dead $scc
     S_CBRANCH_VCCZ %bb.1, implicit killed $vcc
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: and_execz_mov_vccz_live_sreg_commute
 # GCN:      $sgpr0_sgpr1 = S_MOV_B64 -1
 # GCN-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec
 name:            and_execz_mov_vccz_live_sreg_commute
 body:             |
   bb.0:
     S_NOP 0
 
   bb.1:
     S_NOP 0
 
   bb.2:
     $sgpr0_sgpr1 = S_MOV_B64 -1
     $vcc = S_AND_B64 $sgpr0_sgpr1, $exec, implicit-def dead $scc
     S_CBRANCH_VCCZ %bb.1, implicit killed $vcc
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: and_execz_mov_vccz_live_scc_commute
 # GCN-NOT: S_MOV_
 # GCN: $vcc = S_AND_B64 $exec, -1, implicit-def $scc
 # GCN: S_CBRANCH_EXECZ %bb.1, implicit $exec
 name:            and_execz_mov_vccz_live_scc_commute
 body:             |
   bb.0:
     S_NOP 0
 
   bb.1:
     S_NOP 0
 
   bb.2:
     $sgpr0_sgpr1 = S_MOV_B64 -1
     $vcc = S_AND_B64 killed $sgpr0_sgpr1, $exec, implicit-def $scc
     S_CBRANCH_VCCZ %bb.1, implicit killed $vcc
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: and_execz_mov_vccz_commute
 # GCN-NOT: S_MOV_
 # GCN-NOT: S_AND_
 # GCN: S_CBRANCH_EXECZ %bb.1, implicit $exec
 name:            and_execz_mov_vccz_commute
 body:             |
   bb.0:
     S_NOP 0
 
   bb.1:
     S_NOP 0
 
   bb.2:
     $sgpr0_sgpr1 = S_MOV_B64 -1
     $vcc = S_AND_B64 killed $sgpr0_sgpr1, $exec, implicit-def dead $scc
     S_CBRANCH_VCCZ %bb.1, implicit killed $vcc
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: and_execz_mov_exec_vccz
 # GCN:      $exec = S_MOV_B64 -1
-# GCN-NEXT: S_ENDPGM
+# GCN-NEXT: S_ENDPGM 0
 name:            and_execz_mov_exec_vccz
 body:             |
   bb.0:
     S_NOP 0
 
   bb.1:
     S_NOP 0
 
   bb.2:
     $exec = S_MOV_B64 -1
     $vcc = S_AND_B64 $exec, $exec, implicit-def dead $scc
     S_CBRANCH_VCCZ %bb.1, implicit killed $vcc
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: and_execz_mov_exec_vccnz
 # GCN:      $exec = S_MOV_B64 -1
 # GCN-NEXT: S_BRANCH %bb.1{{$}}
 name:            and_execz_mov_exec_vccnz
 body:             |
   bb.0:
     S_NOP 0
 
   bb.1:
     S_NOP 0
 
   bb.2:
     $exec = S_MOV_B64 -1
     $vcc = S_AND_B64 $exec, $exec, implicit-def dead $scc
     S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: and_execz_mov_vccz_reads_sreg_early
 # GCN:      $sgpr0_sgpr1 = S_MOV_B64 -1
 # GCN-NEXT: $sgpr2 = S_MOV_B32 $sgpr1
 # GCN-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec
 name:            and_execz_mov_vccz_reads_sreg_early
 body:             |
   bb.0:
     S_NOP 0
 
   bb.1:
     S_NOP 0
 
   bb.2:
     $sgpr0_sgpr1 = S_MOV_B64 -1
     $sgpr2 = S_MOV_B32 $sgpr1
     $vcc = S_AND_B64 $exec, killed $sgpr0_sgpr1, implicit-def dead $scc
     S_CBRANCH_VCCZ %bb.1, implicit killed $vcc
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: and_execz_mov_vccz_reads_sreg_late
 # GCN:      $sgpr0_sgpr1 = S_MOV_B64 -1
 # GCN-NEXT: $sgpr2 = S_MOV_B32 $sgpr1
 # GCN-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec
 name:            and_execz_mov_vccz_reads_sreg_late
 body:             |
   bb.0:
     S_NOP 0
 
   bb.1:
     S_NOP 0
 
   bb.2:
     $sgpr0_sgpr1 = S_MOV_B64 -1
     $vcc = S_AND_B64 $exec, $sgpr0_sgpr1, implicit-def dead $scc
     $sgpr2 = S_MOV_B32 $sgpr1
     S_CBRANCH_VCCZ %bb.1, implicit killed $vcc
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 # GCN-LABEL: name: and_execz_mov_vccz_reads_writes_sreg_early
 # GCN:      $sgpr0_sgpr1 = S_MOV_B64 -1
 # GCN-NEXT: $sgpr1 = S_MOV_B32 $sgpr0
 # GCN-NEXT: $vcc = S_AND_B64 $exec, killed $sgpr0_sgpr1, implicit-def dead $scc
 # GCN-NEXT: S_CBRANCH_VCCZ %bb.1, implicit killed $vcc
 name:            and_execz_mov_vccz_reads_writes_sreg_early
 body:             |
   bb.0:
     S_NOP 0
 
   bb.1:
     S_NOP 0
 
   bb.2:
     $sgpr0_sgpr1 = S_MOV_B64 -1
     $sgpr1 = S_MOV_B32 $sgpr0
     $vcc = S_AND_B64 $exec, killed $sgpr0_sgpr1, implicit-def dead $scc
     S_CBRANCH_VCCZ %bb.1, implicit killed $vcc
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: and_execz_mov_vccz_reads_cond
 # GCN:      $vcc = S_AND_B64 $exec, -1, implicit-def dead $scc
 # GCN-NEXT: $sgpr2 = S_MOV_B32 $vcc_lo
 # GCN-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec
 name:            and_execz_mov_vccz_reads_cond
 body:             |
   bb.0:
     S_NOP 0
 
   bb.1:
     S_NOP 0
 
   bb.2:
     $sgpr0_sgpr1 = S_MOV_B64 -1
     $vcc = S_AND_B64 $exec, killed $sgpr0_sgpr1, implicit-def dead $scc
     $sgpr2 = S_MOV_B32 $vcc_lo
     S_CBRANCH_VCCZ %bb.1, implicit killed $vcc
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: and_execz_mov_vccz_modifies_sreg
 # GCN:      $sgpr0_sgpr1 = S_MOV_B64 -1
 # GCN-NEXT: $sgpr0 = S_MOV_B32 0
 # GCN-NEXT: $vcc = S_AND_B64 $exec, killed $sgpr0_sgpr1, implicit-def dead $scc
 # GCN-NEXT: S_CBRANCH_VCCZ %bb.1, implicit killed $vcc
 name:            and_execz_mov_vccz_modifies_sreg
 body:             |
   bb.0:
     S_NOP 0
 
   bb.1:
     S_NOP 0
 
   bb.2:
     $sgpr0_sgpr1 = S_MOV_B64 -1
     $sgpr0 = S_MOV_B32 0
     $vcc = S_AND_B64 $exec, killed $sgpr0_sgpr1, implicit-def dead $scc
     S_CBRANCH_VCCZ %bb.1, implicit killed $vcc
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: and_execz_imm_vccz_liveout_scc
 # GCN:      $vcc = S_AND_B64 $exec, -1, implicit-def $scc
 # GCN-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec
-# GCN-NEXT  S_ENDPGM implicit $scc
+# GCN-NEXT  S_ENDPGM 0, implicit $scc
 name:            and_execz_imm_vccz_liveout_scc
 body:             |
   bb.0:
     S_NOP 0
 
   bb.1:
     S_NOP 0
 
   bb.2:
     $vcc = S_AND_B64 $exec, -1, implicit-def $scc
     S_CBRANCH_VCCZ %bb.1, implicit killed $vcc
-    S_ENDPGM implicit $scc
+    S_ENDPGM 0, implicit $scc
 ...

test/CodeGen/AMDGPU/insert-skips-kill-uncond.mir

 # CHECK: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
 
 # CHECK: bb.1:
 # CHECK: V_CMPX_LE_F32_e32
 # CHECK-NEXT: S_CBRANCH_EXECNZ %bb.2, implicit $exec
 
 # CHECK: bb.3:
 # CHECK-NEXT: EXP_DONE
-# CHECK: S_ENDPGM
+# CHECK: S_ENDPGM 0
 
 # CHECK: bb.2:
-# CHECK: S_ENDPGM
+# CHECK: S_ENDPGM 0
 
 name: kill_uncond_branch
 
 body: |
   bb.0:
     successors: %bb.1
     S_CBRANCH_VCCNZ %bb.1, implicit $vcc
 
   bb.1:
     successors: %bb.2
     $vgpr0 = V_MOV_B32_e32 0, implicit $exec
     SI_KILL_F32_COND_IMM_TERMINATOR $vgpr0, 0, 3, implicit-def $exec, implicit-def $vcc, implicit-def $scc, implicit $exec
     S_BRANCH %bb.2
 
   bb.2:
-    S_ENDPGM
+    S_ENDPGM 0

test/CodeGen/AMDGPU/inserted-wait-states.mir

body: |
   bb.2:
     $vcc = V_CMP_EQ_I32_e64 $vgpr1, $vgpr2, implicit $exec
     $vgpr0 = V_DIV_FMAS_F32 0, $vgpr1, 0, $vgpr2, 0, $vgpr3, 0, 0, implicit $vcc, implicit $exec
     S_BRANCH %bb.3
 
   bb.3:
     $vgpr4, $vcc = V_DIV_SCALE_F32 $vgpr1, $vgpr1, $vgpr3, implicit $exec
     $vgpr0 = V_DIV_FMAS_F32 0, $vgpr1, 0, $vgpr2, 0, $vgpr3, 0, 0, implicit $vcc, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 
 ...
 ---
 # GCN-LABEL: name: s_getreg
 
 # GCN-LABEL: bb.0:
bb.2:
     S_SETREG_B32 $sgpr0, 1
     $sgpr1 = S_MOV_B32 0
     $sgpr2 = S_GETREG_B32 1
     S_BRANCH %bb.3
 
   bb.3:
     S_SETREG_B32 $sgpr0, 0
     $sgpr1 = S_GETREG_B32 1
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 ...
 ---
 # GCN-LABEL: name: s_setreg
 
 # GCN-LABEL: bb.0:
 # GCN: S_SETREG
body: |
   bb.1:
     S_SETREG_B32 $sgpr0, 64
     S_SETREG_B32 $sgpr1, 128
     S_BRANCH %bb.2
 
   bb.2:
     S_SETREG_B32 $sgpr0, 1
     S_SETREG_B32 $sgpr1, 0
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 ...
 ---
 # GCN-LABEL: name: vmem_gt_8dw_store
 
 # GCN-LABEL: bb.0:
 # GCN: BUFFER_STORE_DWORD_OFFSET
bb.1:
     FLAT_STORE_DWORDX3 $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr3 = V_MOV_B32_e32 0, implicit $exec
     FLAT_STORE_DWORDX4 $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr3 = V_MOV_B32_e32 0, implicit $exec
     FLAT_ATOMIC_CMPSWAP_X2 $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr3 = V_MOV_B32_e32 0, implicit $exec
     FLAT_ATOMIC_FCMPSWAP_X2 $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, implicit $exec, implicit $flat_scr
     $vgpr3 = V_MOV_B32_e32 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 
 ...
 ---
 
 # GCN-LABEL: name: readwrite_lane
 
body: |
   bb.2:
     $vgpr0,implicit $vcc = V_ADD_I32_e32 $vgpr1, $vgpr2, implicit $vcc, implicit $exec
     $sgpr4 = V_READLANE_B32 $vgpr4, $vcc_lo
     S_BRANCH %bb.3
 
   bb.3:
     $vgpr0,implicit $vcc = V_ADD_I32_e32 $vgpr1, $vgpr2, implicit $vcc, implicit $exec
     $vgpr4 = V_WRITELANE_B32 $sgpr4, $vcc_lo, $vgpr4
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 
 ...
 ---
 
 # GCN-LABEL: name: rfe
 
body: |
   bb.0:
     S_SETREG_B32 $sgpr0, 3
     S_RFE_B64 $sgpr2_sgpr3
     S_BRANCH %bb.1
 
   bb.1:
     S_SETREG_B32 $sgpr0, 0
     S_RFE_B64 $sgpr2_sgpr3
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 
 ...
 ---
 
 # GCN-LABEL: name: s_mov_fed_b32
 
body: |
   bb.0:
     $sgpr0 = S_MOV_FED_B32 $sgpr0
     $sgpr0 = S_MOV_B32 $sgpr0
     S_BRANCH %bb.1
 
   bb.1:
     $sgpr0 = S_MOV_FED_B32 $sgpr0
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 
 ...
 ---
 
 # GCN-LABEL: name: s_movrel
 
body: |
   bb.2:
     $m0 = S_MOV_B32 0
     $sgpr0 = S_MOVRELD_B32 $sgpr0, implicit $m0
     S_BRANCH %bb.3
 
   bb.3:
     $m0 = S_MOV_B32 0
     $sgpr0_sgpr1 = S_MOVRELD_B64 $sgpr0_sgpr1, implicit $m0
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 ...
 ---
 
 # GCN-LABEL: name: v_interp
 
 # GCN-LABEL: bb.0:
body: |
   bb.2:
     $m0 = S_MOV_B32 0
     $vgpr0 = V_INTERP_P1_F32_16bank $vgpr0, 0, 0, implicit $m0, implicit $exec
     S_BRANCH %bb.3
 
   bb.3:
     $m0 = S_MOV_B32 0
     $vgpr0 = V_INTERP_MOV_F32 0, 0, 0, implicit $m0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 ...
 ---
 
 # GCN-LABEL: name: dpp
 
 # VI-LABEL: bb.0:
body: |
   bb.0:
     $vgpr0 = V_MOV_B32_e32 0, implicit $exec
     $vgpr1 = V_MOV_B32_dpp $vgpr1, $vgpr0, 0, 15, 15, 0, implicit $exec
     S_BRANCH %bb.1
 
   bb.1:
     implicit $exec, implicit $vcc = V_CMPX_EQ_I32_e32 $vgpr0, $vgpr1, implicit $exec
     $vgpr3 = V_MOV_B32_dpp $vgpr3, $vgpr0, 0, 15, 15, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 name:            mov_fed_hazard_crash_on_dbg_value
 alignment:       0
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
bb.0.entry:
     $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed $sgpr4_sgpr5, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
     dead $sgpr6_sgpr7 = KILL $sgpr4_sgpr5
     $sgpr8 = S_MOV_B32 $sgpr5
     $vgpr0 = V_MOV_B32_e32 killed $sgpr8, implicit $exec
     BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr9, 4, 0, 0, 0, implicit $exec :: (store 4 into %ir.A.addr + 4)
     $sgpr8 = S_MOV_B32 $sgpr4, implicit killed $sgpr4_sgpr5
     $vgpr0 = V_MOV_B32_e32 killed $sgpr8, implicit $exec
     BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr9, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.A.addr)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...

test/CodeGen/AMDGPU/invert-br-undef-vcc.mir

bb.2.if:
     $vgpr0 = V_MOV_B32_e32 0, implicit $exec
 
   bb.3.done:
     liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
 
     $sgpr3 = S_MOV_B32 61440
     $sgpr2 = S_MOV_B32 -1
     BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.out)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...

test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir

bb.1.atomic:
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     S_WAITCNT 3952
     BUFFER_ATOMIC_SMAX_ADDR64 killed $vgpr0, killed $vgpr1_vgpr2, killed $sgpr4_sgpr5_sgpr6_sgpr7, 0, 400, 0, implicit $exec :: (volatile load seq_cst 4 from %ir.gep)
 
   bb.2.exit:
     liveins: $sgpr2_sgpr3
 
     $exec = S_OR_B64 $exec, killed $sgpr2_sgpr3, implicit-def $scc
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 

test/CodeGen/AMDGPU/memory-legalizer-invalid-addrspace.mir

bb.0:
     liveins: $sgpr0_sgpr1
 
     $vgpr0 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr2_sgpr3
     $vgpr1 = V_MOV_B32_e32 killed $sgpr3, implicit $exec, implicit $sgpr2_sgpr3, implicit $exec
     renamable $vgpr2 = FLAT_LOAD_DWORD killed renamable $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load seq_cst 4 from `i32 addrspace(42)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN: error: <unknown>:0:0: in function invalid_store void (): Unsupported atomic address space
 
 name:            invalid_store
 body:             |
   bb.0:
     liveins: $sgpr0_sgpr1
 
     $vgpr2 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile store syncscope("agent") seq_cst 4 into `i32 addrspace(42)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN: error: <unknown>:0:0: in function invalid_cmpxchg void (): Unsupported atomic address space
 
 name:            invalid_cmpxchg
 body:             |
   bb.0:
     liveins: $sgpr0_sgpr1
 
     $vgpr3 = V_MOV_B32_e32 $sgpr1, implicit $exec, implicit-def $vgpr2_vgpr3, implicit $sgpr0_sgpr1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr4, implicit $exec, implicit $exec
     $vgpr1 = V_MOV_B32_e32 killed $sgpr5, implicit $exec, implicit $exec
     $vgpr2 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_ATOMIC_CMPSWAP killed renamable $vgpr2_vgpr3, killed renamable $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store syncscope("workgroup") seq_cst seq_cst 4 on `i32 addrspace(42)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN: error: <unknown>:0:0: in function invalid_rmw void (): Unsupported atomic address space
 
 name:            invalid_rmw
 body:             |
   bb.0:
     liveins: $sgpr0_sgpr1
 
     $vgpr0 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr2_sgpr3
     $vgpr1 = V_MOV_B32_e32 killed $sgpr3, implicit $exec, implicit $sgpr2_sgpr3, implicit $exec
     $vgpr2 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     FLAT_ATOMIC_SWAP killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store syncscope("wavefront") seq_cst 4 on `i32 addrspace(42)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...

test/CodeGen/AMDGPU/memory-legalizer-local.mir

bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("singlethread") unordered 4 from `i32 addrspace(3)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_singlethread_monotonic
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_singlethread_monotonic
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("singlethread") monotonic 4 from `i32 addrspace(3)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_singlethread_acquire
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_singlethread_acquire
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("singlethread") acquire 4 from `i32 addrspace(3)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_singlethread_seq_cst
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_singlethread_seq_cst
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("singlethread") seq_cst 4 from `i32 addrspace(3)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_wavefront_unordered
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_wavefront_unordered
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("wavefront") unordered 4 from `i32 addrspace(3)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_wavefront_monotonic
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_wavefront_monotonic
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("wavefront") monotonic 4 from `i32 addrspace(3)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_wavefront_acquire
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_wavefront_acquire
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("wavefront") acquire 4 from `i32 addrspace(3)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_wavefront_seq_cst
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_wavefront_seq_cst
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("wavefront") seq_cst 4 from `i32 addrspace(3)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_workgroup_unordered
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_workgroup_unordered
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("workgroup") unordered 4 from `i32 addrspace(3)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_workgroup_monotonic
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_workgroup_monotonic
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("workgroup") monotonic 4 from `i32 addrspace(3)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_workgroup_acquire
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_workgroup_acquire
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("workgroup") acquire 4 from `i32 addrspace(3)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_workgroup_seq_cst
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_workgroup_seq_cst
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("workgroup") seq_cst 4 from `i32 addrspace(3)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_agent_unordered
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_agent_unordered
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("agent") unordered 4 from `i32 addrspace(3)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_agent_monotonic
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_agent_monotonic
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("agent") monotonic 4 from `i32 addrspace(3)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_agent_acquire
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_agent_acquire
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("agent") acquire 4 from `i32 addrspace(3)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_agent_seq_cst
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_agent_seq_cst
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("agent") seq_cst 4 from `i32 addrspace(3)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_system_unordered
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_system_unordered
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load unordered 4 from `i32 addrspace(3)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_system_monotonic
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_system_monotonic
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load monotonic 4 from `i32 addrspace(3)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_system_acquire
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_system_acquire
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load acquire 4 from `i32 addrspace(3)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_system_seq_cst
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_system_seq_cst
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load seq_cst 4 from `i32 addrspace(3)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_singlethread_unordered
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_singlethread_unordered
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread") unordered 4 into `i32 addrspace(3)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_singlethread_monotonic
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_singlethread_monotonic
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread") monotonic 4 into `i32 addrspace(3)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_singlethread_release
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_singlethread_release
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread") release 4 into `i32 addrspace(3)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_singlethread_seq_cst
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_singlethread_seq_cst
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread") seq_cst 4 into `i32 addrspace(3)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_wavefront_unordered
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_wavefront_unordered
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("wavefront") unordered 4 into `i32 addrspace(3)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_wavefront_monotonic
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_wavefront_monotonic
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("wavefront") monotonic 4 into `i32 addrspace(3)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_wavefront_release
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_wavefront_release
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("wavefront") release 4 into `i32 addrspace(3)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_wavefront_seq_cst
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_wavefront_seq_cst
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("wavefront") seq_cst 4 into `i32 addrspace(3)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_workgroup_unordered
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_workgroup_unordered
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("workgroup") unordered 4 into `i32 addrspace(3)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_workgroup_monotonic
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_workgroup_monotonic
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("workgroup") monotonic 4 into `i32 addrspace(3)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_workgroup_release
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_workgroup_release
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("workgroup") release 4 into `i32 addrspace(3)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_workgroup_seq_cst
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_workgroup_seq_cst
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("workgroup") seq_cst 4 into `i32 addrspace(3)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_agent_unordered
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_agent_unordered
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("agent") unordered 4 into `i32 addrspace(3)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_agent_monotonic
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_agent_monotonic
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("agent") monotonic 4 into `i32 addrspace(3)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_agent_release
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_agent_release
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("agent") release 4 into `i32 addrspace(3)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_agent_seq_cst
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_agent_seq_cst
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("agent") seq_cst 4 into `i32 addrspace(3)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_system_unordered
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_system_unordered
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store unordered 4 into `i32 addrspace(3)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_system_monotonic
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_system_monotonic
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store monotonic 4 into `i32 addrspace(3)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_system_release
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_system_release
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store release 4 into `i32 addrspace(3)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_system_seq_cst
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_system_seq_cst
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store seq_cst 4 into `i32 addrspace(3)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: atomicrmw_singlethread_unordered
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRXCHG_RTN_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            atomicrmw_singlethread_unordered
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     $vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread") unordered 4 into `i32 addrspace(3)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: atomicrmw_singlethread_monotonic
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRXCHG_RTN_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            atomicrmw_singlethread_monotonic
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     $vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread") monotonic 4 into `i32 addrspace(3)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: atomicrmw_singlethread_acquire
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRXCHG_RTN_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            atomicrmw_singlethread_acquire
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     $vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread") acquire 4 into `i32 addrspace(3)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: atomicrmw_singlethread_release
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRXCHG_RTN_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            atomicrmw_singlethread_release
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     $vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread") release 4 into `i32 addrspace(3)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: atomicrmw_singlethread_acq_rel
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRXCHG_RTN_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            atomicrmw_singlethread_acq_rel
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     $vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread") acq_rel 4 into `i32 addrspace(3)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: atomicrmw_singlethread_seq_cst
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRXCHG_RTN_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            atomicrmw_singlethread_seq_cst
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     $vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread") seq_cst 4 into `i32 addrspace(3)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...

test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir

bb.3:
     S_WAITCNT 127
     $sgpr0 = S_LSHL_B32 killed $sgpr0, 2, implicit-def dead $scc
     $vgpr0 = V_ADD_I32_e32 killed $sgpr0, killed $vgpr0, implicit-def dead $vcc, implicit $exec
     $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr0, killed $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 0, 0, 0, implicit $exec :: (load syncscope("agent") unordered 4 from `i32 addrspace(1)* undef`), (load syncscope("workgroup") seq_cst 4 from `[8192 x i32] addrspace(5)* undef`)
     $vgpr1 = V_MOV_B32_e32 $sgpr4, implicit $exec, implicit-def $vgpr1_vgpr2, implicit $sgpr4_sgpr5
     $vgpr2 = V_MOV_B32_e32 killed $sgpr5, implicit $exec, implicit $sgpr4_sgpr5, implicit $exec
     S_WAITCNT 3952
     FLAT_STORE_DWORD killed $vgpr1_vgpr2, killed $vgpr0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32 addrspace(1)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...

test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir

bb.3.done:
     S_WAITCNT 127
     $sgpr0 = S_LSHL_B32 killed $sgpr0, 2, implicit-def dead $scc
     $vgpr0 = V_ADD_I32_e32 killed $sgpr0, killed $vgpr0, implicit-def dead $vcc, implicit $exec
     $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr0, killed $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 0, 0, 0, implicit $exec :: (non-temporal load 4 from %ir.else_ptr), (non-temporal load 4 from %ir.if_ptr)
     $vgpr1 = V_MOV_B32_e32 $sgpr4, implicit $exec, implicit-def $vgpr1_vgpr2, implicit $sgpr4_sgpr5
     $vgpr2 = V_MOV_B32_e32 killed $sgpr5, implicit $exec, implicit $sgpr4_sgpr5, implicit $exec
     S_WAITCNT 3952
     FLAT_STORE_DWORD killed $vgpr1_vgpr2, killed $vgpr0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into %ir.out)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...

test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir

bb.3.done:
     S_WAITCNT 127
     $sgpr0 = S_LSHL_B32 killed $sgpr0, 2, implicit-def dead $scc
     $vgpr0 = V_ADD_I32_e32 killed $sgpr0, killed $vgpr0, implicit-def dead $vcc, implicit $exec
     $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr0, killed $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 0, 0, 0, implicit $exec :: (load 4 from %ir.else_ptr), (non-temporal load 4 from %ir.if_ptr)
     $vgpr1 = V_MOV_B32_e32 $sgpr4, implicit $exec, implicit-def $vgpr1_vgpr2, implicit $sgpr4_sgpr5
     $vgpr2 = V_MOV_B32_e32 killed $sgpr5, implicit $exec, implicit $sgpr4_sgpr5, implicit $exec
     S_WAITCNT 3952
     FLAT_STORE_DWORD killed $vgpr1_vgpr2, killed $vgpr0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into %ir.out)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...

test/CodeGen/AMDGPU/memory-legalizer-region.mir

bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 1, 0, implicit $m0, implicit $exec :: (volatile load syncscope("singlethread") unordered 4 from `i32 addrspace(2)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_singlethread_monotonic
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_singlethread_monotonic
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("singlethread") monotonic 4 from `i32 addrspace(2)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_singlethread_acquire
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_singlethread_acquire
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("singlethread") acquire 4 from `i32 addrspace(2)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_singlethread_seq_cst
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_singlethread_seq_cst
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("singlethread") seq_cst 4 from `i32 addrspace(2)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_wavefront_unordered
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_wavefront_unordered
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("wavefront") unordered 4 from `i32 addrspace(2)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_wavefront_monotonic
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_wavefront_monotonic
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("wavefront") monotonic 4 from `i32 addrspace(2)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_wavefront_acquire
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_wavefront_acquire
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("wavefront") acquire 4 from `i32 addrspace(2)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_wavefront_seq_cst
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_wavefront_seq_cst
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("wavefront") seq_cst 4 from `i32 addrspace(2)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_workgroup_unordered
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_workgroup_unordered
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("workgroup") unordered 4 from `i32 addrspace(2)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_workgroup_monotonic
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_workgroup_monotonic
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("workgroup") monotonic 4 from `i32 addrspace(2)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_workgroup_acquire
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_workgroup_acquire
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("workgroup") acquire 4 from `i32 addrspace(2)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_workgroup_seq_cst
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_workgroup_seq_cst
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("workgroup") seq_cst 4 from `i32 addrspace(2)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_agent_unordered
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_agent_unordered
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("agent") unordered 4 from `i32 addrspace(2)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_agent_monotonic
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_agent_monotonic
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("agent") monotonic 4 from `i32 addrspace(2)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_agent_acquire
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_agent_acquire
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("agent") acquire 4 from `i32 addrspace(2)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_agent_seq_cst
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_agent_seq_cst
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("agent") seq_cst 4 from `i32 addrspace(2)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_system_unordered
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_system_unordered
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load unordered 4 from `i32 addrspace(2)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_system_monotonic
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_system_monotonic
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load monotonic 4 from `i32 addrspace(2)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_system_acquire
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_system_acquire
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load acquire 4 from `i32 addrspace(2)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: load_system_seq_cst
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_READ_B32
 # GCN-NOT:   S_WAITCNT
 # GCN:       FLAT_STORE_DWORD
 
 name:            load_system_seq_cst
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load seq_cst 4 from `i32 addrspace(2)* undef`)
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_singlethread_unordered
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_singlethread_unordered
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread") unordered 4 into `i32 addrspace(2)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_singlethread_monotonic
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_singlethread_monotonic
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread") monotonic 4 into `i32 addrspace(2)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_singlethread_release
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_singlethread_release
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread") release 4 into `i32 addrspace(2)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_singlethread_seq_cst
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_singlethread_seq_cst
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread") seq_cst 4 into `i32 addrspace(2)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_wavefront_unordered
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_wavefront_unordered
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("wavefront") unordered 4 into `i32 addrspace(2)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_wavefront_monotonic
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_wavefront_monotonic
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("wavefront") monotonic 4 into `i32 addrspace(2)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_wavefront_release
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_wavefront_release
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("wavefront") release 4 into `i32 addrspace(2)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_wavefront_seq_cst
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_wavefront_seq_cst
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("wavefront") seq_cst 4 into `i32 addrspace(2)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_workgroup_unordered
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_workgroup_unordered
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("workgroup") unordered 4 into `i32 addrspace(2)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_workgroup_monotonic
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_workgroup_monotonic
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("workgroup") monotonic 4 into `i32 addrspace(2)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_workgroup_release
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_workgroup_release
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("workgroup") release 4 into `i32 addrspace(2)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_workgroup_seq_cst
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_workgroup_seq_cst
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("workgroup") seq_cst 4 into `i32 addrspace(2)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_agent_unordered
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_agent_unordered
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("agent") unordered 4 into `i32 addrspace(2)* undef`)
-    S_ENDPGM
-
+    S_ENDPGM 0
 ...
 ---
 
 # GCN-LABEL: name: store_agent_monotonic
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_agent_monotonic
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("agent") monotonic 4 into `i32 addrspace(2)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_agent_release
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_agent_release
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("agent") release 4 into `i32 addrspace(2)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_agent_seq_cst
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_agent_seq_cst
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("agent") seq_cst 4 into `i32 addrspace(2)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_system_unordered
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_system_unordered
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store unordered 4 into `i32 addrspace(2)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_system_monotonic
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_system_monotonic
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store monotonic 4 into `i32 addrspace(2)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_system_release
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_system_release
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store release 4 into `i32 addrspace(2)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: store_system_seq_cst
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRITE_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            store_system_seq_cst
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store seq_cst 4 into `i32 addrspace(2)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: atomicrmw_singlethread_unordered
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRXCHG_RTN_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            atomicrmw_singlethread_unordered
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     $vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread") unordered 4 into `i32 addrspace(2)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: atomicrmw_singlethread_monotonic
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRXCHG_RTN_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            atomicrmw_singlethread_monotonic
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     $vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread") monotonic 4 into `i32 addrspace(2)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: atomicrmw_singlethread_acquire
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRXCHG_RTN_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            atomicrmw_singlethread_acquire
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     $vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread") acquire 4 into `i32 addrspace(2)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: atomicrmw_singlethread_release
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRXCHG_RTN_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            atomicrmw_singlethread_release
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     $vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread") release 4 into `i32 addrspace(2)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: atomicrmw_singlethread_acq_rel
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRXCHG_RTN_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            atomicrmw_singlethread_acq_rel
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     $vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread") acq_rel 4 into `i32 addrspace(2)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # GCN-LABEL: name: atomicrmw_singlethread_seq_cst
 
 # GCN-LABEL: bb.0:
 # GCN-NOT:   S_WAITCNT
 # GCN:       DS_WRXCHG_RTN_B32
 # GCN-NOT:   S_WAITCNT
-# GCN:       S_ENDPGM
+# GCN:       S_ENDPGM 0
 
 name:            atomicrmw_singlethread_seq_cst
 body:             |
   bb.0:
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
     $m0 = S_MOV_B32 -1
     $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     $vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread") seq_cst 4 into `i32 addrspace(2)* undef`)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...

test/CodeGen/AMDGPU/memory_clause.mir

 ...
 
 # GCN-LABEL: {{^}}name: atomic{{$}}
 # GCN:      %1:vgpr_32 = IMPLICIT_DEF
 # GCN-NEXT: dead %2:vgpr_32 = FLAT_ATOMIC_ADD_RTN %0, %1, 0, 0, implicit $exec, implicit $flat_scr
 # GCN-NEXT: dead %3:vgpr_32 = FLAT_ATOMIC_ADD_RTN %0, %1, 0, 0, implicit $exec, implicit $flat_scr
 # GCN-NEXT: FLAT_ATOMIC_ADD %0, %1, 0, 0, implicit $exec, implicit $flat_scr
 # GCN-NEXT: FLAT_ATOMIC_ADD %0, %1, 0, 0, implicit $exec, implicit $flat_scr
-# GCN-NEXT: S_ENDPGM
+# GCN-NEXT: S_ENDPGM 0
 
 ---
 name:            atomic
 tracksRegLiveness: true
 registers:
   - { id: 0, class: vreg_64 }
   - { id: 1, class: vgpr_32 }
   - { id: 2, class: vgpr_32 }
   - { id: 3, class: vgpr_32 }
 body:             |
   bb.0:
     %0 = IMPLICIT_DEF
     %1 = IMPLICIT_DEF
     %2:vgpr_32 = FLAT_ATOMIC_ADD_RTN %0, %1, 0, 0, implicit $exec, implicit $flat_scr
     %3:vgpr_32 = FLAT_ATOMIC_ADD_RTN %0, %1, 0, 0, implicit $exec, implicit $flat_scr
     FLAT_ATOMIC_ADD %0, %1, 0, 0, implicit $exec, implicit $flat_scr
     FLAT_ATOMIC_ADD %0, %1, 0, 0, implicit $exec, implicit $flat_scr
-    S_ENDPGM
+    S_ENDPGM 0
 ...

test/CodeGen/AMDGPU/merge-load-store-physreg.mir

bb.0:
 
     $m0 = S_MOV_B32 -1
     %2:vgpr_32 = DS_READ_B32 %1, 0, 0, implicit $m0, implicit $exec :: (load 4 from %ir.ptr.0)
 
     %11:sgpr_32 = S_ADD_U32 %10, 4, implicit-def $scc
     %12:sgpr_32 = S_ADDC_U32 %10, 0, implicit-def dead $scc, implicit $scc
 
     %3:vgpr_32 = DS_READ_B32 %1, 64, 0, implicit $m0, implicit $exec :: (load 4 from %ir.ptr.64)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 
 # CHECK-LABEL: name: scc_def_and_use_dependency
 # CHECK: DS_READ2_B32
 # CHECK: S_ADD_U32
 # CHECK: S_ADDC_U32
 ---
bb.0:
     %2:vgpr_32 = DS_READ_B32 %1, 0, 0, implicit $m0, implicit $exec :: (load 4 from %ir.ptr.0)
     %20:sgpr_32 = V_READFIRSTLANE_B32 %2, implicit $exec
 
     %21:sgpr_32 = S_ADD_U32 %20, 4, implicit-def $scc
     ; The S_ADDC_U32 depends on the first DS_READ_B32 only via SCC
     %11:sgpr_32 = S_ADDC_U32 %10, 0, implicit-def dead $scc, implicit $scc
 
     %3:vgpr_32 = DS_READ_B32 %1, 64, 0, implicit $m0, implicit $exec :: (load 4 from %ir.ptr.64)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...

test/CodeGen/AMDGPU/merge-load-store-vreg.mir

 ---
 name:            ds_combine_base_offset
 body:             |
   bb.0:
     %0:vgpr_32 = IMPLICIT_DEF
     S_BRANCH %bb.2
 
   bb.1:
-    S_ENDPGM
+    S_ENDPGM 0
 
   bb.2:
     %1:sreg_64_xexec = V_CMP_NE_U32_e64 %0, 0, implicit $exec
     %2:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %1, implicit $exec
     V_CMP_NE_U32_e32 1, %2, implicit-def $vcc, implicit $exec
     DS_WRITE_B32 %0, %0, 1024, 0, implicit $m0, implicit $exec :: (store 4 into %ir.tmp)
     %3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
     DS_WRITE_B32 %0, %3, 1056, 0, implicit $m0, implicit $exec :: (store 4 into %ir.tmp1)

 ---
 name:            ds_combine_base_offset_subreg
 body:             |
   bb.0:
     %0:vreg_64 = IMPLICIT_DEF
     S_BRANCH %bb.2
 
   bb.1:
-    S_ENDPGM
+    S_ENDPGM 0
 
   bb.2:
     %1:sreg_64_xexec = V_CMP_NE_U32_e64 %0.sub0, 0, implicit $exec
     %2:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %1, implicit $exec
     V_CMP_NE_U32_e32 1, %2, implicit-def $vcc, implicit $exec
     DS_WRITE_B32 %0.sub0, %0.sub0, 1024, 0, implicit $m0, implicit $exec :: (store 4 into %ir.tmp)
     undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
     DS_WRITE_B32 %0.sub0, %3.sub0, 1056, 0, implicit $m0, implicit $exec :: (store 4 into %ir.tmp1)

 ---
 name:            ds_combine_subreg
 body:             |
   bb.0:
     %0:vreg_64 = IMPLICIT_DEF
     S_BRANCH %bb.2
 
   bb.1:
-    S_ENDPGM
+    S_ENDPGM 0
 
   bb.2:
     %1:sreg_64_xexec = V_CMP_NE_U32_e64 %0.sub0, 0, implicit $exec
     %2:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %1, implicit $exec
     V_CMP_NE_U32_e32 1, %2, implicit-def $vcc, implicit $exec
     DS_WRITE_B32 %0.sub0, %0.sub0, 0, 0, implicit $m0, implicit $exec :: (store 4 into %ir.tmp)
     undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
     DS_WRITE_B32 %0.sub0, %3.sub0, 32, 0, implicit $m0, implicit $exec :: (store 4 into %ir.tmp1)
     %4:vgpr_32 = DS_READ_B32 %3.sub0, 0, 0, implicit $m0, implicit $exec :: (load 4 from %ir.tmp2)
     %5:vgpr_32 = DS_READ_B32 %3.sub0, 32, 0, implicit $m0, implicit $exec :: (load 4 from %ir.tmp3)
     $vcc = S_AND_B64 $exec, $vcc, implicit-def $scc
     S_CBRANCH_VCCNZ %bb.1, implicit $vcc
     S_BRANCH %bb.1
 ...

test/CodeGen/AMDGPU/merge-load-store.mir

bb.0:
 
     ; Make this load unmergeable, to tempt SILoadStoreOptimizer into merging the
     ; other two loads.
     %6:vreg_64 = DS_READ2_B32 %1, 16, 17, 0, implicit $m0, implicit $exec :: (load 8 from %ir.ptr.64, align 4)
     %3:vgpr_32 = COPY %6.sub0
     %4:vgpr_32 = DS_READ_B32 %1, 4, 0, implicit $m0, implicit $exec :: (load 4 from %ir.ptr.4)
     %5:vgpr_32 = V_ADD_I32_e32 killed %3, killed %4, implicit-def $vcc, implicit $exec
     DS_WRITE_B32 killed %1, %5, 0, 0, implicit killed $m0, implicit $exec :: (store 4 into %ir.ptr.0)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 # Make sure the asm def isn't moved after the point where it's used for
 # the address.
 # CHECK-LABEL: name: asm_defines_address
 # CHECK: DS_READ2ST64_B32
 # CHECK: DS_READ2ST64_B32

test/CodeGen/AMDGPU/misched-killflags.mir

BUNDLE implicit-def $sgpr6_sgpr7, implicit-def $sgpr6, implicit-def $sgpr7, implicit-def $scc {
       $sgpr7 = S_ADDC_U32 internal $sgpr7,0, implicit-def $scc, implicit internal $scc
     }
     $sgpr4 = S_MOV_B32 $sgpr33
     $vgpr0 = V_MOV_B32_e32 $sgpr8, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $sgpr8_sgpr9_sgpr10_sgpr11
     $vgpr1 = V_MOV_B32_e32 $sgpr9, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11
     $vgpr2 = V_MOV_B32_e32 $sgpr10, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11
     $vgpr3 = V_MOV_B32_e32 $sgpr11, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11, implicit $exec
     S_NOP 0, implicit killed $sgpr6_sgpr7, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 # CHECK-LABEL: name: func0
 # CHECK-DAG: $sgpr10 = S_MOV_B32 5
 # CHECK-DAG: $sgpr9 = S_MOV_B32 4
 # CHECK-DAG: $sgpr8 = S_MOV_B32 3
 # CHECK-DAG: $sgpr33 = S_MOV_B32 killed $sgpr7
 # CHECK: $vgpr0 = V_MOV_B32_e32 $sgpr8, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $sgpr8_sgpr9_sgpr10_sgpr11
 # CHECK: $sgpr32 = S_MOV_B32 $sgpr33
 # CHECK: BUNDLE implicit-def $sgpr6_sgpr7, implicit-def $sgpr6, implicit-def $sgpr7, implicit-def $scc {
 # CHECK:   $sgpr6_sgpr7 = S_GETPC_B64
 # CHECK:   $sgpr6 = S_ADD_U32 internal $sgpr6, 0, implicit-def $scc
 # CHECK:   $sgpr7 = S_ADDC_U32 internal $sgpr7, 0, implicit-def $scc, implicit internal $scc
 # CHECK: }
 # CHECK: $sgpr4 = S_MOV_B32 killed $sgpr33
 # CHECK: $vgpr1 = V_MOV_B32_e32 $sgpr9, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11
 # CHECK: $vgpr2 = V_MOV_B32_e32 $sgpr10, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11
 # CHECK: $vgpr3 = V_MOV_B32_e32 killed $sgpr11, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11, implicit $exec
 # CHECK: S_NOP 0, implicit killed $sgpr6_sgpr7, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3
-# CHECK: S_ENDPGM
+# CHECK: S_ENDPGM 0

test/CodeGen/AMDGPU/mode-register.mir

bb.0:
     $m0 = S_MOV_B32 killed $sgpr2
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     $vgpr1 = V_INTERP_P1LL_F16 0, $vgpr0, 2, 1, 0, 0, 0, implicit $m0, implicit $exec
     $vgpr2 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $exec
     $vgpr0 = V_INTERP_P1LL_F16 0, killed $vgpr0, 2, 1, -1, 0, 0, implicit $m0, implicit $exec
     $vgpr1 = V_INTERP_P2_F16 0, $vgpr2, 2, 1, 0, killed $vgpr1, 0, 0, implicit $m0, implicit $exec
     $vgpr0 = V_INTERP_P2_F16 0, killed $vgpr2, 2, 1, 0, killed $vgpr0, -1, 0, implicit $m0, implicit $exec
     $vgpr0 = V_ADD_F16_e32 killed $vgpr1, killed $vgpr0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # check that the mode is not changed for interp f16 when the mode is already RTZ
 # CHECK-LABEL: name: interp_f16_explicit_rtz
 # CHECK-LABEL: bb.0:
 # CHECK: S_SETREG_IMM32_B32 3, 2177
 # CHECK-NEXT: V_MOV_B32_e32
 # CHECK: S_SETREG_IMM32_B32 0, 2177
bb.0:
     S_SETREG_IMM32_B32 3, 2177
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     $vgpr1 = V_INTERP_P1LL_F16 0, $vgpr0, 2, 1, 0, 0, 0, implicit $m0, implicit $exec
     $vgpr2 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $exec
     $vgpr0 = V_INTERP_P1LL_F16 0, killed $vgpr0, 2, 1, -1, 0, 0, implicit $m0, implicit $exec
     $vgpr1 = V_INTERP_P2_F16 0, $vgpr2, 2, 1, 0, killed $vgpr1, 0, 0, implicit $m0, implicit $exec
     $vgpr0 = V_INTERP_P2_F16 0, killed $vgpr2, 2, 1, 0, killed $vgpr0, -1, 0, implicit $m0, implicit $exec
     $vgpr0 = V_ADD_F16_e32 killed $vgpr1, killed $vgpr0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # check that explicit RTN mode change is registered
 # CHECK-LABEL: name: explicit_rtn
 # CHECK-LABEL: bb.0:
 # CHECK: S_SETREG_IMM32_B32 3, 2177
 # CHECK-NEXT: V_INTERP_P1LL_F16
 # CHECK: S_SETREG_IMM32_B32 0, 2177
bb.0:
     $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     $vgpr1 = V_INTERP_P1LL_F16 0, $vgpr0, 2, 1, 0, 0, 0, implicit $m0, implicit $exec
     $vgpr2 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $exec
     $vgpr0 = V_INTERP_P1LL_F16 0, killed $vgpr0, 2, 1, -1, 0, 0, implicit $m0, implicit $exec
     $vgpr1 = V_INTERP_P2_F16 0, $vgpr2, 2, 1, 0, killed $vgpr1, 0, 0, implicit $m0, implicit $exec
     $vgpr0 = V_INTERP_P2_F16 0, killed $vgpr2, 2, 1, 0, killed $vgpr0, -1, 0, implicit $m0, implicit $exec
     S_SETREG_IMM32_B32 0, 2177
     $vgpr0 = V_ADD_F16_e32 killed $vgpr1, killed $vgpr0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # check that the mode is unchanged from RTN for F64 instruction
 # CHECK-LABEL: name: rtn_default
 # CHECK-LABEL: bb.0:
 # CHECK-NOT: S_SETREG_IMM32_B32
 # CHECK: V_FRACT_F64
 
 name: rtn_default
 
 body: |
   bb.0:
     liveins: $vgpr1_vgpr2
     $vgpr1_vgpr2 = V_FRACT_F64_e32 killed $vgpr1_vgpr2, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # check that the mode is changed from RTZ to RTN for F64 instruction
 # CHECK-LABEL: name: rtn_from_rtz
 # CHECK-LABEL: bb.0:
 # CHECK: S_SETREG_IMM32_B32 3, 2177
 # CHECK-NEXT: S_SETREG_IMM32_B32 0, 2177
 # CHECK-NEXT: V_FRACT_F64
 # CHECK-NOT: S_SETREG_IMM32_B32
 
 name: rtn_from_rtz
 
 body: |
   bb.0:
     liveins: $vgpr1_vgpr2
     S_SETREG_IMM32_B32 3, 2177
     $vgpr1_vgpr2 = V_FRACT_F64_e32 killed $vgpr1_vgpr2, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # CHECK-LABEL: name: rtz_from_rtn
 # CHECK-LABEL: bb.1:
 # CHECK: S_SETREG_IMM32_B32 3, 2177
 # CHECK-NOT: S_SETREG_IMM32_B32
 
 name: rtz_from_rtn
 
 body: |
   bb.0:
     successors: %bb.1
     liveins: $vgpr1_vgpr2
     $vgpr1_vgpr2 = V_FRACT_F64_e32 killed $vgpr1_vgpr2, implicit $exec
     S_BRANCH %bb.1
 
   bb.1:
     $vgpr1 = V_INTERP_P1LL_F16 0, $vgpr0, 2, 1, 0, 0, 0, implicit $m0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # check that the mode is changed from RTZ to RTN for F64 instruction
 # and back again for remaining interp instruction
 # CHECK-LABEL: name: interp_f16_plus_sqrt_f64
 # CHECK-LABEL: bb.0:
 # CHECK: S_SETREG_IMM32_B32 3, 2177
 # CHECK: V_INTERP_P1LL_F16
bb.0:
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit $exec
     $vgpr1 = V_INTERP_P1LL_F16 0, $vgpr0, 2, 1, 0, 0, 0, implicit $m0, implicit $exec
     $vgpr2 = V_MOV_B32_e32 $sgpr1, implicit $exec, implicit $exec
     $vgpr0 = V_INTERP_P1LL_F16 0, killed $vgpr0, 2, 1, -1, 0, 0, implicit $m0, implicit $exec
     $vgpr1 = V_INTERP_P2_F16 0, $vgpr2, 2, 1, 0, killed $vgpr1, 0, 0, implicit $m0, implicit $exec
     $vgpr3_vgpr4 = V_FRACT_F64_e32 killed $vgpr3_vgpr4, implicit $exec
     $vgpr0 = V_INTERP_P2_F16 0, killed $vgpr2, 2, 1, 0, killed $vgpr0, -1, 0, implicit $m0, implicit $exec
     $vgpr0 = V_ADD_F16_e32 killed $sgpr0, killed $vgpr0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # check that an explicit change to the single precision mode has no effect
 # CHECK-LABEL: name: single_precision_mode_change
 # CHECK-LABEL: bb.0:
 # CHECK: S_SETREG_IMM32_B32 3, 2177
 # CHECK: V_INTERP_P1LL_F16
 # CHECK: V_INTERP_P1LL_F16
bb.0:
     $vgpr1 = V_INTERP_P1LL_F16 0, $vgpr0, 2, 1, 0, 0, 0, implicit $m0, implicit $exec
     S_SETREG_IMM32_B32 2, 2049
     $vgpr2 = V_MOV_B32_e32 $sgpr1, implicit $exec, implicit $exec
     $vgpr0 = V_INTERP_P1LL_F16 0, killed $vgpr0, 2, 1, -1, 0, 0, implicit $m0, implicit $exec
     $vgpr1 = V_INTERP_P2_F16 0, $vgpr2, 2, 1, 0, killed $vgpr1, 0, 0, implicit $m0, implicit $exec
     $vgpr3_vgpr4 = V_FRACT_F64_e32 killed $vgpr3_vgpr4, implicit $exec
     $vgpr0 = V_INTERP_P2_F16 0, killed $vgpr2, 2, 1, 0, killed $vgpr0, -1, 0, implicit $m0, implicit $exec
     $vgpr0 = V_ADD_F16_e32 killed $sgpr0, killed $vgpr0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # check that mode is propagated back to start of loop - first instruction is RTN but needs
 # setreg as RTZ is set in loop
 # CHECK-LABEL: name: loop
 # CHECK-LABEL: bb.1:
 # CHECK: S_SETREG_IMM32_B32 0, 2177
 # CHECK: V_FRACT_F64
body: |
   bb.2:
     successors: %bb.1, %bb.3
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit $exec
     $vgpr1 = V_INTERP_P1LL_F16 0, $vgpr0, 2, 1, 0, 0, 0, implicit $m0, implicit $exec
     S_CBRANCH_VCCZ %bb.1, implicit $vcc
     S_BRANCH %bb.3
 
   bb.3:
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # two back-edges to same node with different modes
 # CHECK-LABEL: name: double_loop
 # CHECK-NOT: S_SETREG_IMM32_B32
 # CHECK-LABEL: bb.2:
 # CHECK: S_SETREG_IMM32_B32 0, 2177
 # CHECK: V_FRACT_F64_e32
body: |
 
   bb.5:
     successors: %bb.1, %bb.6
     S_SETREG_IMM32_B32 3, 2177
     S_CBRANCH_VCCZ %bb.1, implicit $vcc
     S_BRANCH %bb.6
 
   bb.6:
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # check that mode is propagated back to start of loop and through a block that
 # neither sets or uses the mode.
 # CHECK-LABEL: name: loop_indirect
 # CHECK_NOT: S_SETREG_IMM32_B32
 # CHECK-LABEL: bb.3:
 # CHECK: S_SETREG_IMM32_B32 3, 2177
body: |
   bb.3:
     successors: %bb.1, %bb.4
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit $exec
     $vgpr1 = V_INTERP_P1LL_F16 0, $vgpr0, 2, 1, 0, 0, 0, implicit $m0, implicit $exec
     S_CBRANCH_VCCZ %bb.1, implicit $vcc
     S_BRANCH %bb.4
 
   bb.4:
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # check that multiple mode values are propagated to a block that uses the mode
 # CHECK-LABEL: name: multiple_mode_direct
 # CHECK-LABEL: bb.3:
 # CHECK: S_SETREG_IMM32_B32 0, 2177
 # CHECK: V_FRACT_F64_e32
 # CHECK-NOT: S_SETREG_IMM32_B32
bb.2:
     S_BRANCH %bb.3
 
   bb.3:
     successors: %bb.4
     $vgpr3_vgpr4 = V_FRACT_F64_e32 killed $vgpr3_vgpr4, implicit $exec
     S_BRANCH %bb.4
 
   bb.4:
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # check that multiple mode values are propagated through a block that neither
 # sets or uses the mode.
 # CHECK-LABEL: name: multiple_mode_indirect
 # CHECK-LABEL: bb.4:
 # CHECK: S_SETREG_IMM32_B32 0, 2177
 # CHECK: V_FRACT_F64_e32
bb.3:
     S_BRANCH %bb.4
 
   bb.4:
     successors: %bb.5
     $vgpr3_vgpr4 = V_FRACT_F64_e32 killed $vgpr3_vgpr4, implicit $exec
     S_BRANCH %bb.5
 
   bb.5:
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # CHECK-LABEL: name: pass_through_blocks
 # CHECK-LABEL: bb.0:
 # CHECK: V_FRACT_F64_e32
 # CHECK-NEXT: S_SETREG_IMM32_B32 3, 2177
 # CHECK-NOT: S_SETREG_IMM32_B32
 
bb.2:
     S_BRANCH %bb.3
 
   bb.3:
     successors: %bb.4
     S_BRANCH %bb.4
 
   bb.4:
     $vgpr1 = V_INTERP_P1LL_F16 0, $vgpr0, 2, 1, 0, 0, 0, implicit $m0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # check that multiple mode values are propagated
 # CHECK-LABEL: name: if_then_else
 # CHECK-LABEL: bb.3:
 # CHECK: S_SETREG_IMM32_B32 0, 2177
 # CHECK: V_FRACT_F64_e32
 # CHECK-NOT: S_SETREG_IMM32_B32
bb.2:
     S_BRANCH %bb.3
 
   bb.3:
     successors: %bb.4
     $vgpr3_vgpr4 = V_FRACT_F64_e32 killed $vgpr3_vgpr4, implicit $exec
     S_BRANCH %bb.4
 
   bb.4:
-    S_ENDPGM
+    S_ENDPGM 0
 ...

test/CodeGen/AMDGPU/movrels-bug.mir

 body:             |
   bb.0:
     $m0 = S_MOV_B32 undef $sgpr0
     V_MOVRELD_B32_e32 undef $vgpr2, 0, implicit $m0, implicit $exec, implicit-def $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8, implicit undef $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8(tied-def 4)
     $m0 = S_MOV_B32 undef $sgpr0
     $vgpr1 = V_MOVRELS_B32_e32 undef $vgpr1, implicit $m0, implicit $exec, implicit killed $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8
     $vgpr4 = V_MAC_F32_e32 undef $vgpr0, undef $vgpr0, undef $vgpr4, implicit $exec
     EXP_DONE 15, undef $vgpr0, killed $vgpr1, killed $vgpr4, undef $vgpr0, 0, 0, 12, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...

test/CodeGen/AMDGPU/omod-nsz-flag.mir

 ...
 
 ---
 
 # FIXME: Is it OK to fold omod for this?
 # GCN-LABEL: name: omod_inst_flag_nsz_src
 # GCN: %0:vgpr_32 = nsz V_ADD_F32_e64 0, $vgpr0, 0, $vgpr1, 0, 0, implicit $exec
 # GCN-NEXT: %1:vgpr_32 = V_MUL_F32_e64 0, %0, 0, 1073741824, 0, 0, implicit $exec
-# GCN-NEXT: S_ENDPGM implicit %1
+# GCN-NEXT: S_ENDPGM 0, implicit %1
 name: omod_inst_flag_nsz_src
 tracksRegLiveness: true
 
 body:             |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
   %0:vgpr_32 = nsz V_ADD_F32_e64 0, $vgpr0, 0, $vgpr1, 0, 0, implicit $exec
   %1:vgpr_32 = V_MUL_F32_e64 0, %0, 0, 1073741824, 0, 0, implicit $exec
-  S_ENDPGM implicit %1
+  S_ENDPGM 0, implicit %1
 
 ...
 ---
 
 # GCN-LABEL: name: omod_inst_flag_nsz_result
 # GCN: %0:vgpr_32 = V_ADD_F32_e64 0, $vgpr0, 0, $vgpr1, 0, 1, implicit $exec
-# GCN-NEXT: S_ENDPGM implicit %0
+# GCN-NEXT: S_ENDPGM 0, implicit %0
 
 name: omod_inst_flag_nsz_result
 tracksRegLiveness: true
 
 body:             |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
   %0:vgpr_32 = V_ADD_F32_e64 0, $vgpr0, 0, $vgpr1, 0, 0, implicit $exec
   %1:vgpr_32 = nsz V_MUL_F32_e64 0, %0, 0, 1073741824, 0, 0, implicit $exec
-  S_ENDPGM implicit %1
+  S_ENDPGM 0, implicit %1
 ...
 
 ---
 
 # GCN-LABEL: name: omod_inst_flag_nsz_both
 # GCN: %0:vgpr_32 = nsz V_ADD_F32_e64 0, $vgpr0, 0, $vgpr1, 0, 1, implicit $exec
-# GCN-NEXT: S_ENDPGM implicit %0
+# GCN-NEXT: S_ENDPGM 0, implicit %0
 
 name: omod_inst_flag_nsz_both
 tracksRegLiveness: true
 
 body:             |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
   %0:vgpr_32 = nsz V_ADD_F32_e64 0, $vgpr0, 0, $vgpr1, 0, 0, implicit $exec
   %1:vgpr_32 = nsz V_MUL_F32_e64 0, %0, 0, 1073741824, 0, 0, implicit $exec
-  S_ENDPGM implicit %1
+  S_ENDPGM 0, implicit %1
 ...

test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir

bb.1.bb1:
     %27 = REG_SEQUENCE killed %26, %subreg.sub0, killed %25, %subreg.sub1
     %28 = REG_SEQUENCE %6, 17, killed %27, 18
     %29 = V_MOV_B32_e32 0, implicit $exec
     %30 = COPY %24
     BUFFER_STORE_DWORD_ADDR64 killed %29, killed %30, killed %28, 0, 0, 0, 0, 0, implicit $exec
 
   bb.2.bb2:
     SI_END_CF %1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 name:            const_to_sgpr_multiple_use
 alignment:       0
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
bb.1.bb1:
     %36 = REG_SEQUENCE killed %35, %subreg.sub0, killed %34, %subreg.sub1
     %37 = REG_SEQUENCE %6, 17, killed %36, 18
     %38 = V_MOV_B32_e32 0, implicit $exec
     %39 = COPY %33
     BUFFER_STORE_DWORD_ADDR64 killed %38, killed %39, killed %37, 0, 0, 0, 0, 0, implicit $exec
 
   bb.2.bb2:
     SI_END_CF %1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 name:            const_to_sgpr_subreg
 alignment:       0
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
bb.1.bb1:
     %27 = REG_SEQUENCE killed %26, %subreg.sub0, killed %25, %subreg.sub1
     %28 = REG_SEQUENCE %6, 17, killed %27, 18
     %29 = V_MOV_B32_e32 0, implicit $exec
     %30 = COPY %24
     BUFFER_STORE_DWORD_ADDR64 killed %29, killed %30, killed %28, 0, 0, 0, 0, 0, implicit $exec
 
   bb.2.bb2:
     SI_END_CF %1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...

test/CodeGen/AMDGPU/optimize-if-exec-masking.mir

body:             |
 
   bb.2.end:
     liveins: $vgpr0, $sgpr0_sgpr1
 
     $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
     $sgpr3 = S_MOV_B32 61440
     $sgpr2 = S_MOV_B32 -1
     BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 # CHECK-LABEL: name: optimize_if_and_saveexec{{$}}
 # CHECK: $sgpr0_sgpr1 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
 # CHECK-NEXT: SI_MASK_BRANCH
 
 name:            optimize_if_and_saveexec
body:             |
 
   bb.2.end:
     liveins: $vgpr0, $sgpr0_sgpr1
 
     $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
     $sgpr3 = S_MOV_B32 61440
     $sgpr2 = S_MOV_B32 -1
     BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 # CHECK-LABEL: name: optimize_if_or_saveexec{{$}}
 # CHECK: $sgpr0_sgpr1 = S_OR_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
 # CHECK-NEXT: SI_MASK_BRANCH
 
 name:            optimize_if_or_saveexec
body:             |
 
   bb.2.end:
     liveins: $vgpr0, $sgpr0_sgpr1
 
     $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
     $sgpr3 = S_MOV_B32 61440
     $sgpr2 = S_MOV_B32 -1
     BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 # CHECK-LABEL: name: optimize_if_and_saveexec_xor_valu_middle
 # CHECK: $sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc
 # CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr0, undef $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec
 # CHECK-NEXT: $sgpr0_sgpr1 = S_XOR_B64 $sgpr2_sgpr3, killed $sgpr0_sgpr1, implicit-def $scc
 # CHECK-NEXT: $exec = COPY killed $sgpr2_sgpr3
body:             |
 
   bb.2.end:
     liveins: $vgpr0, $sgpr0_sgpr1
 
     $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
     $sgpr3 = S_MOV_B32 61440
     $sgpr2 = S_MOV_B32 -1
     BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 # CHECK-LABEL: name: optimize_if_and_saveexec_xor_wrong_reg{{$}}
 # CHECK: $sgpr0_sgpr1 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc
 # CHECK-NEXT: $sgpr0_sgpr1 = S_XOR_B64 undef $sgpr2_sgpr3, killed $sgpr0_sgpr1, implicit-def $scc
 # CHECK-NEXT: $exec = COPY $sgpr0_sgpr1
 # CHECK-NEXT: SI_MASK_BRANCH %bb.2, implicit $exec
body:             |
 
   bb.2.end:
     liveins: $vgpr0, $sgpr0_sgpr1, $sgpr4_sgpr5_sgpr6_sgpr7
 
     $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
     $sgpr3 = S_MOV_B32 61440
     $sgpr2 = S_MOV_B32 -1
     BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 # CHECK-LABEL: name: optimize_if_and_saveexec_xor_modify_copy_to_exec{{$}}
 # CHECK: $sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc
 # CHECK-NEXT: $sgpr2_sgpr3 = S_OR_B64 killed $sgpr2_sgpr3, 1, implicit-def $scc
 # CHECK-NEXT: $sgpr0_sgpr1 = S_XOR_B64 $sgpr2_sgpr3, killed $sgpr0_sgpr1, implicit-def $scc
 # CHECK-NEXT: $exec = COPY killed $sgpr2_sgpr3
bb.2.end:
     liveins: $vgpr0, $sgpr0_sgpr1
 
     $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
     $sgpr0 = S_MOV_B32 0
     $sgpr1 = S_MOV_B32 1
     $sgpr2 = S_MOV_B32 -1
     $sgpr3 = S_MOV_B32 61440
     BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 # CHECK-LABEL: name: optimize_if_and_saveexec_xor_live_out_setexec{{$}}
 # CHECK: $sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc
 # CHECK-NEXT: $sgpr0_sgpr1 = S_XOR_B64 $sgpr2_sgpr3, killed $sgpr0_sgpr1, implicit-def $scc
 # CHECK-NEXT: $exec = COPY $sgpr2_sgpr3
 # CHECK-NEXT: SI_MASK_BRANCH
body:             |
 
   bb.2.end:
     liveins: $vgpr0, $sgpr0_sgpr1
 
     $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
     $sgpr3 = S_MOV_B32 61440
     $sgpr2 = S_MOV_B32 -1
     BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 
 # CHECK-LABEL: name: optimize_if_unknown_saveexec{{$}}
 # CHECK: $sgpr0_sgpr1 = COPY $exec
 # CHECK: $sgpr2_sgpr3 = S_LSHR_B64 $sgpr0_sgpr1, killed $vcc_lo, implicit-def $scc
 # CHECK-NEXT: $exec = COPY killed $sgpr2_sgpr3
 # CHECK-NEXT: SI_MASK_BRANCH %bb.2, implicit $exec
body:             |
 
   bb.2.end:
     liveins: $vgpr0, $sgpr0_sgpr1
 
     $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
     $sgpr3 = S_MOV_B32 61440
     $sgpr2 = S_MOV_B32 -1
     BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 # CHECK-LABEL: name: optimize_if_andn2_saveexec{{$}}
 # CHECK: $sgpr0_sgpr1 = S_ANDN2_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
 # CHECK-NEXT: SI_MASK_BRANCH
 
 name:            optimize_if_andn2_saveexec
body:             |
 
   bb.2.end:
     liveins: $vgpr0, $sgpr0_sgpr1
 
     $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
     $sgpr3 = S_MOV_B32 61440
     $sgpr2 = S_MOV_B32 -1
     BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 # CHECK-LABEL: name: optimize_if_andn2_saveexec_no_commute{{$}}
 # CHECK: $sgpr2_sgpr3 = S_ANDN2_B64 killed $vcc, $sgpr0_sgpr1, implicit-def $scc
 # CHECK-NEXT: $exec = COPY killed $sgpr2_sgpr3
 # CHECK-NEXT: SI_MASK_BRANCH %bb.2, implicit $exec
 name:            optimize_if_andn2_saveexec_no_commute
body:             |
 
   bb.2.end:
     liveins: $vgpr0, $sgpr0_sgpr1
 
     $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
     $sgpr3 = S_MOV_B32 61440
     $sgpr2 = S_MOV_B32 -1
     BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 # A read from exec copy subreg prevents optimization
 # CHECK-LABEL: name: if_and_xor_read_exec_copy_subreg{{$}}
 # CHECK: $sgpr0_sgpr1 = COPY $exec
 # CHECK-NEXT: $sgpr4 = S_MOV_B32 $sgpr1
 name:            if_and_xor_read_exec_copy_subreg
body:             |
 
   bb.2.end:
     liveins: $vgpr0, $sgpr0_sgpr1
 
     $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
     $sgpr3 = S_MOV_B32 61440
     $sgpr2 = S_MOV_B32 -1
     BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 ...

test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir

bb.0:
     $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
     S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
     S_BRANCH %bb.1
 
   bb.1:
     S_BRANCH %bb.0
 
   bb.2:
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 # GCN: name: negated_cond_vop3
 # GCN:      %0:sreg_64_xexec = IMPLICIT_DEF
 # GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def $scc
 # GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
 ---
 name:            negated_cond_vop3
 body:             |
   bb.0:
     %0:sreg_64_xexec = IMPLICIT_DEF
     %1:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
     %2:sreg_64_xexec = V_CMP_NE_U32_e64 %1, 1, implicit $exec
     $vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc
     S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
     S_BRANCH %bb.1
 
   bb.1:
     S_BRANCH %bb.0
 
   bb.2:
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 # GCN: name: negated_cond_vop2_redef_vcc1
 # GCN:      %0:sreg_64_xexec = IMPLICIT_DEF
 # GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
 # GCN-NEXT: V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
 # GCN-NEXT: $vcc_lo = COPY $sgpr0
 # GCN-NEXT: $vcc = S_AND_B64 $exec, $vcc, implicit-def dead $scc
bb.0:
     $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
     S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
     S_BRANCH %bb.1
 
   bb.1:
     S_BRANCH %bb.0
 
   bb.2:
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 # GCN: name: negated_cond_vop2_redef_vcc2
 # GCN:      %0:sreg_64_xexec = IMPLICIT_DEF
 # GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
 # GCN-NEXT: V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
 # GCN-NEXT: $vcc_hi = COPY $sgpr0
 # GCN-NEXT: $vcc = S_AND_B64 $exec, $vcc, implicit-def dead $scc
bb.0:
     $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
     S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
     S_BRANCH %bb.1
 
   bb.1:
     S_BRANCH %bb.0
 
   bb.2:
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 # GCN: name: negated_cond_vop3_redef_cmp
 # GCN:      %0:sreg_64_xexec = IMPLICIT_DEF
 # GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
 # GCN-NEXT: %2:sreg_64_xexec = V_CMP_NE_U32_e64 %1, 1, implicit $exec
 # GCN-NEXT: %2.sub1:sreg_64_xexec = COPY $sgpr0
 # GCN-NEXT: $vcc = S_AND_B64 %2, $exec, implicit-def dead $scc
bb.0:
     $vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc
     S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
     S_BRANCH %bb.1
 
   bb.1:
     S_BRANCH %bb.0
 
   bb.2:
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 # GCN: name: negated_cond_undef_vcc
 # GCN:      $vcc = S_AND_B64 $exec, undef $vcc, implicit-def dead $scc
 # GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
 ---
 name:            negated_cond_undef_vcc
 body:             |
   bb.0:
     $vcc = S_AND_B64 $exec, undef $vcc, implicit-def dead $scc
     S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
     S_BRANCH %bb.1
 
   bb.1:
     S_BRANCH %bb.0
 
   bb.2:
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 # GCN: name: negated_cond_vop3_imp_vcc
 # GCN:      $vcc = IMPLICIT_DEF
 # GCN-NEXT: $vcc = S_ANDN2_B64 $exec, $vcc, implicit-def $scc
 # GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
 ---
 name:            negated_cond_vop3_imp_vcc
 body:             |
   bb.0:
     $vcc = IMPLICIT_DEF
     %1:vgpr_32 = V_CNDMASK_B32_e64 0, 1, $vcc, implicit $exec
     %2:sreg_64_xexec = V_CMP_NE_U32_e64 %1, 1, implicit $exec
     $vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc
     S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
     S_BRANCH %bb.1
 
   bb.1:
     S_BRANCH %bb.0
 
   bb.2:
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 # GCN: name: negated_cond_vop2_imp_vcc
 # GCN:      $vcc = IMPLICIT_DEF
 # GCN-NEXT: $vcc = S_ANDN2_B64 $exec, $vcc, implicit-def $scc
 # GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
 ---
 name:            negated_cond_vop2_imp_vcc
 body:             |
   bb.0:
     $vcc = IMPLICIT_DEF
     %1:vgpr_32 = V_CNDMASK_B32_e64 0, 1, $vcc, implicit $exec
     V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
     $vcc = S_AND_B64 killed $vcc, $exec, implicit-def dead $scc
     S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
     S_BRANCH %bb.1
 
   bb.1:
     S_BRANCH %bb.0
 
   bb.2:
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 # GCN: name: negated_cond_vop3_redef_sel
 # GCN:      %0:sreg_64_xexec = IMPLICIT_DEF
 # GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
 # GCN-NEXT: %1:vgpr_32 = COPY $vgpr0
 # GCN-NEXT: %2:sreg_64_xexec = V_CMP_NE_U32_e64 %1, 1, implicit $exec
 # GCN-NEXT: $vcc = S_AND_B64 %2, $exec, implicit-def dead $scc
bb.0:
     $vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc
     S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
     S_BRANCH %bb.1
 
   bb.1:
     S_BRANCH %bb.0
 
   bb.2:
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 # GCN: name: negated_cond_vop2_used_sel
 # GCN:      %0:sreg_64_xexec = IMPLICIT_DEF
 # GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
 # GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def $scc
 # GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
 ---
 name:            negated_cond_vop2_used_sel
 body:             |
   bb.0:
     %0:sreg_64_xexec = IMPLICIT_DEF
     %1:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
     V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
     $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
     S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
     S_BRANCH %bb.1
 
   bb.1:
     S_BRANCH %bb.0
 
   bb.2:
     $vgpr0 = COPY %1
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 # GCN: name: negated_cond_vop2_used_vcc
 # GCN:      %0:sreg_64_xexec = IMPLICIT_DEF
 # GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
 # GCN-NEXT: V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
 # GCN-NEXT: $sgpr0_sgpr1 = COPY $vcc
 # GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def $scc
bb.0:
     $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
     S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
     S_BRANCH %bb.1
 
   bb.1:
     S_BRANCH %bb.0
 
   bb.2:
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 # GCN: name: negated_cond_vop3_sel_wrong_subreg1
 # GCN:      %0:sreg_64_xexec = IMPLICIT_DEF
 # GCN-NEXT: %1.sub1:vreg_64 = IMPLICIT_DEF
 # GCN-NEXT: %1.sub0:vreg_64 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
 # GCN-NEXT: %2:sreg_64_xexec = V_CMP_NE_U32_e64 %1.sub1, 1, implicit $exec
 # GCN-NEXT: $vcc = S_AND_B64 %2, $exec, implicit-def dead $scc
bb.0:
     $vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc
     S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
     S_BRANCH %bb.1
 
   bb.1:
     S_BRANCH %bb.0
 
   bb.2:
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 # GCN: name: negated_cond_vop3_sel_wrong_subreg2
 # GCN:      %0:sreg_64_xexec = IMPLICIT_DEF
 # GCN-NEXT: %1.sub0:vreg_64 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
 # GCN-NEXT: %1.sub1:vreg_64 = IMPLICIT_DEF
 # GCN-NEXT: %2:sreg_64_xexec = V_CMP_NE_U32_e64 %1.sub1, 1, implicit $exec
 # GCN-NEXT: $vcc = S_AND_B64 %2, $exec, implicit-def dead $scc
bb.0:
     $vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc
     S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
     S_BRANCH %bb.1
 
   bb.1:
     S_BRANCH %bb.0
 
   bb.2:
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 # GCN: name: negated_cond_vop3_sel_right_subreg1
 # GCN:      %0:sreg_64_xexec = IMPLICIT_DEF
 # GCN-NEXT: %1.sub1:vreg_64 = IMPLICIT_DEF
 # GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def $scc
 # GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
 ---
 name:            negated_cond_vop3_sel_right_subreg1
 body:             |
   bb.0:
     %0:sreg_64_xexec = IMPLICIT_DEF
     %1.sub1 = IMPLICIT_DEF
     %1.sub0:vreg_64 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
     %2:sreg_64_xexec = V_CMP_NE_U32_e64 %1.sub0, 1, implicit $exec
     $vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc
     S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
     S_BRANCH %bb.1
 
   bb.1:
     S_BRANCH %bb.0
 
   bb.2:
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 # GCN: name: negated_cond_vop3_sel_right_subreg2
 # GCN:      %0:sreg_64_xexec = IMPLICIT_DEF
 # GCN-NEXT: %1.sub1:vreg_64 = IMPLICIT_DEF
 # GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def $scc
 # GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
 ---
 name:            negated_cond_vop3_sel_right_subreg2
 body:             |
   bb.0:
     %0:sreg_64_xexec = IMPLICIT_DEF
     %1.sub0:vreg_64 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
     %1.sub1 = IMPLICIT_DEF
     %2:sreg_64_xexec = V_CMP_NE_U32_e64 %1.sub0, 1, implicit $exec
     $vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc
     S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
     S_BRANCH %bb.1
 
   bb.1:
     S_BRANCH %bb.0
 
   bb.2:
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 # GCN: name: negated_cond_vop3_sel_subreg_overlap
 # GCN:      %0:sreg_64_xexec = IMPLICIT_DEF
 # GCN-NEXT: %1.sub2:vreg_128 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
 # GCN-NEXT: %1.sub2_sub3:vreg_128 = IMPLICIT_DEF
 # GCN-NEXT: %2:sreg_64_xexec = V_CMP_NE_U32_e64 %1.sub2, 1, implicit $exec
 # GCN-NEXT: $vcc = S_AND_B64 %2, $exec, implicit-def dead $scc
bb.0:
     $vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc
     S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
     S_BRANCH %bb.1
 
   bb.1:
     S_BRANCH %bb.0
 
   bb.2:
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 # GCN: name: negated_cond_vop2_dominated_blocks
 # GCN:      %0:sreg_64_xexec = IMPLICIT_DEF
 # GCN:      $vcc = S_ANDN2_B64 $exec, %0, implicit-def $scc
 # GCN-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit $vcc
 ---
 name:            negated_cond_vop2_dominated_blocks
 body:             |
   bb.0:
     %0:sreg_64_xexec = IMPLICIT_DEF
     %1:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
 
   bb.1:
     V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
     $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
     S_CBRANCH_VCCNZ %bb.3, implicit killed $vcc
     S_BRANCH %bb.2
 
   bb.2:
     S_BRANCH %bb.1
 
   bb.3:
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 # GCN: name: negated_cond_vop2_different_blocks_cmp_and
 # GCN:      %1:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
 # GCN:      $vcc = S_AND_B64 $exec, %2, implicit-def dead $scc
 # GCN-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit $vcc
 ---
 name:            negated_cond_vop2_different_blocks_cmp_and
 body:             |
   bb.0:
     %0:sreg_64_xexec = IMPLICIT_DEF
     %1:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
     %2:sreg_64_xexec = V_CMP_NE_U32_e64 %1, 1, implicit $exec
 
   bb.1:
     $vcc = S_AND_B64 $exec, killed %2, implicit-def dead $scc
     S_CBRANCH_VCCNZ %bb.3, implicit killed $vcc
     S_BRANCH %bb.2
 
   bb.2:
     S_BRANCH %bb.1
 
   bb.3:
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 # GCN: name: negated_cond_vop2_not_dominated_blocks
 # GCN:      V_CNDMASK_B32_e64 0, 1,
 # GCN:      $vcc = S_AND_B64 $exec, $vcc, implicit-def dead $scc
 # GCN-NEXT: S_CBRANCH_VCCNZ %bb.4, implicit $vcc
 ---
 name:            negated_cond_vop2_not_dominated_blocks
bb.2:
     $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
     S_CBRANCH_VCCNZ %bb.4, implicit killed $vcc
     S_BRANCH %bb.3
 
   bb.3:
     S_BRANCH %bb.2
 
   bb.4:
-    S_ENDPGM
+    S_ENDPGM 0
 ...

test/CodeGen/AMDGPU/reduce-saveexec.mir

 # RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-optimize-exec-masking %s -o - | FileCheck -check-prefix=GCN %s
 
 ---
 # GCN-LABEL: name: reduce_and_saveexec
 # GCN:      $exec = S_AND_B64 $exec, killed $vcc
-# GCN-NEXT: S_ENDPGM
+# GCN-NEXT: S_ENDPGM 0
 name: reduce_and_saveexec
 tracksRegLiveness: true
 body:             |
   bb.0:
     $vcc = IMPLICIT_DEF
     $sgpr0_sgpr1 = S_AND_B64 $exec, killed $vcc, implicit-def $scc
     $exec = COPY killed $sgpr0_sgpr1
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: reduce_and_saveexec_commuted
 # GCN:      $exec = S_AND_B64 killed $vcc, $exec
-# GCN-NEXT: S_ENDPGM
+# GCN-NEXT: S_ENDPGM 0
 name: reduce_and_saveexec_commuted
 tracksRegLiveness: true
 body:             |
   bb.0:
     $vcc = IMPLICIT_DEF
     $sgpr0_sgpr1 = S_AND_B64 killed $vcc, $exec, implicit-def $scc
     $exec = COPY killed $sgpr0_sgpr1
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: reduce_and_saveexec_liveout
 # GCN:      $sgpr0_sgpr1 = S_AND_B64 $exec, killed $vcc
 # GCN-NEXT: $exec = COPY
 name: reduce_and_saveexec_liveout
 tracksRegLiveness: true
 body:             |
   bb.0:
     $vcc = IMPLICIT_DEF
     $sgpr0_sgpr1 = S_AND_B64 $exec, killed $vcc, implicit-def $scc
     $exec = COPY $sgpr0_sgpr1
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: and_saveexec
 # GCN:      $sgpr0_sgpr1 = S_AND_SAVEEXEC_B64 $vcc
-# GCN-NEXT: S_ENDPGM
+# GCN-NEXT: S_ENDPGM 0
 name: and_saveexec
 tracksRegLiveness: true
 body:             |
   bb.0:
     $vcc = IMPLICIT_DEF
     $sgpr0_sgpr1 = COPY $exec
     $sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc
     $exec = S_MOV_B64_term $sgpr2_sgpr3
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: reduce_or_saveexec
 # GCN:      $exec = S_OR_B64 $exec, killed $vcc
-# GCN-NEXT: S_ENDPGM
+# GCN-NEXT: S_ENDPGM 0
 name: reduce_or_saveexec
 tracksRegLiveness: true
 body:             |
   bb.0:
     $vcc = IMPLICIT_DEF
     $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
     $exec = COPY killed $sgpr0_sgpr1
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: reduce_xor_saveexec
 # GCN:      $exec = S_XOR_B64 $exec, killed $vcc
-# GCN-NEXT: S_ENDPGM
+# GCN-NEXT: S_ENDPGM 0
 name: reduce_xor_saveexec
 tracksRegLiveness: true
 body:             |
   bb.0:
     $vcc = IMPLICIT_DEF
     $sgpr0_sgpr1 = S_XOR_B64 $exec, killed $vcc, implicit-def $scc
     $exec = COPY killed $sgpr0_sgpr1
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: reduce_andn2_saveexec
 # GCN:      $exec = S_ANDN2_B64 $exec, killed $vcc
-# GCN-NEXT: S_ENDPGM
+# GCN-NEXT: S_ENDPGM 0
 name: reduce_andn2_saveexec
 tracksRegLiveness: true
 body:             |
   bb.0:
     $vcc = IMPLICIT_DEF
     $sgpr0_sgpr1 = S_ANDN2_B64 $exec, killed $vcc, implicit-def $scc
     $exec = COPY killed $sgpr0_sgpr1
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: reduce_orn2_saveexec
 # GCN:      $exec = S_ORN2_B64 $exec, killed $vcc
-# GCN-NEXT: S_ENDPGM
+# GCN-NEXT: S_ENDPGM 0
 name: reduce_orn2_saveexec
 tracksRegLiveness: true
 body:             |
   bb.0:
     $vcc = IMPLICIT_DEF
     $sgpr0_sgpr1 = S_ORN2_B64 $exec, killed $vcc, implicit-def $scc
     $exec = COPY killed $sgpr0_sgpr1
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: reduce_nand_saveexec
 # GCN:      $exec = S_NAND_B64 $exec, killed $vcc
-# GCN-NEXT: S_ENDPGM
+# GCN-NEXT: S_ENDPGM 0
 name: reduce_nand_saveexec
 tracksRegLiveness: true
 body:             |
   bb.0:
     $vcc = IMPLICIT_DEF
     $sgpr0_sgpr1 = S_NAND_B64 $exec, killed $vcc, implicit-def $scc
     $exec = COPY killed $sgpr0_sgpr1
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: reduce_nor_saveexec
 # GCN:      $exec = S_NOR_B64 $exec, killed $vcc
-# GCN-NEXT: S_ENDPGM
+# GCN-NEXT: S_ENDPGM 0
 name: reduce_nor_saveexec
 tracksRegLiveness: true
 body:             |
   bb.0:
     $vcc = IMPLICIT_DEF
     $sgpr0_sgpr1 = S_NOR_B64 $exec, killed $vcc, implicit-def $scc
     $exec = COPY killed $sgpr0_sgpr1
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: reduce_xnor_saveexec
 # GCN:      $exec = S_XNOR_B64 $exec, killed $vcc
-# GCN-NEXT: S_ENDPGM
+# GCN-NEXT: S_ENDPGM 0
 name: reduce_xnor_saveexec
 tracksRegLiveness: true
 body:             |
   bb.0:
     $vcc = IMPLICIT_DEF
     $sgpr0_sgpr1 = S_XNOR_B64 $exec, killed $vcc, implicit-def $scc
     $exec = COPY killed $sgpr0_sgpr1
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---

test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir

bb.32:
     S_CBRANCH_SCC1 %bb.34, implicit undef $scc
     S_BRANCH %bb.33
 
   bb.33:
 
   bb.34:
 
   bb.35:
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...

test/CodeGen/AMDGPU/regcoal-subrange-join.mir

bb.3:
     S_CMP_LT_I32 %8, %40, implicit-def $scc
     %60 = COPY killed %8
     %61 = COPY killed %57
     S_CBRANCH_SCC1 %bb.3, implicit killed $scc
     S_BRANCH %bb.4
 
   bb.4:
     EXP 32, undef %53, undef %54, killed %46, undef %55, 0, 0, 15, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...

test/CodeGen/AMDGPU/regcoalesce-cannot-join-failures.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-coalescing -run-pass=simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck %s
 
 ---
 name: couldnt_join_subrange_implicit_def_pred_block
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: couldnt_join_subrange_implicit_def_pred_block
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x80000000)
   ; CHECK:   undef %0.sub0:sreg_64_xexec = IMPLICIT_DEF
   ; CHECK: bb.1:
   ; CHECK:   successors: %bb.2(0x80000000)
   ; CHECK:   %0.sub1:sreg_64_xexec = COPY %0.sub0
   ; CHECK:   S_BRANCH %bb.2
   ; CHECK: bb.2:
-  ; CHECK:   S_ENDPGM implicit %0
+  ; CHECK:   S_ENDPGM 0, implicit %0
   bb.0:
     successors: %bb.1
 
     undef %0.sub0:sreg_64_xexec = IMPLICIT_DEF
 
   bb.1:
     successors: %bb.2
 
     %1:sreg_64 = COPY %0:sreg_64_xexec
     %0.sub1:sreg_64_xexec = COPY %0.sub0:sreg_64_xexec
     S_BRANCH %bb.2
 
   bb.2:
     dead %2:sreg_32_xm0 = COPY %0.sub0:sreg_64_xexec
-    S_ENDPGM implicit killed %1
+    S_ENDPGM 0, implicit killed %1
 
 ...
 ---
 name: couldnt_join_subrange_no_implicit_def_inst
 tracksRegLiveness: true
 body:             |
   bb.0:
     ; CHECK-LABEL: name: couldnt_join_subrange_no_implicit_def_inst
     ; CHECK: undef %0.sub0:sreg_64 = S_MOV_B32 0
     ; CHECK: %0.sub1:sreg_64 = COPY %0.sub0
-    ; CHECK: S_ENDPGM implicit %0.sub1
+    ; CHECK: S_ENDPGM 0, implicit %0.sub1
     undef %0.sub0:sreg_64 = S_MOV_B32 0
     %1:sreg_64 = COPY %0:sreg_64
     %0.sub1:sreg_64 = COPY %0.sub0:sreg_64
-    S_ENDPGM implicit %1.sub1:sreg_64
+    S_ENDPGM 0, implicit %1.sub1:sreg_64
 
 ...
 ---
 name: couldnt_join_subrange0
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: couldnt_join_subrange0
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x80000000)
   ; CHECK:   undef %0.sub1:sreg_64 = S_MOV_B32 -1
   ; CHECK: bb.1:
   ; CHECK:   %0.sub0:sreg_64 = S_MOV_B32 0
   ; CHECK:   [[COPY:%[0-9]+]]:sreg_64 = COPY %0
   ; CHECK:   dead %0.sub1:sreg_64 = COPY %0.sub0
-  ; CHECK:   S_ENDPGM implicit [[COPY]].sub1
+  ; CHECK:   S_ENDPGM 0, implicit [[COPY]].sub1
   bb.0:
     successors: %bb.1
     undef %0.sub1:sreg_64 = S_MOV_B32 -1
 
   bb.1:
     %0.sub0:sreg_64 = S_MOV_B32 0
     %1:sreg_64 = COPY %0:sreg_64
     dead %0.sub1:sreg_64 = COPY %0.sub0:sreg_64
-    S_ENDPGM implicit %1.sub1:sreg_64
+    S_ENDPGM 0, implicit %1.sub1:sreg_64
 
 ...
 ---
 name: lanes_not_tracked_subreg_join_couldnt_join_subrange
 tracksRegLiveness: true
 body:             |
   bb.0:
 
     ; CHECK-LABEL: name: lanes_not_tracked_subreg_join_couldnt_join_subrange
     ; CHECK: undef %0.sub0:sreg_64_xexec = S_MOV_B32 0
     ; CHECK: %0.sub1:sreg_64_xexec = S_MOV_B32 0
     ; CHECK: S_NOP 0, implicit %0.sub1
     ; CHECK: S_NOP 0, implicit %0
-    ; CHECK: S_ENDPGM
+    ; CHECK: S_ENDPGM 0
     undef %0.sub0:sreg_64_xexec = S_MOV_B32 0
     %1:sreg_64 = COPY %0
     %0.sub1:sreg_64_xexec = S_MOV_B32 0
     S_NOP 0, implicit %0.sub1
     S_NOP 0, implicit %1
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 name: couldnt_join_subrange1
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: couldnt_join_subrange1
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x80000000)
   ; CHECK:   undef %0.sub0:sreg_64_xexec = S_MOV_B32 0
   ; CHECK:   %0.sub1:sreg_64_xexec = COPY %0.sub0
   ; CHECK: bb.1:
   ; CHECK:   S_NOP 0, implicit %0.sub1
-  ; CHECK:   S_ENDPGM implicit %0
+  ; CHECK:   S_ENDPGM 0, implicit %0
   bb.0:
     successors: %bb.1
 
     undef %0.sub0:sreg_64_xexec = S_MOV_B32 0
     %1:sreg_64 = COPY %0
     %0.sub1:sreg_64_xexec = COPY %0.sub0
 
   bb.1:
 
     S_NOP 0, implicit %0.sub1
-    S_ENDPGM implicit %1
+    S_ENDPGM 0, implicit %1
 
 ...

test/CodeGen/AMDGPU/regcoalesce-dbg.mir

bb.0:
     DBG_VALUE debug-use %11, debug-use $noreg, !1, !8, debug-location !9
     undef %12.sub0 = COPY killed %11
     %12.sub1 = COPY killed %10
     undef %13.sub0_sub1 = COPY killed %4
     %13.sub2_sub3 = COPY killed %12
     %20 = V_LSHL_B64 killed %19, 2, implicit $exec
     %16 = COPY killed %5
     BUFFER_STORE_DWORD_ADDR64 killed %16, killed %20, killed %13, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.out)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...

test/CodeGen/AMDGPU/regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir

body:             |
   ; CHECK-LABEL: name: lost_valid_lanes_maybe_erasable_implicit_def
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x80000000)
   ; CHECK:   undef %0.sub1:sreg_64 = IMPLICIT_DEF
   ; CHECK: bb.1:
   ; CHECK:   %0.sub0:sreg_64 = S_MOV_B32 0
   ; CHECK:   [[COPY:%[0-9]+]]:sreg_64 = COPY %0
   ; CHECK:   dead %0.sub1:sreg_64 = COPY %0.sub0
-  ; CHECK:   S_ENDPGM implicit [[COPY]].sub1
+  ; CHECK:   S_ENDPGM 0, implicit [[COPY]].sub1
   bb.0:
     successors: %bb.1
     undef %0.sub1:sreg_64 = IMPLICIT_DEF
 
   bb.1:
     %0.sub0:sreg_64 = S_MOV_B32 0
     %1:sreg_64 = COPY %0:sreg_64
     dead %0.sub1:sreg_64 = COPY %0.sub0:sreg_64
-    S_ENDPGM implicit %1.sub1:sreg_64
+    S_ENDPGM 0, implicit %1.sub1:sreg_64
 
 ...
 ---
 # Same as previous, except with a real value instead of
 # IMPLICIT_DEF. These should both be handled the same way.
 
 name:  lost_valid_lanes_real_value
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: lost_valid_lanes_real_value
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x80000000)
   ; CHECK:   undef %0.sub1:sreg_64 = S_MOV_B32 -1
   ; CHECK: bb.1:
   ; CHECK:   %0.sub0:sreg_64 = S_MOV_B32 0
   ; CHECK:   [[COPY:%[0-9]+]]:sreg_64 = COPY %0
   ; CHECK:   dead %0.sub1:sreg_64 = COPY %0.sub0
-  ; CHECK:   S_ENDPGM implicit [[COPY]].sub1
+  ; CHECK:   S_ENDPGM 0, implicit [[COPY]].sub1
   bb.0:
     successors: %bb.1
     undef %0.sub1:sreg_64 = S_MOV_B32 -1
 
   bb.1:
     %0.sub0:sreg_64 = S_MOV_B32 0
     %1:sreg_64 = COPY %0:sreg_64
     dead %0.sub1:sreg_64 = COPY %0.sub0:sreg_64
-    S_ENDPGM implicit %1.sub1:sreg_64
+    S_ENDPGM 0, implicit %1.sub1:sreg_64
 
 ...

test/CodeGen/AMDGPU/regcoalesce-prune.mir

bb.1:
     %5 : vreg_64 = IMPLICIT_DEF
     %6 : vreg_64 = COPY killed %4
 
   bb.2:
     %2 : vgpr_32 = V_CVT_F32_I32_e32 killed %5.sub1, implicit $exec
 
   bb.3:
     %3 : vgpr_32 = V_CVT_F32_I32_e32 killed %6.sub1, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 ...

test/CodeGen/AMDGPU/regcoalescing-remove-partial-redundancy-assert.mir

body:             |
   
   bb.32:
     dead %130:vreg_128 = IMPLICIT_DEF
     dead %128:vreg_128 = COPY undef %130
     %139:vreg_128 = IMPLICIT_DEF
     S_BRANCH %bb.29
   
   bb.33:
-    S_ENDPGM
+    S_ENDPGM 0
   
   bb.34:
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...

test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir

body:             |
   bb.3:
     %1 = COPY killed %17
     FLAT_STORE_DWORD undef %10, %1.sub2, 0, 0, 0, implicit $exec, implicit $flat_scr
     %14 = COPY %1.sub1
     %16 = COPY killed %1.sub0
     undef %15.sub0 = COPY killed %16
     %15.sub1 = COPY killed %14
     FLAT_STORE_DWORDX2 undef %11, killed %15, 0, 0, 0, implicit $exec, implicit $flat_scr
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 # Make sure others uses after the mac are properly handled and not
 # left unreplaced due to iterator issues from substituteRegister.
 
 # GCN-LABEL: name: vreg_does_not_dominate
 

test/CodeGen/AMDGPU/scalar-store-cache-flush.mir

--- |
   }
 
 ...
 ---
 # CHECK-LABEL: name: basic_insert_dcache_wb
 # CHECK: bb.0:
 # CHECK-NEXT: S_STORE_DWORD
 # CHECK-NEXT: S_DCACHE_WB
-# CHECK-NEXT: S_ENDPGM
+# CHECK-NEXT: S_ENDPGM 0
 
 name: basic_insert_dcache_wb
 tracksRegLiveness: false
 
 body: |
   bb.0:
     S_STORE_DWORD_SGPR undef $sgpr2, undef $sgpr0_sgpr1, undef $m0, 0
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # Already has an explicitly requested flush after the last store.
 # CHECK-LABEL: name: explicit_flush_after
 # CHECK: bb.0:
 # CHECK-NEXT: S_STORE_DWORD
 # CHECK-NEXT: S_DCACHE_WB
-# CHECK-NEXT: S_ENDPGM
+# CHECK-NEXT: S_ENDPGM 0
 
 name: explicit_flush_after
 tracksRegLiveness: false
 
 body: |
   bb.0:
     S_STORE_DWORD_SGPR undef $sgpr2, undef $sgpr0_sgpr1, undef $m0, 0
     S_DCACHE_WB
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # Already has an explicitly requested flush before the last store.
 # CHECK-LABEL: name: explicit_flush_before
 # CHECK: bb.0:
 # CHECK-NEXT: S_DCACHE_WB
 # CHECK-NEXT: S_STORE_DWORD
 # CHECK-NEXT: S_DCACHE_WB
-# CHECK-NEXT: S_ENDPGM
+# CHECK-NEXT: S_ENDPGM 0
 
 name: explicit_flush_before
 tracksRegLiveness: false
 
 body: |
   bb.0:
     S_DCACHE_WB
     S_STORE_DWORD_SGPR undef $sgpr2, undef $sgpr0_sgpr1, undef $m0, 0
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # CHECK-LABEL: no_scalar_store
 # CHECK: bb.0
-# CHECK-NEXT: S_ENDPGM
+# CHECK-NEXT: S_ENDPGM 0
 name: no_scalar_store
 tracksRegLiveness: false
 
 body: |
   bb.0:
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 # CHECK-LABEL: name: multi_block_store
 # CHECK: bb.0:
 # CHECK-NEXT: S_STORE_DWORD
 # CHECK-NEXT: S_DCACHE_WB
-# CHECK-NEXT: S_ENDPGM
+# CHECK-NEXT: S_ENDPGM 0
 
 # CHECK: bb.1:
 # CHECK-NEXT: S_STORE_DWORD
 # CHECK-NEXT: S_DCACHE_WB
-# CHECK-NEXT: S_ENDPGM
+# CHECK-NEXT: S_ENDPGM 0
 
 name: multi_block_store
 tracksRegLiveness: false
 
 body: |
   bb.0:
     S_STORE_DWORD_SGPR undef $sgpr2, undef $sgpr0_sgpr1, undef $m0, 0
-    S_ENDPGM
+    S_ENDPGM 0
 
   bb.1:
     S_STORE_DWORD_SGPR undef $sgpr4, undef $sgpr6_sgpr7, undef $m0, 0
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ...
 
 # This one should be able to omit the flush in the storeless block but
 # this isn't handled now.
 
 # CHECK-LABEL: name: one_block_store
 # CHECK: bb.0:
 # CHECK-NEXT: S_DCACHE_WB
-# CHECK-NEXT: S_ENDPGM
+# CHECK-NEXT: S_ENDPGM 0
 
 # CHECK: bb.1:
 # CHECK-NEXT: S_STORE_DWORD
 # CHECK-NEXT: S_DCACHE_WB
-# CHECK-NEXT: S_ENDPGM
+# CHECK-NEXT: S_ENDPGM 0
 
 name: one_block_store
 tracksRegLiveness: false
 
 body: |
   bb.0:
-    S_ENDPGM
+    S_ENDPGM 0
 
   bb.1:
     S_STORE_DWORD_SGPR undef $sgpr4, undef $sgpr6_sgpr7, undef $m0, 0
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # CHECK-LABEL: name: si_return
 # CHECK: bb.0:
 # CHECK-NEXT: S_STORE_DWORD
 # CHECK-NEXT: S_WAITCNT
 # CHECK-NEXT: S_DCACHE_WB
 # CHECK-NEXT: SI_RETURN

test/CodeGen/AMDGPU/sched-crash-dbg-value.mir

bb.0.bb:
     %127:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @func + 4, target-flags(amdgpu-rel32-hi) @func + 4, implicit-def dead $scc
     $sgpr4 = COPY $sgpr101
     $vgpr0 = COPY %124
     $vgpr1_vgpr2 = IMPLICIT_DEF
     $vgpr3 = COPY %126
     dead $sgpr30_sgpr31 = SI_CALL %127, @func, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4, implicit $vgpr0, implicit $vgpr1_vgpr2, implicit killed $vgpr3
     ADJCALLSTACKDOWN 0, 0, implicit-def $sgpr32, implicit $sgpr32
     %128:vreg_64, dead %129:sreg_64 = V_MAD_I64_I32 %20, %34, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...

test/CodeGen/AMDGPU/schedule-regpressure.mir

bb.0:
     liveins: $sgpr4_sgpr5
 
     %1 = COPY $sgpr4_sgpr5
     %5 = S_LOAD_DWORD_IMM %1, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`)
     $m0 = S_MOV_B32 -1
     %7 = COPY %5
     %6 = DS_READ_B32 %7, 0, 0, implicit $m0, implicit $exec
     DS_WRITE_B32 %7, %6, 4, 0, implicit killed $m0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...

test/CodeGen/AMDGPU/sdwa-preserve.mir

bb.0:
     %3 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
     %4 = FLAT_LOAD_DWORD %1, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
 
     %9:vgpr_32 = V_LSHRREV_B16_e64 8, %3, implicit $exec
     %10:sreg_32_xm0 = S_MOV_B32 255
     %11:vgpr_32 = V_AND_B32_e64 %3, killed %10, implicit $exec
     %17:vgpr_32 = V_MOV_B32_sdwa 0, %4, 0, 5, 2, 4, implicit $exec, implicit %11(tied-def 0)
     FLAT_STORE_DWORD %0, %17, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 # SDWA-LABEL: sdwa_preserve_remove
 # SDWA: flat_load_dword [[FIRST:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]
 # SDWA: flat_load_dword [[SECOND:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]
 
 # SDWA: v_mov_b32_sdwa [[FIRST]], [[SECOND]] dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_0
bb.0:
     %3 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
     %4 = FLAT_LOAD_DWORD %1, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
 
     %9:vgpr_32 = V_LSHRREV_B16_e64 8, %3, implicit $exec
     %10:sreg_32_xm0 = S_MOV_B32 65535
     %11:vgpr_32 = V_AND_B32_e64 %3, killed %10, implicit $exec
     %17:vgpr_32 = V_MOV_B32_sdwa 0, %4, 0, 5, 2, 4, implicit $exec, implicit %11(tied-def 0)
     FLAT_STORE_DWORD %0, %17, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...

test/CodeGen/AMDGPU/sdwa-scalar-ops.mir

bb.0.bb:
     %4 = COPY $sgpr4_sgpr5
     %9 = S_LOAD_DWORDX2_IMM %4, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
     %8 = S_MOV_B64 0
     %7 = COPY %9
     %30 = V_MOV_B32_e32 1, implicit $exec
     S_BRANCH %bb.2.bb2
 
   bb.1.bb1:
-    S_ENDPGM
+    S_ENDPGM 0
 
   bb.2.bb2:
     successors: %bb.1.bb1(0x04000000), %bb.2.bb2(0x7c000000)
 
     %0 = PHI %8, %bb.0.bb, %1, %bb.2.bb2
     %13 = COPY %7.sub1
     %14 = S_ADD_U32 %7.sub0, %0.sub0, implicit-def $scc
     %15 = S_ADDC_U32 %7.sub1, %0.sub1, implicit-def dead $scc, implicit $scc
bb.0.bb:
     %9 = S_LOAD_DWORDX2_IMM %4, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
     %8 = S_MOV_B64 0
     %7 = COPY %9
     %30 = V_MOV_B32_e32 1, implicit $exec
     %84 = S_MOV_B32 2
     S_BRANCH %bb.2.bb2
 
   bb.1.bb1:
-    S_ENDPGM
+    S_ENDPGM 0
 
   bb.2.bb2:
     successors: %bb.1.bb1(0x04000000), %bb.2.bb2(0x7c000000)
 
     %0 = PHI %8, %bb.0.bb, %1, %bb.2.bb2
     %13 = COPY %7.sub1
     %14 = S_ADD_U32 %7.sub0, %0.sub0, implicit-def $scc
     %15 = S_ADDC_U32 %7.sub1, %0.sub1, implicit-def dead $scc, implicit $scc

test/CodeGen/AMDGPU/sendmsg-m0-hazard.mir

body: |
   ; GCN:  $m0 = S_MOV_B32 -1
   ; VI-NEXT: S_NOP 0
   ; GFX9-NEXT: S_NOP 0
   ; GCN-NEXT: S_SENDMSG 3, implicit $exec, implicit $m0
 
   bb.0:
     $m0 = S_MOV_B32 -1
     S_SENDMSG 3, implicit $exec, implicit $m0
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 
 name: m0_sendmsghalt
 body: |
   ; GCN-LABEL: name: m0_sendmsghalt
   ; GCN:  $m0 = S_MOV_B32 -1
   ; VI-NEXT: S_NOP 0
   ; GFX9-NEXT: S_NOP 0
   ; GCN-NEXT: S_SENDMSGHALT 3, implicit $exec, implicit $m0
 
   bb.0:
     $m0 = S_MOV_B32 -1
     S_SENDMSGHALT 3, implicit $exec, implicit $m0
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 
 name: m0_ttracedata
 body: |
   ; GCN-LABEL: name: m0_ttracedata
   ; GCN:  $m0 = S_MOV_B32 -1
   ; VI-NEXT: S_NOP 0
   ; GFX9-NEXT: S_NOP 0
   ; GCN-NEXT: S_TTRACEDATA implicit $m0
 
   bb.0:
     $m0 = S_MOV_B32 -1
     S_TTRACEDATA implicit $m0
-    S_ENDPGM
+    S_ENDPGM 0
 ...

test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir

bb.0:
     %13 = REG_SEQUENCE killed %5, 17, %12, 18
     %28 = V_LSHL_B64 killed %27, 2, implicit $exec
     %16 = REG_SEQUENCE killed %4, 17, %12, 18
     %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit $exec
     %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit $exec
     %29, %9 = V_ADD_I32_e64 %19, %17, implicit $exec
     %24 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit $exec
     BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 # GCN-LABEL: name: shrink_sub_vop3{{$}}
 # GCN: %29:vgpr_32, %9:sreg_64_xexec = V_SUB_I32_e64 %19, %17, implicit $exec
 # GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit $exec
 
 name:            shrink_sub_vop3
bb.0:
     %13 = REG_SEQUENCE killed %5, 17, %12, 18
     %28 = V_LSHL_B64 killed %27, 2, implicit $exec
     %16 = REG_SEQUENCE killed %4, 17, %12, 18
     %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit $exec
     %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit $exec
     %29, %9 = V_SUB_I32_e64 %19, %17, implicit $exec
     %24 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit $exec
     BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 # GCN-LABEL: name: shrink_subrev_vop3{{$}}
 # GCN: %29:vgpr_32, %9:sreg_64_xexec = V_SUBREV_I32_e64 %19, %17, implicit $exec
 # GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit $exec
 
 name:            shrink_subrev_vop3
bb.0:
     %13 = REG_SEQUENCE killed %5, 17, %12, 18
     %28 = V_LSHL_B64 killed %27, 2, implicit $exec
     %16 = REG_SEQUENCE killed %4, 17, %12, 18
     %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit $exec
     %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit $exec
     %29, %9 = V_SUBREV_I32_e64 %19, %17, implicit $exec
     %24 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit $exec
     BUFFER_STORE_DWORD_ADDR64 %29, %28, killed %16, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 # GCN-LABEL: name: check_addc_src2_vop3{{$}}
 # GCN: %29:vgpr_32, $vcc = V_ADDC_U32_e64 %19, %17, %9, implicit $exec
 # GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 1, killed $vcc, implicit $exec
 name: check_addc_src2_vop3
 alignment:       0
bb.0:
     %28 = V_LSHL_B64 killed %27, 2, implicit $exec
     %16 = REG_SEQUENCE killed %4, 17, %12, 18
     %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit $exec
     %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit $exec
     %9 = S_MOV_B64 0
     %29, $vcc = V_ADDC_U32_e64 %19, %17, %9, implicit $exec
     %24 = V_CNDMASK_B32_e64 0, 1, killed $vcc, implicit $exec
     BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 # GCN-LABEL: name: shrink_addc_vop3{{$}}
 # GCN: %29:vgpr_32 = V_ADDC_U32_e32 %19, %17, implicit-def $vcc, implicit $vcc, implicit $exec
 # GCN %24 = V_CNDMASK_B32_e64 0, 1, killed $vcc, implicit $exec
 
 name:            shrink_addc_vop3
bb.0:
     %28 = V_LSHL_B64 killed %27, 2, implicit $exec
     %16 = REG_SEQUENCE killed %4, 17, %12, 18
     %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit $exec
     %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit $exec
     $vcc = S_MOV_B64 0
     %29, $vcc = V_ADDC_U32_e64 %19, %17, $vcc, implicit $exec
     %24 = V_CNDMASK_B32_e64 0, 1, killed $vcc, implicit $exec
     BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 
 ---
 # GCN-LABEL: name: shrink_addc_undef_vcc{{$}}
 # GCN: %29:vgpr_32 = V_ADDC_U32_e32 %19, %17, implicit-def $vcc, implicit undef $vcc, implicit $exec
 # GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 1, killed $vcc, implicit $exec
 name:            shrink_addc_undef_vcc
bb.0:
     %13 = REG_SEQUENCE killed %5, 17, %12, 18
     %28 = V_LSHL_B64 killed %27, 2, implicit $exec
     %16 = REG_SEQUENCE killed %4, 17, %12, 18
     %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit $exec
     %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit $exec
     %29, $vcc = V_ADDC_U32_e64 %19, %17, undef $vcc, implicit $exec
     %24 = V_CNDMASK_B32_e64 0, 1, killed $vcc, implicit $exec
     BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...

test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir

 
 ...
 
 ---
 
 # GCN-LABEL: name: dead_illegal_virtreg_copy
 # GCN: %0:vgpr_32 = COPY $vgpr0
 # GCN: %1:sreg_32_xm0 = IMPLICIT_DEF
-# GCN: S_ENDPGM implicit %0
+# GCN: S_ENDPGM 0, implicit %0
 
 name: dead_illegal_virtreg_copy
 tracksRegLiveness: true
 
 body: |
   bb.0:
     liveins: $vgpr0
     %0:vgpr_32 = COPY $vgpr0
     %1:sreg_32_xm0 = COPY %0
-    S_ENDPGM implicit %1
+    S_ENDPGM 0, implicit %1
 ...
 
 ---
 
 # GCN-LABEL: name: dead_illegal_physreg_copy
 # GCN %2:vgpr_32 = COPY $vgpr0
 # GCN: %1:sreg_32_xm0 = IMPLICIT_DEF
-# GCN: S_ENDPGM implicit %2
+# GCN: S_ENDPGM 0, implicit %2
 
 name: dead_illegal_physreg_copy
 tracksRegLiveness: true
 
 body: |
   bb.0:
     liveins: $vgpr0
     %0:sreg_32_xm0 = COPY $vgpr0
     %1:sreg_32_xm0 = COPY %0
-    S_ENDPGM implicit %1
+    S_ENDPGM 0, implicit %1
 ...

test/CodeGen/AMDGPU/si-lower-control-flow.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=si-lower-control-flow -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN %s
 
 # Check that assert is not triggered
 
 ...
 ---
 name: si-lower-control-flow
 body: |
   bb.0:
     ; GCN-LABEL: name: si-lower-control-flow
     ; GCN: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
     ; GCN: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]], 16, 0
     ; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[S_LOAD_DWORD_IMM]], 255, implicit-def $scc
     ; GCN: [[S_AND_B32_1:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 65535, [[S_AND_B32_]], implicit-def $scc
-    ; GCN: S_ENDPGM
+    ; GCN: S_ENDPGM 0
     %0:sgpr_64 = COPY $sgpr4_sgpr5
     %1:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0, 16, 0
     %2:sreg_32_xm0 = S_AND_B32 %1, 255, implicit-def $scc
     %3:sreg_32_xm0 = S_AND_B32 65535, %2, implicit-def $scc
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 ---
 name: preserve_undef_flag_si_if_src
 tracksRegLiveness: true
 body:             |
   ; GCN-LABEL: name: preserve_undef_flag_si_if_src
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; GCN:   [[COPY:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
   ; GCN:   [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], undef %1:sreg_64, implicit-def dead $scc
   ; GCN:   [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[S_AND_B64_]], [[COPY]], implicit-def dead $scc
   ; GCN:   $exec = S_MOV_B64_term killed [[S_AND_B64_]]
   ; GCN:   SI_MASK_BRANCH %bb.2, implicit $exec
   ; GCN:   S_BRANCH %bb.1
   ; GCN: bb.1:
   ; GCN:   successors: %bb.2(0x80000000)
   ; GCN: bb.2:
-  ; GCN:   S_ENDPGM
+  ; GCN:   S_ENDPGM 0
   bb.0:
     successors: %bb.1, %bb.2
 
     %1:sreg_64 = SI_IF undef %0:sreg_64, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
     S_BRANCH %bb.1
 
   bb.1:
     successors: %bb.2
 
   bb.2:
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...

test/CodeGen/AMDGPU/smem-no-clause-coalesced.mir

bb.0:
     %7.sub0:sreg_64_xexec = COPY %1
     %3.sub1:sgpr_128 = S_AND_B32 %2, 65535, implicit-def dead $scc
     %3.sub3:sgpr_128 = S_MOV_B32 151468
     %3.sub2:sgpr_128 = S_MOV_B32 -1
     %7.sub0:sreg_64_xexec = S_LOAD_DWORD_IMM %7, 48, 0 :: (load 4 from `i8 addrspace(4)* undef`, addrspace 4)
     %8:sreg_64_xexec = S_BUFFER_LOAD_DWORDX2_IMM %3, 640, 0 :: (dereferenceable invariant load 8)
     undef %9.sub0:vreg_128 = V_LSHL_ADD_U32 %6, 4, %4, implicit $exec
     %9.sub1:vreg_128 = V_LSHL_ADD_U32 %5, 4, %0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 
 
 

test/CodeGen/AMDGPU/subreg-split-live-in-error.mir

bb.23:
     %63:vgpr_32 = V_MAC_F32_e32 %15.sub2, %62, %63, implicit $exec
     %4:vgpr_32 = V_ADD_F32_e32 %63, %67, implicit $exec
     S_BRANCH %bb.22
 
   bb.24:
     %68:vgpr_32 = V_MUL_F32_e32 0, %4, implicit $exec
     %69:vgpr_32 = V_CVT_PKRTZ_F16_F32_e64 0, undef %70:vgpr_32, 0, %68, 0, 0, implicit $exec
     EXP 0, undef %71:vgpr_32, %69, undef %72:vgpr_32, undef %73:vgpr_32, -1, -1, 15, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 ...

test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir

bb.2:
 
     $sgpr0_sgpr1 = SI_SPILL_S64_RESTORE %stack.0, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11, implicit $sgpr13, implicit-def dead $m0 :: (load 8 from %stack.0, align 4, addrspace 5)
     $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
 
   bb.3:
     liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr2_sgpr3, $sgpr4_sgpr5
 
     $vcc = COPY $vgpr1
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 
 # Move spill to after future save instruction
 # CHECK-LABEL: {{^}}name: undefined_physreg_sgpr_spill_reorder
 # CHECK: $sgpr0_sgpr1 = COPY $exec, implicit-def $exec
 # CHECK: $sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def dead $scc
bb.2:
 
     $sgpr0_sgpr1 = SI_SPILL_S64_RESTORE %stack.0, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11, implicit $sgpr13, implicit-def dead $m0 :: (load 8 from %stack.0, align 4, addrspace 5)
     $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
 
   bb.3:
     liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr2_sgpr3, $sgpr4_sgpr5
 
     $vcc = COPY $vgpr1
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...

test/CodeGen/AMDGPU/v_swap_b32.mir

 ---
 name:            swap_phys_clobber_y
 body:             |
   bb.0:
     $vgpr2 = V_MOV_B32_e32 $vgpr0, implicit $exec
     $vgpr0 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
     $vgpr1 = V_MOV_B32_e32 0, implicit $exec
     $vgpr1 = V_MOV_B32_e32 killed $vgpr2, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 # GCN-LABEL: name: swap_virt_copy_condense
 # GCN: %0:vgpr_32, %1:vgpr_32 = V_SWAP_B32 %1, %0, implicit $exec
 ---
 name:            swap_virt_copy_condense
 registers:
   - { id: 0, class: vgpr_32 }

 # GCN-LABEL: name: swap_virt_read_x
 # GCN: bb.0:
 # GCN-NEXT: %0:vgpr_32 = IMPLICIT_DEF
 # GCN-NEXT: %1:vgpr_32 = IMPLICIT_DEF
 # GCN-NEXT: %2:vgpr_32 = COPY %0
 # GCN-NEXT: %3:vgpr_32 = COPY %0
 # GCN-NEXT: %0:vgpr_32 = COPY %1
 # GCN-NEXT: %1:vgpr_32 = COPY %2
-# GCN-NEXT: S_ENDPGM
+# GCN-NEXT: S_ENDPGM 0
 
 ---
 name:            swap_virt_read_x
 registers:
   - { id: 0, class: vgpr_32 }
   - { id: 1, class: vgpr_32 }
   - { id: 2, class: vgpr_32 }
   - { id: 3, class: vgpr_32 }
 body:             |
   bb.0:
     %0 = IMPLICIT_DEF
     %1 = IMPLICIT_DEF
     %2 = COPY %0
     %3 = COPY %0
     %0 = COPY %1
     %1 = COPY %2
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 # GCN-LABEL: name: swap_virt_read_t_twice
 # GCN: bb.0:
 # GCN-NEXT: %0:vgpr_32 = IMPLICIT_DEF
 # GCN-NEXT: %1:vgpr_32 = IMPLICIT_DEF
 # GCN-NEXT: %2:vgpr_32 = COPY %0
 # GCN-NEXT: %3:vgpr_32 = COPY %2
 # GCN-NEXT: %0:vgpr_32, %1:vgpr_32 = V_SWAP_B32 %1, %0, implicit $exec
-# GCN-NEXT: S_ENDPGM
+# GCN-NEXT: S_ENDPGM 0
 
 ---
 name:            swap_virt_read_t_twice
 registers:
   - { id: 0, class: vgpr_32 }
   - { id: 1, class: vgpr_32 }
   - { id: 2, class: vgpr_32 }
   - { id: 3, class: vgpr_32 }
 body:             |
   bb.0:
     %0 = IMPLICIT_DEF
     %1 = IMPLICIT_DEF
     %2 = COPY %0
     %3 = COPY %2
     %0 = COPY %1
     %1 = COPY %2
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 # GCN-LABEL: name: swap_virt_clobber_y
 # GCN: bb.0:
 # GCN-NEXT: %0:vgpr_32 = IMPLICIT_DEF
 # GCN-NEXT: %1:vgpr_32 = IMPLICIT_DEF
 # GCN-NEXT: %2:vgpr_32 = COPY %0
 # GCN-NEXT: %0:vgpr_32 = COPY %1
 # GCN-NEXT: %1:vgpr_32 = IMPLICIT_DEF
 # GCN-NEXT: %1:vgpr_32 = COPY %2
-# GCN-NEXT: S_ENDPGM
+# GCN-NEXT: S_ENDPGM 0
 
 ---
 name:            swap_virt_clobber_y
 registers:
   - { id: 0, class: vgpr_32 }
   - { id: 1, class: vgpr_32 }
   - { id: 2, class: vgpr_32 }
 body:             |
   bb.0:
     %0 = IMPLICIT_DEF
     %1 = IMPLICIT_DEF
     %2 = COPY %0
     %0 = COPY %1
     %1 = IMPLICIT_DEF
     %1 = COPY %2
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 # GCN-LABEL: name: swap_virt_clobber_x1
 # GCN: bb.0:
 # GCN-NEXT: %0:vgpr_32 = IMPLICIT_DEF
 # GCN-NEXT: %1:vgpr_32 = IMPLICIT_DEF
 # GCN-NEXT: %2:vgpr_32 = COPY %0
 # GCN-NEXT: %0:vgpr_32 = COPY %1
 # GCN-NEXT: %0:vgpr_32 = IMPLICIT_DEF
 # GCN-NEXT: %1:vgpr_32 = COPY %2
-# GCN-NEXT: S_ENDPGM
+# GCN-NEXT: S_ENDPGM 0
 
 ---
 name:            swap_virt_clobber_x1
 registers:
   - { id: 0, class: vgpr_32 }
   - { id: 1, class: vgpr_32 }
   - { id: 2, class: vgpr_32 }
 body:             |
   bb.0:
     %0 = IMPLICIT_DEF
     %1 = IMPLICIT_DEF
     %2 = COPY %0
     %0 = COPY %1
     %0 = IMPLICIT_DEF
     %1 = COPY %2
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 # GCN-LABEL: name: swap_virt_clobber_x2
 # GCN: bb.0:
 # GCN-NEXT: %0:vgpr_32 = IMPLICIT_DEF
 # GCN-NEXT: %1:vgpr_32 = IMPLICIT_DEF
 # GCN-NEXT: %2:vgpr_32 = COPY %0
 # GCN-NEXT: %0:vgpr_32 = IMPLICIT_DEF
 # GCN-NEXT: %0:vgpr_32 = COPY %1
 # GCN-NEXT: %1:vgpr_32 = COPY %2
-# GCN-NEXT: S_ENDPGM
+# GCN-NEXT: S_ENDPGM 0
 
 ---
 name:            swap_virt_clobber_x2
 registers:
   - { id: 0, class: vgpr_32 }
   - { id: 1, class: vgpr_32 }
   - { id: 2, class: vgpr_32 }
 body:             |
   bb.0:
     %0 = IMPLICIT_DEF
     %1 = IMPLICIT_DEF
     %2 = COPY %0
     %0 = IMPLICIT_DEF
     %0 = COPY %1
     %1 = COPY %2
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 # GCN-LABEL: name: swap_virt_clobber_t
 # GCN: bb.0:
 # GCN-NEXT: %0:vgpr_32 = IMPLICIT_DEF
 # GCN-NEXT: %1:vgpr_32 = IMPLICIT_DEF
 # GCN-NEXT: %2:vgpr_32 = COPY %0
 # GCN-NEXT: %0:vgpr_32 = COPY %1
 # GCN-NEXT: %2:vgpr_32 = IMPLICIT_DEF
 # GCN-NEXT: %1:vgpr_32 = COPY %2
-# GCN-NEXT: S_ENDPGM
+# GCN-NEXT: S_ENDPGM 0
 
 ---
 name:            swap_virt_clobber_t
 registers:
   - { id: 0, class: vgpr_32 }
   - { id: 1, class: vgpr_32 }
   - { id: 2, class: vgpr_32 }
 body:             |
   bb.0:
     %0 = IMPLICIT_DEF
     %1 = IMPLICIT_DEF
     %2 = COPY %0
     %0 = COPY %1
     %2 = IMPLICIT_DEF
     %1 = COPY %2
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 # GCN-LABEL: name: swap_virt_copy_subreg_overlap_x_full
 # GCN: bb.0:
 # GCN-NEXT: %0:vreg_64 = IMPLICIT_DEF
 # GCN-NEXT: %1:vreg_64 = IMPLICIT_DEF
 # GCN-NEXT: %2.sub0:vreg_64 = COPY %0.sub0
 # GCN-NEXT: %3:vreg_64 = COPY %0

 ...
 
 # GCN-LABEL: name: swap_virt_b128_sub0_1
 # GCN: bb.0:
 # GCN-NEXT: %0:vreg_128 = IMPLICIT_DEF
 # GCN-NEXT: %1:vreg_128 = IMPLICIT_DEF
 # GCN-NEXT: %0.sub0:vreg_128, %1.sub0:vreg_128 = V_SWAP_B32 %1.sub0, %0.sub0, implicit $exec
 # GCN-NEXT: %0.sub1:vreg_128, %1.sub1:vreg_128 = V_SWAP_B32 %1.sub1, %0.sub1, implicit $exec
-# GCN-NEXT: S_ENDPGM
+# GCN-NEXT: S_ENDPGM 0
 ---
 name:            swap_virt_b128_sub0_1
 registers:
   - { id: 0, class: vreg_128 }
   - { id: 1, class: vreg_128 }
   - { id: 2, class: vreg_128 }
 body:             |
   bb.0:
     %0 = IMPLICIT_DEF
     %1 = IMPLICIT_DEF
     %2.sub0_sub1 = COPY %0.sub0_sub1
     %0.sub0_sub1 = COPY %1.sub0_sub1
     %1.sub0_sub1 = COPY %2.sub0_sub1
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 # GCN-LABEL: name: swap_virt_b128_sub2_3
 # GCN: bb.0:
 # GCN-NEXT: %0:vreg_128 = IMPLICIT_DEF
 # GCN-NEXT: %1:vreg_128 = IMPLICIT_DEF
 # GCN-NEXT: %0.sub2:vreg_128, %1.sub2:vreg_128 = V_SWAP_B32 %1.sub2, %0.sub2, implicit $exec
 # GCN-NEXT: %0.sub3:vreg_128, %1.sub3:vreg_128 = V_SWAP_B32 %1.sub3, %0.sub3, implicit $exec
-# GCN-NEXT: S_ENDPGM
+# GCN-NEXT: S_ENDPGM 0
 ---
 name:            swap_virt_b128_sub2_3
 registers:
   - { id: 0, class: vreg_128 }
   - { id: 1, class: vreg_128 }
   - { id: 2, class: vreg_128 }
 body:             |
   bb.0:
     %0 = IMPLICIT_DEF
     %1 = IMPLICIT_DEF
     %2.sub2_sub3 = COPY %0.sub2_sub3
     %0.sub2_sub3 = COPY %1.sub2_sub3
     %1.sub2_sub3 = COPY %2.sub2_sub3
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 
 
 # GCN-LABEL: name: swap_virt_s_to_s
 # GCN: bb.0:
 # GCN-NEXT: %0:sgpr_32 = IMPLICIT_DEF
 # GCN-NEXT: %1:sgpr_32 = IMPLICIT_DEF
 # GCN-NEXT: %2:sgpr_32 = COPY %0

 # GCN: bb.0:
 # GCN-NEXT: %0:vreg_64 = IMPLICIT_DEF
 # GCN-NEXT: %1:vreg_64 = IMPLICIT_DEF
 # GCN-NEXT: %2.sub0:vreg_64 = COPY %0.sub0
 # GCN-NEXT: %2.sub1:vreg_64 = COPY %0.sub1
 # GCN-NEXT: %0.sub0:vreg_64 = COPY %1.sub0, implicit %0
 # GCN-NEXT: %0.sub1:vreg_64 = COPY %1.sub1
 # GCN-NEXT: %1.sub0:vreg_64 = COPY %2.sub0
-# GCN-NEXT: S_ENDPGM
+# GCN-NEXT: S_ENDPGM 0
 ---
 name:            swap_virt_copy_subreg_impuse_x
 registers:
   - { id: 0, class: vreg_64 }
   - { id: 1, class: vreg_64 }
   - { id: 2, class: vreg_64 }
 body:             |
   bb.0:
     %0 = IMPLICIT_DEF
     %1 = IMPLICIT_DEF
     %2.sub0 = COPY %0.sub0
     %2.sub1 = COPY %0.sub1
     %0.sub0 = COPY %1.sub0, implicit %0
     %0.sub1 = COPY %1.sub1
     %1.sub0 = COPY %2.sub0
-    S_ENDPGM
+    S_ENDPGM 0
 ...

test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir

bb.1.else:
     $vgpr0 = V_MOV_B32_e32 1, implicit $exec
 
   bb.3.done:
     liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
 
     $sgpr3 = S_MOV_B32 61440
     $sgpr2 = S_MOV_B32 -1
     BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.out)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 ---
 # CHECK-LABEL: name: vccz_corrupt_undef_vcc
 # CHECK: S_WAITCNT 3855
 # CHECK-NEXT: $vgpr0 = V_MOV_B32_e32
 
 name:            vccz_corrupt_undef_vcc
bb.1.else:
     $vgpr0 = V_MOV_B32_e32 1, implicit $exec
 
   bb.3.done:
     liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
 
     $sgpr3 = S_MOV_B32 61440
     $sgpr2 = S_MOV_B32 -1
     BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.out)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...

test/CodeGen/AMDGPU/vop-shrink-frame-index.mir

stack:
   - { id: 0, name: alloca, type: default, offset: 0, size: 128, alignment: 8,
       callee-saved-register: '', local-offset: 0, debug-info-variable: '',
       debug-info-expression: '', debug-info-location: '' }
 body:             |
   bb.0:
     %0 = V_MOV_B32_e32 %stack.0.alloca, implicit $exec
     %1 = IMPLICIT_DEF
     %2, $vcc = V_ADD_I32_e64 %0, %1, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 # GCN-LABEL: name: fold_vgpr_fi{{$}}
 # GCN: %1:vgpr_32 = IMPLICIT_DEF
 # GCN: %2:vgpr_32 = V_ADD_I32_e32 %stack.0.alloca, %1, implicit-def $vcc, implicit $exec
 name: fold_vgpr_fi
 tracksRegLiveness: true
 registers:
   - { id: 0, class: vgpr_32 }
   - { id: 1, class: vgpr_32 }
   - { id: 2, class: vgpr_32 }
 stack:
   - { id: 0, name: alloca, type: default, offset: 0, size: 128, alignment: 8,
       callee-saved-register: '', local-offset: 0, debug-info-variable: '',
       debug-info-expression: '', debug-info-location: '' }
 body:             |
   bb.0:
     %0 = V_MOV_B32_e32 %stack.0.alloca, implicit $exec
     %1 = IMPLICIT_DEF
     %2, $vcc = V_ADD_I32_e64 %1, %0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 # GCN-LABEL: name: fold_sgpr_fi{{$}}
 # GCN: %0:vgpr_32 = V_MOV_B32_e32 %stack.0.alloca, implicit $exec
 # GCN: %1:sgpr_32 = IMPLICIT_DEF
 # GCN: %2:vgpr_32 = V_ADD_I32_e32 %1, %0, implicit-def $vcc, implicit $exec
 name: fold_sgpr_fi
 tracksRegLiveness: true
 registers:
   - { id: 0, class: vgpr_32 }
   - { id: 1, class: sgpr_32 }
   - { id: 2, class: vgpr_32 }
 stack:
   - { id: 0, name: alloca, type: default, offset: 0, size: 128, alignment: 8,
       callee-saved-register: '', local-offset: 0, debug-info-variable: '',
       debug-info-expression: '', debug-info-location: '' }
 body:             |
   bb.0:
     %0 = V_MOV_B32_e32 %stack.0.alloca, implicit $exec
     %1 = IMPLICIT_DEF
     %2, $vcc = V_ADD_I32_e64 %1, %0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 # GCN-LABEL: name: fold_fi_sgpr{{$}}
 # GCN: %0:vgpr_32 = V_MOV_B32_e32 %stack.0.alloca, implicit $exec
 # GCN: %1:sgpr_32 = IMPLICIT_DEF
 # GCN: %2:vgpr_32 = V_ADD_I32_e32 %1, %0, implicit-def $vcc, implicit $exec
 name: fold_fi_sgpr
 tracksRegLiveness: true
 registers:
   - { id: 0, class: vgpr_32 }
   - { id: 1, class: sgpr_32 }
   - { id: 2, class: vgpr_32 }
 stack:
   - { id: 0, name: alloca, type: default, offset: 0, size: 128, alignment: 8,
       callee-saved-register: '', local-offset: 0, debug-info-variable: '',
       debug-info-expression: '', debug-info-location: '' }
 body:             |
   bb.0:
     %0 = V_MOV_B32_e32 %stack.0.alloca, implicit $exec
     %1 = IMPLICIT_DEF
     %2, $vcc = V_ADD_I32_e64 %0, %1, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 # TODO: Should probably prefer folding immediate first
 # GCN-LABEL: name: fold_fi_imm{{$}}
 # GCN: %1:vgpr_32 = V_MOV_B32_e32 999, implicit $exec
 # GCN: %2:vgpr_32 = V_ADD_I32_e32 %stack.0.alloca, %1, implicit-def $vcc, implicit $exec
 name: fold_fi_imm
 tracksRegLiveness: true
 registers:
   - { id: 0, class: vgpr_32 }
   - { id: 1, class: vgpr_32 }
   - { id: 2, class: vgpr_32 }
 stack:
   - { id: 0, name: alloca, type: default, offset: 0, size: 128, alignment: 8,
       callee-saved-register: '', local-offset: 0, debug-info-variable: '',
       debug-info-expression: '', debug-info-location: '' }
 body:             |
   bb.0:
     %0 = V_MOV_B32_e32 %stack.0.alloca, implicit $exec
     %1 = V_MOV_B32_e32 999, implicit $exec
     %2, $vcc = V_ADD_I32_e64 %0, %1, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 # GCN-LABEL: name: fold_imm_fi{{$}}
 # GCN: %0:vgpr_32 = V_MOV_B32_e32 %stack.0.alloca, implicit $exec
 # GCN: %2:vgpr_32 = V_ADD_I32_e32 999, %0, implicit-def $vcc, implicit $exec
 name: fold_imm_fi
 tracksRegLiveness: true
 registers:
   - { id: 0, class: vgpr_32 }
   - { id: 1, class: vgpr_32 }
   - { id: 2, class: vgpr_32 }
 stack:
   - { id: 0, name: alloca, type: default, offset: 0, size: 128, alignment: 8,
       callee-saved-register: '', local-offset: 0, debug-info-variable: '',
       debug-info-expression: '', debug-info-location: '' }
 body:             |
   bb.0:
     %0 = V_MOV_B32_e32 %stack.0.alloca, implicit $exec
     %1 = V_MOV_B32_e32 999, implicit $exec
     %2, $vcc = V_ADD_I32_e64 %1, %0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0

test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir

registers:
   - { id: 2, class: vgpr_32 }
   - { id: 3, class: sreg_64 }
 body:             |
   bb.0:
     %0 = COPY undef %0
     %0 = V_MOV_B32_e32 123, implicit $exec
     %1 = V_MOV_B32_e32 456, implicit $exec
     %2, $vcc = V_ADD_I32_e64 %0, %1, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 # GCN-LABEL: name: fold_partially_defined_superreg{{$}}
 # GCN: %1:vgpr_32 = V_MOV_B32_e32 456, implicit $exec
 # GCN: %2:vgpr_32 = V_ADD_I32_e32 123, %1, implicit-def $vcc, implicit $exec
 name: fold_partially_defined_superreg
 tracksRegLiveness: true
 registers:
   - { id: 0, class: vgpr_32 }
   - { id: 1, class: vgpr_32 }
   - { id: 2, class: vgpr_32 }
   - { id: 3, class: vreg_64 }
 body:             |
   bb.0:
     undef %3.sub0 = V_MOV_B32_e32 123, implicit $exec, implicit-def %3
     %1 = V_MOV_B32_e32 456, implicit $exec
     %2, $vcc = V_ADD_I32_e64 %3.sub0, %1, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...

test/CodeGen/AMDGPU/waitcnt-back-edge-loop.mir

bb.4:
     $vgpr4 = V_MOV_B32_e32 $vgpr5, implicit $exec, implicit $exec
     S_CBRANCH_VCCZ %bb.1, implicit killed $vcc
     S_BRANCH %bb.3
 
   bb.5:
 
     $vgpr4 = V_MAC_F32_e32 killed $vgpr0, killed $vgpr3, killed $vgpr4, implicit $exec
     EXP_DONE 12, killed $vgpr4, undef $vgpr0, undef $vgpr0, undef $vgpr0, 0, 0, 15, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 
 # GCN-LABEL: name: waitcnt-multiple-back-edges{{$}}
 # GCN: bb.0:
 # GCN: S_WAITCNT 0
 # GCN-NEXT: S_BRANCH %bb.2
 
bb.4:
     S_BRANCH %bb.6
 
   bb.5:
     S_CBRANCH_SCC0 %bb.2, implicit $scc
     S_BRANCH %bb.6
 
   bb.6:
     S_CBRANCH_SCC1 %bb.0, implicit $scc
-    S_ENDPGM
+    S_ENDPGM 0
 ...

test/CodeGen/AMDGPU/waitcnt-loop-irreducible.mir

body:             |
   bb.3:
     successors: %bb.1, %bb.4
 
     S_CMP_GE_I32 renamable $sgpr2, renamable $sgpr3, implicit-def $scc
     S_CBRANCH_SCC0 %bb.1, implicit killed $scc
 
   bb.4:
 
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...
 
 # GCN-LABEL: name: irreducible_loop_extended
 
 # GCN: S_LOAD_DWORDX4_IMM
 # GFX8: S_WAITCNT 127{{$}}
 # GFX9: S_WAITCNT 49279{{$}}
 # GCN: BUFFER_STORE_DWORD_OFFEN_exact
 # GFX8: S_WAITCNT 127{{$}}
 # GFX9: S_WAITCNT 49279{{$}}
 # GCN: BUFFER_STORE_DWORD_OFFEN_exact
 # GCN: S_LOAD_DWORDX4_IMM
 # GFX8: S_WAITCNT 127{{$}}
 # GFX9: S_WAITCNT 49279{{$}}
 # GCN: BUFFER_ATOMIC_ADD_OFFSET_RTN
 # GCN: S_WAITCNT 3952
 # GCN: FLAT_STORE_DWORD
-# GCN: S_ENDPGM
+# GCN: S_ENDPGM 0
 name: irreducible_loop_extended
 
 body: |
   bb.0:
     successors: %bb.1, %bb.2
     $sgpr4_sgpr5_sgpr6_sgpr7 = S_LOAD_DWORDX4_IMM renamable $sgpr2_sgpr3, 0, 0
     S_CBRANCH_VCCZ %bb.2, implicit $vcc
 
bb.4:
     renamable $sgpr12_sgpr13_sgpr14_sgpr15 = S_LOAD_DWORDX4_IMM killed renamable $sgpr2_sgpr3, 64, 0
     renamable $vgpr2 = BUFFER_ATOMIC_ADD_OFFSET_RTN killed renamable $vgpr2, killed renamable $sgpr12_sgpr13_sgpr14_sgpr15, 0, 0, 0, implicit $exec
 
   bb.5:
     successors: %bb.6
 
   bb.6:
     FLAT_STORE_DWORD $vgpr3_vgpr4, $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr
-    S_ENDPGM
+    S_ENDPGM 0
 ...

test/CodeGen/AMDGPU/waitcnt-loop-single-basic-block.mir

body: |
   bb.1:
     GLOBAL_STORE_DWORD $vgpr7_vgpr8, $vgpr11, 0, 0, 0, implicit $exec
     $vgpr21 = GLOBAL_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec
     $vgpr10 = GLOBAL_LOAD_DWORD $vgpr10_vgpr11, 0, 0, 0, implicit $exec
     GLOBAL_STORE_DWORD $vgpr14_vgpr15, $vgpr21, 0, 0, 0, implicit $exec
     $vgpr11 = GLOBAL_LOAD_DWORD $vgpr11_vgpr12, 0, 0, 0, implicit $exec
     S_CBRANCH_SCC1 %bb.1, implicit $scc
   bb.2:
-    S_ENDPGM
+    S_ENDPGM 0
 ...

test/CodeGen/AMDGPU/waitcnt-preexisting.mir

bb.0:
     renamable $vgpr1 = V_ADD_U32_e32 1, killed $vgpr1, implicit $exec
     renamable $vgpr1 = V_MAX_U32_e32 killed $vgpr0, killed $vgpr1, implicit $exec
     renamable $vgpr1 = V_MAX_U32_e32 killed $vgpr2, killed $vgpr1, implicit $exec
     renamable $vgpr1 = V_MAX_U32_e32 killed $vgpr3, killed $vgpr1, implicit $exec
     $vgpr0 = V_MOV_B32_e32 $vgpr1, implicit $exec, implicit $exec
     $vgpr2 = V_MOV_B32_e32 $vgpr1, implicit $exec, implicit $exec
     $vgpr3 = V_MOV_B32_e32 $vgpr1, implicit $exec, implicit $exec
     IMAGE_STORE_V4_V2 killed renamable $vgpr0_vgpr1_vgpr2_vgpr3, killed renamable $vgpr0_vgpr1, killed renamable $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, 15, -1, 1, 0, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 ...

test/CodeGen/AMDGPU/waitcnt.mir

bb.1:
     $vgpr3_vgpr4_vgpr5_vgpr6 = FLAT_LOAD_DWORDX4 $vgpr7_vgpr8, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 16 from %ir.global16)
     $vgpr0 = V_MOV_B32_e32 $vgpr1, implicit $exec
     S_BRANCH %bb.2
 
   bb.2:
     $vgpr0 = FLAT_LOAD_DWORD $vgpr1_vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4 from %ir.flat4)
     $vgpr3_vgpr4_vgpr5_vgpr6 = FLAT_LOAD_DWORDX4 $vgpr7_vgpr8, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 16 from %ir.flat16)
     $vgpr0 = V_MOV_B32_e32 $vgpr1, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # There is only a single fallthrough successor block, so there's no
 # need to wait immediately.
 
 # CHECK-LABEL: name: single_fallthrough_successor_no_end_block_wait
 # CHECK:   $vgpr0 = FLAT_LOAD_DWORD $vgpr1_vgpr2
 # CHECK-NOT: S_WAITCNT
 
 # CHECK: bb.1:
 # CHECK-NEXT: V_LSHLREV_B64
 # CHECK-NEXT: S_WAITCNT 112
 # CHECK-NEXT: FLAT_STORE_DWORD
 name: single_fallthrough_successor_no_end_block_wait
 
 body: |
   bb.0:
     successors: %bb.1
     $vgpr0 = FLAT_LOAD_DWORD $vgpr1_vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr
 
   bb.1:
     $vgpr3_vgpr4 = V_LSHLREV_B64 4, $vgpr7_vgpr8, implicit $exec
     FLAT_STORE_DWORD $vgpr3_vgpr4, $vgpr0, 0, 0, 0, implicit $exec, implicit $flat_scr
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 # The block has a single predecessor with a single successor, but it
 # is not the next block so it's non-obvious that the wait is not needed.
 
 
 # CHECK-LABEL: name: single_branch_successor_not_next_block
 
 # CHECK: bb.1
 # CHECK-NEXT: FLAT_STORE_DWORD
-# CHECK-NEXT: S_ENDPGM
+# CHECK-NEXT: S_ENDPGM 0
 
 # CHECK: bb.2:
 # CHECK-NEXT: V_LSHLREV_B64
 # CHECK-NEXT: S_WAITCNT 112
 # CHECK-NEXT: FLAT_STORE_DWORD
 name: single_branch_successor_not_next_block
 
 body: |
   bb.0:
     successors: %bb.2
     $vgpr0 = FLAT_LOAD_DWORD $vgpr1_vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr
    S_BRANCH %bb.2
 
   bb.1:
     FLAT_STORE_DWORD $vgpr8_vgpr9, $vgpr10, 0, 0, 0, implicit $exec, implicit $flat_scr
-    S_ENDPGM
+    S_ENDPGM 0
 
   bb.2:
      $vgpr3_vgpr4 = V_LSHLREV_B64 4, $vgpr7_vgpr8, implicit $exec
     FLAT_STORE_DWORD $vgpr3_vgpr4, $vgpr0, 0, 0, 0, implicit $exec, implicit $flat_scr
-    S_ENDPGM
+    S_ENDPGM 0
 ...

test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir

; CHECK: [[@LINE+1]]:45: expected the name of the target index
     $sgpr4 = S_ADD_U32 $sgpr2, $sgpr6, implicit-def $scc
     $sgpr5 = S_ADDC_U32 $sgpr3, $sgpr7, implicit-def dead $scc, implicit $scc
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr4_sgpr5, 0
     $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 9
     $sgpr7 = S_MOV_B32 61440
     $sgpr6 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec
     BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 ...

test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir

; CHECK: [[@LINE+1]]:45: use of undefined target index 'constdata-start'
     $sgpr4 = S_ADD_U32 $sgpr2, $sgpr6, implicit-def $scc
     $sgpr5 = S_ADDC_U32 $sgpr3, $sgpr7, implicit-def dead $scc, implicit $scc
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr4_sgpr5, 0
     $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 9
     $sgpr7 = S_MOV_B32 61440
     $sgpr6 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec
     BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 ...

test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir

bb.0:
     %27:vreg_64 = REG_SEQUENCE %vreg123_0, %subreg.sub0, %vreg123_1, %subreg.sub1
     %4:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 9, 0
     %vreg123_2:vgpr_32 = COPY %4
     %5:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 11, 0
     %vreg123_3:vgpr_32 = COPY %5
     %16:sgpr_128 = REG_SEQUENCE killed %vreg123_0, %subreg.sub0, %vreg123_1, %subreg.sub1, %vreg123_2, %subreg.sub2, %vreg123_3, %subreg.sub3
 
     BUFFER_STORE_DWORD_ADDR64 %vreg123_1, %27, killed %16, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...

test/CodeGen/MIR/AMDGPU/stack-id.mir

fixedStack:
   - { id: 2, type: spill-slot, offset: 0, size: 4, alignment: 4 }
 stack:
   - { id: 0, name: '', type: spill-slot, offset: 0, size: 16, alignment: 4, stack-id: 3 }
   - { id: 1, name: '', type: spill-slot, offset: 0, size: 8, alignment: 4, stack-id: 0 }
   - { id: 2, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4 }
 
 body: |
   bb.0:
-    S_ENDPGM
+    S_ENDPGM 0
 ...

test/CodeGen/MIR/AMDGPU/syncscopes.mir

bb.0.entry:
     $vgpr1 = V_MOV_B32_e32 killed $sgpr3, implicit $exec, implicit killed $sgpr2_sgpr3, implicit $sgpr2_sgpr3, implicit $exec
     $vgpr2 = V_MOV_B32_e32 killed $sgpr7, implicit $exec, implicit $exec
     FLAT_STORE_DWORD killed $vgpr0_vgpr1, killed $vgpr2, 0, -1, 0, implicit $exec, implicit $flat_scr :: (volatile non-temporal store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out)
     S_WAITCNT 112
     $vgpr0 = V_MOV_B32_e32 $sgpr4, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr4_sgpr5
     $vgpr1 = V_MOV_B32_e32 killed $sgpr5, implicit $exec, implicit killed $sgpr4_sgpr5, implicit $sgpr4_sgpr5, implicit $exec
     $vgpr2 = V_MOV_B32_e32 killed $sgpr8, implicit $exec, implicit $exec
     FLAT_STORE_DWORD killed $vgpr0_vgpr1, killed $vgpr2, 0, -1, 0, implicit $exec, implicit $flat_scr :: (volatile non-temporal store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out)
-    S_ENDPGM
+    S_ENDPGM 0
 
 ...

test/CodeGen/MIR/AMDGPU/target-flags.mir

registers:
   - { id: 0, class: sreg_64, preferred-register: '' }
   - { id: 1, class: sreg_64, preferred-register: '' }
 body: |
   bb.0:
     liveins: $sgpr0_sgpr1
     ; CHECK-LABEL: name: flags
     ; CHECK: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @foo + 4, implicit-def dead $scc
     ; CHECK: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 target-flags(amdgpu-gotprel) @foo
-    ; CHECK: S_ENDPGM
+    ; CHECK: S_ENDPGM 0
     %0 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @foo + 4, implicit-def dead $scc
   %1 = S_MOV_B64 target-flags(amdgpu-gotprel) @foo
 
-    S_ENDPGM
+    S_ENDPGM 0
 ...

test/CodeGen/MIR/AMDGPU/target-index-operands.mir

; CHECK: $sgpr2 = S_ADD_U32 $sgpr2, target-index(amdgpu-constdata-start), implicit-def $scc, implicit-def $scc
     $sgpr4 = S_ADD_U32 $sgpr2, $sgpr6, implicit-def $scc
     $sgpr5 = S_ADDC_U32 $sgpr3, $sgpr7, implicit-def dead $scc, implicit $scc
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr4_sgpr5, 0, 0
     $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 9, 0
     $sgpr7 = S_MOV_B32 61440
     $sgpr6 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec
     BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 ...
 ---
 name: float2
 liveins:
   - { reg: '$sgpr0_sgpr1' }
 frameInfo:
   maxAlignment:  8
 body: |
; CHECK: $sgpr2 = S_ADD_U32 $sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def $scc, implicit-def $scc
     $sgpr4 = S_ADD_U32 $sgpr2, $sgpr6, implicit-def $scc
     $sgpr5 = S_ADDC_U32 $sgpr3, $sgpr7, implicit-def dead $scc, implicit $scc
     $sgpr2 = S_LOAD_DWORD_IMM $sgpr4_sgpr5, 0, 0
     $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 9, 0
     $sgpr7 = S_MOV_B32 61440
     $sgpr6 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec
     BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec
-    S_ENDPGM
+    S_ENDPGM 0
 ...

test/MC/AMDGPU/s_endpgm.s

+// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=GCN
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -filetype=obj %s | llvm-objcopy -S -K keep_symbol - | llvm-objdump -disassemble -mcpu=gfx900 - | FileCheck %s --check-prefix=BIN
+
+// GCN: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
+// BIN: s_endpgm    // 000000000000: BF810000
+s_endpgm
+
+// GCN: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
+// BIN: s_endpgm    // 000000000004: BF810000
+s_endpgm 0
+
+  
+// GCN: s_endpgm 1 ; encoding: [0x01,0x00,0x81,0xbf]
+// BIN: s_endpgm 1  // 000000000008: BF810001
+s_endpgm 1
+  
+  

test/MachineVerifier/verifier-implicit-virtreg-invalid-physreg-liveness.mir

 # RUN: not llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s
 # REQUIRES: amdgpu-registered-target
 
 # When the verifier was detecting the invalid liveness for vcc, it would assert when trying to iterate the subregisters of the implicit virtual register use.
 
 
 # ERROR: *** Bad machine code: Using an undefined physical register ***
-# ERROR: instruction: S_ENDPGM implicit %0:vgpr_32, implicit $vcc
-# ERROR: operand 1:   implicit $vcc
+# ERROR: instruction: S_ENDPGM 0, implicit %0:vgpr_32, implicit $vcc
+# ERROR: operand 2:   implicit $vcc
 
 ...
 
 name: invalid_implicit_physreg_use_with_implicit_virtreg
 tracksRegLiveness: true
 
 body:             |
   bb.0:
     %0:vgpr_32 = IMPLICIT_DEF
-    S_ENDPGM implicit %0, implicit $vcc
+    S_ENDPGM 0, implicit %0, implicit $vcc
 
 ...