[RISCV] Support -target-abi at the MC layer and for codegen

[asb]

Summary

This patch adds proper handling of -target-abi, as accepted by llvm-mc and llc. Lowering (codegen) for the hard-float ABIs will follow in a subsequent patch. However, this patch does add MC layer support for the hard float and RVE ABIs (emission of the appropriate ELF flags https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#-file-header).

ABI parsing must be shared between codegen and the MC layer, so we add computeTargetABI to RISCVUtils. A warning will be printed if an invalid or unrecognized ABI is given.

[asb]

RV32E is intentionally left out of this patch as well. I feel it will be cleaner to add basic recognition of -target-abi=rv32e alongside basic support for the E extension (e.g. -march=risc32 -mattr=+e).

[apazos]

lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h

41

I find strange that instantiating a backend can cause an error.

lib/Target/RISCV/Utils/RISCVBaseInfo.cpp

55

Instead of returning error, should we just use the default abi setting you apply in the beginning of this function (ILP32 or ILP64) and print a warning?

[asb]

Updated to print a warning if an invalid ABI name is given, or if an ABI can't be selected for the current -march. Also add minimal support for recognising ilp32e, including setting the EF_RISCV_RVE ELF flag if -target-abi ilp32e is specified.

[apazos]

lib/Target/RISCV/RISCVSubtarget.cpp

42

Now it always returns a valid ABI, right? Do we need this check?

[asb]

Removed unnecessary use of Expected<T> that was missed in the last update.

lib/Target/RISCV/RISCVSubtarget.cpp

42

Meant to remove this, thanks for catching.

[asb]

Add missed MC rv32ifd -target-abi=ilp32d test case.

[apazos]

Thanks Alex, LGTM.

lib/Target/RISCV/MCTargetDesc/LLVMBuild.txt

 ;   http://llvm.org/docs/LLVMBuild.html
 ;
 ;===------------------------------------------------------------------------===;
 
 [component_0]
 type = Library
 name = RISCVDesc
 parent = RISCV
-required_libraries = MC RISCVAsmPrinter RISCVInfo Support
+required_libraries = MC RISCVAsmPrinter RISCVInfo RISCVUtils Support
 add_to_library_groups = RISCV

lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h

 //===-- RISCVAsmBackend.h - RISCV Assembler Backend -----------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVASMBACKEND_H
 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVASMBACKEND_H
 
 #include "MCTargetDesc/RISCVFixupKinds.h"
 #include "MCTargetDesc/RISCVMCTargetDesc.h"
+#include "Utils/RISCVBaseInfo.h"
 #include "llvm/MC/MCAsmBackend.h"
 #include "llvm/MC/MCFixupKindInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 
 namespace llvm {
 class MCAssembler;
 class MCObjectTargetWriter;
 class raw_ostream;
 
 class RISCVAsmBackend : public MCAsmBackend {
   const MCSubtargetInfo &STI;
   uint8_t OSABI;
   bool Is64Bit;
   bool ForceRelocs = false;
+  const MCTargetOptions &TargetOptions;
+  RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
 
 public:
-  RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit)
-      : MCAsmBackend(support::little), STI(STI), OSABI(OSABI),
-        Is64Bit(Is64Bit) {}
+  RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit,
+                  const MCTargetOptions &Options)
+      : MCAsmBackend(support::little), STI(STI), OSABI(OSABI), Is64Bit(Is64Bit),
+        TargetOptions(Options) {
+    TargetABI = RISCVABI::computeTargetABI(
+        STI.getTargetTriple(), STI.getFeatureBits(), Options.getABIName());
+  }
   ~RISCVAsmBackend() override {}
 
   void setForceRelocs() { ForceRelocs = true; }
 
   // Generate diff expression relocations if the relax feature is enabled or had
   // previously been enabled, otherwise it is safe for the assembler to
   // calculate these internally.
   bool requiresDiffExpressionRelocations() const override {
     return STI.getFeatureBits()[RISCV::FeatureRelax] || ForceRelocs;
   }
bool mayNeedRelaxation(const MCInst &Inst,
                          const MCSubtargetInfo &STI) const override;
   unsigned getRelaxedOpcode(unsigned Op) const;
 
   void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
                         MCInst &Res) const override;
 
 
   bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
+
+  const MCTargetOptions &getTargetOptions() const { return TargetOptions; }
+  RISCVABI::ABI getTargetABI() const { return TargetABI; }
 };
 }
 
 #endif

lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

 }
 
 MCAsmBackend *llvm::createRISCVAsmBackend(const Target &T,
                                           const MCSubtargetInfo &STI,
                                           const MCRegisterInfo &MRI,
                                           const MCTargetOptions &Options) {
   const Triple &TT = STI.getTargetTriple();
   uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
-  return new RISCVAsmBackend(STI, OSABI, TT.isArch64Bit());
+  return new RISCVAsmBackend(STI, OSABI, TT.isArch64Bit(), Options);
 }

lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp

 //===-- RISCVELFStreamer.cpp - RISCV ELF Target Streamer Methods ----------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file provides RISCV specific target streamer methods.
 //
 //===----------------------------------------------------------------------===//
 
 #include "RISCVELFStreamer.h"
+#include "MCTargetDesc/RISCVAsmBackend.h"
 #include "RISCVMCTargetDesc.h"
+#include "Utils/RISCVBaseInfo.h"
 #include "llvm/BinaryFormat/ELF.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 
 using namespace llvm;
 
 // This part is for ELF object output.
 RISCVTargetELFStreamer::RISCVTargetELFStreamer(MCStreamer &S,
                                                const MCSubtargetInfo &STI)
     : RISCVTargetStreamer(S) {
   MCAssembler &MCA = getStreamer().getAssembler();
-
   const FeatureBitset &Features = STI.getFeatureBits();
+  auto &MAB = static_cast<RISCVAsmBackend &>(MCA.getBackend());
+  RISCVABI::ABI ABI = MAB.getTargetABI();
+  assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialised target ABI");
 
   unsigned EFlags = MCA.getELFHeaderEFlags();
 
   if (Features[RISCV::FeatureStdExtC])
     EFlags |= ELF::EF_RISCV_RVC;
 
+  switch (ABI) {
+  case RISCVABI::ABI_ILP32:
+  case RISCVABI::ABI_LP64:
+    break;
+  case RISCVABI::ABI_ILP32F:
+  case RISCVABI::ABI_LP64F:
+    EFlags |= ELF::EF_RISCV_FLOAT_ABI_SINGLE;
+    break;
+  case RISCVABI::ABI_ILP32D:
+  case RISCVABI::ABI_LP64D:
+    EFlags |= ELF::EF_RISCV_FLOAT_ABI_DOUBLE;
+    break;
+  case RISCVABI::ABI_ILP32E:
+    EFlags |= ELF::EF_RISCV_RVE;
+    break;
+  case RISCVABI::ABI_Unknown:
+    llvm_unreachable("Improperly initialised target ABI");
+  }
+
   MCA.setELFHeaderEFlags(EFlags);
 }
 
 MCELFStreamer &RISCVTargetELFStreamer::getStreamer() {
   return static_cast<MCELFStreamer &>(Streamer);
 }
 
 void RISCVTargetELFStreamer::emitDirectiveOptionPush() {}
 void RISCVTargetELFStreamer::emitDirectiveOptionPop() {}
 void RISCVTargetELFStreamer::emitDirectiveOptionRVC() {}
 void RISCVTargetELFStreamer::emitDirectiveOptionNoRVC() {}
 void RISCVTargetELFStreamer::emitDirectiveOptionRelax() {}
 void RISCVTargetELFStreamer::emitDirectiveOptionNoRelax() {}

lib/Target/RISCV/RISCVISelLowering.cpp

 #define DEBUG_TYPE "riscv-lower"
 
 STATISTIC(NumTailCalls, "Number of tail calls");
 
 RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
                                          const RISCVSubtarget &STI)
     : TargetLowering(TM), Subtarget(STI) {
 
+  RISCVABI::ABI ABI = Subtarget.getTargetABI();
+  assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialised target ABI");
+
+  if (ABI != RISCVABI::ABI_ILP32 && ABI != RISCVABI::ABI_LP64)
+    report_fatal_error("Don't know how to lower this ABI");
+
   MVT XLenVT = Subtarget.getXLenVT();
 
   // Set up the register classes.
   addRegisterClass(XLenVT, &RISCV::GPRRegClass);
 
   if (Subtarget.hasStdExtF())
     addRegisterClass(MVT::f32, &RISCV::FPR32RegClass);
   if (Subtarget.hasStdExtD())

lib/Target/RISCV/RISCVSubtarget.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
 #define LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
 
 #include "RISCVFrameLowering.h"
 #include "RISCVISelLowering.h"
 #include "RISCVInstrInfo.h"
+#include "Utils/RISCVBaseInfo.h"
 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/Target/TargetMachine.h"
 
 #define GET_SUBTARGETINFO_HEADER
 #include "RISCVGenSubtargetInfo.inc"
 
 namespace llvm {
 class StringRef;
 
 class RISCVSubtarget : public RISCVGenSubtargetInfo {
   virtual void anchor();
   bool HasStdExtM = false;
   bool HasStdExtA = false;
   bool HasStdExtF = false;
   bool HasStdExtD = false;
   bool HasStdExtC = false;
   bool HasRV64 = false;
   bool EnableLinkerRelax = false;
   unsigned XLen = 32;
   MVT XLenVT = MVT::i32;
+  RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
   RISCVFrameLowering FrameLowering;
   RISCVInstrInfo InstrInfo;
   RISCVRegisterInfo RegInfo;
   RISCVTargetLowering TLInfo;
   SelectionDAGTargetInfo TSInfo;
 
   /// Initializes using the passed in CPU and feature strings so that we can
   /// use initializer lists for subtarget initialization.
-  RISCVSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
-                                                  bool Is64Bit);
+  RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT,
+                                                  StringRef CPU, StringRef FS,
+                                                  StringRef ABIName);
 
 public:
   // Initializes the data members to match that of the specified triple.
   RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
-                 const TargetMachine &TM);
+                 StringRef ABIName, const TargetMachine &TM);
 
   // Parses features string setting specified subtarget options. The
   // definition of this function is auto-generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
 
   const RISCVFrameLowering *getFrameLowering() const override {
     return &FrameLowering;
   }
public:
   bool hasStdExtA() const { return HasStdExtA; }
   bool hasStdExtF() const { return HasStdExtF; }
   bool hasStdExtD() const { return HasStdExtD; }
   bool hasStdExtC() const { return HasStdExtC; }
   bool is64Bit() const { return HasRV64; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }
   MVT getXLenVT() const { return XLenVT; }
   unsigned getXLen() const { return XLen; }
+  RISCVABI::ABI getTargetABI() const { return TargetABI; }
 };
 } // End llvm namespace
 
 #endif

lib/Target/RISCV/RISCVSubtarget.cpp

 #define DEBUG_TYPE "riscv-subtarget"
 
 #define GET_SUBTARGETINFO_TARGET_DESC
 #define GET_SUBTARGETINFO_CTOR
 #include "RISCVGenSubtargetInfo.inc"
 
 void RISCVSubtarget::anchor() {}
 
-RISCVSubtarget &RISCVSubtarget::initializeSubtargetDependencies(StringRef CPU,
-                                                                StringRef FS,
-                                                                bool Is64Bit) {
+RISCVSubtarget &RISCVSubtarget::initializeSubtargetDependencies(
+    const Triple &TT, StringRef CPU, StringRef FS, StringRef ABIName) {
   // Determine default and user-specified characteristics
+  bool Is64Bit = TT.isArch64Bit();
   std::string CPUName = CPU;
   if (CPUName.empty())
     CPUName = Is64Bit ? "generic-rv64" : "generic-rv32";
   ParseSubtargetFeatures(CPUName, FS);
   if (Is64Bit) {
     XLenVT = MVT::i64;
     XLen = 64;
   }
+
+  TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName);
   return *this;
 }
 
 RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
-                               const TargetMachine &TM)
+                               StringRef ABIName, const TargetMachine &TM)
     : RISCVGenSubtargetInfo(TT, CPU, FS),
-      FrameLowering(initializeSubtargetDependencies(CPU, FS, TT.isArch64Bit())),
+      FrameLowering(initializeSubtargetDependencies(TT, CPU, FS, ABIName)),
       InstrInfo(), RegInfo(getHwMode()), TLInfo(TM, *this) {}

lib/Target/RISCV/RISCVTargetMachine.cpp

RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT,
                                        const TargetOptions &Options,
                                        Optional<Reloc::Model> RM,
                                        Optional<CodeModel::Model> CM,
                                        CodeGenOpt::Level OL, bool JIT)
     : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
                         getEffectiveRelocModel(TT, RM),
                         getEffectiveCodeModel(CM, CodeModel::Small), OL),
       TLOF(make_unique<RISCVELFTargetObjectFile>()),
-      Subtarget(TT, CPU, FS, *this) {
+      Subtarget(TT, CPU, FS, Options.MCOptions.getABIName(), *this) {
   initAsmInfo();
 }
 
 namespace {
 class RISCVPassConfig : public TargetPassConfig {
 public:
   RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
       : TargetPassConfig(TM, PM) {}

lib/Target/RISCV/Utils/RISCVBaseInfo.h

bool haveRequiredFeatures(FeatureBitset ActiveFeatures) const {
     return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
   }
 };
 
 #define GET_SysRegsList_DECL
 #include "RISCVGenSystemOperands.inc"
 } // end namespace RISCVSysReg
 
+namespace RISCVABI {
+
+enum ABI {
+  ABI_ILP32,
+  ABI_ILP32F,
+  ABI_ILP32D,
+  ABI_ILP32E,
+  ABI_LP64,
+  ABI_LP64F,
+  ABI_LP64D,
+  ABI_Unknown
+};
+
+// Returns the target ABI, or else a StringError if the requested ABIName is
+// not supported for the given TT and FeatureBits combination.
+ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
+                     StringRef ABIName);
+
+} // namespace RISCVABI
+
 } // namespace llvm
 
 #endif

lib/Target/RISCV/Utils/RISCVBaseInfo.cpp

 #include "RISCVBaseInfo.h"
 #include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/Triple.h"
+#include "llvm/Support/raw_ostream.h"
 
 namespace llvm {
 namespace RISCVSysReg {
 #define GET_SysRegsList_IMPL
 #include "RISCVGenSystemOperands.inc"
 } // namespace RISCVSysReg
+
+namespace RISCVABI {
+ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
+                     StringRef ABIName) {
+  auto TargetABI = StringSwitch<ABI>(ABIName)
+                       .Case("ilp32", ABI_ILP32)
+                       .Case("ilp32f", ABI_ILP32F)
+                       .Case("ilp32d", ABI_ILP32D)
+                       .Case("ilp32e", ABI_ILP32E)
+                       .Case("lp64", ABI_LP64)
+                       .Case("lp64f", ABI_LP64F)
+                       .Case("lp64d", ABI_LP64D)
+                       .Default(ABI_Unknown);
+
+  if (!ABIName.empty() && TargetABI == ABI_Unknown) {
+    errs()
+        << "'" << ABIName
+        << "' is not a recognized ABI for this target (ignoring target-abi)\n";
+  } else if (ABIName.startswith("ilp32") && TT.isArch64Bit()) {
+    errs() << "32-bit ABIs are not supported for 64-bit targets (ignoring "
+              "target-abi)\n";
+    TargetABI = ABI_Unknown;
+  } else if (ABIName.startswith("lp64") && !TT.isArch64Bit()) {
+    errs() << "64-bit ABIs are not supported for 32-bit targets (ignoring "
+              "target-abi)\n";
+    TargetABI = ABI_Unknown;
+  } else if (ABIName.endswith("f") && !FeatureBits[RISCV::FeatureStdExtF]) {
+    errs() << "Hard-float 'f' ABI can't be used for a target that "
+              "doesn't support the F instruction set extension (ignoring "
+              "target-abi)\n";
+    TargetABI = ABI_Unknown;
+  } else if (ABIName.endswith("d") && !FeatureBits[RISCV::FeatureStdExtD]) {
+    errs() << "Hard-float 'd' ABI can't be used for a target that "
+              "doesn't support the D instruction set extension (ignoring "
+              "target-abi)\n";
+    TargetABI = ABI_Unknown;
+  }
+
+  // For now, default to the ilp32/lp64 if no explicit ABI is given or an
+  // invalid/unrecognised string is given. In the future, it might be worth
+  // changing this to default to ilp32f/lp64f and ilp32d/lp64d when hardware
+  // support for floating point is present.
+  if (TargetABI == ABI_Unknown) {
+    TargetABI = TT.isArch64Bit() ? ABI_LP64 : ABI_ILP32;
+  }
+
+  return TargetABI;
+}
+} // namespace RISCVABI
 } // namespace llvm

test/CodeGen/RISCV/target-abi-invalid.ll

+; RUN: llc -mtriple=riscv32 -target-abi foo < %s 2>&1 \
+; RUN:   | FileCheck -check-prefix=RV32I-FOO %s
+; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32foof < %s 2>&1 \
+; RUN:   | FileCheck -check-prefix=RV32IF-ILP32FOOF %s
+
+; RV32I-FOO: 'foo' is not a recognized ABI for this target (ignoring target-abi)
+; RV32IF-ILP32FOOF: 'ilp32foof' is not a recognized ABI for this target (ignoring target-abi)
+
+; RUN: llc -mtriple=riscv64 -target-abi ilp32 < %s 2>&1 \
+; RUN:   | FileCheck -check-prefix=RV64I-ILP32 %s
+; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi ilp32f < %s 2>&1 \
+; RUN:   | FileCheck -check-prefix=RV64IF-ILP32F %s
+; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi ilp32d < %s 2>&1 \
+; RUN:   | FileCheck -check-prefix=RV64IFD-ILP32D %s
+; RUN: llc -mtriple=riscv64 -target-abi ilp32e < %s 2>&1 \
+; RUN:   | FileCheck -check-prefix=RV64I-ILP32E %s
+
+; RV64I-ILP32: 32-bit ABIs are not supported for 64-bit targets (ignoring target-abi)
+; RV64IF-ILP32F: 32-bit ABIs are not supported for 64-bit targets (ignoring target-abi)
+; RV64IFD-ILP32D: 32-bit ABIs are not supported for 64-bit targets (ignoring target-abi)
+; RV64I-ILP32E: 32-bit ABIs are not supported for 64-bit targets (ignoring target-abi)
+
+; RUN: llc -mtriple=riscv32 -target-abi lp64 < %s 2>&1 \
+; RUN:   | FileCheck -check-prefix=RV32I-LP64 %s
+; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi lp64f < %s 2>&1 \
+; RUN:   | FileCheck -check-prefix=RV32IF-LP64F %s
+; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi lp64d < %s 2>&1 \
+; RUN:   | FileCheck -check-prefix=RV32IFD-LP64D %s
+
+; RV32I-LP64: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
+; RV32IF-LP64F: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
+; RV32IFD-LP64D: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
+
+; RUN: llc -mtriple=riscv32 -target-abi ilp32f < %s 2>&1 \
+; RUN:   | FileCheck -check-prefix=RV32I-ILP32F %s
+; RUN: llc -mtriple=riscv64 -target-abi lp64f < %s 2>&1 \
+; RUN:   | FileCheck -check-prefix=RV64I-LP64F %s
+
+; RV32I-ILP32F: Hard-float 'f' ABI can't be used for a target that doesn't support the F instruction set extension (ignoring target-abi)
+; RV64I-LP64F: Hard-float 'f' ABI can't be used for a target that doesn't support the F instruction set extension (ignoring target-abi)
+
+; RUN: llc -mtriple=riscv32 -target-abi ilp32d < %s 2>&1 \
+; RUN:   | FileCheck -check-prefix=RV32I-ILP32D %s
+; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32d < %s 2>&1 \
+; RUN:   | FileCheck -check-prefix=RV32IF-ILP32D %s
+; RUN: llc -mtriple=riscv64 -target-abi lp64d < %s 2>&1 \
+; RUN:   | FileCheck -check-prefix=RV64I-LP64D %s
+; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64d < %s 2>&1 \
+; RUN:   | FileCheck -check-prefix=RV64IF-LP64D %s
+
+; RV32I-ILP32D: Hard-float 'd' ABI can't be used for a target that doesn't support the D instruction set extension (ignoring target-abi)
+; RV32IF-ILP32D: Hard-float 'd' ABI can't be used for a target that doesn't support the D instruction set extension (ignoring target-abi)
+; RV64I-LP64D: Hard-float 'd' ABI can't be used for a target that doesn't support the D instruction set extension (ignoring target-abi)
+; RV64IF-LP64D: Hard-float 'd' ABI can't be used for a target that doesn't support the D instruction set extension (ignoring target-abi)
+
+define void @nothing() nounwind {
+  ret void
+}

test/CodeGen/RISCV/target-abi-valid.ll

+; RUN: llc -mtriple=riscv32 < %s \
+; RUN:   | FileCheck -check-prefix=CHECK-IMP %s
+; RUN: llc -mtriple=riscv32 -target-abi ilp32 < %s \
+; RUN:   | FileCheck -check-prefix=CHECK-IMP %s
+; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32 < %s \
+; RUN:   | FileCheck -check-prefix=CHECK-IMP %s
+; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32 < %s \
+; RUN:   | FileCheck -check-prefix=CHECK-IMP %s
+; RUN: llc -mtriple=riscv64 < %s \
+; RUN:   | FileCheck -check-prefix=CHECK-IMP %s
+; RUN: llc -mtriple=riscv64 -target-abi lp64 < %s \
+; RUN:   | FileCheck -check-prefix=CHECK-IMP %s
+; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64 < %s \
+; RUN:   | FileCheck -check-prefix=CHECK-IMP %s
+; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64 < %s \
+; RUN:   | FileCheck -check-prefix=CHECK-IMP %s
+
+define void @nothing() nounwind {
+; CHECK-IMP-LABEL: nothing:
+; CHECK-IMP:       # %bb.0:
+; CHECK-IMP-NEXT:    ret
+  ret void
+}
+
+; RUN: not llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f < %s 2>&1 \
+; RUN:   | FileCheck -check-prefix=CHECK-UNIMP %s
+; RUN: not llc -mtriple=riscv32 -mattr=+d -target-abi ilp32f < %s 2>&1 \
+; RUN:   | FileCheck -check-prefix=CHECK-UNIMP %s
+; RUN: not llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d < %s 2>&1 \
+; RUN:   | FileCheck -check-prefix=CHECK-UNIMP %s
+; RUN: not llc -mtriple=riscv32 -target-abi ilp32e < %s 2>&1 \
+; RUN:   | FileCheck -check-prefix=CHECK-UNIMP %s
+; RUN: not llc -mtriple=riscv64 -mattr=+f -target-abi lp64f < %s 2>&1 \
+; RUN:   | FileCheck -check-prefix=CHECK-UNIMP %s
+; RUN: not llc -mtriple=riscv64 -mattr=+d -target-abi lp64f < %s 2>&1 \
+; RUN:   | FileCheck -check-prefix=CHECK-UNIMP %s
+; RUN: not llc -mtriple=riscv64 -mattr=+d -target-abi lp64d < %s 2>&1 \
+; RUN:   | FileCheck -check-prefix=CHECK-UNIMP %s
+
+; CHECK-UNIMP: LLVM ERROR: Don't know how to lower this ABI

test/MC/RISCV/target-abi-invalid.s

+# RUN: llvm-mc -triple=riscv32 -target-abi foo < %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=RV32I-FOO %s
+# RUN: llvm-mc -triple=riscv32 -mattr=+f -target-abi ilp32foof < %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=RV32IF-ILP32FOOF %s
+
+# RV32I-FOO: 'foo' is not a recognized ABI for this target (ignoring target-abi)
+# RV32IF-ILP32FOOF: 'ilp32foof' is not a recognized ABI for this target (ignoring target-abi)
+
+# RUN: llvm-mc -triple=riscv64 -target-abi ilp32 < %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=RV64I-ILP32 %s
+# RUN: llvm-mc -triple=riscv64 -mattr=+f -target-abi ilp32f < %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=RV64IF-ILP32F %s
+# RUN: llvm-mc -triple=riscv64 -mattr=+d -target-abi ilp32d < %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=RV64IFD-ILP32D %s
+# RUN: llvm-mc -triple=riscv64 -target-abi ilp32e < %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=RV64I-ILP32E %s
+
+# RV64I-ILP32: 32-bit ABIs are not supported for 64-bit targets (ignoring target-abi)
+# RV64IF-ILP32F: 32-bit ABIs are not supported for 64-bit targets (ignoring target-abi)
+# RV64IFD-ILP32D: 32-bit ABIs are not supported for 64-bit targets (ignoring target-abi)
+# RV64I-ILP32E: 32-bit ABIs are not supported for 64-bit targets (ignoring target-abi)
+
+# RUN: llvm-mc -triple=riscv32 -target-abi lp64 < %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=RV32I-LP64 %s
+# RUN: llvm-mc -triple=riscv32 -mattr=+f -target-abi lp64f < %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=RV32IF-LP64F %s
+# RUN: llvm-mc -triple=riscv32 -mattr=+d -target-abi lp64d < %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=RV32IFD-LP64D %s
+
+# RV32I-LP64: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
+# RV32IF-LP64F: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
+# RV32IFD-LP64D: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
+
+# RUN: llvm-mc -triple=riscv32 -target-abi ilp32f < %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=RV32I-ILP32F %s
+# RUN: llvm-mc -triple=riscv64 -target-abi lp64f < %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=RV64I-LP64F %s
+
+# RV32I-ILP32F: Hard-float 'f' ABI can't be used for a target that doesn't support the F instruction set extension (ignoring target-abi)
+# RV64I-LP64F: Hard-float 'f' ABI can't be used for a target that doesn't support the F instruction set extension (ignoring target-abi)
+
+# RUN: llvm-mc -triple=riscv32 -target-abi ilp32d < %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=RV32I-ILP32D %s
+# RUN: llvm-mc -triple=riscv32 -mattr=+f -target-abi ilp32d < %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=RV32IF-ILP32D %s
+# RUN: llvm-mc -triple=riscv64 -target-abi lp64d < %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=RV64I-LP64D %s
+# RUN: llvm-mc -triple=riscv64 -mattr=+f -target-abi lp64d < %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=RV64IF-LP64D %s
+
+# RV32I-ILP32D: Hard-float 'd' ABI can't be used for a target that doesn't support the D instruction set extension (ignoring target-abi)
+# RV32IF-ILP32D: Hard-float 'd' ABI can't be used for a target that doesn't support the D instruction set extension (ignoring target-abi)
+# RV64I-LP64D: Hard-float 'd' ABI can't be used for a target that doesn't support the D instruction set extension (ignoring target-abi)
+# RV64IF-LP64D: Hard-float 'd' ABI can't be used for a target that doesn't support the D instruction set extension (ignoring target-abi)
+
+nop

test/MC/RISCV/target-abi-valid.s

+# RUN: llvm-mc -triple=riscv32 -filetype=obj < %s \
+# RUN:   | llvm-readobj -file-headers - \
+# RUN:   | FileCheck -check-prefix=CHECK-NONE %s
+# RUN: llvm-mc -triple=riscv32 -target-abi ilp32 -filetype=obj < %s \
+# RUN:   | llvm-readobj -file-headers - \
+# RUN:   | FileCheck -check-prefix=CHECK-NONE %s
+# RUN: llvm-mc -triple=riscv32 -mattr=+f -target-abi ilp32 -filetype=obj < %s \
+# RUN:   | llvm-readobj -file-headers - \
+# RUN:   | FileCheck -check-prefix=CHECK-NONE %s
+# RUN: llvm-mc -triple=riscv32 -mattr=+d -target-abi ilp32 -filetype=obj < %s \
+# RUN:   | llvm-readobj -file-headers - \
+# RUN:   | FileCheck -check-prefix=CHECK-NONE %s
+# RUN: llvm-mc -triple=riscv64 -filetype=obj < %s \
+# RUN:   | llvm-readobj -file-headers - \
+# RUN:   | FileCheck -check-prefix=CHECK-NONE %s
+# RUN: llvm-mc -triple=riscv64 -target-abi lp64 -filetype=obj < %s \
+# RUN:   | llvm-readobj -file-headers - \
+# RUN:   | FileCheck -check-prefix=CHECK-NONE %s
+# RUN: llvm-mc -triple=riscv64 -mattr=+f -target-abi lp64 -filetype=obj < %s \
+# RUN:   | llvm-readobj -file-headers - \
+# RUN:   | FileCheck -check-prefix=CHECK-NONE %s
+# RUN: llvm-mc -triple=riscv64 -mattr=+d -target-abi lp64 -filetype=obj < %s \
+# RUN:   | llvm-readobj -file-headers - \
+# RUN:   | FileCheck -check-prefix=CHECK-NONE %s
+
+# RUN: llvm-mc -triple=riscv32 -mattr=+f -target-abi ilp32f -filetype=obj < %s \
+# RUN:   | llvm-readobj -file-headers - \
+# RUN:   | FileCheck -check-prefix=CHECK-FLOAT-SINGLE %s
+# RUN: llvm-mc -triple=riscv32 -mattr=+d -target-abi ilp32f -filetype=obj < %s \
+# RUN:   | llvm-readobj -file-headers - \
+# RUN:   | FileCheck -check-prefix=CHECK-FLOAT-SINGLE %s
+# RUN: llvm-mc -triple=riscv64 -mattr=+f -target-abi lp64f -filetype=obj < %s \
+# RUN:   | llvm-readobj -file-headers - \
+# RUN:   | FileCheck -check-prefix=CHECK-FLOAT-SINGLE %s
+# RUN: llvm-mc -triple=riscv64 -mattr=+d -target-abi lp64f -filetype=obj < %s \
+# RUN:   | llvm-readobj -file-headers - \
+# RUN:   | FileCheck -check-prefix=CHECK-FLOAT-SINGLE %s
+
+# RUN: llvm-mc -triple=riscv64 -mattr=+d -target-abi lp64d -filetype=obj < %s \
+# RUN:   | llvm-readobj -file-headers - \
+# RUN:   | FileCheck -check-prefix=CHECK-FLOAT-DOUBLE %s
+
+# RUN: llvm-mc -triple=riscv32 -target-abi ilp32e -filetype=obj < %s \
+# RUN:   | llvm-readobj -file-headers - \
+# RUN:   | FileCheck -check-prefix=CHECK-RVE %s
+
+# CHECK-NONE:               Flags [ (0x0)
+# CHECK-NONE-NEXT:          ]
+
+# CHECK-FLOAT-SINGLE:       Flags [ (0x2)
+# CHECK-FLOAT-SINGLE-NEXT:    EF_RISCV_FLOAT_ABI_SINGLE (0x2)
+# CHECK-FLOAT-SINGLE-NEXT:  ]
+
+# CHECK-FLOAT-DOUBLE:       Flags [ (0x4)
+# CHECK-FLOAT-DOUBLE-NEXT:    EF_RISCV_FLOAT_ABI_DOUBLE (0x4)
+# CHECK-FLOAT-DOUBLE-NEXT:  ]
+
+# CHECK-RVE:                Flags [ (0x8)
+# CHECK-RVE-NEXT:             EF_RISCV_RVE (0x8)
+# CHECK-RVE-NEXT:           ]
+
+nop