[ARM] [FIX] Restrict vfmal.f16 and vfmsl.f16 indexed version

[dnsampaio]

Summary

The indexed variant of vfmal.f16 and vfmsl.f16 q/d variations allows only d0 - d7 / s0 - s15 in the respective indexed operand.
Reference:
https://developer.arm.com/docs/ddi0597/b/simd-and-floating-point-instructions-alphabetic-order/vfmal-by-scalar-vector-floating-point-multiply-add-long-to-accumulator-by-scalar

Currently all registers are accepted, but the 2 / 1 upper bit[s] are / is ignored:

llvm-mc -triple arm -mattr=+fp16fml,+neon -show-encoding -o - -
vfmsl.f16       q0, d1, d0[0]
vfmsl.f16       q0, d1, d8[0]
vfmsl.f16       q0, d1, d16[0]
        .text
        vfmsl.f16       q0, d1, d0[0]   @ encoding: [0x50,0x08,0x11,0xfe]
        vfmsl.f16       q0, d1, d8[0]   @ encoding: [0x50,0x08,0x11,0xfe]
        vfmsl.f16       q0, d1, d16[0]  @ encoding: [0x50,0x08,0x11,0xfe]

vfmsl.f16       d0, s1, s0[0]
vfmsl.f16       d0, s1, s16[0]
        vfmsl.f16       d0, s1, s0[0]   @ encoding: [0x90,0x08,0x10,0xfe]
        vfmsl.f16       d0, s1, s16[0]  @ encoding: [0x90,0x08,0x10,0xfe]

This patch restrict the indexed operand to be between d0 - d7 and s0 - s15 ranges.

[dnsampaio]

I can just fix the existing class declaration.

[dnsampaio]

Fixed existing class.

[dnsampaio]

Added the D variant.

[dnsampaio]

Fixed DecodeDPRRegisterClass to DecodeDPRRegisterClass on the custom decoder.

[olista01]

LGTM

llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

class N3VCP8F16Q1<string asm, RegisterClass Td, RegisterClass Tn,
   : N3VCP8<op1, op2, 1, op3, (outs Td:$Vd), (ins Tn:$Vn, Tm:$Vm), NoItinerary,
            asm, "f16", "$Vd, $Vn, $Vm", "", []>;
 
 class N3VCP8F16Q0<string asm, RegisterClass Td, RegisterClass Tn,
                 RegisterClass Tm, bits<2> op1, bits<2> op2, bit op3>
   : N3VCP8Q0<op1, op2, 0, op3, (outs Td:$Vd), (ins Tn:$Vn, Tm:$Vm), NoItinerary,
            asm, "f16", "$Vd, $Vn, $Vm", "", []>;
 
-class VFMQ0<string opc, bits<2> S>
+// Vd, Vs, Vs[0-15], Idx[0-1]
+class VFMD<string opc, string type, bits<2> S>
   : N3VLaneCP8<0, S, 0, 1, (outs DPR:$Vd),
-               (ins SPR:$Vn, SPR:$Vm, VectorIndex32:$idx),
-               IIC_VMACD, opc, "f16", "$Vd, $Vn, $Vm$idx", "", []> {
+               (ins SPR:$Vn, SPR_8:$Vm, VectorIndex32:$idx),
+               IIC_VMACD, opc, type, "$Vd, $Vn, $Vm$idx", "", []> {
   bit idx;
   let Inst{3} = idx;
   let Inst{19-16} = Vn{4-1};
   let Inst{7}     = Vn{0};
   let Inst{5}     = Vm{0};
   let Inst{2-0}   = Vm{3-1};
 }
 
-class VFMQ1<string opc, bits<2> S>
+// Vq, Vd, Vd[0-7], Idx[0-3]
+class VFMQ<string opc, string type, bits<2> S>
   : N3VLaneCP8<0, S, 1, 1, (outs QPR:$Vd),
-               (ins DPR:$Vn, DPR:$Vm, VectorIndex16:$idx),
-               IIC_VMACD, opc, "f16", "$Vd, $Vn, $Vm$idx", "", []> {
+               (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$idx),
+               IIC_VMACD, opc, type, "$Vd, $Vn, $Vm$idx", "", []> {
   bits<2> idx;
   let Inst{5} = idx{1};
   let Inst{3} = idx{0};
 }
 
 let hasNoSchedulingInfo = 1 in {
 //                                                op1   op2   op3
 def VFMALD  : N3VCP8F16Q0<"vfmal", DPR, SPR, SPR, 0b00, 0b10, 1>;
 def VFMSLD  : N3VCP8F16Q0<"vfmsl", DPR, SPR, SPR, 0b01, 0b10, 1>;
 def VFMALQ  : N3VCP8F16Q1<"vfmal", QPR, DPR, DPR, 0b00, 0b10, 1>;
 def VFMSLQ  : N3VCP8F16Q1<"vfmsl", QPR, DPR, DPR, 0b01, 0b10, 1>;
-def VFMALDI : VFMQ0<"vfmal", 0b00>;
-def VFMSLDI : VFMQ0<"vfmsl", 0b01>;
-def VFMALQI : VFMQ1<"vfmal", 0b00>;
-def VFMSLQI : VFMQ1<"vfmsl", 0b01>;
+def VFMALDI : VFMD<"vfmal", "f16", 0b00>;
+def VFMSLDI : VFMD<"vfmsl", "f16", 0b01>;
+def VFMALQI : VFMQ<"vfmal", "f16", 0b00>;
+def VFMSLQI : VFMQ<"vfmsl", "f16", 0b01>;
 }
 } // HasNEON, HasFP16FML
 
 
 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vm",
                    (VACGTfd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vm",
                    (VACGTfq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;

llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
+                                   uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
                                                 unsigned RegNo,
                                                 uint64_t Address,
                                                 const void *Decoder);
 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);

 
 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder) {
   if (RegNo > 7)
     return MCDisassembler::Fail;
   return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
 }
 
+static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
+                                   uint64_t Address, const void *Decoder) {
+  if (RegNo > 15)
+    return MCDisassembler::Fail;
+  return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
+}
+
 static DecodeStatus
 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
                             uint64_t Address, const void *Decoder) {
   if (RegNo > 15)
     return MCDisassembler::Fail;
   return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
 }
 

llvm/trunk/test/MC/ARM/armv8a-fpmul-error.s

 // RUN: not llvm-mc -triple arm -mattr=+fp16fml,+neon -show-encoding < %s 2>&1 | FileCheck %s  --check-prefix=CHECK-ERROR
 
 VFMAL.F16 D0, S1, S2[2]
 vfmsl.f16 d0, s1, s2[2]
 vfmsl.f16 d0, s1, s2[-1]
 vfmal.f16 q0, d1, d2[4]
 VFMSL.F16 Q0, D1, D2[4]
 vfmal.f16 q0, d1, d2[-1]
+VFMSL.F16 D0, S1, S16[0]
+vfmal.f16 d0, s1, s16[0]
+VFMSL.F16 Q0, D1, D8[0]
+vfmal.f16 q0, d1, d8[0]
 
 //CHECK-ERROR:      error: invalid operand for instruction
 //CHECK-ERROR-NEXT: VFMAL.F16 D0, S1, S2[2]
 //CHECK-ERROR-NEXT:                     ^
 //CHECK-ERROR-NEXT: error: invalid operand for instruction
 //CHECK-ERROR-NEXT: vfmsl.f16 d0, s1, s2[2]
 //CHECK-ERROR-NEXT:                     ^
 //CHECK-ERROR-NEXT: error: invalid operand for instruction
 //CHECK-ERROR-NEXT: vfmsl.f16 d0, s1, s2[-1]
 //CHECK-ERROR-NEXT:                     ^
 //CHECK-ERROR-NEXT: error: invalid operand for instruction
 //CHECK-ERROR-NEXT: vfmal.f16 q0, d1, d2[4]
 //CHECK-ERROR-NEXT:                     ^
 //CHECK-ERROR-NEXT: error: invalid operand for instruction
 //CHECK-ERROR-NEXT: VFMSL.F16 Q0, D1, D2[4]
 //CHECK-ERROR-NEXT:                     ^
 //CHECK-ERROR-NEXT: error: invalid operand for instruction
 //CHECK-ERROR-NEXT: vfmal.f16 q0, d1, d2[-1]
 //CHECK-ERROR-NEXT:                     ^
+//CHECK-ERROR-NEXT: error: invalid instruction, any one of the following would fix this:
+//CHECK-ERROR-NEXT: VFMSL.F16 D0, S1, S16[0]
+//CHECK-ERROR-NEXT: ^
+//CHECK-ERROR-NEXT: note: operand must be a register in range [s0, s15]
+//CHECK-ERROR-NEXT: VFMSL.F16 D0, S1, S16[0]
+//CHECK-ERROR-NEXT:                   ^
+//CHECK-ERROR-NEXT: note: too many operands for instruction
+//CHECK-ERROR-NEXT: VFMSL.F16 D0, S1, S16[0]
+//CHECK-ERROR-NEXT:                      ^
+//CHECK-ERROR-NEXT: error: invalid instruction, any one of the following would fix this:
+//CHECK-ERROR-NEXT: vfmal.f16 d0, s1, s16[0]
+//CHECK-ERROR-NEXT: ^
+//CHECK-ERROR-NEXT: note: operand must be a register in range [s0, s15]
+//CHECK-ERROR-NEXT: vfmal.f16 d0, s1, s16[0]
+//CHECK-ERROR-NEXT:                   ^
+//CHECK-ERROR-NEXT: note: too many operands for instruction
+//CHECK-ERROR-NEXT: vfmal.f16 d0, s1, s16[0]
+//CHECK-ERROR-NEXT:                      ^
+//CHECK-ERROR-NEXT: : error: invalid instruction, any one of the following would fix this:
+//CHECK-ERROR-NEXT: VFMSL.F16 Q0, D1, D8[0]
+//CHECK-ERROR-NEXT: ^
+//CHECK-ERROR-NEXT: : note: operand must be a register in range [d0, d7]
+//CHECK-ERROR-NEXT: VFMSL.F16 Q0, D1, D8[0]
+//CHECK-ERROR-NEXT:                   ^
+//CHECK-ERROR-NEXT: : note: too many operands for instruction
+//CHECK-ERROR-NEXT: VFMSL.F16 Q0, D1, D8[0]
+//CHECK-ERROR-NEXT:                     ^
+//CHECK-ERROR-NEXT: : error: invalid instruction, any one of the following would fix this:
+//CHECK-ERROR-NEXT: vfmal.f16 q0, d1, d8[0]
+//CHECK-ERROR-NEXT: ^
+//CHECK-ERROR-NEXT: : note: operand must be a register in range [d0, d7]
+//CHECK-ERROR-NEXT: vfmal.f16 q0, d1, d8[0]
+//CHECK-ERROR-NEXT:                   ^
+//CHECK-ERROR-NEXT: 1: note: too many operands for instruction
+//CHECK-ERROR-NEXT: vfmal.f16 q0, d1, d8[0]
+//CHECK-ERROR-NEXT:                     ^