[MIPS GlobalISel] NarrowScalar G_SMULH

[Petar.Avramovic]

Summary

NarrowScalar G_SMULH in LegalizerHelper using MultiplyRegisters helper function.
NarrowScalar G_SMULH for MIPS32.

[Petar.Avramovic]

We need to wait for NarrowScalar of G_SEXT and G_ZEXT and for perfecting artifact legalization
(since here it depends in which order we attempt to combine artifacts that are chained).

[atanasyan]

Could you rebase the patch?

[Petar.Avramovic]

Rebased

[atanasyan]

lib/Target/Mips/MipsInstructionSelector.cpp

152

Join declaration and initialization.

161

ditto

[Petar.Avramovic]

Addressed review comments.

[arsenm]

Needs a test. This may need the -gisel-abort=0 trick to hack around the artifact issues

[Petar.Avramovic]

I added this patch to show how we can handle G_SMULH in narrowScalarMul, will add the test in the future.

lib/CodeGen/GlobalISel/LegalizerHelper.cpp

for (int i = 1; i < NumParts; ++i) {
       BorrowIn = BorrowOut;
     }
     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
     MI.eraseFromParent();
     return Legalized;
   }
   case TargetOpcode::G_MUL:
   case TargetOpcode::G_UMULH:
+  case TargetOpcode::G_SMULH:
     return narrowScalarMul(MI, NarrowTy);
   case TargetOpcode::G_EXTRACT:
     return narrowScalarExtract(MI, TypeIdx, NarrowTy);
   case TargetOpcode::G_INSERT:
     return narrowScalarInsert(MI, TypeIdx, NarrowTy);
   case TargetOpcode::G_LOAD: {
     const auto &MMO = **MI.memoperands_begin();
     unsigned DstReg = MI.getOperand(0).getReg();
LegalizerHelper::narrowScalarMul(MachineInstr &MI, LLT NarrowTy) {
   unsigned SrcSize = MRI.getType(Src1).getSizeInBits();
   unsigned DstSize = Ty.getSizeInBits();
   unsigned NarrowSize = NarrowTy.getSizeInBits();
   if (DstSize % NarrowSize != 0 || SrcSize % NarrowSize != 0)
     return UnableToLegalize;
 
   unsigned NumDstParts = DstSize / NarrowSize;
   unsigned NumSrcParts = SrcSize / NarrowSize;
-  bool IsMulHigh = MI.getOpcode() == TargetOpcode::G_UMULH;
+  bool IsMulHigh = MI.getOpcode() == TargetOpcode::G_UMULH ||
+                   MI.getOpcode() == TargetOpcode::G_SMULH;
   unsigned DstTmpParts = NumDstParts * (IsMulHigh ? 2 : 1);
 
   SmallVector<unsigned, 2> Src1Parts, Src2Parts, DstTmpRegs;
+  if (MI.getOpcode() == TargetOpcode::G_SMULH) {
+    LLT SextTy = LLT::scalar(SrcSize * 2);
+    Src1 = MRI.createGenericVirtualRegister(SextTy);
+    Src2 = MRI.createGenericVirtualRegister(SextTy);
+    MIRBuilder.buildSExt(Src1, MI.getOperand(1).getReg());
+    MIRBuilder.buildSExt(Src2, MI.getOperand(2).getReg());
+  }
   extractParts(Src1, NarrowTy, NumSrcParts, Src1Parts);
   extractParts(Src2, NarrowTy, NumSrcParts, Src2Parts);
   DstTmpRegs.resize(DstTmpParts);
   MultiplyRegisters(DstTmpRegs, Src1Parts, Src2Parts, NarrowTy);
 
   // Take only high half of registers if this is high mul.
   ArrayRef<unsigned> DstRegs(
       IsMulHigh ? &DstTmpRegs[DstTmpParts / 2] : &DstTmpRegs[0], NumDstParts);
   MIRBuilder.buildMerge(DstReg, DstRegs);
-
   MI.eraseFromParent();
   return Legalized;
 }
 
 LegalizerHelper::LegalizeResult
 LegalizerHelper::narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx,
                                      LLT NarrowTy) {
   if (TypeIdx != 1)

lib/Target/Mips/MipsInstructionSelector.cpp

if (selectImpl(I, CoverageInfo)) {
     }
     return true;
   }
 
   MachineInstr *MI = nullptr;
   using namespace TargetOpcode;
 
   switch (I.getOpcode()) {
-  case G_UMULH: {
-    unsigned PseudoMULTuReg = MRI.createVirtualRegister(&Mips::ACC64RegClass);
-    MachineInstr *PseudoMULTu, *PseudoMove;
-
-    PseudoMULTu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMULTu))
-                      .addDef(PseudoMULTuReg)
-                      .add(I.getOperand(1))
-                      .add(I.getOperand(2));
-    if (!constrainSelectedInstRegOperands(*PseudoMULTu, TII, TRI, RBI))
+  case G_UMULH:
+  case G_SMULH: {
+    unsigned PseudoMULReg = MRI.createVirtualRegister(&Mips::ACC64RegClass);
+    bool IsSigned = I.getOpcode() == TargetOpcode::G_SMULH;
+    MachineInstr *PseudoMUL, *PseudoMove;
+
+    PseudoMUL =
+        BuildMI(MBB, I, I.getDebugLoc(),
+                TII.get(IsSigned ? Mips::PseudoMULT : Mips::PseudoMULTu))
+            .addDef(PseudoMULReg)
+    if (!constrainSelectedInstRegOperands(*PseudoMUL, TII, TRI, RBI))
       return false;
 
     PseudoMove = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMFHI))
                      .addDef(I.getOperand(0).getReg())
-                     .addUse(PseudoMULTuReg);
+                     .addUse(PseudoMULReg);
     if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI))
       return false;
 
     I.eraseFromParent();
     return true;
   }
   case G_GEP: {
     MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu))

lib/Target/Mips/MipsLegalizerInfo.cpp

MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
 
   getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL})
       .legalFor({s32})
       .clampScalar(0, s32, s32);
 
   getActionDefinitionsBuilder({G_UADDO, G_UADDE, G_USUBO, G_USUBE, G_UMULO})
       .lowerFor({{s32, s1}});
 
-  getActionDefinitionsBuilder(G_UMULH)
+  getActionDefinitionsBuilder({G_UMULH, G_SMULH})
       .legalFor({s32})
       .maxScalar(0, s32);
 
   getActionDefinitionsBuilder({G_LOAD, G_STORE})
       .legalForTypesWithMemDesc({{s32, p0, 8, 8},
                                  {s32, p0, 16, 8},
                                  {s32, p0, 32, 8},
                                  {p0, p0, 32, 8}})

lib/Target/Mips/MipsRegisterBankInfo.cpp

MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   const ValueMapping *OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
 
   switch (Opc) {
   case G_TRUNC:
   case G_ADD:
   case G_SUB:
   case G_MUL:
   case G_UMULH:
+  case G_SMULH:
   case G_LOAD:
   case G_STORE:
   case G_ZEXTLOAD:
   case G_SEXTLOAD:
   case G_GEP:
   case G_AND:
   case G_OR:
   case G_XOR: