[PowerPC] exploit P9 new instruction maddld

[shchenz]

Summary

typedef long long T;
T foo(T a, T b)
{
    return a*b+a;
}

on Power8 we get:

0000000000000000 <foo>:
   0:   d2 19 84 7c     mulld   r4,r4,r3
   4:   14 1a 64 7c     add     r3,r4,r3
   8:   20 00 80 4e     blr

On power9 we can fold add + mulld to maddld

[nemanjai]

LGTM once the minor nits are addressed.

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

779 ↗

(On Diff #187289)

Here and below, it looks like the lines are too long. Please keep them to 80 columns.

llvm/test/CodeGen/PowerPC/maddld.ll

5 ↗

(On Diff #187289)

It would perhaps be nice to make one of these use 3 different registers (i.e. by taking 3 parameters).

[shchenz]

address comments

llvm/trunk/lib/Target/PowerPC/P9InstrResources.td

def : InstRW<[P9_DPE_7C, P9_DPO_7C, IP_EXECE_1C, IP_EXECO_1C,
     VSUMSWS
 )>;
 
 
 // 5 cycle Restricted DP operation. One DP unit, one EXEC pipeline and all three
 //  dispatch units for the superslice.
 def : InstRW<[P9_DP_5C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
       (instrs
-    (instregex "MADD(HD|HDU|LD)$"),
+    (instregex "MADD(HD|HDU|LD|LD8)$"),
     (instregex "MUL(HD|HW|LD|LI|LI8|LW)(U)?$")
 )>;
 
 // 7 cycle Restricted DP operation. One DP unit, one EXEC pipeline and all three
 //  dispatch units for the superslice.
 def : InstRW<[P9_DP_7C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
       (instrs
     FRSP,

llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td

 def DIVDE : XOForm_1<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
                      "divde $rT, $rA, $rB", IIC_IntDivD,
                      [(set i64:$rT, (int_ppc_divde g8rc:$rA, g8rc:$rB))]>,
                      isPPC64, Requires<[HasExtDiv]>;
 
 let Predicates = [IsISA3_0] in {
 def MADDHD : VAForm_1a<48, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
                        "maddhd $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64;
-def MADDHDU : VAForm_1a<49, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
+def MADDHDU : VAForm_1a<49, 
+                       (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
                        "maddhdu $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64;
-def MADDLD : VAForm_1a<51, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
-                       "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64;
+def MADDLD : VAForm_1a<51, (outs gprc :$RT), (ins gprc:$RA, gprc:$RB, gprc:$RC),
+                       "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD,
+                       [(set i32:$RT, (add (mul i32:$RA, i32:$RB), i32:$RC))]>,
+                       isPPC64;
 def SETB : XForm_44<31, 128, (outs gprc:$RT), (ins crrc:$BFA),
                        "setb $RT, $BFA", IIC_IntGeneral>, isPPC64;
 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
+  def MADDLD8 : VAForm_1a<51, 
+                       (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
+                       "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD,
+                       [(set i64:$RT, (add (mul i64:$RA, i64:$RB), i64:$RC))]>,
+                       isPPC64;
   def SETB8 : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA),
                        "setb $RT, $BFA", IIC_IntGeneral>, isPPC64;
 }
 def DARN : XForm_45<31, 755, (outs g8rc:$RT), (ins i32imm:$L),
                      "darn $RT, $L", IIC_LdStLD>, isPPC64;
 def ADDPCIS : DXForm<19, 2, (outs g8rc:$RT), (ins i32imm:$D),
                      "addpcis $RT, $D", IIC_BrB, []>, isPPC64;
 def MODSD : XForm_8<31, 777, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),

llvm/trunk/test/CodeGen/PowerPC/maddld.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=CHECK-P9
+; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=CHECK-P8
+
+define signext i64 @maddld64(i64 signext %a, i64 signext %b) {
+; CHECK-P9-LABEL: maddld64:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    maddld 3, 4, 3, 3
+; CHECK-P9-NEXT:    blr
+;
+; CHECK-P8-LABEL: maddld64:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    mulld 4, 4, 3
+; CHECK-P8-NEXT:    add 3, 4, 3
+; CHECK-P8-NEXT:    blr
+entry:
+  %mul = mul i64 %b, %a
+  %add = add i64 %mul, %a
+  ret i64 %add
+}
+
+define signext i32 @maddld32(i32 signext %a, i32 signext %b) {
+; CHECK-P9-LABEL: maddld32:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    maddld 3, 4, 3, 3
+; CHECK-P9-NEXT:    extsw 3, 3
+; CHECK-P9-NEXT:    blr
+;
+; CHECK-P8-LABEL: maddld32:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    mullw 4, 4, 3
+; CHECK-P8-NEXT:    add 3, 4, 3
+; CHECK-P8-NEXT:    extsw 3, 3
+; CHECK-P8-NEXT:    blr
+entry:
+  %mul = mul i32 %b, %a
+  %add = add i32 %mul, %a
+  ret i32 %add
+}
+
+define signext i16 @maddld16(i16 signext %a, i16 signext %b, i16 signext %c) {
+; CHECK-P9-LABEL: maddld16:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    maddld 3, 4, 3, 5
+; CHECK-P9-NEXT:    extsh 3, 3
+; CHECK-P9-NEXT:    blr
+;
+; CHECK-P8-LABEL: maddld16:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    mullw 3, 4, 3
+; CHECK-P8-NEXT:    add 3, 3, 5 
+; CHECK-P8-NEXT:    extsh 3, 3
+; CHECK-P8-NEXT:    blr
+entry:
+  %mul = mul i16 %b, %a
+  %add = add i16 %mul, %c
+  ret i16 %add
+}
+
+define zeroext i32 @maddld32zeroext(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-P9-LABEL: maddld32zeroext:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    maddld 3, 4, 3, 3
+; CHECK-P9-NEXT:    clrldi 3, 3, 32
+; CHECK-P9-NEXT:    blr
+;
+; CHECK-P8-LABEL: maddld32zeroext:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    mullw 4, 4, 3
+; CHECK-P8-NEXT:    add 3, 4, 3
+; CHECK-P8-NEXT:    clrldi 3, 3, 32
+; CHECK-P8-NEXT:    blr
+entry:
+  %mul = mul i32 %b, %a
+  %add = add i32 %mul, %a
+  ret i32 %add
+}
+
+define signext i32 @maddld32nsw(i32 signext %a, i32 signext %b) {
+; CHECK-P9-LABEL: maddld32nsw:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    maddld 3, 4, 3, 3
+; CHECK-P9-NEXT:    extsw 3, 3
+; CHECK-P9-NEXT:    blr
+;
+; CHECK-P8-LABEL: maddld32nsw:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    mullw 4, 4, 3
+; CHECK-P8-NEXT:    add 3, 4, 3
+; CHECK-P8-NEXT:    extsw 3, 3
+; CHECK-P8-NEXT:    blr
+entry:
+  %mul = mul nsw i32 %b, %a
+  %add = add nsw i32 %mul, %a
+  ret i32 %add
+}
+
+define zeroext i32 @maddld32nuw(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-P9-LABEL: maddld32nuw:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    maddld 3, 4, 3, 3
+; CHECK-P9-NEXT:    clrldi 3, 3, 32
+; CHECK-P9-NEXT:    blr
+;
+; CHECK-P8-LABEL: maddld32nuw:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    mullw 4, 4, 3
+; CHECK-P8-NEXT:    add 3, 4, 3
+; CHECK-P8-NEXT:    clrldi 3, 3, 32
+; CHECK-P8-NEXT:    blr
+entry:
+  %mul = mul nuw i32 %b, %a
+  %add = add nuw i32 %mul, %a
+  ret i32 %add
+}