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[AMDGPU][MC] Added register size check for VOP3/SDWA/DPP operands
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Authored by dp on Feb 15 2019, 9:01 AM.

Details

Summary

See bug 37943: https://bugs.llvm.org/show_bug.cgi?id=37943

It turned out that the issue affects VOP3/SDWA/DPP operands.

Examples of code which should trigger errors:

v_add_f32 v0, s[0:1], v0
v_add_f32_sdwa v0, s[0:1], v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
v_add_f32_dpp v5, v[1:2], v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0

Diff Detail

Repository
rL LLVM

Event Timeline

dp created this revision.Feb 15 2019, 9:01 AM
arsenm accepted this revision.Feb 22 2019, 7:08 AM

LGTM

This revision is now accepted and ready to land.Feb 22 2019, 7:08 AM
This revision was automatically updated to reflect the committed changes.
Herald added a project: Restricted Project. · View Herald TranscriptFeb 27 2019, 5:58 AM