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Differential D58182

[MIPS GlobalISel] Select branch instructions
ClosedPublic

Authored by Petar.Avramovic on Feb 13 2019, 7:30 AM.

Details

Reviewers
atanasyan
petarj
Commits
rG5d9b8eed85e5: [MIPS GlobalISel] Select branch instructions
rL354022: [MIPS GlobalISel] Select branch instructions
Summary

Select G_BR and G_BRCOND for MIPS32.
Unconditional branch G_BR does not have register operand,
for that reason we only add tests.
Since conditional branch G_BRCOND compares register to zero on MIPS32,
explicit extension must be performed on i1 condition in order to set
high bits to appropriate value.

Diff Detail

Repository
rL LLVM

Event Timeline

Petar.Avramovic created this revision.Feb 13 2019, 7:30 AM
Herald added subscribers: jdoerfert, volkan, arichardson and 3 others. · View Herald TranscriptFeb 13 2019, 7:30 AM
Petar.Avramovic added a child revision: D58183: [MIPS GlobalISel] Select phi instruction for integers .Feb 13 2019, 7:32 AM
atanasyan accepted this revision.Feb 14 2019, 2:33 AM

LGTM

This revision is now accepted and ready to land.Feb 14 2019, 2:33 AM
Closed by commit rL354022: [MIPS GlobalISel] Select branch instructions (authored by Petar.Avramovic). · Explain WhyFeb 14 2019, 3:39 AM
This revision was automatically updated to reflect the committed changes.
Herald added a project: Restricted Project. · View Herald TranscriptFeb 14 2019, 3:39 AM
Herald added subscribers: llvm-commits, jrtc27. · View Herald Transcript

Revision Contents

PathSize
llvm/
trunk/
lib/
CodeGen/
GlobalISel/
2 lines
Target/
Mips/
7 lines
4 lines
1 line
test/
CodeGen/
Mips/
GlobalISel/
instruction-select/
105 lines
legalizer/
100 lines
llvm-ir/
58 lines
regbankselect/
103 lines

Diff 186811

llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Show First 20 Lines • Show All 1,170 Lines • ▼ Show 20 LinesLegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
case TargetOpcode::G_IMPLICIT_DEF: { case TargetOpcode::G_IMPLICIT_DEF: {
Observer.changingInstr(MI); Observer.changingInstr(MI);
widenScalarDst(MI, WideTy); widenScalarDst(MI, WideTy);
Observer.changedInstr(MI); Observer.changedInstr(MI);
return Legalized; return Legalized;
} }
case TargetOpcode::G_BRCOND: case TargetOpcode::G_BRCOND:
Observer.changingInstr(MI); Observer.changingInstr(MI);
widenScalarSrc(MI, WideTy, 0, TargetOpcode::G_ANYEXT); widenScalarSrc(MI, WideTy, 0, MIRBuilder.getBoolExtOp(false, false));
Observer.changedInstr(MI); Observer.changedInstr(MI);
return Legalized; return Legalized;
case TargetOpcode::G_FCMP: case TargetOpcode::G_FCMP:
Observer.changingInstr(MI); Observer.changingInstr(MI);
if (TypeIdx == 0) if (TypeIdx == 0)
widenScalarDst(MI, WideTy); widenScalarDst(MI, WideTy);
else { else {
▲ Show 20 Lines • Show All 1,480 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp

Show First 20 Lines • Show All 147 Lines • ▼ Show 20 Linesbool MipsInstructionSelector::select(MachineInstr &I,
} }
case G_FRAME_INDEX: { case G_FRAME_INDEX: {
MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
.add(I.getOperand(0)) .add(I.getOperand(0))
.add(I.getOperand(1)) .add(I.getOperand(1))
.addImm(0); .addImm(0);
break; break;
} }
case G_BRCOND: {
MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::BNE))
.add(I.getOperand(0))
.addUse(Mips::ZERO)
.add(I.getOperand(1));
break;
}
case G_STORE: case G_STORE:
case G_LOAD: case G_LOAD:
case G_ZEXTLOAD: case G_ZEXTLOAD:
case G_SEXTLOAD: { case G_SEXTLOAD: {
const unsigned DestReg = I.getOperand(0).getReg(); const unsigned DestReg = I.getOperand(0).getReg();
const unsigned DestRegBank = RBI.getRegBank(DestReg, MRI, TRI)->getID(); const unsigned DestRegBank = RBI.getRegBank(DestReg, MRI, TRI)->getID();
const unsigned OpSize = MRI.getType(DestReg).getSizeInBits(); const unsigned OpSize = MRI.getType(DestReg).getSizeInBits();
const unsigned OpMemSizeInBytes = (*I.memoperands_begin())->getSize(); const unsigned OpMemSizeInBytes = (*I.memoperands_begin())->getSize();
▲ Show 20 Lines • Show All 195 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp

Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Lines getActionDefinitionsBuilder({G_ZEXTLOAD, G_SEXTLOAD})
{s32, p0, 16}}) {s32, p0, 16}})
.minScalar(0, s32); .minScalar(0, s32);
getActionDefinitionsBuilder(G_SELECT) getActionDefinitionsBuilder(G_SELECT)
.legalForCartesianProduct({p0, s32}, {s32}) .legalForCartesianProduct({p0, s32}, {s32})
.minScalar(0, s32) .minScalar(0, s32)
.minScalar(1, s32); .minScalar(1, s32);
getActionDefinitionsBuilder(G_BRCOND)
.legalFor({s32})
.minScalar(0, s32);
getActionDefinitionsBuilder({G_AND, G_OR, G_XOR}) getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
.legalFor({s32}) .legalFor({s32})
.clampScalar(0, s32, s32); .clampScalar(0, s32, s32);
getActionDefinitionsBuilder({G_SDIV, G_SREM, G_UREM, G_UDIV}) getActionDefinitionsBuilder({G_SDIV, G_SREM, G_UREM, G_UDIV})
.legalFor({s32}) .legalFor({s32})
.minScalar(0, s32) .minScalar(0, s32)
.libcallFor({s64}); .libcallFor({s64});
Show All 37 Lines

llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp

Show First 20 Lines • Show All 100 Lines • ▼ Show 20 LinesMipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case G_UDIV: case G_UDIV:
case G_SREM: case G_SREM:
case G_UREM: case G_UREM:
OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx]; OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
break; break;
case G_CONSTANT: case G_CONSTANT:
case G_FRAME_INDEX: case G_FRAME_INDEX:
case G_GLOBAL_VALUE: case G_GLOBAL_VALUE:
case G_BRCOND:
OperandsMapping = OperandsMapping =
getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr}); getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr});
break; break;
case G_ICMP: case G_ICMP:
OperandsMapping = OperandsMapping =
getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr, getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr,
&Mips::ValueMappings[Mips::GPRIdx], &Mips::ValueMappings[Mips::GPRIdx],
&Mips::ValueMappings[Mips::GPRIdx]}); &Mips::ValueMappings[Mips::GPRIdx]});
Show All 15 Lines

llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/branch.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define i32 @Unconditional_branch(i32 %a, i32 %b) {
entry:
br label %block
end: ; preds = %block
ret i32 %a
block: ; preds = %entry
br label %end
}
define i32 @Conditional_branch(i1 %cond, i32 %a, i32 %b) {
br i1 %cond, label %if.then, label %if.else
if.then: ; preds = %0
ret i32 %a
if.else: ; preds = %0
ret i32 %b
}
...
---
name: Unconditional_branch
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
; MIPS32-LABEL: name: Unconditional_branch
; MIPS32: bb.0.entry:
; MIPS32: successors: %bb.2(0x80000000)
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: J %bb.2, implicit-def $at
; MIPS32: bb.1.end:
; MIPS32: $v0 = COPY [[COPY]]
; MIPS32: RetRA implicit $v0
; MIPS32: bb.2.block:
; MIPS32: successors: %bb.1(0x80000000)
; MIPS32: J %bb.1, implicit-def $at
bb.1.entry:
liveins: $a0, $a1
%0:gprb(s32) = COPY $a0
G_BR %bb.3
bb.2.end:
$v0 = COPY %0(s32)
RetRA implicit $v0
bb.3.block:
G_BR %bb.2
...
---
name: Conditional_branch
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
; MIPS32-LABEL: name: Conditional_branch
; MIPS32: bb.0 (%ir-block.0):
; MIPS32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; MIPS32: liveins: $a0, $a1, $a2
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
; MIPS32: BNE [[AND]], $zero, %bb.1, implicit-def $at
; MIPS32: J %bb.2, implicit-def $at
; MIPS32: bb.1.if.then:
; MIPS32: $v0 = COPY [[COPY1]]
; MIPS32: RetRA implicit $v0
; MIPS32: bb.2.if.else:
; MIPS32: $v0 = COPY [[COPY2]]
; MIPS32: RetRA implicit $v0
bb.1 (%ir-block.0):
liveins: $a0, $a1, $a2
%3:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
%2:gprb(s32) = COPY $a2
%5:gprb(s32) = G_CONSTANT i32 1
%6:gprb(s32) = COPY %3(s32)
%4:gprb(s32) = G_AND %6, %5
G_BRCOND %4(s32), %bb.2
G_BR %bb.3
bb.2.if.then:
$v0 = COPY %1(s32)
RetRA implicit $v0
bb.3.if.else:
$v0 = COPY %2(s32)
RetRA implicit $v0
...

llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/branch.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define i32 @Unconditional_branch(i32 %a, i32 %b) {
entry:
br label %block
end: ; preds = %block
ret i32 %a
block: ; preds = %entry
br label %end
}
define i32 @Conditional_branch(i1 %cond, i32 %a, i32 %b) {
br i1 %cond, label %if.then, label %if.else
if.then: ; preds = %0
ret i32 %a
if.else: ; preds = %0
ret i32 %b
}
...
---
name: Unconditional_branch
alignment: 2
tracksRegLiveness: true
body: |
; MIPS32-LABEL: name: Unconditional_branch
; MIPS32: bb.0.entry:
; MIPS32: successors: %bb.2(0x80000000)
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: G_BR %bb.2
; MIPS32: bb.1.end:
; MIPS32: $v0 = COPY [[COPY]](s32)
; MIPS32: RetRA implicit $v0
; MIPS32: bb.2.block:
; MIPS32: successors: %bb.1(0x80000000)
; MIPS32: G_BR %bb.1
bb.1.entry:
liveins: $a0, $a1
%0:_(s32) = COPY $a0
G_BR %bb.3
bb.2.end:
$v0 = COPY %0(s32)
RetRA implicit $v0
bb.3.block:
G_BR %bb.2
...
---
name: Conditional_branch
alignment: 2
tracksRegLiveness: true
body: |
; MIPS32-LABEL: name: Conditional_branch
; MIPS32: bb.0 (%ir-block.0):
; MIPS32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; MIPS32: liveins: $a0, $a1, $a2
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; MIPS32: G_BRCOND [[AND]](s32), %bb.1
; MIPS32: G_BR %bb.2
; MIPS32: bb.1.if.then:
; MIPS32: $v0 = COPY [[COPY1]](s32)
; MIPS32: RetRA implicit $v0
; MIPS32: bb.2.if.else:
; MIPS32: $v0 = COPY [[COPY2]](s32)
; MIPS32: RetRA implicit $v0
bb.1 (%ir-block.0):
liveins: $a0, $a1, $a2
%3:_(s32) = COPY $a0
%0:_(s1) = G_TRUNC %3(s32)
%1:_(s32) = COPY $a1
%2:_(s32) = COPY $a2
G_BRCOND %0(s1), %bb.2
G_BR %bb.3
bb.2.if.then:
$v0 = COPY %1(s32)
RetRA implicit $v0
bb.3.if.else:
$v0 = COPY %2(s32)
RetRA implicit $v0
...

llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/branch.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
define i32 @Unconditional_branch(i32 %a, i32 %b) {
; MIPS32-LABEL: Unconditional_branch:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -8
; MIPS32-NEXT: .cfi_def_cfa_offset 8
; MIPS32-NEXT: sw $4, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB0_2
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_1: # %end
; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 8
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_2: # %block
; MIPS32-NEXT: j $BB0_1
; MIPS32-NEXT: nop
entry:
br label %block
ret i32 %b
end:
ret i32 %a
block:
br label %end
}
define i32 @Conditional_branch(i1 %cond, i32 %a, i32 %b) {
; MIPS32-LABEL: Conditional_branch:
; MIPS32: # %bb.0:
; MIPS32-NEXT: addiu $sp, $sp, -8
; MIPS32-NEXT: .cfi_def_cfa_offset 8
; MIPS32-NEXT: lui $1, 0
; MIPS32-NEXT: ori $1, $1, 1
; MIPS32-NEXT: and $1, $4, $1
; MIPS32-NEXT: sw $5, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 0($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $1, $BB1_2
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.1:
; MIPS32-NEXT: j $BB1_3
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB1_2: # %if.then
; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 8
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB1_3: # %if.else
; MIPS32-NEXT: lw $2, 0($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 8
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
br i1 %cond, label %if.then, label %if.else
if.then:
ret i32 %a
if.else:
ret i32 %b
}

llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/branch.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define i32 @Unconditional_branch(i32 %a, i32 %b) {
entry:
br label %block
end: ; preds = %block
ret i32 %a
block: ; preds = %entry
br label %end
}
define i32 @Conditional_branch(i1 %cond, i32 %a, i32 %b) {
br i1 %cond, label %if.then, label %if.else
if.then: ; preds = %0
ret i32 %a
if.else: ; preds = %0
ret i32 %b
}
...
---
name: Unconditional_branch
alignment: 2
legalized: true
tracksRegLiveness: true
body: |
; MIPS32-LABEL: name: Unconditional_branch
; MIPS32: bb.0.entry:
; MIPS32: successors: %bb.2(0x80000000)
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: G_BR %bb.2
; MIPS32: bb.1.end:
; MIPS32: $v0 = COPY [[COPY]](s32)
; MIPS32: RetRA implicit $v0
; MIPS32: bb.2.block:
; MIPS32: successors: %bb.1(0x80000000)
; MIPS32: G_BR %bb.1
bb.1.entry:
liveins: $a0, $a1
%0:_(s32) = COPY $a0
G_BR %bb.3
bb.2.end:
$v0 = COPY %0(s32)
RetRA implicit $v0
bb.3.block:
G_BR %bb.2
...
---
name: Conditional_branch
alignment: 2
legalized: true
tracksRegLiveness: true
body: |
; MIPS32-LABEL: name: Conditional_branch
; MIPS32: bb.0 (%ir-block.0):
; MIPS32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; MIPS32: liveins: $a0, $a1, $a2
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a2
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[COPY]](s32)
; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY3]], [[C]]
; MIPS32: G_BRCOND [[AND]](s32), %bb.1
; MIPS32: G_BR %bb.2
; MIPS32: bb.1.if.then:
; MIPS32: $v0 = COPY [[COPY1]](s32)
; MIPS32: RetRA implicit $v0
; MIPS32: bb.2.if.else:
; MIPS32: $v0 = COPY [[COPY2]](s32)
; MIPS32: RetRA implicit $v0
bb.1 (%ir-block.0):
liveins: $a0, $a1, $a2
%3:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = COPY $a2
%5:_(s32) = G_CONSTANT i32 1
%6:_(s32) = COPY %3(s32)
%4:_(s32) = G_AND %6, %5
G_BRCOND %4(s32), %bb.2
G_BR %bb.3
bb.2.if.then:
$v0 = COPY %1(s32)
RetRA implicit $v0
bb.3.if.else:
$v0 = COPY %2(s32)
RetRA implicit $v0
...