This is an archive of the discontinued LLVM Phabricator instance.

Differential D57816

[MIPS GlobalISel] Select mul
ClosedPublic

Authored by Petar.Avramovic on Feb 6 2019, 6:25 AM.

Details

Reviewers
atanasyan
petarj
Commits
rG56dc218dc120: [MIPS GlobalISel] Select mul
rL353506: [MIPS GlobalISel] Select mul
Summary

Legalize and select G_MUL for s32 and smaller types for MIPS32.

Diff Detail

Repository
rL LLVM

Event Timeline

Petar.Avramovic created this revision.Feb 6 2019, 6:25 AM
Herald added subscribers: arichardson, kristof.beyls, rovka, sdardis. · View Herald TranscriptFeb 6 2019, 6:25 AM
atanasyan added a comment.Feb 6 2019, 2:24 PM

The mul.mir failed on my machine:

mul.mir:22:12: error: MIPS32: expected string not found in input
Petar.Avramovic updated this revision to Diff 185723.Feb 7 2019, 1:52 AM

Fixed test.

atanasyan accepted this revision.Feb 7 2019, 3:08 PM

LGTM

This revision is now accepted and ready to land.Feb 7 2019, 3:08 PM
Closed by commit rL353506: [MIPS GlobalISel] Select mul (authored by Petar.Avramovic). · Explain WhyFeb 8 2019, 2:12 AM
This revision was automatically updated to reflect the committed changes.
Herald added a project: Restricted Project. · View Herald TranscriptFeb 8 2019, 2:12 AM
Herald added subscribers: llvm-commits, jrtc27. · View Herald Transcript

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
4 lines
1 line
test/
CodeGen/
Mips/
GlobalISel/
instruction-select/
31 lines
legalizer/
213 lines
llvm-ir/
88 lines
regbankselect/
30 lines

Diff 185930

llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp

Show All 22 LinesMipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
const LLT s32 = LLT::scalar(32); const LLT s32 = LLT::scalar(32);
const LLT s64 = LLT::scalar(64); const LLT s64 = LLT::scalar(64);
const LLT p0 = LLT::pointer(0, 32); const LLT p0 = LLT::pointer(0, 32);
getActionDefinitionsBuilder({G_ADD, G_SUB}) getActionDefinitionsBuilder({G_ADD, G_SUB})
.legalFor({s32}) .legalFor({s32})
.clampScalar(0, s32, s32); .clampScalar(0, s32, s32);
getActionDefinitionsBuilder(G_MUL)
.legalFor({s32})
.minScalar(0, s32);
getActionDefinitionsBuilder({G_UADDE, G_USUBO, G_USUBE}) getActionDefinitionsBuilder({G_UADDE, G_USUBO, G_USUBE})
.lowerFor({{s32, s1}}); .lowerFor({{s32, s1}});
getActionDefinitionsBuilder({G_LOAD, G_STORE}) getActionDefinitionsBuilder({G_LOAD, G_STORE})
.legalForCartesianProduct({p0, s32}, {p0}); .legalForCartesianProduct({p0, s32}, {p0});
getActionDefinitionsBuilder({G_ZEXTLOAD, G_SEXTLOAD}) getActionDefinitionsBuilder({G_ZEXTLOAD, G_SEXTLOAD})
.legalForTypesWithMemSize({{s32, p0, 8}, .legalForTypesWithMemSize({{s32, p0, 8},
▲ Show 20 Lines • Show All 53 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp

Show First 20 Lines • Show All 79 Lines • ▼ Show 20 LinesMipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
unsigned NumOperands = MI.getNumOperands(); unsigned NumOperands = MI.getNumOperands();
const ValueMapping *OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx]; const ValueMapping *OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
switch (Opc) { switch (Opc) {
case G_TRUNC: case G_TRUNC:
case G_ADD: case G_ADD:
case G_SUB: case G_SUB:
case G_MUL:
case G_LOAD: case G_LOAD:
case G_STORE: case G_STORE:
case G_ZEXTLOAD: case G_ZEXTLOAD:
case G_SEXTLOAD: case G_SEXTLOAD:
case G_GEP: case G_GEP:
case G_AND: case G_AND:
case G_OR: case G_OR:
case G_XOR: case G_XOR:
Show All 35 Lines

llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @mul_i32(i32 %x, i32 %y) {entry: ret void}
...
---
name: mul_i32
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $a0, $a1
; MIPS32-LABEL: name: mul_i32
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[MUL:%[0-9]+]]:gpr32 = MUL [[COPY]], [[COPY1]], implicit-def $hi0, implicit-def $lo0
; MIPS32: $v0 = COPY [[MUL]]
; MIPS32: RetRA implicit $v0
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
%2:gprb(s32) = G_MUL %0, %1
$v0 = COPY %2(s32)
RetRA implicit $v0
...

llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @mul_i32() {entry: ret void}
define void @mul_i8_sext() {entry: ret void}
define void @mul_i8_zext() {entry: ret void}
define void @mul_i8_aext() {entry: ret void}
define void @mul_i16_sext() {entry: ret void}
define void @mul_i16_zext() {entry: ret void}
define void @mul_i16_aext() {entry: ret void}
...
---
name: mul_i32
alignment: 2
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $a0, $a1
; MIPS32-LABEL: name: mul_i32
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]]
; MIPS32: $v0 = COPY [[MUL]](s32)
; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_MUL %0, %1
$v0 = COPY %2(s32)
RetRA implicit $v0
...
---
name: mul_i8_sext
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1
; MIPS32-LABEL: name: mul_i8_sext
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY3]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; MIPS32: $v0 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_MUL %1, %0
%5:_(s32) = G_SEXT %4(s8)
$v0 = COPY %5(s32)
RetRA implicit $v0
...
---
name: mul_i8_zext
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1
; MIPS32-LABEL: name: mul_i8_zext
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY3]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; MIPS32: $v0 = COPY [[AND]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_MUL %1, %0
%5:_(s32) = G_ZEXT %4(s8)
$v0 = COPY %5(s32)
RetRA implicit $v0
...
---
name: mul_i8_aext
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1
; MIPS32-LABEL: name: mul_i8_aext
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY3]]
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
; MIPS32: $v0 = COPY [[COPY4]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_MUL %1, %0
%5:_(s32) = G_ANYEXT %4(s8)
$v0 = COPY %5(s32)
RetRA implicit $v0
...
---
name: mul_i16_sext
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1
; MIPS32-LABEL: name: mul_i16_sext
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY3]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; MIPS32: $v0 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_MUL %1, %0
%5:_(s32) = G_SEXT %4(s16)
$v0 = COPY %5(s32)
RetRA implicit $v0
...
---
name: mul_i16_zext
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1
; MIPS32-LABEL: name: mul_i16_zext
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY3]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; MIPS32: $v0 = COPY [[AND]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_MUL %1, %0
%5:_(s32) = G_ZEXT %4(s16)
$v0 = COPY %5(s32)
RetRA implicit $v0
...
---
name: mul_i16_aext
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1
; MIPS32-LABEL: name: mul_i16_aext
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY3]]
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
; MIPS32: $v0 = COPY [[COPY4]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_MUL %1, %0
%5:_(s32) = G_ANYEXT %4(s16)
$v0 = COPY %5(s32)
RetRA implicit $v0
...

llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
define i32 @mul_i32(i32 %x, i32 %y) {
; MIPS32-LABEL: mul_i32:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: mul $2, $4, $5
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%z = mul i32 %x, %y
ret i32 %z
}
define signext i8 @mul_i8_sext(i8 signext %a, i8 signext %b) {
; MIPS32-LABEL: mul_i8_sext:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: mul $4, $5, $4
; MIPS32-NEXT: sll $4, $4, 24
; MIPS32-NEXT: sra $2, $4, 24
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%mul = mul i8 %b, %a
ret i8 %mul
}
define zeroext i8 @mul_i8_zext(i8 zeroext %a, i8 zeroext %b) {
; MIPS32-LABEL: mul_i8_zext:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: mul $4, $5, $4
; MIPS32-NEXT: lui $5, 0
; MIPS32-NEXT: ori $5, $5, 255
; MIPS32-NEXT: and $2, $4, $5
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%mul = mul i8 %b, %a
ret i8 %mul
}
define i8 @mul_i8_aext(i8 %a, i8 %b) {
; MIPS32-LABEL: mul_i8_aext:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: mul $2, $5, $4
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%mul = mul i8 %b, %a
ret i8 %mul
}
define signext i16 @mul_i16_sext(i16 signext %a, i16 signext %b) {
; MIPS32-LABEL: mul_i16_sext:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: mul $4, $5, $4
; MIPS32-NEXT: sll $4, $4, 16
; MIPS32-NEXT: sra $2, $4, 16
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%mul = mul i16 %b, %a
ret i16 %mul
}
define zeroext i16 @mul_i16_zext(i16 zeroext %a, i16 zeroext %b) {
; MIPS32-LABEL: mul_i16_zext:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: mul $4, $5, $4
; MIPS32-NEXT: lui $5, 0
; MIPS32-NEXT: ori $5, $5, 65535
; MIPS32-NEXT: and $2, $4, $5
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%mul = mul i16 %b, %a
ret i16 %mul
}
define i16 @mul_i16_aext(i16 %a, i16 %b) {
; MIPS32-LABEL: mul_i16_aext:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: mul $2, $5, $4
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%mul = mul i16 %b, %a
ret i16 %mul
}

llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @mul_i32(i32 %x, i32 %y) {entry: ret void}
...
---
name: mul_i32
alignment: 2
legalized: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $a0, $a1
; MIPS32-LABEL: name: mul_i32
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
; MIPS32: [[MUL:%[0-9]+]]:gprb(s32) = G_MUL [[COPY]], [[COPY1]]
; MIPS32: $v0 = COPY [[MUL]](s32)
; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_MUL %0, %1
$v0 = COPY %2(s32)
RetRA implicit $v0
...