GlobalISel: Enforce operand types for constants

[arsenm]

Summary

A number of of tests were using imm operands, not cimm. Since CSE
relies on the exact ConstantInt* pointer used, and implicit
conversions are generally evil, also enforce the bitsize of the types.

[aditya_nandakumar]

Looks great. Thanks for fixing this..

[arsenm]

r353113

lib/CodeGen/MachineVerifier.cpp

void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
   case TargetOpcode::G_CONSTANT:
   case TargetOpcode::G_FCONSTANT: {
     if (MI->getNumOperands() < MCID.getNumOperands())
       break;
 
     LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
     if (DstTy.isVector())
       report("Instruction cannot use a vector result type", MI);
+
+    if (MI->getOpcode() == TargetOpcode::G_CONSTANT) {
+      if (!MI->getOperand(1).isCImm()) {
+        report("G_CONSTANT operand must be cimm", MI);
+        break;
+      }
+
+      const ConstantInt *CI = MI->getOperand(1).getCImm();
+      if (CI->getBitWidth() != DstTy.getSizeInBits())
+        report("inconsistent constant size", MI);
+    } else {
+      if (!MI->getOperand(1).isFPImm()) {
+        report("G_FCONSTANT operand must be fpimm", MI);
+        break;
+      }
+      const ConstantFP *CF = MI->getOperand(1).getFPImm();
+
+      if (APFloat::getSizeInBits(CF->getValueAPF().getSemantics()) !=
+          DstTy.getSizeInBits()) {
+        report("inconsistent constant size", MI);
+      }
+    }
+
     break;
   }
   case TargetOpcode::G_LOAD:
   case TargetOpcode::G_STORE:
   case TargetOpcode::G_ZEXTLOAD:
   case TargetOpcode::G_SEXTLOAD: {
     LLT ValTy = MRI->getType(MI->getOperand(0).getReg());
     LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());

test/CodeGen/AArch64/GlobalISel/localizer.mir

 
 ---
 name:            local_use
 legalized:       true
 regBankSelected: true
 body:             |
   bb.0:
     ; CHECK-LABEL: name: local_use
-    ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT 1
+    ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
     ; CHECK: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]
-    %0:gpr(s32) = G_CONSTANT 1
+    %0:gpr(s32) = G_CONSTANT i32 1
     %1:gpr(s32) = G_ADD %0, %0
 ...
 
 ---
 name:            non_local_1use
 legalized:       true
 regBankSelected: true
 body:             |
   ; CHECK-LABEL: name: non_local_1use
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x80000000)
-  ; CHECK:   [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT 1
+  ; CHECK:   [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
   ; CHECK:   [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]
   ; CHECK: bb.1:
-  ; CHECK:   [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT 1
+  ; CHECK:   [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
   ; CHECK:   [[ADD1:%[0-9]+]]:gpr(s32) = G_ADD [[C1]], [[ADD]]
 
   ; Existing registers should be left untouched
   ; The newly created reg should be on the same regbank/regclass as its origin.
 
   bb.0:
     successors: %bb.1
 
-    %0:gpr(s32) = G_CONSTANT 1
+    %0:gpr(s32) = G_CONSTANT i32 1
     %1:gpr(s32) = G_ADD %0, %0
 
   bb.1:
     %2:gpr(s32) = G_ADD %0, %1
 ...
 
 ---
 name:            non_local_2uses
 legalized:       true
 regBankSelected: true
 body:             |
   ; CHECK-LABEL: name: non_local_2uses
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x80000000)
-  ; CHECK:   [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT 1
+  ; CHECK:   [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
   ; CHECK:   [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]
   ; CHECK: bb.1:
-  ; CHECK:   [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT 1
+  ; CHECK:   [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
   ; CHECK:   [[ADD1:%[0-9]+]]:gpr(s32) = G_ADD [[C1]], [[C1]]
 
   ; Existing registers should be left untouched
   ; The newly created reg should be on the same regbank/regclass as its origin.
 
   bb.0:
     successors: %bb.1
 
-    %0:gpr(s32) = G_CONSTANT 1
+    %0:gpr(s32) = G_CONSTANT i32 1
     %1:gpr(s32) = G_ADD %0, %0
 
   bb.1:
     %2:gpr(s32) = G_ADD %0, %0
 ...
 
 ---
 name:            non_local_phi_use
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: non_local_phi_use
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x80000000)
-  ; CHECK:   [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT 1
+  ; CHECK:   [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
   ; CHECK:   [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]
   ; CHECK: bb.1:
   ; CHECK:   successors: %bb.2(0x80000000)
-  ; CHECK:   [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT 1
+  ; CHECK:   [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
   ; CHECK: bb.2:
   ; CHECK:   [[PHI:%[0-9]+]]:gpr(s32) = PHI [[C1]](s32), %bb.1
   ; CHECK:   [[ADD1:%[0-9]+]]:gpr(s32) = G_ADD [[PHI]], [[PHI]]
 
   ; Existing registers should be left untouched
   ; The newly created reg should be on the same regbank/regclass as its origin.
 
   bb.0:
     successors: %bb.1
 
-    %0:gpr(s32) = G_CONSTANT 1
+    %0:gpr(s32) = G_CONSTANT i32 1
     %1:gpr(s32) = G_ADD %0, %0
 
   bb.1:
     successors: %bb.2
 
   bb.2:
     %3:gpr(s32) = PHI %0(s32), %bb.1
     %2:gpr(s32) = G_ADD %3, %3
 ...
 
 ---
 name:            non_local_phi_use_followed_by_use
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: non_local_phi_use_followed_by_use
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x80000000)
-  ; CHECK:   [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT 1
+  ; CHECK:   [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
   ; CHECK:   [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]
   ; CHECK: bb.1:
   ; CHECK:   successors: %bb.2(0x80000000)
-  ; CHECK:   [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT 1
+  ; CHECK:   [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
   ; CHECK: bb.2:
   ; CHECK:   [[PHI:%[0-9]+]]:gpr(s32) = PHI [[C1]](s32), %bb.1
-  ; CHECK:   [[C2:%[0-9]+]]:gpr(s32) = G_CONSTANT 1
+  ; CHECK:   [[C2:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
   ; CHECK:   [[ADD1:%[0-9]+]]:gpr(s32) = G_ADD [[PHI]], [[C2]]
 
   ; Existing registers should be left untouched
   ; The newly created reg should be on the same regbank/regclass as its origin.
 
   bb.0:
     successors: %bb.1
 
-    %0:gpr(s32) = G_CONSTANT 1
+    %0:gpr(s32) = G_CONSTANT i32 1
     %1:gpr(s32) = G_ADD %0, %0
 
   bb.1:
     successors: %bb.2
 
   bb.2:
     %3:gpr(s32) = PHI %0(s32), %bb.1
     %2:gpr(s32) = G_ADD %3, %0

test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads.mir

bb.0.entry:
     ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
     ; CHECK: [[T2:%[0-9]+]]:_(s8) = G_TRUNC [[T1]]
     ; CHECK: [[T3:%[0-9]+]]:_(s8) = G_XOR [[T2]], {{%[0-9]+}}
     ; CHECK: [[T4:%[0-9]+]]:_(s32) = G_ANYEXT [[T3]]
     ; CHECK: $w0 = COPY [[T4]](s32)
     ; CHECK: $w1 = COPY [[T1]](s32)
     %0:_(p0) = COPY $x0
     %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
-    %2:_(s8) = G_CONSTANT i32 -1
+    %2:_(s8) = G_CONSTANT i8 -1
     %3:_(s8) = G_XOR %1, %2
     %5:_(s32) = G_ANYEXT %3
     %6:_(s32) = G_SEXT %1
     $w0 = COPY %5
     $w1 = COPY %6
 ...
 
 ---
 name:            test_1anyext_1zeroext
 body: |
   bb.0.entry:
     liveins: $x0
     ; CHECK-LABEL: name: test_1anyext_1zeroext
     ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
     ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
     ; CHECK: $w0 = COPY [[T1]](s32)
     ; CHECK: $w1 = COPY [[T1]](s32)
     %0:_(p0) = COPY $x0
     %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
     %2:_(s32) = G_ANYEXT %1
     %3:_(s32) = G_ZEXT %1
     $w0 = COPY %2
     $w1 = COPY %3
 ...
- 
 ---
 name:            test_1signext_1zeroext
 body: |
   bb.0.entry:
     liveins: $x0
     ; CHECK-LABEL: name: test_1signext_1zeroext
     ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
     ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)

test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir

 ---
 name:            test_constant_s32
 legalized:       true
 registers:
   - { id: 0, class: _ }
 body: |
   bb.0:
     ; CHECK-LABEL: name: test_constant_s32
-    ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT 123
-    %0(s32) = G_CONSTANT 123
+    ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 123
+    %0(s32) = G_CONSTANT i32 123
 ...
 
 ---
 name:            test_constant_p0
 legalized:       true
 registers:
   - { id: 0, class: _ }
 body: |
   bb.0:
     ; CHECK-LABEL: name: test_constant_p0
-    ; CHECK: [[C:%[0-9]+]]:gpr(p0) = G_CONSTANT 0
-    %0(p0) = G_CONSTANT 0
+    ; CHECK: [[C:%[0-9]+]]:gpr(p0) = G_CONSTANT i64 0
+    %0(p0) = G_CONSTANT i64 0
 ...
 
 ---
 name:            test_icmp_s32
 legalized:       true
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }

test/CodeGen/AArch64/GlobalISel/select-binop.mir

body:             |
   bb.0:
     liveins: $x0, $w1
 
     ; CHECK-LABEL: name: add_imm_s64_gpr
     ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
     ; CHECK: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 1, 0
     ; CHECK: $x0 = COPY [[ADDXri]]
     %0(s64) = COPY $x0
-    %1(s64) = G_CONSTANT i32 1
+    %1(s64) = G_CONSTANT i64 1
     %2(s64) = G_ADD %0, %1
     $x0 = COPY %2(s64)
 ...
 
 ---
 name:            add_imm_s32_gpr_bb
 legalized:       true
 regBankSelected: true

test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir

 
 name:            implicit_def_p0
 legalized:       true
 regBankSelected: true
 
 body: |
   bb.0:
     %0:vgpr(p0) = G_IMPLICIT_DEF
-    %1:vgpr(s32) = G_CONSTANT 4
+    %1:vgpr(s32) = G_CONSTANT i32 4
     G_STORE %1, %0 :: (store 4)
 ...
 
 ---
 
 name:            implicit_def_p1
 legalized:       true
 regBankSelected: true
 
 body: |
   bb.0:
     ; GCN-LABEL: name: implicit_def_p1
     ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
     ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec
     ; GCN: FLAT_STORE_DWORD [[DEF]], [[V_MOV_B32_e32_]], 0, 0, 0, implicit $exec, implicit $flat_scr
     %0:vgpr(p1) = G_IMPLICIT_DEF
-    %1:vgpr(s32) = G_CONSTANT 4
+    %1:vgpr(s32) = G_CONSTANT i32 4
     G_STORE %1, %0 :: (store 4, addrspace 1)
 ...
 ---
 
 name:            implicit_def_p3
 legalized:       true
 regBankSelected: true
 
 body: |
   bb.0:
     ; GCN-LABEL: name: implicit_def_p3
     ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
     ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec
     ; GCN: FLAT_STORE_DWORD [[DEF]], [[V_MOV_B32_e32_]], 0, 0, 0, implicit $exec, implicit $flat_scr
     %0:vgpr(p3) = G_IMPLICIT_DEF
-    %1:vgpr(s32) = G_CONSTANT 4
+    %1:vgpr(s32) = G_CONSTANT i32 4
     G_STORE %1, %0 :: (store 4, addrspace 1)
 ...
 ---
 
 name:            implicit_def_p4
 legalized:       true
 regBankSelected: true
 
 body: |
   bb.0:
     ; GCN-LABEL: name: implicit_def_p4
     ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
     ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec
     ; GCN: FLAT_STORE_DWORD [[DEF]], [[V_MOV_B32_e32_]], 0, 0, 0, implicit $exec, implicit $flat_scr
     %0:vgpr(p4) = G_IMPLICIT_DEF
-    %1:vgpr(s32) = G_CONSTANT 4
+    %1:vgpr(s32) = G_CONSTANT i32 4
     G_STORE %1, %0 :: (store 4, addrspace 1)
 ...

test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir

bb.0:
 
     ; CHECK-LABEL: name: test_and_s1
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
     ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY1]]
     ; CHECK: S_NOP 0, implicit [[AND]](s32)
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = COPY $vgpr1
-    %2:_(s32) = G_CONSTANT i64 0
+    %2:_(s32) = G_CONSTANT i32 0
     %3:_(s1) = G_ICMP intpred(ne), %0, %2
     %4:_(s1) = G_ICMP intpred(ne), %1, %2
     %5:_(s32) = G_AND %0, %1
     S_NOP 0, implicit %5
 ...
 
 ---
 name: test_and_s64

test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir

 ---
 name: extract_vector_elt_0_v2i1_i1
 
 body: |
   bb.0:
 
     ; CHECK-LABEL: name: extract_vector_elt_0_v2i1_i1
     ; CHECK: [[DEF:%[0-9]+]]:_(<2 x s1>) = G_IMPLICIT_DEF
-    ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i32 0
+    ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
     ; CHECK: [[UV:%[0-9]+]]:_(s1), [[UV1:%[0-9]+]]:_(s1) = G_UNMERGE_VALUES [[DEF]](<2 x s1>)
     ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[UV]](s1)
     ; CHECK: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[UV1]](s1)
     ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT]](s32), [[SEXT1]](s32)
     ; CHECK: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[C]](s1)
     ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<2 x s32>), [[SEXT2]](s32)
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
     ; CHECK: $vgpr0 = COPY [[COPY]](s32)
     %0:_(<2 x s1>) = G_IMPLICIT_DEF
-    %1:_(s1) = G_CONSTANT i32 0
+    %1:_(s1) = G_CONSTANT i1 false
     %2:_(s1) = G_EXTRACT_VECTOR_ELT %0, %1
     %3:_(s32) = G_ANYEXT %2
     $vgpr0 = COPY %3
 ...

test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir

bb.0.entry:
     ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
     ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
     ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[AND1]]
     ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
     ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
     ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[COPY3]], [[COPY4]]
     ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
     ; CHECK: $vgpr0 = COPY [[COPY5]](s32)
-    %0:_(s8) = G_CONSTANT i16 0
+    %0:_(s8) = G_CONSTANT i8 0
     %1:_(s32) = COPY $vgpr0
     %2:_(s8) = G_TRUNC %1
     %3:_(s1) = G_ICMP intpred(ne), %0, %2
     %4:_(s8) = G_SELECT %3, %0, %2
     %5:_(s32) = G_ANYEXT %4
     $vgpr0 = COPY %5
 ...
 

test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir

bb.0:
 
     ; CHECK-LABEL: name: test_or_s1
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
     ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[COPY1]]
     ; CHECK: S_NOP 0, implicit [[OR]](s32)
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = COPY $vgpr1
-    %2:_(s32) = G_CONSTANT i64 0
+    %2:_(s32) = G_CONSTANT i32 0
     %3:_(s1) = G_ICMP intpred(ne), %0, %2
     %4:_(s1) = G_ICMP intpred(ne), %1, %2
     %5:_(s32) = G_OR %0, %1
     S_NOP 0, implicit %5
 ...
 
 ---
 name: test_or_s64

test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir

bb.0:
     ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
     ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[COPY1]], [[COPY2]]
     ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
     ; CHECK: $vgpr0 = COPY [[COPY3]](s32)
     %0:_(s32) = G_CONSTANT i32 0
     %1:_(s32) = COPY $vgpr0
 
     %2:_(s1) = G_ICMP intpred(ne), %0, %1
-    %3:_(s8) = G_CONSTANT i16 1
-    %4:_(s8) = G_CONSTANT i16 2
+    %3:_(s8) = G_CONSTANT i8 1
+    %4:_(s8) = G_CONSTANT i8 2
     %5:_(s8) = G_SELECT %2, %3, %4
     %6:_(s32) = G_ANYEXT %5
     $vgpr0 = COPY %6
 
 ...
 
 ---
 name: test_select_s7
bb.0:
     ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
     ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[COPY1]], [[COPY2]]
     ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
     ; CHECK: $vgpr0 = COPY [[COPY3]](s32)
     %0:_(s32) = G_CONSTANT i32 0
     %1:_(s32) = COPY $vgpr0
 
     %2:_(s1) = G_ICMP intpred(ne), %0, %1
-    %3:_(s7) = G_CONSTANT i16 1
-    %4:_(s7) = G_CONSTANT i16 2
+    %3:_(s7) = G_CONSTANT i7 1
+    %4:_(s7) = G_CONSTANT i7 2
     %5:_(s7) = G_SELECT %2, %3, %4
     %6:_(s32) = G_ANYEXT %5
     $vgpr0 = COPY %6
 
 ...
 
 ---
 name: test_select_s96

test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir

bb.0:
 
     ; CHECK-LABEL: name: test_xor_s1
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
     ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[COPY1]]
     ; CHECK: S_NOP 0, implicit [[XOR]](s32)
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = COPY $vgpr1
-    %2:_(s32) = G_CONSTANT i64 0
+    %2:_(s32) = G_CONSTANT i32 0
     %3:_(s1) = G_ICMP intpred(ne), %0, %2
     %4:_(s1) = G_ICMP intpred(ne), %1, %2
     %5:_(s32) = G_XOR %0, %1
     S_NOP 0, implicit %5
 ...
 
 ---
 name: test_xor_s64

test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir

 legalized: true
 
 body: |
   bb.0:
     liveins: $sgpr0, $sgpr1
     ; CHECK-LABEL: name: and_i1_scc_scc
     ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
-    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
     ; CHECK: [[ICMP1:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
     ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
     ; CHECK: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1)
     ; CHECK: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[COPY2]], [[COPY3]]
     ; CHECK: S_NOP 0, implicit [[AND]](s1)
       %0:_(s32) = COPY $sgpr0
       %1:_(s32) = COPY $sgpr1
-      %2:_(s32) = G_CONSTANT i64 0
+      %2:_(s32) = G_CONSTANT i32 0
       %4:_(s1) = G_ICMP intpred(ne), %0, %2
       %5:_(s1) = G_ICMP intpred(ne), %1, %2
       %6:_(s1) = G_AND %4, %5
       S_NOP 0, implicit %6
 ...
 
 ---
 name: and_i1_vcc_vcc
 legalized: true
 
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
     ; CHECK-LABEL: name: and_i1_vcc_vcc
     ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
-    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
     ; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
     ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
     ; CHECK: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1)
     ; CHECK: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[COPY2]], [[COPY3]]
     ; CHECK: S_NOP 0, implicit [[AND]](s1)
       %0:_(s32) = COPY $vgpr0
       %1:_(s32) = COPY $vgpr1
-      %2:_(s32) = G_CONSTANT i64 0
+      %2:_(s32) = G_CONSTANT i32 0
       %4:_(s1) = G_ICMP intpred(ne), %0, %2
       %5:_(s1) = G_ICMP intpred(ne), %1, %2
       %6:_(s1) = G_AND %4, %5
       S_NOP 0, implicit %6
 ...
 
 ---
 name: and_i1_scc_vcc
 legalized: true
 
 body: |
   bb.0:
     liveins: $sgpr0, $vgpr0
     ; CHECK-LABEL: name: and_i1_scc_vcc
     ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
-    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
     ; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
     ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
     ; CHECK: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1)
     ; CHECK: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[COPY2]], [[COPY3]]
     ; CHECK: S_NOP 0, implicit [[AND]](s1)
       %0:_(s32) = COPY $sgpr0
       %1:_(s32) = COPY $vgpr0
-      %2:_(s32) = G_CONSTANT i64 0
+      %2:_(s32) = G_CONSTANT i32 0
       %4:_(s1) = G_ICMP intpred(ne), %0, %2
       %5:_(s1) = G_ICMP intpred(ne), %1, %2
       %6:_(s1) = G_AND %4, %5
       S_NOP 0, implicit %6
 ...
 
 ---
 name: and_i1_sgpr_trunc_sgpr_trunc

test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir

bb.0:
     %0:_(s64) = G_FCONSTANT double 1.0
 ...
 ---
 name:            test_fconstant_f16_1
 legalized:       true
 body: |
   bb.0:
     ; CHECK-LABEL: name: test_fconstant_f16_1
-    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT half 0xH3C00
-    %0:_(s32) = G_FCONSTANT half 1.0
+    ; CHECK: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH3C00
+    %0:_(s16) = G_FCONSTANT half 1.0
+    %1:_(s32) = G_ANYEXT %0
 ...
 
 ---
 name:            test_implicit_def_s32
 legalized:       true
 body: |
   bb.0:
     ; CHECK-LABEL: name: test_implicit_def_s32

test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=FAST %s
 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=GREEDY %s
 
 ---
 name: sadde_s32_sss
 legalized: true
 
 body: |
   bb.0:
     liveins: $sgpr0, $sgpr1, $sgpr2
     ; FAST-LABEL: name: sadde_s32_sss
     ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
     ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
-    ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
     ; FAST: [[SADDE:%[0-9]+]]:sgpr(s32), [[SADDE1:%[0-9]+]]:scc(s1) = G_SADDE [[COPY]], [[COPY1]], [[ICMP]]
     ; GREEDY-LABEL: name: sadde_s32_sss
     ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
     ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
-    ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
     ; GREEDY: [[SADDE:%[0-9]+]]:sgpr(s32), [[SADDE1:%[0-9]+]]:scc(s1) = G_SADDE [[COPY]], [[COPY1]], [[ICMP]]
     %0:_(s32) = COPY $sgpr0
     %1:_(s32) = COPY $sgpr1
     %2:_(s32) = COPY $sgpr2
-    %3:_(s32) = G_CONSTANT i64 0
+    %3:_(s32) = G_CONSTANT i32 0
     %4:_(s1) = G_ICMP intpred(eq), %2, %3
     %5:_(s32), %6:_(s1) = G_SADDE %0, %1, %4
 ...
 
 ---
 name: sadde_s32_vss
 legalized: true
 
 body: |
   bb.0:
     liveins: $vgpr0, $sgpr0, $sgpr1
     ; FAST-LABEL: name: sadde_s32_vss
     ; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
-    ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
     ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
     ; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
     ; FAST: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:vcc(s1) = G_SADDE [[COPY]], [[COPY3]], [[COPY4]]
     ; GREEDY-LABEL: name: sadde_s32_vss
     ; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
-    ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
     ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
     ; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
     ; GREEDY: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:vcc(s1) = G_SADDE [[COPY]], [[COPY3]], [[COPY4]]
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = COPY $sgpr0
     %2:_(s32) = COPY $sgpr1
-    %3:_(s32) = G_CONSTANT i64 0
+    %3:_(s32) = G_CONSTANT i32 0
     %4:_(s1) = G_ICMP intpred(eq), %2, %3
     %5:_(s32), %6:_(s1) = G_SADDE %0, %1, %4
 ...
 ---
 name: sadde_s32_ssv
 legalized: true
 
 body: |

test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=FAST %s
 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=GREEDY %s
 
 ---
 name: ssube_s32_sss
 legalized: true
 
 body: |
   bb.0:
     liveins: $sgpr0, $sgpr1, $sgpr2
     ; FAST-LABEL: name: ssube_s32_sss
     ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
     ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
-    ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
     ; FAST: [[SSUBE:%[0-9]+]]:sgpr(s32), [[SSUBE1:%[0-9]+]]:scc(s1) = G_SSUBE [[COPY]], [[COPY1]], [[ICMP]]
     ; GREEDY-LABEL: name: ssube_s32_sss
     ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
     ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
-    ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
     ; GREEDY: [[SSUBE:%[0-9]+]]:sgpr(s32), [[SSUBE1:%[0-9]+]]:scc(s1) = G_SSUBE [[COPY]], [[COPY1]], [[ICMP]]
     %0:_(s32) = COPY $sgpr0
     %1:_(s32) = COPY $sgpr1
     %2:_(s32) = COPY $sgpr2
-    %3:_(s32) = G_CONSTANT i64 0
+    %3:_(s32) = G_CONSTANT i32 0
     %4:_(s1) = G_ICMP intpred(eq), %2, %3
     %5:_(s32), %6:_(s1) = G_SSUBE %0, %1, %4
 ...
 
 ---
 name: ssube_s32_vss
 legalized: true
 
 body: |
   bb.0:
     liveins: $vgpr0, $sgpr0, $sgpr1
     ; FAST-LABEL: name: ssube_s32_vss
     ; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
-    ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
     ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
     ; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
     ; FAST: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:vcc(s1) = G_SSUBE [[COPY]], [[COPY3]], [[COPY4]]
     ; GREEDY-LABEL: name: ssube_s32_vss
     ; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
-    ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
     ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
     ; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
     ; GREEDY: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:vcc(s1) = G_SSUBE [[COPY]], [[COPY3]], [[COPY4]]
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = COPY $sgpr0
     %2:_(s32) = COPY $sgpr1
-    %3:_(s32) = G_CONSTANT i64 0
+    %3:_(s32) = G_CONSTANT i32 0
     %4:_(s1) = G_ICMP intpred(eq), %2, %3
     %5:_(s32), %6:_(s1) = G_SSUBE %0, %1, %4
 ...
 ---
 name: ssube_s32_ssv
 legalized: true
 
 body: |

test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=FAST %s
 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=GREEDY %s
 ---
 name: uadde_s32_sss
 legalized: true
 
 body: |
   bb.0:
     liveins: $sgpr0, $sgpr1, $sgpr2
     ; FAST-LABEL: name: uadde_s32_sss
     ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
     ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
-    ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
     ; FAST: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:scc(s1) = G_UADDE [[COPY]], [[COPY1]], [[ICMP]]
     ; GREEDY-LABEL: name: uadde_s32_sss
     ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
     ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
-    ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
     ; GREEDY: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:scc(s1) = G_UADDE [[COPY]], [[COPY1]], [[ICMP]]
     %0:_(s32) = COPY $sgpr0
     %1:_(s32) = COPY $sgpr1
     %2:_(s32) = COPY $sgpr2
-    %3:_(s32) = G_CONSTANT i64 0
+    %3:_(s32) = G_CONSTANT i32 0
     %4:_(s1) = G_ICMP intpred(eq), %2, %3
     %5:_(s32), %6:_(s1) = G_UADDE %0, %1, %4
 ...
 
 ---
 name: uadde_s32_vss
 legalized: true
 
 body: |
   bb.0:
     liveins: $vgpr0, $sgpr0, $sgpr1
     ; FAST-LABEL: name: uadde_s32_vss
     ; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
-    ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
     ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
     ; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
     ; FAST: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:vcc(s1) = G_UADDE [[COPY]], [[COPY3]], [[COPY4]]
     ; GREEDY-LABEL: name: uadde_s32_vss
     ; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
-    ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
     ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
     ; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
     ; GREEDY: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:vcc(s1) = G_UADDE [[COPY]], [[COPY3]], [[COPY4]]
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = COPY $sgpr0
     %2:_(s32) = COPY $sgpr1
-    %3:_(s32) = G_CONSTANT i64 0
+    %3:_(s32) = G_CONSTANT i32 0
     %4:_(s1) = G_ICMP intpred(eq), %2, %3
     %5:_(s32), %6:_(s1) = G_UADDE %0, %1, %4
 ...
 ---
 name: uadde_s32_ssv
 legalized: true
 
 body: |

test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=FAST %s
 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=GREEDY %s
 
 ---
 name: usube_s32_sss
 legalized: true
 
 body: |
   bb.0:
     liveins: $sgpr0, $sgpr1, $sgpr2
     ; FAST-LABEL: name: usube_s32_sss
     ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
     ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
-    ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
     ; FAST: [[USUBE:%[0-9]+]]:sgpr(s32), [[USUBE1:%[0-9]+]]:scc(s1) = G_USUBE [[COPY]], [[COPY1]], [[ICMP]]
     ; GREEDY-LABEL: name: usube_s32_sss
     ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
     ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
-    ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
     ; GREEDY: [[USUBE:%[0-9]+]]:sgpr(s32), [[USUBE1:%[0-9]+]]:scc(s1) = G_USUBE [[COPY]], [[COPY1]], [[ICMP]]
     %0:_(s32) = COPY $sgpr0
     %1:_(s32) = COPY $sgpr1
     %2:_(s32) = COPY $sgpr2
-    %3:_(s32) = G_CONSTANT i64 0
+    %3:_(s32) = G_CONSTANT i32 0
     %4:_(s1) = G_ICMP intpred(eq), %2, %3
     %5:_(s32), %6:_(s1) = G_USUBE %0, %1, %4
 ...
 
 ---
 name: usube_s32_vss
 legalized: true
 
 body: |
   bb.0:
     liveins: $vgpr0, $sgpr0, $sgpr1
     ; FAST-LABEL: name: usube_s32_vss
     ; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
-    ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
     ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
     ; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
     ; FAST: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:vcc(s1) = G_USUBE [[COPY]], [[COPY3]], [[COPY4]]
     ; GREEDY-LABEL: name: usube_s32_vss
     ; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
-    ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
     ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
     ; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
     ; GREEDY: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:vcc(s1) = G_USUBE [[COPY]], [[COPY3]], [[COPY4]]
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = COPY $sgpr0
     %2:_(s32) = COPY $sgpr1
-    %3:_(s32) = G_CONSTANT i64 0
+    %3:_(s32) = G_CONSTANT i32 0
     %4:_(s1) = G_ICMP intpred(eq), %2, %3
     %5:_(s32), %6:_(s1) = G_USUBE %0, %1, %4
 ...
 ---
 name: usube_s32_ssv
 legalized: true
 
 body: |

test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir

 legalized:       true
 regBankSelected: true
 selected:        false
 # CHECK: selected: true
 registers:
   - { id: 0, class: gprb }
 body:             |
   bb.0:
-    %0(s32) = G_CONSTANT 65537
+    %0(s32) = G_CONSTANT i32 65537
     ; CHECK: %[[C:[0-9]+]]:gpr = MOVi32imm 65537
 
     $r0 = COPY %0(s32)
     BX_RET 14, $noreg, implicit $r0
 ...
 ---
 name:            test_constant_imm
 # CHECK-LABEL: name: test_constant_imm
 legalized:       true
 regBankSelected: true
 selected:        false
 # CHECK: selected: true
 registers:
   - { id: 0, class: gprb }
 body:             |
   bb.0:
-    %0(s32) = G_CONSTANT 42
+    %0(s32) = G_CONSTANT i32 42
     ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 42, 14, $noreg, $noreg
 
     $r0 = COPY %0(s32)
     BX_RET 14, $noreg, implicit $r0
 ...
 ---
 name:            test_constant_cimm
 # CHECK-LABEL: name: test_constant_cimm

test/CodeGen/ARM/GlobalISel/arm-legalize-consts.mir

registers:
   - { id: 4, class: _ }
   - { id: 5, class: _ }
 body:             |
   bb.0:
     liveins: $r0
 
     %4(p0) = COPY $r0
 
-    %0(s32) = G_CONSTANT 42
-    ; CHECK: {{%[0-9]+}}:_(s32) = G_CONSTANT 42
+    %0(s32) = G_CONSTANT i32 42
+    ; CHECK: {{%[0-9]+}}:_(s32) = G_CONSTANT i32 42
 
     %1(s16) = G_CONSTANT i16 21
     G_STORE %1(s16), %4(p0) :: (store 2)
     ; CHECK-NOT: G_CONSTANT i16
     ; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
     ; CHECK: {{%[0-9]+}}:_(s16) = G_TRUNC [[EXT]](s32)
     ; CHECK-NOT: G_CONSTANT i16
 
     %2(s8) = G_CONSTANT i8 10
     G_STORE %2(s8), %4(p0) :: (store 1)
     ; CHECK-NOT: G_CONSTANT i8
     ; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
     ; CHECK: {{%[0-9]+}}:_(s8) = G_TRUNC [[EXT]](s32)
     ; CHECK-NOT: G_CONSTANT i8
 
     %3(s1) = G_CONSTANT i1 1
     G_STORE %3(s1), %4(p0) :: (store 1)
     ; CHECK-NOT: G_CONSTANT i1
     ; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
     ; CHECK: {{%[0-9]+}}:_(s1) = G_TRUNC [[EXT]](s32)
     ; CHECK-NOT: G_CONSTANT i1
 
-    %5(p0) = G_CONSTANT 0
+    %5(p0) = G_CONSTANT i32 0
     G_STORE %5(p0), %4(p0) :: (store 4)
-    ; CHECK: {{%[0-9]+}}:_(p0) = G_CONSTANT 0
+    ; CHECK: {{%[0-9]+}}:_(p0) = G_CONSTANT i32 0
 
     $r0 = COPY %0(s32)
     BX_RET 14, $noreg, implicit $r0
 ...

test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir

 regBankSelected: false
 selected:        false
 # CHECK: registers:
 # CHECK: - { id: 0, class: gprb, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
 body:             |
   bb.0:
-    %0(s32) = G_CONSTANT 42
+    %0(s32) = G_CONSTANT i32 42
     $r0 = COPY %0(s32)
     BX_RET 14, $noreg, implicit $r0
 ...
 ---
 name:            test_inttoptr_s32
 # CHECK-LABEL: name: test_inttoptr_s32
 legalized:       true
 regBankSelected: false

test/CodeGen/ARM/GlobalISel/select-revsh.mir

bb.0:
     %2(s32) = G_SHL %0(s32), %1(s32)
 
     %3(s32) = G_CONSTANT i32 16
     %4(s32) = G_ASHR %2(s32), %3(s32)
 
     %5(s32) = G_CONSTANT i32 8
     %6(s32) = G_LSHR %0(s32), %5(s32)
 
-    %7(s32) = G_CONSTANT 255
+    %7(s32) = G_CONSTANT i32 255
     %8(s32) = G_AND %6(s32), %7(s32)
 
     %9(s32) = G_OR %4(s32), %8(s32)
     ; ARM: [[VREGR:%[0-9]+]]:gpr = REVSH [[VREGX]]
     ; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2REVSH [[VREGX]]
 
     $r0 = COPY %9(s32)
     ; CHECK: $r0 = COPY [[VREGR]]
bb.0:
     %2(s32) = G_SHL %0(s32), %1(s32)
 
     %3(s32) = G_CONSTANT i32 16
     %4(s32) = G_ASHR %2(s32), %3(s32)
 
     %5(s32) = G_CONSTANT i32 8
     %6(s32) = G_LSHR %0(s32), %5(s32)
 
-    %7(s32) = G_CONSTANT 255
+    %7(s32) = G_CONSTANT i32 255
     %8(s32) = G_AND %6(s32), %7(s32)
 
     %9(s32) = G_OR %8(s32), %4(s32)
     ; ARM: [[VREGR:%[0-9]+]]:gpr = REVSH [[VREGX]]
     ; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2REVSH [[VREGX]]
 
     $r0 = COPY %9(s32)
     ; CHECK: $r0 = COPY [[VREGR]]
bb.0:
     %2(s32) = G_SHL %0(s32), %1(s32)
 
     %3(s32) = G_CONSTANT i32 24 ; REVSH needs 16 here
     %4(s32) = G_ASHR %2(s32), %3(s32)
 
     %5(s32) = G_CONSTANT i32 8
     %6(s32) = G_LSHR %0(s32), %5(s32)
 
-    %7(s32) = G_CONSTANT 255
+    %7(s32) = G_CONSTANT i32 255
     %8(s32) = G_AND %6(s32), %7(s32)
 
     %9(s32) = G_OR %4(s32), %8(s32)
     ; We don't really care how this is folded as long as it's not into a REVSH.
     ; CHECK-NOT: REVSH
 
     $r0 = COPY %9(s32)
 
     BX_RET 14, $noreg, implicit $r0
 ...

test/CodeGen/X86/GlobalISel/select-ashr-scalar.mir

bb.1 (%ir-block.0):
 
     ; ALL-LABEL: name: test_ashr_i64_imm
     ; ALL: liveins: $rdi
     ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
     ; ALL: [[SAR64ri:%[0-9]+]]:gr64 = SAR64ri [[COPY]], 5, implicit-def $eflags
     ; ALL: $rax = COPY [[SAR64ri]]
     ; ALL: RET 0, implicit $rax
     %0(s64) = COPY $rdi
-    %1(s8) = G_CONSTANT i64 5
+    %1(s8) = G_CONSTANT i8 5
     %2(s64) = G_ASHR %0, %1
     $rax = COPY %2(s64)
     RET 0, implicit $rax
 
 ...
 ---
 name:            test_ashr_i64_imm1
 alignment:       4
bb.1 (%ir-block.0):
 
     ; ALL-LABEL: name: test_ashr_i64_imm1
     ; ALL: liveins: $rdi
     ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
     ; ALL: [[SAR64r1_:%[0-9]+]]:gr64 = SAR64r1 [[COPY]], implicit-def $eflags
     ; ALL: $rax = COPY [[SAR64r1_]]
     ; ALL: RET 0, implicit $rax
     %0(s64) = COPY $rdi
-    %1(s8) = G_CONSTANT i64 1
+    %1(s8) = G_CONSTANT i8 1
     %2(s64) = G_ASHR %0, %1
     $rax = COPY %2(s64)
     RET 0, implicit $rax
 
 ...
 ---
 name:            test_ashr_i32
 alignment:       4
bb.1 (%ir-block.0):
 
     ; ALL-LABEL: name: test_ashr_i32_imm
     ; ALL: liveins: $edi
     ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
     ; ALL: [[SAR32ri:%[0-9]+]]:gr32 = SAR32ri [[COPY]], 5, implicit-def $eflags
     ; ALL: $eax = COPY [[SAR32ri]]
     ; ALL: RET 0, implicit $eax
     %0(s32) = COPY $edi
-    %1(s8) = G_CONSTANT i32 5
+    %1(s8) = G_CONSTANT i8 5
     %2(s32) = G_ASHR %0, %1
     $eax = COPY %2(s32)
     RET 0, implicit $eax
 
 ...
 ---
 name:            test_ashr_i32_imm1
 alignment:       4
bb.1 (%ir-block.0):
 
     ; ALL-LABEL: name: test_ashr_i32_imm1
     ; ALL: liveins: $edi
     ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
     ; ALL: [[SAR32r1_:%[0-9]+]]:gr32 = SAR32r1 [[COPY]], implicit-def $eflags
     ; ALL: $eax = COPY [[SAR32r1_]]
     ; ALL: RET 0, implicit $eax
     %0(s32) = COPY $edi
-    %1(s8) = G_CONSTANT i32 1
+    %1(s8) = G_CONSTANT i8 1
     %2(s32) = G_ASHR %0, %1
     $eax = COPY %2(s32)
     RET 0, implicit $eax
 
 ...
 ---
 name:            test_ashr_i16
 alignment:       4
bb.1 (%ir-block.0):
     ; ALL-LABEL: name: test_ashr_i16_imm
     ; ALL: liveins: $edi
     ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
     ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
     ; ALL: [[SAR16ri:%[0-9]+]]:gr16 = SAR16ri [[COPY1]], 5, implicit-def $eflags
     ; ALL: $ax = COPY [[SAR16ri]]
     ; ALL: RET 0, implicit $ax
     %0(s32) = COPY $edi
-    %2(s8) = G_CONSTANT i16 5
+    %2(s8) = G_CONSTANT i8 5
     %1(s16) = G_TRUNC %0(s32)
     %3(s16) = G_ASHR %1, %2
     $ax = COPY %3(s16)
     RET 0, implicit $ax
 
 ...
 ---
 name:            test_ashr_i16_imm1
bb.1 (%ir-block.0):
     ; ALL-LABEL: name: test_ashr_i16_imm1
     ; ALL: liveins: $edi
     ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
     ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
     ; ALL: [[SAR16r1_:%[0-9]+]]:gr16 = SAR16r1 [[COPY1]], implicit-def $eflags
     ; ALL: $ax = COPY [[SAR16r1_]]
     ; ALL: RET 0, implicit $ax
     %0(s32) = COPY $edi
-    %2(s8) = G_CONSTANT i16 1
+    %2(s8) = G_CONSTANT i8 1
     %1(s16) = G_TRUNC %0(s32)
     %3(s16) = G_ASHR %1, %2
     $ax = COPY %3(s16)
     RET 0, implicit $ax
 
 ...
 ---
 name:            test_ashr_i8

test/CodeGen/X86/GlobalISel/select-lshr-scalar.mir

bb.1 (%ir-block.0):
 
     ; ALL-LABEL: name: test_lshr_i64_imm
     ; ALL: liveins: $rdi
     ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
     ; ALL: [[SHR64ri:%[0-9]+]]:gr64 = SHR64ri [[COPY]], 5, implicit-def $eflags
     ; ALL: $rax = COPY [[SHR64ri]]
     ; ALL: RET 0, implicit $rax
     %0(s64) = COPY $rdi
-    %1(s8) = G_CONSTANT i64 5
+    %1(s8) = G_CONSTANT i8 5
     %2(s64) = G_LSHR %0, %1
     $rax = COPY %2(s64)
     RET 0, implicit $rax
 
 ...
 ---
 name:            test_lshr_i64_imm1
 alignment:       4
bb.1 (%ir-block.0):
 
     ; ALL-LABEL: name: test_lshr_i64_imm1
     ; ALL: liveins: $rdi
     ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
     ; ALL: [[SHR64r1_:%[0-9]+]]:gr64 = SHR64r1 [[COPY]], implicit-def $eflags
     ; ALL: $rax = COPY [[SHR64r1_]]
     ; ALL: RET 0, implicit $rax
     %0(s64) = COPY $rdi
-    %1(s8) = G_CONSTANT i64 1
+    %1(s8) = G_CONSTANT i8 1
     %2(s64) = G_LSHR %0, %1
     $rax = COPY %2(s64)
     RET 0, implicit $rax
 
 ...
 ---
 name:            test_lshr_i32
 alignment:       4
bb.1 (%ir-block.0):
 
     ; ALL-LABEL: name: test_lshr_i32_imm
     ; ALL: liveins: $edi
     ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
     ; ALL: [[SHR32ri:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 5, implicit-def $eflags
     ; ALL: $eax = COPY [[SHR32ri]]
     ; ALL: RET 0, implicit $eax
     %0(s32) = COPY $edi
-    %1(s8) = G_CONSTANT i32 5
+    %1(s8) = G_CONSTANT i8 5
     %2(s32) = G_LSHR %0, %1
     $eax = COPY %2(s32)
     RET 0, implicit $eax
 
 ...
 ---
 name:            test_lshr_i32_imm1
 alignment:       4
bb.1 (%ir-block.0):
 
     ; ALL-LABEL: name: test_lshr_i32_imm1
     ; ALL: liveins: $edi
     ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
     ; ALL: [[SHR32r1_:%[0-9]+]]:gr32 = SHR32r1 [[COPY]], implicit-def $eflags
     ; ALL: $eax = COPY [[SHR32r1_]]
     ; ALL: RET 0, implicit $eax
     %0(s32) = COPY $edi
-    %1(s8) = G_CONSTANT i32 1
+    %1(s8) = G_CONSTANT i8 1
     %2(s32) = G_LSHR %0, %1
     $eax = COPY %2(s32)
     RET 0, implicit $eax
 
 ...
 ---
 name:            test_lshr_i16
 alignment:       4
bb.1 (%ir-block.0):
     ; ALL-LABEL: name: test_lshr_i16_imm
     ; ALL: liveins: $edi
     ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
     ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
     ; ALL: [[SHR16ri:%[0-9]+]]:gr16 = SHR16ri [[COPY1]], 5, implicit-def $eflags
     ; ALL: $ax = COPY [[SHR16ri]]
     ; ALL: RET 0, implicit $ax
     %0(s32) = COPY $edi
-    %2(s8) = G_CONSTANT i16 5
+    %2(s8) = G_CONSTANT i8 5
     %1(s16) = G_TRUNC %0(s32)
     %3(s16) = G_LSHR %1, %2
     $ax = COPY %3(s16)
     RET 0, implicit $ax
 
 ...
 ---
 name:            test_lshr_i16_imm1
bb.1 (%ir-block.0):
     ; ALL-LABEL: name: test_lshr_i16_imm1
     ; ALL: liveins: $edi
     ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
     ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
     ; ALL: [[SHR16r1_:%[0-9]+]]:gr16 = SHR16r1 [[COPY1]], implicit-def $eflags
     ; ALL: $ax = COPY [[SHR16r1_]]
     ; ALL: RET 0, implicit $ax
     %0(s32) = COPY $edi
-    %2(s8) = G_CONSTANT i16 1
+    %2(s8) = G_CONSTANT i8 1
     %1(s16) = G_TRUNC %0(s32)
     %3(s16) = G_LSHR %1, %2
     $ax = COPY %3(s16)
     RET 0, implicit $ax
 
 ...
 ---
 name:            test_lshr_i8

test/CodeGen/X86/GlobalISel/select-shl-scalar.mir

bb.1 (%ir-block.0):
 
     ; ALL-LABEL: name: test_shl_i64_imm
     ; ALL: liveins: $rdi
     ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
     ; ALL: [[SHL64ri:%[0-9]+]]:gr64 = SHL64ri [[COPY]], 5, implicit-def $eflags
     ; ALL: $rax = COPY [[SHL64ri]]
     ; ALL: RET 0, implicit $rax
     %0(s64) = COPY $rdi
-    %1(s8) = G_CONSTANT i64 5
+    %1(s8) = G_CONSTANT i8 5
     %2(s64) = G_SHL %0, %1
     $rax = COPY %2(s64)
     RET 0, implicit $rax
 
 ...
 ---
 name:            test_shl_i64_imm1
 alignment:       4
bb.1 (%ir-block.0):
 
     ; ALL-LABEL: name: test_shl_i64_imm1
     ; ALL: liveins: $rdi
     ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
     ; ALL: [[ADD64rr:%[0-9]+]]:gr64 = ADD64rr [[COPY]], [[COPY]], implicit-def $eflags
     ; ALL: $rax = COPY [[ADD64rr]]
     ; ALL: RET 0, implicit $rax
     %0(s64) = COPY $rdi
-    %1(s8) = G_CONSTANT i64 1
+    %1(s8) = G_CONSTANT i8 1
     %2(s64) = G_SHL %0, %1
     $rax = COPY %2(s64)
     RET 0, implicit $rax
 
 ...
 ---
 name:            test_shl_i32
 alignment:       4
bb.1 (%ir-block.0):
 
     ; ALL-LABEL: name: test_shl_i32_imm
     ; ALL: liveins: $edi
     ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
     ; ALL: [[SHL32ri:%[0-9]+]]:gr32 = SHL32ri [[COPY]], 5, implicit-def $eflags
     ; ALL: $eax = COPY [[SHL32ri]]
     ; ALL: RET 0, implicit $eax
     %0(s32) = COPY $edi
-    %1(s8) = G_CONSTANT i32 5
+    %1(s8) = G_CONSTANT i8 5
     %2(s32) = G_SHL %0, %1
     $eax = COPY %2(s32)
     RET 0, implicit $eax
 
 ...
 ---
 name:            test_shl_i32_imm1
 alignment:       4
bb.1 (%ir-block.0):
 
     ; ALL-LABEL: name: test_shl_i32_imm1
     ; ALL: liveins: $edi
     ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
     ; ALL: [[ADD32rr:%[0-9]+]]:gr32 = ADD32rr [[COPY]], [[COPY]], implicit-def $eflags
     ; ALL: $eax = COPY [[ADD32rr]]
     ; ALL: RET 0, implicit $eax
     %0(s32) = COPY $edi
-    %1(s8) = G_CONSTANT i32 1
+    %1(s8) = G_CONSTANT i8 1
     %2(s32) = G_SHL %0, %1
     $eax = COPY %2(s32)
     RET 0, implicit $eax
 
 ...
 ---
 name:            test_shl_i16
 alignment:       4
bb.1 (%ir-block.0):
     ; ALL-LABEL: name: test_shl_i16_imm
     ; ALL: liveins: $edi
     ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
     ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
     ; ALL: [[SHL16ri:%[0-9]+]]:gr16 = SHL16ri [[COPY1]], 5, implicit-def $eflags
     ; ALL: $ax = COPY [[SHL16ri]]
     ; ALL: RET 0, implicit $ax
     %0(s32) = COPY $edi
-    %2(s8) = G_CONSTANT i16 5
+    %2(s8) = G_CONSTANT i8 5
     %1(s16) = G_TRUNC %0(s32)
     %3(s16) = G_SHL %1, %2
     $ax = COPY %3(s16)
     RET 0, implicit $ax
 
 ...
 ---
 name:            test_shl_i16_imm1
bb.1 (%ir-block.0):
     ; ALL-LABEL: name: test_shl_i16_imm1
     ; ALL: liveins: $edi
     ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
     ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
     ; ALL: [[ADD16rr:%[0-9]+]]:gr16 = ADD16rr [[COPY1]], [[COPY1]], implicit-def $eflags
     ; ALL: $ax = COPY [[ADD16rr]]
     ; ALL: RET 0, implicit $ax
     %0(s32) = COPY $edi
-    %2(s8) = G_CONSTANT i16 1
+    %2(s8) = G_CONSTANT i8 1
     %1(s16) = G_TRUNC %0(s32)
     %3(s16) = G_SHL %1, %2
     $ax = COPY %3(s16)
     RET 0, implicit $ax
 
 ...
 ---
 name:            test_shl_i8

test/Verifier/test_g_constant.mir

-#RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+#RUN: not llc -march=aarch64 -o - -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
 # REQUIRES: global-isel, aarch64-registered-target
 
 ---
 name:            test_constant
 legalized:       true
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 liveins:
 body:             |
   bb.0:
     ; CHECK: Bad machine code: Instruction cannot use a vector result type
     %0:_(<2 x s32>) = G_CONSTANT i32 0
 
     ; CHECK: Bad machine code: Too few operands
     %1:_(s32) = G_CONSTANT
+
+    ; Not a cimm
+    ; CHECK: Bad machine code:  G_CONSTANT operand must be cimm
+    %2:_(s32) = G_CONSTANT 0
+
+    ; Not a cimm
+    ; CHECK: Bad machine code:  G_CONSTANT operand must be cimm
+    %3:_(s32) = G_CONSTANT float 1.0
+
+   ;  Size is bigger than result
+   ; CHECK: Bad machine code: inconsistent constant size
+    %4:_(s32) = G_CONSTANT i64 0
+
+    ; Size is smaller than result
+    ; CHECK: Bad machine code: inconsistent constant size
+    %4:_(s32) = G_CONSTANT i16 0
+
+   ; CHECK: Bad machine code: inconsistent constant size
+    %5:_(p0) = G_CONSTANT i64 0
+
+    ; CHECK: Bad machine code: inconsistent constant size
+    %6:_(p0) = G_CONSTANT i128 0
+
 ...

test/Verifier/test_g_fconstant.mir

-#RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+#RUN: not llc -march=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
 # REQUIRES: global-isel, aarch64-registered-target
 
 ---
-name:            test_fconstant_vector
+name:            test_fconstant
 legalized:       true
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 liveins:
 body:             |
   bb.0:
     ; CHECK: Bad machine code: Instruction cannot use a vector result type
     %0:_(<2 x s32>) = G_FCONSTANT float 0.0
+
+    ; CHECK: Bad machine code: Too few operands
+    %1:_(s32) = G_FCONSTANT
+
+    ; Not a cimm
+    ; CHECK: Bad machine code:  G_FCONSTANT operand must be fpimm
+    %2:_(s32) = G_FCONSTANT 0
+
+    ; Not a cimm
+    ; CHECK: Bad machine code:  G_FCONSTANT operand must be fpimm
+    %3:_(s32) = G_FCONSTANT i32 0
+
+   ;  Size is bigger than result
+   ; CHECK: Bad machine code: inconsistent constant size
+    %4:_(s32) = G_FCONSTANT double 1.0
+
+    ; Size is smaller than result
+    ; CHECK: Bad machine code: inconsistent constant size
+    %4:_(s32) = G_FCONSTANT half 1.0
+
 ...