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[PowerPC] more opportunity for converting reg+reg to reg+imm
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Authored by shchenz on Jan 27 2019, 8:08 PM.

Details

Summary

PowerPC should convert following reg+reg to reg+imm.

body: |
  bb.0.entry:
    liveins: $x3, $f1, $x5  
    $x3 = ADDI8 $x5, 100  
    STFSX killed $f1, $zero8, $x3  
    STD killed $x3, killed $x5, 100  
    BLR8 implicit $lr8, implicit $rm

Fix the bug to make it work.

Diff Detail

Repository
rL LLVM

Event Timeline

shchenz created this revision.Jan 27 2019, 8:08 PM
shchenz edited reviewers, added: steven.zhang; removed: qshanz.Jan 27 2019, 8:09 PM

Looked through this and tried a couple of things but overall it looks good.
My only comments are a couple of minor nit items.

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
3209 ↗(On Diff #183791)

nit:
Since you have updated the condition in the code can you also update the comment above it?

llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instr-add.mir
2 ↗(On Diff #183791)

nit:
You should probably add to the test a comment to say what you are testing here.
It's not really obvious from the test because you just ask to stop after the peephole opt and that could mean you are looking for any number of things.

shchenz updated this revision to Diff 184002.Jan 28 2019, 5:41 PM

Thanks for your comment @stefanp. Updated.

nemanjai accepted this revision.Jan 29 2019, 5:14 AM

Oh yeah, the existing condition was always true. Thanks for fixing this. LGTM.

This revision is now accepted and ready to land.Jan 29 2019, 5:14 AM
shchenz updated this revision to Diff 184213.Jan 29 2019, 5:50 PM

@nemanjai Thanks for your comments.

Change test comment position to avoid YAML grammar error.

shchenz updated this revision to Diff 184215.Jan 29 2019, 5:55 PM

use '#' as a comment marker outside of body.

This revision was automatically updated to reflect the committed changes.