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Differential D57178

[GISel]: Change how CSE is enabled by default for each pass
ClosedPublic

Authored by aditya_nandakumar on Jan 24 2019, 11:57 AM.

Details

Reviewers
qcolombet
aemerson
volkan
bogner
arsenm
Summary

Now add a hook in TargetPassConfig to query if CSE needs to be enabled. By default this hook returns false only for O0 opt level but this can be overridden by the target.
As a consequence of the default of enabled for non O0, a few tests needed to be updated to not use CSE (by passing in -O0) to the run line.

Diff Detail

Repository
rL LLVM

Event Timeline

aditya_nandakumar created this revision.Jan 24 2019, 11:57 AM
Herald added subscribers: javed.absar, nhaehnle, jvesely. · View Herald TranscriptJan 24 2019, 11:57 AM
arsenm added a subscriber: arsenm.Jan 24 2019, 1:29 PM
arsenm added inline comments.
lib/CodeGen/GlobalISel/IRTranslator.cpp
1712–1716

Ternary operator?

lib/CodeGen/GlobalISel/Legalizer.cpp
164–168

Ditto

aditya_nandakumar updated this revision to Diff 183389.Jan 24 2019, 1:37 PM
aditya_nandakumar added a reviewer: arsenm.

Updated based on feedback.

Herald added a subscriber: wdng. · View Herald TranscriptJan 24 2019, 1:37 PM
aditya_nandakumar marked 2 inline comments as done.Jan 24 2019, 1:37 PM
arsenm accepted this revision.Jan 24 2019, 2:03 PM

LGTM

This revision is now accepted and ready to land.Jan 24 2019, 2:03 PM
aditya_nandakumar closed this revision.Jan 24 2019, 3:11 PM

Thanks. Submitted in r352126.

Revision Contents

Diff 183363

include/llvm/CodeGen/TargetPassConfig.h

Show First 20 Lines • Show All 309 Lines • ▼ Show 20 Linespublic:
/// erroring out. /// erroring out.
bool isGlobalISelAbortEnabled() const; bool isGlobalISelAbortEnabled() const;
/// Check whether or not a diagnostic should be emitted when GlobalISel /// Check whether or not a diagnostic should be emitted when GlobalISel
/// uses the fallback path. In other words, it will emit a diagnostic /// uses the fallback path. In other words, it will emit a diagnostic
/// when GlobalISel failed and isGlobalISelAbortEnabled is false. /// when GlobalISel failed and isGlobalISelAbortEnabled is false.
virtual bool reportDiagnosticWhenGlobalISelFallback() const; virtual bool reportDiagnosticWhenGlobalISelFallback() const;
/// Check whether continuous CSE should be enabled in GISel passes.
/// By default, it's enabled for non O0 levels.
virtual bool isGISelCSEEnabled() const;
protected: protected:
// Helper to verify the analysis is really immutable. // Helper to verify the analysis is really immutable.
void setOpt(bool &Opt, bool Val); void setOpt(bool &Opt, bool Val);
/// Methods with trivial inline returns are convenient points in the common /// Methods with trivial inline returns are convenient points in the common
/// codegen pass pipeline where targets may insert passes. Methods with /// codegen pass pipeline where targets may insert passes. Methods with
/// out-of-line standard implementations are major CodeGen stages called by /// out-of-line standard implementations are major CodeGen stages called by
/// addMachinePasses. Some targets may override major stages when inserting /// addMachinePasses. Some targets may override major stages when inserting
▲ Show 20 Lines • Show All 110 Lines • Show Last 20 Lines

lib/CodeGen/GlobalISel/IRTranslator.cpp

Show First 20 Lines • Show All 1,703 Lines • ▼ Show 20 Linesbool IRTranslator::runOnMachineFunction(MachineFunction &CurMF) {
const Function &F = MF->getFunction(); const Function &F = MF->getFunction();
if (F.empty()) if (F.empty())
return false; return false;
GISelCSEAnalysisWrapper &Wrapper = GISelCSEAnalysisWrapper &Wrapper =
getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper(); getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper();
// Set the CSEConfig and run the analysis. // Set the CSEConfig and run the analysis.
GISelCSEInfo *CSEInfo = nullptr; GISelCSEInfo *CSEInfo = nullptr;
TPC = &getAnalysis<TargetPassConfig>(); TPC = &getAnalysis<TargetPassConfig>();
bool IsO0 = TPC->getOptLevel() == CodeGenOpt::Level::None; bool EnableCSE;
// Disable CSE for O0. if (EnableCSEInIRTranslator.getNumOccurrences())
bool EnableCSE = !IsO0 && EnableCSEInIRTranslator; EnableCSE = EnableCSEInIRTranslator;
else
EnableCSE = TPC->isGISelCSEEnabled();
arsenmUnsubmitted
Done
ReplyInline Actions

Ternary operator?

arsenm: Ternary operator?
if (EnableCSE) { if (EnableCSE) {
EntryBuilder = make_unique<CSEMIRBuilder>(CurMF); EntryBuilder = make_unique<CSEMIRBuilder>(CurMF);
std::unique_ptr<CSEConfig> Config = make_unique<CSEConfig>(); std::unique_ptr<CSEConfig> Config = make_unique<CSEConfig>();
CSEInfo = &Wrapper.get(std::move(Config)); CSEInfo = &Wrapper.get(std::move(Config));
EntryBuilder->setCSEInfo(CSEInfo); EntryBuilder->setCSEInfo(CSEInfo);
CurBuilder = make_unique<CSEMIRBuilder>(CurMF); CurBuilder = make_unique<CSEMIRBuilder>(CurMF);
CurBuilder->setCSEInfo(CSEInfo); CurBuilder->setCSEInfo(CSEInfo);
} else { } else {
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lib/CodeGen/GlobalISel/Legalizer.cpp

Show First 20 Lines • Show All 155 Lines • ▼ Show 20 Lines for (MachineInstr &MI : *MBB) {
if (isArtifact(MI)) if (isArtifact(MI))
ArtifactList.insert(&MI); ArtifactList.insert(&MI);
else else
InstList.insert(&MI); InstList.insert(&MI);
} }
} }
std::unique_ptr<MachineIRBuilder> MIRBuilder; std::unique_ptr<MachineIRBuilder> MIRBuilder;
GISelCSEInfo *CSEInfo = nullptr; GISelCSEInfo *CSEInfo = nullptr;
bool IsO0 = TPC.getOptLevel() == CodeGenOpt::Level::None; bool EnableCSE;
// Disable CSE for O0. if (EnableCSEInLegalizer.getNumOccurrences())
bool EnableCSE = !IsO0 && EnableCSEInLegalizer; EnableCSE = EnableCSEInLegalizer;
else
EnableCSE = TPC.isGISelCSEEnabled();
arsenmUnsubmitted
Done
ReplyInline Actions

Ditto

arsenm: Ditto
if (EnableCSE) { if (EnableCSE) {
MIRBuilder = make_unique<CSEMIRBuilder>(); MIRBuilder = make_unique<CSEMIRBuilder>();
std::unique_ptr<CSEConfig> Config = make_unique<CSEConfig>(); std::unique_ptr<CSEConfig> Config = make_unique<CSEConfig>();
CSEInfo = &Wrapper.get(std::move(Config)); CSEInfo = &Wrapper.get(std::move(Config));
MIRBuilder->setCSEInfo(CSEInfo); MIRBuilder->setCSEInfo(CSEInfo);
} else } else
MIRBuilder = make_unique<MachineIRBuilder>(); MIRBuilder = make_unique<MachineIRBuilder>();
// This observer keeps the worklist updated. // This observer keeps the worklist updated.
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lib/CodeGen/TargetPassConfig.cpp

Show First 20 Lines • Show All 1,214 Lines • ▼ Show 20 Lines
//===---------------------------------------------------------------------===// //===---------------------------------------------------------------------===//
bool TargetPassConfig::isGlobalISelAbortEnabled() const { bool TargetPassConfig::isGlobalISelAbortEnabled() const {
return TM->Options.GlobalISelAbort == GlobalISelAbortMode::Enable; return TM->Options.GlobalISelAbort == GlobalISelAbortMode::Enable;
} }
bool TargetPassConfig::reportDiagnosticWhenGlobalISelFallback() const { bool TargetPassConfig::reportDiagnosticWhenGlobalISelFallback() const {
return TM->Options.GlobalISelAbort == GlobalISelAbortMode::DisableWithDiag; return TM->Options.GlobalISelAbort == GlobalISelAbortMode::DisableWithDiag;
} }
bool TargetPassConfig::isGISelCSEEnabled() const {
return getOptLevel() != CodeGenOpt::Level::None;
}

test/CodeGen/AArch64/GlobalISel/call-translator-cse.ll

; RUN: llc -mtriple=aarch64-linux-gnu -O1 -stop-after=irtranslator -enable-cse-in-irtranslator=1 -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s ; RUN: llc -mtriple=aarch64-linux-gnu -stop-after=irtranslator -enable-cse-in-irtranslator=1 -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
; CHECK-LABEL: name: test_split_struct ; CHECK-LABEL: name: test_split_struct
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[LO:%[0-9]+]]:_(s64) = G_LOAD %0(p0) :: (load 8 from %ir.ptr) ; CHECK: [[LO:%[0-9]+]]:_(s64) = G_LOAD %0(p0) :: (load 8 from %ir.ptr)
; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[ADDR]], [[CST]](s64) ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[ADDR]], [[CST]](s64)
; CHECK: [[HI:%[0-9]+]]:_(s64) = G_LOAD [[GEP]](p0) :: (load 8 from %ir.ptr + 8) ; CHECK: [[HI:%[0-9]+]]:_(s64) = G_LOAD [[GEP]](p0) :: (load 8 from %ir.ptr + 8)
Show All 25 Lines

test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s # RUN: llc -O0 -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
--- ---
name: test_icmp name: test_icmp
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_icmp ; CHECK-LABEL: name: test_icmp
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[COPY]](s64), [[COPY1]] ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[COPY]](s64), [[COPY1]]
Show All 31 Lines

test/CodeGen/AArch64/GlobalISel/legalize-div.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s # RUN: llc -O0 -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
--- ---
name: test_div name: test_div
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_div ; CHECK-LABEL: name: test_div
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
Show All 31 Lines

test/CodeGen/AArch64/GlobalISel/legalize-ext-cse.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - -enable-cse-in-legalizer=1 -O1 | FileCheck %s # RUN: llc -march=aarch64 -run-pass=legalizer %s -o - -enable-cse-in-legalizer=1 | FileCheck %s
--- ---
name: test_cse_in_legalizer name: test_cse_in_legalizer
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_cse_in_legalizer ; CHECK-LABEL: name: test_cse_in_legalizer
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
Show All 11 Lines

test/CodeGen/AArch64/GlobalISel/legalize-ext.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s # RUN: llc -O0 -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
--- ---
name: test_ext name: test_ext
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_ext ; CHECK-LABEL: name: test_ext
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: $w0 = COPY [[TRUNC]](s32) ; CHECK: $w0 = COPY [[TRUNC]](s32)
▲ Show 20 Lines • Show All 164 Lines • Show Last 20 Lines

test/CodeGen/AArch64/GlobalISel/legalize-load-store-fewerElts.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=aarch64 -o - -run-pass=legalizer %s | FileCheck %s # RUN: llc -O0 -march=aarch64 -o - -run-pass=legalizer %s | FileCheck %s
--- ---
name: load_v4s32 name: load_v4s32
legalized: false legalized: false
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1: bb.1:
liveins: $x0, $x1 liveins: $x0, $x1
▲ Show 20 Lines • Show All 44 Lines • Show Last 20 Lines

test/CodeGen/AArch64/GlobalISel/legalize-load-store-s128-unaligned.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=aarch64 -o - -run-pass=legalizer %s | FileCheck %s # RUN: llc -O0 -march=aarch64 -o - -run-pass=legalizer %s | FileCheck %s
--- ---
name: loadstore128_align4 name: loadstore128_align4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1: bb.1:
liveins: $x0, $x1 liveins: $x0, $x1
Show All 21 Lines

test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s # RUN: llc -O0 -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
--- ---
name: test_load name: test_load
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: test_load ; CHECK-LABEL: name: test_load
▲ Show 20 Lines • Show All 95 Lines • Show Last 20 Lines

test/CodeGen/AArch64/GlobalISel/legalize-phi.mir

# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -run-pass=legalizer %s -o - | FileCheck %s # RUN: llc -O0 -mtriple=aarch64-unknown-unknown -verify-machineinstrs -run-pass=legalizer %s -o - | FileCheck %s
--- | --- |
; ModuleID = '/tmp/test.ll' ; ModuleID = '/tmp/test.ll'
source_filename = "/tmp/test.ll" source_filename = "/tmp/test.ll"
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-unknown-unknown" target triple = "aarch64-unknown-unknown"
define i32 @legalize_phi(i32 %argc) { define i32 @legalize_phi(i32 %argc) {
entry: entry:
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test/CodeGen/AArch64/GlobalISel/legalize-rem.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s # RUN: llc -O0 -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
--- ---
name: test_urem_64 name: test_urem_64
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_urem_64 ; CHECK-LABEL: name: test_urem_64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[COPY]], [[COPY1]] ; CHECK: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[COPY]], [[COPY1]]
▲ Show 20 Lines • Show All 96 Lines • Show Last 20 Lines

test/CodeGen/AArch64/GlobalISel/legalize-shift.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s # RUN: llc -O0 -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
--- ---
name: test_shift name: test_shift
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_shift ; CHECK-LABEL: name: test_shift
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
▲ Show 20 Lines • Show All 88 Lines • Show Last 20 Lines

test/CodeGen/AArch64/GlobalISel/legalize-simple.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s # RUN: llc -O0 -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
--- ---
name: test_simple name: test_simple
body: | body: |
; CHECK-LABEL: name: test_simple ; CHECK-LABEL: name: test_simple
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64) ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64)
▲ Show 20 Lines • Show All 134 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s # RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
--- ---
name: test_sext_s32_to_s64 name: test_sext_s32_to_s64
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_sext_s32_to_s64 ; CHECK-LABEL: name: test_sext_s32_to_s64
▲ Show 20 Lines • Show All 66 Lines • Show Last 20 Lines

test/CodeGen/ARM/GlobalISel/arm-legalize-bitcounts.mir

# RUN: llc -mtriple arm-linux-gnueabi -mattr=+v5t -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,CLZ # RUN: llc -O0 -mtriple arm-linux-gnueabi -mattr=+v5t -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,CLZ
# RUN: llc -mtriple arm-linux-gnueabi -mattr=-v5t -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,LIBCALLS # RUN: llc -O0 -mtriple arm-linux-gnueabi -mattr=-v5t -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,LIBCALLS
--- | --- |
define void @test_ctlz_s32() { ret void } define void @test_ctlz_s32() { ret void }
define void @test_ctlz_zero_undef_s32() { ret void } define void @test_ctlz_zero_undef_s32() { ret void }
; same as above but with extensions ; same as above but with extensions
define void @test_ctlz_s16() { ret void } define void @test_ctlz_s16() { ret void }
define void @test_ctlz_zero_undef_s8() { ret void } define void @test_ctlz_zero_undef_s8() { ret void }
... ...
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test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir

# RUN: llc -mtriple arm-linux-gnueabi -mattr=+hwdiv-arm -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,HWDIV # RUN: llc -O0 -mtriple arm-linux-gnueabi -mattr=+hwdiv-arm -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,HWDIV
# RUN: llc -mtriple arm-linux-gnueabi -mattr=-hwdiv-arm -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,SOFT,SOFT-AEABI # RUN: llc -O0 -mtriple arm-linux-gnueabi -mattr=-hwdiv-arm -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,SOFT,SOFT-AEABI
# RUN: llc -mtriple arm-linux-gnu -mattr=+hwdiv-arm -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,HWDIV # RUN: llc -O0 -mtriple arm-linux-gnu -mattr=+hwdiv-arm -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,HWDIV
# RUN: llc -mtriple arm-linux-gnu -mattr=-hwdiv-arm -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,SOFT,SOFT-DEFAULT # RUN: llc -O0 -mtriple arm-linux-gnu -mattr=-hwdiv-arm -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,SOFT,SOFT-DEFAULT
--- | --- |
define void @test_sdiv_i32() { ret void } define void @test_sdiv_i32() { ret void }
define void @test_udiv_i32() { ret void } define void @test_udiv_i32() { ret void }
define void @test_sdiv_i16() { ret void } define void @test_sdiv_i16() { ret void }
define void @test_udiv_i16() { ret void } define void @test_udiv_i16() { ret void }
define void @test_sdiv_i8() { ret void } define void @test_sdiv_i8() { ret void }
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test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir

# RUN: llc -mtriple arm-linux-gnueabihf -mattr=+vfp2 -float-abi=hard -run-pass=legalizer %s -o - | FileCheck %s -check-prefix CHECK -check-prefix HARD # RUN: llc -O0 -mtriple arm-linux-gnueabihf -mattr=+vfp2 -float-abi=hard -run-pass=legalizer %s -o - | FileCheck %s -check-prefix CHECK -check-prefix HARD
# RUN: llc -mtriple arm-linux-gnueabi -mattr=+vfp2,+soft-float -float-abi=soft -run-pass=legalizer %s -o - | FileCheck %s -check-prefix CHECK -check-prefix SOFT -check-prefix SOFT-AEABI # RUN: llc -O0 -mtriple arm-linux-gnueabi -mattr=+vfp2,+soft-float -float-abi=soft -run-pass=legalizer %s -o - | FileCheck %s -check-prefix CHECK -check-prefix SOFT -check-prefix SOFT-AEABI
# RUN: llc -mtriple arm-linux-gnu -mattr=+soft-float -float-abi=soft -run-pass=legalizer %s -o - | FileCheck %s -check-prefix CHECK -check-prefix SOFT -check-prefix SOFT-DEFAULT # RUN: llc -O0 -mtriple arm-linux-gnu -mattr=+soft-float -float-abi=soft -run-pass=legalizer %s -o - | FileCheck %s -check-prefix CHECK -check-prefix SOFT -check-prefix SOFT-DEFAULT
--- | --- |
define void @test_frem_float() { ret void } define void @test_frem_float() { ret void }
define void @test_frem_double() { ret void } define void @test_frem_double() { ret void }
define void @test_fpow_float() { ret void } define void @test_fpow_float() { ret void }
define void @test_fpow_double() { ret void } define void @test_fpow_double() { ret void }
define void @test_fadd_float() { ret void } define void @test_fadd_float() { ret void }
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test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll

; RUN: llc -mtriple arm-unknown -mattr=+vfp2,+v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=ARM -check-prefix=LITTLE ; RUN: llc -O0 -mtriple arm-unknown -mattr=+vfp2,+v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=ARM -check-prefix=LITTLE
; RUN: llc -mtriple armeb-unknown -mattr=+vfp2,+v4t -global-isel -global-isel-abort=0 -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=ARM -check-prefix=BIG ; RUN: llc -O0 -mtriple armeb-unknown -mattr=+vfp2,+v4t -global-isel -global-isel-abort=0 -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=ARM -check-prefix=BIG
; XFAIL: armeb ; XFAIL: armeb
; RUN: llc -mtriple thumb-unknown -mattr=+vfp2,+v6t2 -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=LITTLE -check-prefix=THUMB ; RUN: llc -O0 -mtriple thumb-unknown -mattr=+vfp2,+v6t2 -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=LITTLE -check-prefix=THUMB
declare arm_aapcscc i32* @simple_reg_params_target(i32, i32*) declare arm_aapcscc i32* @simple_reg_params_target(i32, i32*)
define arm_aapcscc i32* @test_call_simple_reg_params(i32 *%a, i32 %b) { define arm_aapcscc i32* @test_call_simple_reg_params(i32 *%a, i32 %b) {
; CHECK-LABEL: name: test_call_simple_reg_params ; CHECK-LABEL: name: test_call_simple_reg_params
; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY $r0 ; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY $r0
; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
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test/CodeGen/X86/GlobalISel/callingconv.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=i386-linux-gnu -mattr=+sse2 -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32 ; RUN: llc -enable-cse-in-irtranslator=0 -enable-cse-in-legalizer=0 -mtriple=i386-linux-gnu -mattr=+sse2 -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32
; RUN: llc -mtriple=x86_64-linux-gnu -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64 ; RUN: llc -enable-cse-in-irtranslator=0 -enable-cse-in-legalizer=0 -mtriple=x86_64-linux-gnu -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64
define i32 @test_ret_i32() { define i32 @test_ret_i32() {
; X32-LABEL: test_ret_i32: ; X32-LABEL: test_ret_i32:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: movl $20, %eax ; X32-NEXT: movl $20, %eax
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_ret_i32: ; X64-LABEL: test_ret_i32:
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test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple=i386-linux-gnu -mattr=+sse2 -global-isel -stop-after=irtranslator < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32 ; RUN: llc -O0 -mtriple=i386-linux-gnu -mattr=+sse2 -global-isel -stop-after=irtranslator < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32
; RUN: llc -mtriple=x86_64-linux-gnu -global-isel -stop-after=irtranslator < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64 ; RUN: llc -O0 -mtriple=x86_64-linux-gnu -global-isel -stop-after=irtranslator < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64
@a1_8bit = external global i8 @a1_8bit = external global i8
@a7_8bit = external global i8 @a7_8bit = external global i8
@a8_8bit = external global i8 @a8_8bit = external global i8
define i8 @test_i8_args_8(i8 %arg1, i8 %arg2, i8 %arg3, i8 %arg4, define i8 @test_i8_args_8(i8 %arg1, i8 %arg2, i8 %arg3, i8 %arg4,
; X32-LABEL: name: test_i8_args_8 ; X32-LABEL: name: test_i8_args_8
; X32: bb.1.entry: ; X32: bb.1.entry:
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test/CodeGen/X86/GlobalISel/legalize-add.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64 # RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64
# RUN: llc -mtriple=i386-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32 # RUN: llc -O0 -mtriple=i386-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32
--- | --- |
define void @test_add_i1() { ret void} define void @test_add_i1() { ret void}
define void @test_add_i32() { ret void } define void @test_add_i32() { ret void }
define void @test_add_i64() { ret void } define void @test_add_i64() { ret void }
... ...
--- ---
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test/CodeGen/X86/GlobalISel/legalize-and-scalar.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s # RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s
--- | --- |
define i1 @test_and_i1() { define i1 @test_and_i1() {
%ret = and i1 undef, undef %ret = and i1 undef, undef
ret i1 %ret ret i1 %ret
} }
define i8 @test_and_i8() { define i8 @test_and_i8() {
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test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s # RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s
--- | --- |
define i64 @test_sext_i1(i8 %a) { define i64 @test_sext_i1(i8 %a) {
%val = trunc i8 %a to i1 %val = trunc i8 %a to i1
%r = sext i1 %val to i64 %r = sext i1 %val to i64
ret i64 %r ret i64 %r
} }
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test/CodeGen/X86/GlobalISel/legalize-memop-scalar.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64 # RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64
# RUN: llc -mtriple=i386-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32 # RUN: llc -O0 -mtriple=i386-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32
--- | --- |
define void @test_memop_s8tos32() { define void @test_memop_s8tos32() {
ret void ret void
} }
define void @test_memop_s64() { define void @test_memop_s64() {
ret void ret void
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test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s # RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s
--- | --- |
define void @test_mul_i1() { ret void} define void @test_mul_i1() { ret void}
define i16 @test_mul_i16(i16 %arg1, i16 %arg2) { define i16 @test_mul_i16(i16 %arg1, i16 %arg2) {
%ret = mul i16 %arg1, %arg2 %ret = mul i16 %arg1, %arg2
ret i16 %ret ret i16 %ret
} }
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test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s # RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s
--- | --- |
define i1 @test_or_i1() { define i1 @test_or_i1() {
%ret = or i1 undef, undef %ret = or i1 undef, undef
ret i1 %ret ret i1 %ret
} }
define i8 @test_or_i8() { define i8 @test_or_i8() {
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test/CodeGen/X86/GlobalISel/legalize-sub.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s # RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s
--- | --- |
define void @test_sub_i1() { ret void} define void @test_sub_i1() { ret void}
define i32 @test_sub_i32(i32 %arg1, i32 %arg2) { define i32 @test_sub_i32(i32 %arg1, i32 %arg2) {
%ret = sub i32 %arg1, %arg2 %ret = sub i32 %arg1, %arg2
ret i32 %ret ret i32 %ret
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test/CodeGen/X86/GlobalISel/legalize-trunc.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=i386-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32 # RUN: llc -O0 -mtriple=i386-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32
# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64 # RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64
--- | --- |
define void @trunc_check() { define void @trunc_check() {
ret void ret void
} }
... ...
--- ---
name: trunc_check name: trunc_check
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test/CodeGen/X86/GlobalISel/legalize-xor-scalar.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s # RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s
--- | --- |
define i1 @test_xor_i1() { define i1 @test_xor_i1() {
%ret = xor i1 undef, undef %ret = xor i1 undef, undef
ret i1 %ret ret i1 %ret
} }
define i8 @test_xor_i8() { define i8 @test_xor_i8() {
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test/CodeGen/X86/GlobalISel/x86_64-legalize-sitofp.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s # RUN: llc -O0 -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
--- | --- |
; ModuleID = 'sitofp.ll' ; ModuleID = 'sitofp.ll'
source_filename = "sitofp.c" source_filename = "sitofp.c"
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
; Function Attrs: norecurse nounwind readnone uwtable ; Function Attrs: norecurse nounwind readnone uwtable
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