[RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI

[apazos]

Summary

Affected instructions:
PseudoLI simplest form (ADDI with X0)
ALU operations with immediate (they do not set status flag - ADDI, ORI, XORI)

[asb]

Adding myself as reviewer.

[asb]

I think it would be best to have a separate patch to fix isReMaterializable for LUI affecting the neighbouring instructions, and leave this patch for the isAsCheapAsAMove changes.

I'd be very happy for you to directly commit the change to isReMaterializable for LUI, and we can focus on discussing isAsCheapAsAMove here.

lib/Target/RISCV/RISCVInstrInfo.td

311 ↗

(On Diff #181360)

Should LUI have isAsCheapAsAMove = 1?

[apazos]

Sure, will update this patch and I have pushed the other changes to separate patches:
R351895 - Fixed isReMaterializable setting for LUI instruction.
https://reviews.llvm.org/D57069 [RISCV] Fixed isReMaterializable setting for ORI, XORI

[asb]

LGTM, thanks. Might be best titled as something like "[RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI"

[asb]

Hi Ana. I reviewed the test changes caused by this commit, and they all seem fine to me.

llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.h

public:
 
   bool
   reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
 
   MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
 
   bool isBranchOffsetInRange(unsigned BranchOpc,
                              int64_t BrOffset) const override;
+
+  bool isAsCheapAsAMove(const MachineInstr &MI) const override;
 };
 }
 #endif

llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.cpp

unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
   case TargetOpcode::INLINEASM: {
     const MachineFunction &MF = *MI.getParent()->getParent();
     const auto &TM = static_cast<const RISCVTargetMachine &>(MF.getTarget());
     return getInlineAsmLength(MI.getOperand(0).getSymbolName(),
                               *TM.getMCAsmInfo());
   }
   }
 }
+
+bool RISCVInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
+  const unsigned Opcode = MI.getOpcode();
+  switch(Opcode) {
+    default:
+      break;
+    case RISCV::ADDI:
+    case RISCV::ORI:
+    case RISCV::XORI:
+      return (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0);
+  }
+  return MI.isAsCheapAsAMove();
+}

llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td

class Priv<string opcodestr, bits<7> funct7>
     : RVInstR<funct7, 0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1, GPR:$rs2),
               opcodestr, "">;
 
 //===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
-let isReMaterializable = 1 in
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
 def LUI : RVInstU<OPC_LUI, (outs GPR:$rd), (ins uimm20_lui:$imm20),
                   "lui", "$rd, $imm20">;
 
 def AUIPC : RVInstU<OPC_AUIPC, (outs GPR:$rd), (ins uimm20_auipc:$imm20),
                     "auipc", "$rd, $imm20">;
 
 let isCall = 1 in
 def JAL : RVInstJ<OPC_JAL, (outs GPR:$rd), (ins simm21_lsb0_jal:$imm20),

 def LHU : Load_ri<0b101, "lhu">;
 
 def SB : Store_rri<0b000, "sb">;
 def SH : Store_rri<0b001, "sh">;
 def SW : Store_rri<0b010, "sw">;
 
 // ADDI isn't always rematerializable, but isReMaterializable will be used as
 // a hint which is verified in isReallyTriviallyReMaterializable.
-let isReMaterializable = 1 in
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
 def ADDI  : ALU_ri<0b000, "addi">;
 
 def SLTI  : ALU_ri<0b010, "slti">;
 def SLTIU : ALU_ri<0b011, "sltiu">;
 
-let isReMaterializable = 1 in {
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
 def XORI  : ALU_ri<0b100, "xori">;
 def ORI   : ALU_ri<0b110, "ori">;
 }
 
 def ANDI  : ALU_ri<0b111, "andi">;
 
 def SLLI : Shift_ri<0, 0b001, "slli">;
 def SRLI : Shift_ri<0, 0b101, "srli">;