[RISCV] Set isReMaterializable for ORI, XORI

[apazos]

Sure, will update this patch and I have pushed the other changes to separate patches:
R351895 - Fixed isReMaterializable setting for LUI instruction.
https://reviews.llvm.org/D57069 [RISCV] Fixed isReMaterializable setting for ORI, XORI

[apazos]

I meant to comment https://reviews.llvm.org/D56526

[asb]

LGTM, thanks. I think the commit would be best titled as something like "[RISCV] Set isReMaterializable for ORI, XORI".

llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td

 
 // ADDI isn't always rematerializable, but isReMaterializable will be used as
 // a hint which is verified in isReallyTriviallyReMaterializable.
 let isReMaterializable = 1 in
 def ADDI  : ALU_ri<0b000, "addi">;
 
 def SLTI  : ALU_ri<0b010, "slti">;
 def SLTIU : ALU_ri<0b011, "sltiu">;
+
+let isReMaterializable = 1 in {
 def XORI  : ALU_ri<0b100, "xori">;
 def ORI   : ALU_ri<0b110, "ori">;
+}
+
 def ANDI  : ALU_ri<0b111, "andi">;
 
 def SLLI : Shift_ri<0, 0b001, "slli">;
 def SRLI : Shift_ri<0, 0b101, "srli">;
 def SRAI : Shift_ri<1, 0b101, "srai">;
 
 def ADD  : ALU_rr<0b0000000, 0b000, "add">;
 def SUB  : ALU_rr<0b0100000, 0b000, "sub">;