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[RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI

Description

[RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI

Summary:
Affected instructions:
PseudoLI simplest form (ADDI with X0)
ALU operations with immediate (they do not set status flag - ADDI, ORI, XORI)

Reviewers: asb

Reviewed By: asb

Subscribers: shiva0217, rkruppe, kito-cheng, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei

Differential Revision: https://reviews.llvm.org/D56526

Details

Committed
apazosJan 23 2019, 6:41 PM
Reviewer
asb
Differential Revision
D56526: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI
Parents
rL352009: Skip test on clang <8 instead of 7
Branches
Unknown
Tags
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