[PowerPC] Fix ADDE, SUBE do not know how to promote operator

[ZhangKang]

Summary

This patch is created to fix the Bugzilla bug 39815.

This patch is to support promotion integer result for the instruction ADDE, SUBE.

Before this fix, for below test case:

@b = common local_unnamed_addr global i64* null, align 8
@a = common local_unnamed_addr global i8 0, align 1

define void @testADDEPromoteResult() {
entry:
  %0 = load i64*, i64** @b, align 8
  %1 = load i64, i64* %0, align 8
  %cmp = icmp ne i64* %0, null
  %conv1 = zext i1 %cmp to i64
  %add = add nsw i64 %1, %conv1
  %2 = trunc i64 %add to i8
  %conv2 = and i8 %2, 5
  store i8 %conv2, i8* @a, align 1
  ret void
}

We use llc test.ll to build the case, then we will get below error:

PromoteIntegerResult #0: t28: i8,i64 = adde t29, Constant:i8<0>, t24:1

Do not know how to promote this operator!
UNREACHABLE executed at /home/ken/llvm/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:55!
Stack dump:
0.	Program arguments: llc sim.ll
1.	Running pass 'Function Pass Manager' on module 'sim.ll'.
2.	Running pass 'PowerPC DAG->DAG Pattern Instruction Selection' on function '@testPromoteOperand'

[hfinkel]

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

146 ↗

(On Diff #179604)

I think that this works, but...

Please add a comment to PromoteIntRes_ADDSUBCARRY stating that it is also handling promotion for the ADDE/SUBE nodes (which differ from the ADDCARRY/SUBCARRY nodes in that the third operand is the input carry flag instead of a carry Boolean).

LGTM.

[ZhangKang]

Add the comments for PromoteIntRes_ADDSUBCARRY.

[ZhangKang]

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

146 ↗

(On Diff #179604)

I have added comments for PromoteIntRes_ADDSUBCARRY.

[jsji]

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

871 ↗

(On Diff #179643)

typo: noes -> nodes

[ZhangKang]

Modify the spelling erros.

[ZhangKang]

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

871 ↗

(On Diff #179643)

Done.

llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

#endif
 
   case ISD::SADDO:
   case ISD::SSUBO:       Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
   case ISD::UADDO:
   case ISD::USUBO:       Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
   case ISD::SMULO:
   case ISD::UMULO:       Res = PromoteIntRes_XMULO(N, ResNo); break;
 
+  case ISD::ADDE:
+  case ISD::SUBE:
   case ISD::ADDCARRY:
   case ISD::SUBCARRY:    Res = PromoteIntRes_ADDSUBCARRY(N, ResNo); break;
 
   case ISD::SADDSAT:
   case ISD::UADDSAT:
   case ISD::SSUBSAT:
   case ISD::USUBSAT:     Res = PromoteIntRes_ADDSUBSAT(N); break;
   case ISD::SMULFIX:     Res = PromoteIntRes_SMULFIX(N); break;
SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
   Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
 
   // Use the calculated overflow everywhere.
   ReplaceValueWith(SDValue(N, 1), Ofl);
 
   return Res;
 }
 
+// Handle promotion for the ADDE/SUBE/ADDCARRY/SUBCARRY nodes. Notice that
+// the third operand of ADDE/SUBE nodes is carry flag, which differs from 
+// the ADDCARRY/SUBCARRY nodes in that the third operand is carry Boolean.
 SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBCARRY(SDNode *N, unsigned ResNo) {
   if (ResNo == 1)
     return PromoteIntRes_Overflow(N);
 
   // We need to sign-extend the operands so the carry value computed by the
   // wide operation will be equivalent to the carry value computed by the
   // narrow operation.
   // An ADDCARRY can generate carry only if any of the operands has its

llvm/trunk/test/CodeGen/PowerPC/pr39815.ll

+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s \
+; RUN:   -verify-machineinstrs | FileCheck %s
+
+@b = common dso_local local_unnamed_addr global i64* null, align 8
+@a = common dso_local local_unnamed_addr global i8 0, align 1
+
+define void @testADDEPromoteResult() {
+entry:
+  %0 = load i64*, i64** @b, align 8
+  %1 = load i64, i64* %0, align 8
+  %cmp = icmp ne i64* %0, null
+  %conv1 = zext i1 %cmp to i64
+  %add = add nsw i64 %1, %conv1
+  %2 = trunc i64 %add to i8
+  %conv2 = and i8 %2, 5
+  store i8 %conv2, i8* @a, align 1
+  ret void
+
+; CHECK-LABEL: @testADDEPromoteResult
+; CHECK:      # %bb.0:
+; CHECK-DAG:   addis [[REG1:[0-9]+]], [[REG2:[0-9]+]], [[VAR1:[a-z0-9A-Z_.]+]]@toc@ha
+; CHECK-DAG:   ld [[REG3:[0-9]+]], [[VAR1]]@toc@l([[REG1]])
+; CHECK-DAG:   lbz [[REG4:[0-9]+]], 0([[REG3]])
+; CHECK-DAG:   addic [[REG5:[0-9]+]], [[REG3]], -1
+; CHECK-DAG:   extsb [[REG6:[0-9]+]], [[REG4]]
+; CHECK-DAG:   addze [[REG7:[0-9]+]], [[REG6]]
+; CHECK-DAG:   addis [[REG8:[0-9]+]], [[REG2]], [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha
+; CHECK-DAG:   andi. [[REG9:[0-9]+]], [[REG7]], 5
+; CHECK-DAG:   stb [[REG9]], [[VAR2]]@toc@l([[REG8]])
+; CHECK:       blr
+}