[PowerPC] fix register class after converting X-FORM instruction to D-FORM instruction

[shchenz]

Summary

This is a issue when adding verify-machineinstrs to PowerPC testcases. The curprit test is CodeGen/PowerPC/convert-rr-to-ri-instrs.mir.

llc -run-pass ppc-mi-peepholes -ppc-convert-rr-to-ri llvm/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir -o - -verify-machineinstrs

** Bad machine code: Illegal virtual register for instruction ***

    function: testLBZX
    basic block: %bb.0 entry (0x1003e7914b8)
    instruction: %7:gprc = LBZ 45, killed %6:g8rc :: (load 1 from %ir.arrayidx, !tbaa !3)
    operand 2: killed %6:g8rc
    Expected a G8RC_NOX0 register, but got a G8RC register

Transform of -ppc-convert-rr-to-ri:
before:

%0:g8rc_and_g8rc_nox0 = LI8 45
 %6:g8rc = RLDICL killed %4:g8rc, 0, 32
 %7:gprc = LBZX %0:g8rc_and_g8rc_nox0, killed %6:g8rc :: (load 1 from %ir.arrayidx, !tbaa !3)

after:

%6:g8rc = RLDICL killed %4:g8rc, 0, 32
 %7:gprc = LBZ 45, killed %6:g8rc :: (load 1 from %ir.arrayidx, !tbaa !3)

Register class for LBZ operand 2 is not right. It should be G8RC_NOX0.

[shchenz]

ping.

[hfinkel]

LGTM

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

bool PPCInstrInfo::transformToImmFormFedByLI(MachineInstr &MI,
   } else
     llvm_unreachable("Should have exited early!");
 
   // For instructions for which the constant register replaces a different
   // operand than where the immediate goes, we need to swap them.
   if (III.OpNoForForwarding != III.ImmOpNo)
     swapMIOperands(MI, III.OpNoForForwarding, III.ImmOpNo);
 
-  // If the R0/X0 register is special for the original instruction and not for
-  // the new instruction (or vice versa), we need to fix up the register class.
+  // If the special R0/X0 register index are different for original instruction
+  // and new instruction, we need to fix up the register class in new
+  // instruction.
   if (!PostRA && III.ZeroIsSpecialOrig != III.ZeroIsSpecialNew) {
-    if (!III.ZeroIsSpecialOrig) {
+    if (III.ZeroIsSpecialNew) {
+      // If operand at III.ZeroIsSpecialNew is physical reg(eg: ZERO/ZERO8), no
+      // need to fix up register class.
       unsigned RegToModify = MI.getOperand(III.ZeroIsSpecialNew).getReg();
+      if (TargetRegisterInfo::isVirtualRegister(RegToModify)) {
         const TargetRegisterClass *NewRC =
           MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ?
           &PPC::GPRC_and_GPRC_NOR0RegClass : &PPC::G8RC_and_G8RC_NOX0RegClass;
         MRI.setRegClass(RegToModify, NewRC);
       }
     }
+  }
   return true;
 }
 
 const TargetRegisterClass *
 PPCInstrInfo::updatedRC(const TargetRegisterClass *RC) const {
   if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
     return &PPC::VSRCRegClass;
   return RC;

llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir

-# RUN: llc -run-pass ppc-mi-peepholes -ppc-convert-rr-to-ri %s -o - | FileCheck %s
-# RUN: llc -start-after ppc-mi-peepholes -ppc-late-peephole %s -o - | FileCheck %s --check-prefix=CHECK-LATE
+# RUN: llc -run-pass ppc-mi-peepholes -ppc-convert-rr-to-ri %s -o - -verify-machineinstrs | FileCheck %s
+# RUN: llc -start-after ppc-mi-peepholes -ppc-late-peephole %s -o - -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-LATE
 
 --- |
   ; ModuleID = 'convert-rr-to-ri-instrs.ll'
   source_filename = "convert-rr-to-ri-instrs.c"
   target datalayout = "e-m:e-i64:64-n32:64"
   target triple = "powerpc64le-unknown-linux-gnu"
   
   ; Function Attrs: norecurse nounwind readnone