This is an archive of the discontinued LLVM Phabricator instance.

[PowerPC] fix register class after converting X-FORM instruction to D-FORM instruction
ClosedPublic

Authored by shchenz on Dec 17 2018, 9:06 PM.

Details

Summary

This is a issue when adding verify-machineinstrs to PowerPC testcases. The curprit test is CodeGen/PowerPC/convert-rr-to-ri-instrs.mir.

llc -run-pass ppc-mi-peepholes -ppc-convert-rr-to-ri llvm/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir -o - -verify-machineinstrs

** Bad machine code: Illegal virtual register for instruction ***

    function: testLBZX
    basic block: %bb.0 entry (0x1003e7914b8)
    instruction: %7:gprc = LBZ 45, killed %6:g8rc :: (load 1 from %ir.arrayidx, !tbaa !3)
    operand 2: killed %6:g8rc
    Expected a G8RC_NOX0 register, but got a G8RC register

Transform of -ppc-convert-rr-to-ri:
before:

%0:g8rc_and_g8rc_nox0 = LI8 45
 %6:g8rc = RLDICL killed %4:g8rc, 0, 32
 %7:gprc = LBZX %0:g8rc_and_g8rc_nox0, killed %6:g8rc :: (load 1 from %ir.arrayidx, !tbaa !3)

after:

%6:g8rc = RLDICL killed %4:g8rc, 0, 32
 %7:gprc = LBZ 45, killed %6:g8rc :: (load 1 from %ir.arrayidx, !tbaa !3)

Register class for LBZ operand 2 is not right. It should be G8RC_NOX0.

Diff Detail

Repository
rL LLVM

Event Timeline

shchenz created this revision.Dec 17 2018, 9:06 PM
jsji edited reviewers, added: steven.zhang; removed: qshanz.Dec 18 2018, 7:44 AM
hfinkel accepted this revision.Dec 27 2018, 3:38 PM

LGTM

This revision is now accepted and ready to land.Dec 27 2018, 3:38 PM
This revision was automatically updated to reflect the committed changes.