ELF: AArch64: Fix errata patch address calculation.

[pcc]

Summary

The code here wants the output section offset of the instruction
requiring the errata patch, not the virtual address. Without this
change we can end up placing a patch out of range if the virtual
address of the code section is large enough.

[ruiu]

LGTM

lld/trunk/ELF/AArch64ErrataFix.cpp

 // InputSections that follow them, we try and place the patches after all the
 // executable sections, although we may need to insert them earlier if the
 // InputSectionDescription is larger than the maximum branch range.
 void AArch64Err843419Patcher::insertPatches(
     InputSectionDescription &ISD, std::vector<Patch843419Section *> &Patches) {
   uint64_t ISLimit;
   uint64_t PrevISLimit = ISD.Sections.front()->OutSecOff;
   uint64_t PatchUpperBound = PrevISLimit + Target->getThunkSectionSpacing();
+  uint64_t OutSecAddr = ISD.Sections.front()->getParent()->Addr;
 
   // Set the OutSecOff of patches to the place where we want to insert them.
   // We use a similar strategy to Thunk placement. Place patches roughly
   // every multiple of maximum branch range.
   auto PatchIt = Patches.begin();
   auto PatchEnd = Patches.end();
   for (const InputSection *IS : ISD.Sections) {
     ISLimit = IS->OutSecOff + IS->getSize();
     if (ISLimit > PatchUpperBound) {
       while (PatchIt != PatchEnd) {
-        if ((*PatchIt)->getLDSTAddr() >= PrevISLimit)
+        if ((*PatchIt)->getLDSTAddr() - OutSecAddr >= PrevISLimit)
           break;
         (*PatchIt)->OutSecOff = PrevISLimit;
         ++PatchIt;
       }
       PatchUpperBound = PrevISLimit + Target->getThunkSectionSpacing();
     }
     PrevISLimit = ISLimit;
   }

lld/trunk/test/ELF/aarch64-cortex-a53-843419-large2.s

+// REQUIRES: aarch64
+// RUN: llvm-mc -filetype=obj -triple=aarch64-none-linux %s -o %t.o
+// RUN: ld.lld --fix-cortex-a53-843419 -Ttext=0x8000000 %t.o -o %t2
+// RUN: llvm-objdump -d --start-address=0x8001000 --stop-address=0x8001004 %t2 | FileCheck %s
+
+.section .text.01, "ax", %progbits
+.balign 4096
+.space 4096 - 8
+adrp x0, thunk
+ldr x1, [x1, #0]
+// CHECK: thunk:
+// CHECK-NEXT: b #67108872 <__CortexA53843419_8001000>
+thunk:
+ldr x0, [x0, :got_lo12:thunk]
+ret
+.space 64 * 1024 * 1024
+
+.section .text.02, "ax", %progbits
+.space 64 * 1024 * 1024