[llvm-mca] Move llvm-mca library to llvm/lib/MCA.

[courbet]

Summary

See PR38731.

[courbet]

update OWNERS

[mattd]

Thanks @courbet , these changes LGTM. I'd wait a day or two to see if anyone else has any feedback from the RFC on the mailinglist:
https://lists.llvm.org/pipermail/llvm-dev/2018-December/128435.html

[andreadb]

This patch LGTM.

The feedback on llvmdev is all positive so far. I suggest to wait until tomorrow morning before committing it (to give a bit more time to other people to reply).

CODE_OWNERS.TXT

 
 N: Quentin Colombet
 E: [e-mail]
 D: Loop Strength Reduction, Register allocators
 
 N: Andrea Di Biagio
 E: [e-mail]
 E: [e-mail]
-D: llvm-mca
+D: MCA, llvm-mca
 
 N: Duncan P. N. Exon Smith
 E: [e-mail]
 D: Branch weights and BlockFrequencyInfo
 
 N: Hal Finkel
 E: [e-mail]
 D: The loop reroller, alias analysis and the PowerPC target

include/llvm/MCA/Context.h

 ///
 /// This file defines a class for holding ownership of various simulated
 /// hardware units.  A Context also provides a utility routine for constructing
 /// a default out-of-order pipeline with fetch, dispatch, execute, and retire
 /// stages.
 ///
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_TOOLS_LLVM_MCA_CONTEXT_H
-#define LLVM_TOOLS_LLVM_MCA_CONTEXT_H
-#include "HardwareUnits/HardwareUnit.h"
-#include "InstrBuilder.h"
-#include "Pipeline.h"
-#include "SourceMgr.h"
+#ifndef LLVM_MCA_CONTEXT_H
+#define LLVM_MCA_CONTEXT_H
+
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MCA/HardwareUnits/HardwareUnit.h"
+#include "llvm/MCA/InstrBuilder.h"
+#include "llvm/MCA/Pipeline.h"
+#include "llvm/MCA/SourceMgr.h"
 #include <memory>
 
 namespace llvm {
 namespace mca {
 
 /// This is a convenience struct to hold the parameters necessary for creating
 /// the pre-built "default" out-of-order pipeline.
 struct PipelineOptions {
public:
   /// This pipeline consists of Fetch, Dispatch, Execute, and Retire stages.
   std::unique_ptr<Pipeline> createDefaultPipeline(const PipelineOptions &Opts,
                                                   InstrBuilder &IB,
                                                   SourceMgr &SrcMgr);
 };
 
 } // namespace mca
 } // namespace llvm
-#endif // LLVM_TOOLS_LLVM_MCA_CONTEXT_H
+#endif // LLVM_MCA_CONTEXT_H

include/llvm/MCA/HWEventListener.h

 //===----------------------- HWEventListener.h ------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file defines the main interface for hardware event listeners.
 ///
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_TOOLS_LLVM_MCA_HWEVENTLISTENER_H
-#define LLVM_TOOLS_LLVM_MCA_HWEVENTLISTENER_H
+#ifndef LLVM_MCA_HWEVENTLISTENER_H
+#define LLVM_MCA_HWEVENTLISTENER_H
 
-#include "Instruction.h"
-#include "Support.h"
 #include "llvm/ADT/ArrayRef.h"
+#include "llvm/MCA/Instruction.h"
+#include "llvm/MCA/Support.h"
 
 namespace llvm {
 namespace mca {
 
 // An HWInstructionEvent represents state changes of instructions that
 // listeners might be interested in. Listeners can choose to ignore any event
 // they are not interested in.
 class HWInstructionEvent {
public:
   virtual ~HWEventListener() {}
 
 private:
   virtual void anchor();
 };
 } // namespace mca
 } // namespace llvm
 
-#endif
+#endif // LLVM_MCA_HWEVENTLISTENER_H

include/llvm/MCA/HardwareUnits/HardwareUnit.h

 //===-------------------------- HardwareUnit.h ------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file defines a base class for describing a simulated hardware
 /// unit.  These units are used to construct a simulated backend.
 ///
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_TOOLS_LLVM_MCA_HARDWAREUNIT_H
-#define LLVM_TOOLS_LLVM_MCA_HARDWAREUNIT_H
+#ifndef LLVM_MCA_HARDWAREUNIT_H
+#define LLVM_MCA_HARDWAREUNIT_H
 
 namespace llvm {
 namespace mca {
 
 class HardwareUnit {
   HardwareUnit(const HardwareUnit &H) = delete;
   HardwareUnit &operator=(const HardwareUnit &H) = delete;
 
 public:
   HardwareUnit() = default;
   virtual ~HardwareUnit();
 };
 
 } // namespace mca
 } // namespace llvm
-#endif // LLVM_TOOLS_LLVM_MCA_HARDWAREUNIT_H
+#endif // LLVM_MCA_HARDWAREUNIT_H

include/llvm/MCA/HardwareUnits/LSUnit.h

 //===------------------------- LSUnit.h --------------------------*- C++-*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// A Load/Store unit class that models load/store queues and that implements
 /// a simple weak memory consistency model.
 ///
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_TOOLS_LLVM_MCA_LSUNIT_H
-#define LLVM_TOOLS_LLVM_MCA_LSUNIT_H
+#ifndef LLVM_MCA_LSUNIT_H
+#define LLVM_MCA_LSUNIT_H
 
-#include "HardwareUnits/HardwareUnit.h"
 #include "llvm/ADT/SmallSet.h"
 #include "llvm/MC/MCSchedule.h"
+#include "llvm/MCA/HardwareUnits/HardwareUnit.h"
 
 namespace llvm {
 namespace mca {
 
 class InstRef;
 class Scheduler;
 
 /// A Load/Store Unit implementing a load and store queues.
#endif
   // store instructions. In practice, store operations don't tend to leave the
   // store queue until they reach the 'Retired' stage (See PR39830).
   void onInstructionExecuted(const InstRef &IR);
 };
 
 } // namespace mca
 } // namespace llvm
 
-#endif
+#endif // LLVM_MCA_LSUNIT_H

include/llvm/MCA/HardwareUnits/RegisterFile.h

 //===--------------------- RegisterFile.h -----------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file defines a register mapping file class.  This class is responsible
 /// for managing hardware register files and the tracking of data dependencies
 /// between registers.
 ///
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_TOOLS_LLVM_MCA_REGISTER_FILE_H
-#define LLVM_TOOLS_LLVM_MCA_REGISTER_FILE_H
+#ifndef LLVM_MCA_REGISTER_FILE_H
+#define LLVM_MCA_REGISTER_FILE_H
 
-#include "HardwareUnits/HardwareUnit.h"
 #include "llvm/ADT/APInt.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSchedule.h"
+#include "llvm/MCA/HardwareUnits/HardwareUnit.h"
 #include "llvm/Support/Error.h"
 
 namespace llvm {
 namespace mca {
 
 class ReadState;
 class WriteState;
 class WriteRef;

 #ifndef NDEBUG
   void dump() const;
 #endif
 };
 
 } // namespace mca
 } // namespace llvm
 
-#endif // LLVM_TOOLS_LLVM_MCA_REGISTER_FILE_H
+#endif // LLVM_MCA_REGISTER_FILE_H

include/llvm/MCA/HardwareUnits/ResourceManager.h

 //===--------------------- ResourceManager.h --------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// The classes here represent processor resource units and their management
 /// strategy.  These classes are managed by the Scheduler.
 ///
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_TOOLS_LLVM_MCA_RESOURCE_MANAGER_H
-#define LLVM_TOOLS_LLVM_MCA_RESOURCE_MANAGER_H
+#ifndef LLVM_MCA_RESOURCE_MANAGER_H
+#define LLVM_MCA_RESOURCE_MANAGER_H
 
-#include "Instruction.h"
-#include "Support.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/MC/MCSchedule.h"
+#include "llvm/MCA/Instruction.h"
+#include "llvm/MCA/Support.h"
 
 namespace llvm {
 namespace mca {
 
 /// Used to notify the internal state of a processor resource.
 ///
 /// A processor resource is available if it is not reserved, and there are
 /// available slots in the buffer.  A processor resource is unavailable if it
void dump() const {
     for (const std::unique_ptr<ResourceState> &Resource : Resources)
       Resource->dump();
   }
 #endif
 };
 } // namespace mca
 } // namespace llvm
 
-#endif // LLVM_TOOLS_LLVM_MCA_RESOURCE_MANAGER_H
+#endif // LLVM_MCA_RESOURCE_MANAGER_H

include/llvm/MCA/HardwareUnits/RetireControlUnit.h

 //===---------------------- RetireControlUnit.h -----------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file simulates the hardware responsible for retiring instructions.
 ///
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_TOOLS_LLVM_MCA_RETIRE_CONTROL_UNIT_H
-#define LLVM_TOOLS_LLVM_MCA_RETIRE_CONTROL_UNIT_H
+#ifndef LLVM_MCA_RETIRE_CONTROL_UNIT_H
+#define LLVM_MCA_RETIRE_CONTROL_UNIT_H
 
-#include "HardwareUnits/HardwareUnit.h"
-#include "Instruction.h"
 #include "llvm/MC/MCSchedule.h"
+#include "llvm/MCA/HardwareUnits/HardwareUnit.h"
+#include "llvm/MCA/Instruction.h"
 #include <vector>
 
 namespace llvm {
 namespace mca {
 
 /// This class tracks which instructions are in-flight (i.e., dispatched but not
 /// retired) in the OoO backend.
 //

 #ifndef NDEBUG
   void dump() const;
 #endif
 };
 
 } // namespace mca
 } // namespace llvm
 
-#endif // LLVM_TOOLS_LLVM_MCA_RETIRE_CONTROL_UNIT_H
+#endif // LLVM_MCA_RETIRE_CONTROL_UNIT_H

include/llvm/MCA/HardwareUnits/Scheduler.h

 //===--------------------- Scheduler.h ------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// A scheduler for Processor Resource Units and Processor Resource Groups.
 ///
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_TOOLS_LLVM_MCA_SCHEDULER_H
-#define LLVM_TOOLS_LLVM_MCA_SCHEDULER_H
+#ifndef LLVM_MCA_SCHEDULER_H
+#define LLVM_MCA_SCHEDULER_H
 
-#include "HardwareUnits/HardwareUnit.h"
-#include "HardwareUnits/LSUnit.h"
-#include "ResourceManager.h"
-#include "Support.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/MC/MCSchedule.h"
+#include "llvm/MCA/HardwareUnits/HardwareUnit.h"
+#include "llvm/MCA/HardwareUnits/LSUnit.h"
+#include "llvm/MCA/HardwareUnits/ResourceManager.h"
+#include "llvm/MCA/Support.h"
 
 namespace llvm {
 namespace mca {
 
 class SchedulerStrategy {
 public:
   SchedulerStrategy() = default;
   virtual ~SchedulerStrategy();
void sanityCheck(const InstRef &IR) const {
     assert(find(ReadySet, IR) == ReadySet.end() && "Already in the ready set!");
     assert(find(IssuedSet, IR) == IssuedSet.end() && "Already executing!");
   }
 #endif // !NDEBUG
 };
 } // namespace mca
 } // namespace llvm
 
-#endif // LLVM_TOOLS_LLVM_MCA_SCHEDULER_H
+#endif // LLVM_MCA_SCHEDULER_H

include/llvm/MCA/InstrBuilder.h

 //===--------------------- InstrBuilder.h -----------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// A builder class for instructions that are statically analyzed by llvm-mca.
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_TOOLS_LLVM_MCA_INSTRBUILDER_H
-#define LLVM_TOOLS_LLVM_MCA_INSTRBUILDER_H
+#ifndef LLVM_MCA_INSTRBUILDER_H
+#define LLVM_MCA_INSTRBUILDER_H
 
-#include "Instruction.h"
-#include "Support.h"
 #include "llvm/MC/MCInstrAnalysis.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MCA/Instruction.h"
+#include "llvm/MCA/Support.h"
 #include "llvm/Support/Error.h"
 
 namespace llvm {
 namespace mca {
 
 /// A builder class that knows how to construct Instruction objects.
 ///
 /// Every llvm-mca Instruction is described by an object of class InstrDesc.
void clear() {
     FirstReturnInst = true;
   }
 
   Expected<std::unique_ptr<Instruction>> createInstruction(const MCInst &MCI);
 };
 } // namespace mca
 } // namespace llvm
 
-#endif
+#endif // LLVM_MCA_INSTRBUILDER_H

include/llvm/MCA/Instruction.h

 //===--------------------- Instruction.h ------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file defines abstractions used by the Pipeline to model register reads,
 /// register writes and instructions.
 ///
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_TOOLS_LLVM_MCA_INSTRUCTION_H
-#define LLVM_TOOLS_LLVM_MCA_INSTRUCTION_H
+#ifndef LLVM_MCA_INSTRUCTION_H
+#define LLVM_MCA_INSTRUCTION_H
 
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Support/MathExtras.h"
 
 #ifndef NDEBUG
 #include "llvm/Support/raw_ostream.h"

 #ifndef NDEBUG
   void dump() const;
 #endif
 };
 
 } // namespace mca
 } // namespace llvm
 
-#endif
+#endif  // LLVM_MCA_INSTRUCTION_H

include/llvm/MCA/Pipeline.h

 //===--------------------- Pipeline.h ---------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file implements an ordered container of stages that simulate the
 /// pipeline of a hardware backend.
 ///
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_TOOLS_LLVM_MCA_PIPELINE_H
-#define LLVM_TOOLS_LLVM_MCA_PIPELINE_H
+#ifndef LLVM_MCA_PIPELINE_H
+#define LLVM_MCA_PIPELINE_H
 
-#include "HardwareUnits/Scheduler.h"
-#include "Stages/Stage.h"
 #include "llvm/ADT/SmallVector.h"
+#include "llvm/MCA/HardwareUnits/Scheduler.h"
+#include "llvm/MCA/Stages/Stage.h"
 #include "llvm/Support/Error.h"
 
 namespace llvm {
 namespace mca {
 
 class HWEventListener;
 
 /// A pipeline for a specific subtarget.
public:
   /// Returns the total number of simulated cycles.
   Expected<unsigned> run();
 
   void addEventListener(HWEventListener *Listener);
 };
 } // namespace mca
 } // namespace llvm
 
-#endif // LLVM_TOOLS_LLVM_MCA_PIPELINE_H
+#endif // LLVM_MCA_PIPELINE_H

include/llvm/MCA/SourceMgr.h

 //===--------------------- SourceMgr.h --------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 /// This file implements class SourceMgr. Class SourceMgr abstracts the input
 /// code sequence (a sequence of MCInst), and assings unique identifiers to
 /// every instruction in the sequence.
 ///
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_TOOLS_LLVM_MCA_SOURCEMGR_H
-#define LLVM_TOOLS_LLVM_MCA_SOURCEMGR_H
+#ifndef LLVM_MCA_SOURCEMGR_H
+#define LLVM_MCA_SOURCEMGR_H
 
 #include "llvm/ADT/ArrayRef.h"
 
 namespace llvm {
 namespace mca {
 
 class Instruction;
 
public:
   using const_iterator = ArrayRef<UniqueInst>::const_iterator;
   const_iterator begin() const { return Sequence.begin(); }
   const_iterator end() const { return Sequence.end(); }
 };
 
 } // namespace mca
 } // namespace llvm
 
-#endif
+#endif // LLVM_MCA_SOURCEMGR_H

include/llvm/MCA/Stages/DispatchStage.h

 /// This file models the dispatch component of an instruction pipeline.
 ///
 /// The DispatchStage is responsible for updating instruction dependencies
 /// and communicating to the simulated instruction scheduler that an instruction
 /// is ready to be scheduled for execution.
 ///
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_TOOLS_LLVM_MCA_DISPATCH_STAGE_H
-#define LLVM_TOOLS_LLVM_MCA_DISPATCH_STAGE_H
+#ifndef LLVM_MCA_DISPATCH_STAGE_H
+#define LLVM_MCA_DISPATCH_STAGE_H
 
-#include "HWEventListener.h"
-#include "HardwareUnits/RegisterFile.h"
-#include "HardwareUnits/RetireControlUnit.h"
-#include "Instruction.h"
-#include "Stages/Stage.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MCA/HWEventListener.h"
+#include "llvm/MCA/HardwareUnits/RegisterFile.h"
+#include "llvm/MCA/HardwareUnits/RetireControlUnit.h"
+#include "llvm/MCA/Instruction.h"
+#include "llvm/MCA/Stages/Stage.h"
 
 namespace llvm {
 namespace mca {
 
 // Implements the hardware dispatch logic.
 //
 // This class is responsible for the dispatch stage, in which instructions are
 // dispatched in groups to the Scheduler.  An instruction can be dispatched if

 
 #ifndef NDEBUG
   void dump() const;
 #endif
 };
 } // namespace mca
 } // namespace llvm
 
-#endif // LLVM_TOOLS_LLVM_MCA_DISPATCH_STAGE_H
+#endif // LLVM_MCA_DISPATCH_STAGE_H

include/llvm/MCA/Stages/EntryStage.h

 //===---------------------- EntryStage.h ------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file defines the Entry stage of an instruction pipeline.  Its sole
 /// purpose in life is to pick instructions in sequence and move them to the
 /// next pipeline stage.
 ///
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_TOOLS_LLVM_MCA_ENTRY_STAGE_H
-#define LLVM_TOOLS_LLVM_MCA_ENTRY_STAGE_H
+#ifndef LLVM_MCA_ENTRY_STAGE_H
+#define LLVM_MCA_ENTRY_STAGE_H
 
-#include "SourceMgr.h"
-#include "Stages/Stage.h"
 #include "llvm/ADT/SmallVector.h"
+#include "llvm/MCA/SourceMgr.h"
+#include "llvm/MCA/Stages/Stage.h"
 
 namespace llvm {
 namespace mca {
 
 class EntryStage final : public Stage {
   InstRef CurrentInstruction;
   SmallVector<std::unique_ptr<Instruction>, 16> Instructions;
   SourceMgr &SM;
public:
   Error execute(InstRef &IR) override;
   Error cycleStart() override;
   Error cycleEnd() override;
 };
 
 } // namespace mca
 } // namespace llvm
 
-#endif // LLVM_TOOLS_LLVM_MCA_FETCH_STAGE_H
+#endif // LLVM_MCA_FETCH_STAGE_H

include/llvm/MCA/Stages/ExecuteStage.h

 ///
 /// This file defines the execution stage of a default instruction pipeline.
 ///
 /// The ExecuteStage is responsible for managing the hardware scheduler
 /// and issuing notifications that an instruction has been executed.
 ///
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_TOOLS_LLVM_MCA_EXECUTE_STAGE_H
-#define LLVM_TOOLS_LLVM_MCA_EXECUTE_STAGE_H
+#ifndef LLVM_MCA_EXECUTE_STAGE_H
+#define LLVM_MCA_EXECUTE_STAGE_H
 
-#include "HardwareUnits/Scheduler.h"
-#include "Instruction.h"
-#include "Stages/Stage.h"
 #include "llvm/ADT/ArrayRef.h"
+#include "llvm/MCA/HardwareUnits/Scheduler.h"
+#include "llvm/MCA/Instruction.h"
+#include "llvm/MCA/Stages/Stage.h"
 
 namespace llvm {
 namespace mca {
 
 class ExecuteStage final : public Stage {
   Scheduler &HWS;
 
   Error issueInstruction(InstRef &IR);
public:
 
   // Notify listeners that buffered resources have been consumed or freed.
   void notifyReservedOrReleasedBuffers(const InstRef &IR, bool Reserved) const;
 };
 
 } // namespace mca
 } // namespace llvm
 
-#endif // LLVM_TOOLS_LLVM_MCA_EXECUTE_STAGE_H
+#endif // LLVM_MCA_EXECUTE_STAGE_H

include/llvm/MCA/Stages/InstructionTables.h

 //===--------------------- InstructionTables.h ------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file implements a custom stage to generate instruction tables.
 /// See the description of command-line flag -instruction-tables in
 /// docs/CommandGuide/lvm-mca.rst
 ///
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_TOOLS_LLVM_MCA_INSTRUCTIONTABLES_H
-#define LLVM_TOOLS_LLVM_MCA_INSTRUCTIONTABLES_H
+#ifndef LLVM_MCA_INSTRUCTIONTABLES_H
+#define LLVM_MCA_INSTRUCTIONTABLES_H
 
-#include "HardwareUnits/Scheduler.h"
-#include "Stages/Stage.h"
-#include "Support.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/MC/MCSchedule.h"
+#include "llvm/MCA/HardwareUnits/Scheduler.h"
+#include "llvm/MCA/Stages/Stage.h"
+#include "llvm/MCA/Support.h"
 
 namespace llvm {
 namespace mca {
 
 class InstructionTables final : public Stage {
   const MCSchedModel &SM;
   SmallVector<std::pair<ResourceRef, ResourceCycles>, 4> UsedResources;
   SmallVector<uint64_t, 8> Masks;
 
 public:
   InstructionTables(const MCSchedModel &Model) : Stage(), SM(Model) {
     computeProcResourceMasks(Model, Masks);
   }
 
   bool hasWorkToComplete() const override { return false; }
   Error execute(InstRef &IR) override;
 };
 } // namespace mca
 } // namespace llvm
 
-#endif
+#endif // LLVM_MCA_INSTRUCTIONTABLES_H

include/llvm/MCA/Stages/RetireStage.h

 //===---------------------- RetireStage.h -----------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file defines the retire stage of a default instruction pipeline.
 /// The RetireStage represents the process logic that interacts with the
 /// simulated RetireControlUnit hardware.
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_TOOLS_LLVM_MCA_RETIRE_STAGE_H
-#define LLVM_TOOLS_LLVM_MCA_RETIRE_STAGE_H
+#ifndef LLVM_MCA_RETIRE_STAGE_H
+#define LLVM_MCA_RETIRE_STAGE_H
 
-#include "HardwareUnits/RegisterFile.h"
-#include "HardwareUnits/RetireControlUnit.h"
-#include "Stages/Stage.h"
+#include "llvm/MCA/HardwareUnits/RegisterFile.h"
+#include "llvm/MCA/HardwareUnits/RetireControlUnit.h"
+#include "llvm/MCA/Stages/Stage.h"
 
 namespace llvm {
 namespace mca {
 
 class RetireStage final : public Stage {
   // Owner will go away when we move listeners/eventing to the stages.
   RetireControlUnit &RCU;
   RegisterFile &PRF;
public:
   Error cycleStart() override;
   Error execute(InstRef &IR) override;
   void notifyInstructionRetired(const InstRef &IR) const;
 };
 
 } // namespace mca
 } // namespace llvm
 
-#endif // LLVM_TOOLS_LLVM_MCA_RETIRE_STAGE_H
+#endif // LLVM_MCA_RETIRE_STAGE_H

include/llvm/MCA/Stages/Stage.h

 //===---------------------- Stage.h -----------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file defines a stage.
 /// A chain of stages compose an instruction pipeline.
 ///
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_TOOLS_LLVM_MCA_STAGE_H
-#define LLVM_TOOLS_LLVM_MCA_STAGE_H
+#ifndef LLVM_MCA_STAGE_H
+#define LLVM_MCA_STAGE_H
 
-#include "HWEventListener.h"
+#include "llvm/MCA/HWEventListener.h"
 #include "llvm/Support/Error.h"
 #include <set>
 
 namespace llvm {
 namespace mca {
 
 class InstRef;
 
public:
   template <typename EventT> void notifyEvent(const EventT &Event) const {
     for (HWEventListener *Listener : Listeners)
       Listener->onEvent(Event);
   }
 };
 
 } // namespace mca
 } // namespace llvm
-#endif // LLVM_TOOLS_LLVM_MCA_STAGE_H
+#endif // LLVM_MCA_STAGE_H

include/llvm/MCA/Support.h

 //===--------------------- Support.h ----------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// Helper functions used by various pipeline components.
 ///
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_TOOLS_LLVM_MCA_SUPPORT_H
-#define LLVM_TOOLS_LLVM_MCA_SUPPORT_H
+#ifndef LLVM_MCA_SUPPORT_H
+#define LLVM_MCA_SUPPORT_H
 
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/MC/MCSchedule.h"
 #include "llvm/Support/Error.h"
 
 namespace llvm {
 namespace mca {

 ///  - NumMicroOps / DispatchWidth
 ///  - ProcResourceCycles / #ProcResourceUnits  (for every consumed resource).
 double computeBlockRThroughput(const MCSchedModel &SM, unsigned DispatchWidth,
                                unsigned NumMicroOps,
                                ArrayRef<unsigned> ProcResourceUsage);
 } // namespace mca
 } // namespace llvm
 
-#endif
+#endif // LLVM_MCA_SUPPORT_H

lib/CMakeLists.txt

 # `Demangle', `Support' and `TableGen' libraries are added on the top-level
 # CMakeLists.txt
 
 add_subdirectory(IR)
 add_subdirectory(FuzzMutate)
 add_subdirectory(IRReader)
 add_subdirectory(CodeGen)
 add_subdirectory(BinaryFormat)
 add_subdirectory(Bitcode)
 add_subdirectory(Transforms)
 add_subdirectory(Linker)
 add_subdirectory(Analysis)
 add_subdirectory(LTO)
 add_subdirectory(MC)
+add_subdirectory(MCA)
 add_subdirectory(Object)
 add_subdirectory(ObjectYAML)
 add_subdirectory(Option)
 add_subdirectory(OptRemarks)
 add_subdirectory(DebugInfo)
 add_subdirectory(ExecutionEngine)
 add_subdirectory(Target)
 add_subdirectory(AsmParser)
 add_subdirectory(LineEditor)
 add_subdirectory(ProfileData)
 add_subdirectory(Passes)
 add_subdirectory(TextAPI)
 add_subdirectory(ToolDrivers)
 add_subdirectory(XRay)
 add_subdirectory(Testing)
 add_subdirectory(WindowsManifest)

lib/LLVMBuild.txt

  ExecutionEngine
  FuzzMutate
  LineEditor
  Linker
  IR
  IRReader
  LTO
  MC
+ MCA
  Object
  BinaryFormat
  ObjectYAML
  Option
  OptRemarks
  Passes
  ProfileData
  Support

lib/MCA/CMakeLists.txt

-include_directories(${LLVM_MCA_SOURCE_DIR}/include)
-
-add_library(LLVMMCA
-  STATIC
+add_llvm_library(LLVMMCA
   Context.cpp
   HWEventListener.cpp
   HardwareUnits/HardwareUnit.cpp
   HardwareUnits/LSUnit.cpp
   HardwareUnits/RegisterFile.cpp
   HardwareUnits/ResourceManager.cpp
   HardwareUnits/RetireControlUnit.cpp
   HardwareUnits/Scheduler.cpp
   InstrBuilder.cpp
   Instruction.cpp
   Pipeline.cpp
   Stages/DispatchStage.cpp
   Stages/EntryStage.cpp
   Stages/ExecuteStage.cpp
   Stages/InstructionTables.cpp
   Stages/RetireStage.cpp
   Stages/Stage.cpp
   Support.cpp
-  )
 
-llvm_update_compile_flags(LLVMMCA)
-llvm_map_components_to_libnames(libs
-  MC
-  Support
+  ADDITIONAL_HEADER_DIRS
+  ${LLVM_MAIN_INCLUDE_DIR}/llvm/MCA
   )
-
-target_link_libraries(LLVMMCA ${libs})
-set_target_properties(LLVMMCA PROPERTIES FOLDER "Libraries")

lib/MCA/Context.cpp

 ///
 /// This file defines a class for holding ownership of various simulated
 /// hardware units.  A Context also provides a utility routine for constructing
 /// a default out-of-order pipeline with fetch, dispatch, execute, and retire
 /// stages.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "Context.h"
-#include "HardwareUnits/RegisterFile.h"
-#include "HardwareUnits/RetireControlUnit.h"
-#include "HardwareUnits/Scheduler.h"
-#include "Stages/DispatchStage.h"
-#include "Stages/EntryStage.h"
-#include "Stages/ExecuteStage.h"
-#include "Stages/RetireStage.h"
+#include "llvm/MCA/Context.h"
+#include "llvm/MCA/HardwareUnits/RegisterFile.h"
+#include "llvm/MCA/HardwareUnits/RetireControlUnit.h"
+#include "llvm/MCA/HardwareUnits/Scheduler.h"
+#include "llvm/MCA/Stages/DispatchStage.h"
+#include "llvm/MCA/Stages/EntryStage.h"
+#include "llvm/MCA/Stages/ExecuteStage.h"
+#include "llvm/MCA/Stages/RetireStage.h"
 
 namespace llvm {
 namespace mca {
 
 std::unique_ptr<Pipeline>
 Context::createDefaultPipeline(const PipelineOptions &Opts, InstrBuilder &IB,
                                SourceMgr &SrcMgr) {
   const MCSchedModel &SM = STI.getSchedModel();

lib/MCA/HWEventListener.cpp

 //===----------------------- HWEventListener.cpp ----------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file defines a vtable anchor for class HWEventListener.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "HWEventListener.h"
+#include "llvm/MCA/HWEventListener.h"
 
 namespace llvm {
 namespace mca {
 
 // Anchor the vtable here.
 void HWEventListener::anchor() {}
 } // namespace mca
 } // namespace llvm

lib/MCA/HardwareUnits/HardwareUnit.cpp

 //===------------------------- HardwareUnit.cpp -----------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file defines the anchor for the base class that describes
 /// simulated hardware units.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "HardwareUnits/HardwareUnit.h"
+#include "llvm/MCA/HardwareUnits/HardwareUnit.h"
 
 namespace llvm {
 namespace mca {
 
 // Pin the vtable with this method.
 HardwareUnit::~HardwareUnit() = default;
 
 } // namespace mca
 } // namespace llvm

lib/MCA/HardwareUnits/LSUnit.cpp

 //===----------------------- LSUnit.cpp --------------------------*- C++-*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// A Load-Store Unit for the llvm-mca tool.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "HardwareUnits/LSUnit.h"
-#include "Instruction.h"
+#include "llvm/MCA/HardwareUnits/LSUnit.h"
+#include "llvm/MCA/Instruction.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 
 #define DEBUG_TYPE "llvm-mca"
 
 namespace llvm {
 namespace mca {
 

lib/MCA/HardwareUnits/RegisterFile.cpp

 //===--------------------- RegisterFile.cpp ---------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file defines a register mapping file class.  This class is responsible
 /// for managing hardware register files and the tracking of data dependencies
 /// between registers.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "HardwareUnits/RegisterFile.h"
-#include "Instruction.h"
+#include "llvm/MCA/HardwareUnits/RegisterFile.h"
+#include "llvm/MCA/Instruction.h"
 #include "llvm/Support/Debug.h"
 
 #define DEBUG_TYPE "llvm-mca"
 
 namespace llvm {
 namespace mca {
 
 RegisterFile::RegisterFile(const MCSchedModel &SM, const MCRegisterInfo &mri,

lib/MCA/HardwareUnits/ResourceManager.cpp

 //===--------------------- ResourceManager.cpp ------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// The classes here represent processor resource units and their management
 /// strategy.  These classes are managed by the Scheduler.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "HardwareUnits/ResourceManager.h"
-#include "Support.h"
+#include "llvm/MCA/HardwareUnits/ResourceManager.h"
+#include "llvm/MCA/Support.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 
 namespace llvm {
 namespace mca {
 
 #define DEBUG_TYPE "llvm-mca"
 ResourceStrategy::~ResourceStrategy() = default;
uint64_t DefaultResourceStrategy::select(uint64_t ReadyMask) {
   return CandidateMask;
 }
 
 void DefaultResourceStrategy::used(uint64_t Mask) {
   if (Mask > NextInSequenceMask) {
     RemovedFromNextInSequence |= Mask;
     return;
   }
- 
   NextInSequenceMask &= (~Mask);
   if (NextInSequenceMask)
     return;
 
   NextInSequenceMask = ResourceUnitMask ^ RemovedFromNextInSequence;
   RemovedFromNextInSequence = 0;
 }
 

lib/MCA/HardwareUnits/RetireControlUnit.cpp

 //===---------------------- RetireControlUnit.cpp ---------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file simulates the hardware responsible for retiring instructions.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "HardwareUnits/RetireControlUnit.h"
+#include "llvm/MCA/HardwareUnits/RetireControlUnit.h"
 #include "llvm/Support/Debug.h"
 
 #define DEBUG_TYPE "llvm-mca"
 
 namespace llvm {
 namespace mca {
 
 RetireControlUnit::RetireControlUnit(const MCSchedModel &SM)

lib/MCA/HardwareUnits/Scheduler.cpp

 //===--------------------- Scheduler.cpp ------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // A scheduler for processor resource units and processor resource groups.
 //
 //===----------------------------------------------------------------------===//
 
-#include "HardwareUnits/Scheduler.h"
+#include "llvm/MCA/HardwareUnits/Scheduler.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 
 namespace llvm {
 namespace mca {
 
 #define DEBUG_TYPE "llvm-mca"
 

lib/MCA/InstrBuilder.cpp

 //===--------------------- InstrBuilder.cpp ---------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file implements the InstrBuilder interface.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "InstrBuilder.h"
+#include "llvm/MCA/InstrBuilder.h"
 #include "llvm/ADT/APInt.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/WithColor.h"
 #include "llvm/Support/raw_ostream.h"
 
 #define DEBUG_TYPE "llvm-mca"

lib/MCA/Instruction.cpp

 //===--------------------- Instruction.cpp ----------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines abstractions used by the Pipeline to model register reads,
 // register writes and instructions.
 //
 //===----------------------------------------------------------------------===//
 
-#include "Instruction.h"
+#include "llvm/MCA/Instruction.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 
 namespace llvm {
 namespace mca {
 
 void ReadState::writeStartEvent(unsigned Cycles) {
   assert(DependentWrites);

lib/MCA/LLVMBuild.txt

 ;===- ./tools/llvm-mca/lib/LLVMBuild.txt -----------------------*- Conf -*--===;
 ;
 ;                     The LLVM Compiler Infrastructure
 ;
 ; This file is distributed under the University of Illinois Open Source
 ; License. See LICENSE.TXT for details.
 ;
 ;===------------------------------------------------------------------------===;
 ;
 ; This is an LLVMBuild description file for the components in this subdirectory.
 ;
 ; For more information on the LLVMBuild system, please see:
 ;
 ;   http://llvm.org/docs/LLVMBuild.html
 ;
 ;===------------------------------------------------------------------------===;
 
 [component_0]
 type = Library
 name = MCA
 parent = Libraries
 required_libraries = MC Support

lib/MCA/Pipeline.cpp

 //===--------------------- Pipeline.cpp -------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file implements an ordered container of stages that simulate the
 /// pipeline of a hardware backend.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "Pipeline.h"
-#include "HWEventListener.h"
+#include "llvm/MCA/Pipeline.h"
+#include "llvm/MCA/HWEventListener.h"
 #include "llvm/Support/Debug.h"
 
 namespace llvm {
 namespace mca {
 
 #define DEBUG_TYPE "llvm-mca"
 
 void Pipeline::addEventListener(HWEventListener *Listener) {

lib/MCA/Stages/DispatchStage.cpp

 /// This file models the dispatch component of an instruction pipeline.
 ///
 /// The DispatchStage is responsible for updating instruction dependencies
 /// and communicating to the simulated instruction scheduler that an instruction
 /// is ready to be scheduled for execution.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "Stages/DispatchStage.h"
-#include "HWEventListener.h"
-#include "HardwareUnits/Scheduler.h"
+#include "llvm/MCA/Stages/DispatchStage.h"
+#include "llvm/MCA/HWEventListener.h"
+#include "llvm/MCA/HardwareUnits/Scheduler.h"
 #include "llvm/Support/Debug.h"
 
 #define DEBUG_TYPE "llvm-mca"
 
 namespace llvm {
 namespace mca {
 
 void DispatchStage::notifyInstructionDispatched(const InstRef &IR,

lib/MCA/Stages/EntryStage.cpp

 //===---------------------- EntryStage.cpp ----------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file defines the Fetch stage of an instruction pipeline.  Its sole
 /// purpose in life is to produce instructions for the rest of the pipeline.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "Stages/EntryStage.h"
-#include "Instruction.h"
+#include "llvm/MCA/Stages/EntryStage.h"
+#include "llvm/MCA/Instruction.h"
 
 namespace llvm {
 namespace mca {
 
 bool EntryStage::hasWorkToComplete() const { return CurrentInstruction; }
 
 bool EntryStage::isAvailable(const InstRef & /* unused */) const {
   if (CurrentInstruction)

lib/MCA/Stages/ExecuteStage.cpp

 ///
 /// This file defines the execution stage of an instruction pipeline.
 ///
 /// The ExecuteStage is responsible for managing the hardware scheduler
 /// and issuing notifications that an instruction has been executed.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "Stages/ExecuteStage.h"
+#include "llvm/MCA/Stages/ExecuteStage.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Support/Debug.h"
 
 #define DEBUG_TYPE "llvm-mca"
 
 namespace llvm {
 namespace mca {
 

lib/MCA/Stages/InstructionTables.cpp

 ///
 /// This file implements the method InstructionTables::execute().
 /// Method execute() prints a theoretical resource pressure distribution based
 /// on the information available in the scheduling model, and without running
 /// the pipeline.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "Stages/InstructionTables.h"
+#include "llvm/MCA/Stages/InstructionTables.h"
 
 namespace llvm {
 namespace mca {
 
 Error InstructionTables::execute(InstRef &IR) {
   const InstrDesc &Desc = IR.getInstruction()->getDesc();
   UsedResources.clear();
 

lib/MCA/Stages/RetireStage.cpp

 //===---------------------- RetireStage.cpp ---------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file defines the retire stage of an instruction pipeline.
 /// The RetireStage represents the process logic that interacts with the
 /// simulated RetireControlUnit hardware.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "Stages/RetireStage.h"
-#include "HWEventListener.h"
+#include "llvm/MCA/Stages/RetireStage.h"
+#include "llvm/MCA/HWEventListener.h"
 #include "llvm/Support/Debug.h"
 
 #define DEBUG_TYPE "llvm-mca"
 
 namespace llvm {
 namespace mca {
 
 llvm::Error RetireStage::cycleStart() {

lib/MCA/Stages/Stage.cpp

 //===---------------------- Stage.cpp ---------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file defines a stage.
 /// A chain of stages compose an instruction pipeline.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "Stages/Stage.h"
+#include "llvm/MCA/Stages/Stage.h"
 
 namespace llvm {
 namespace mca {
 
 // Pin the vtable here in the implementation file.
 Stage::~Stage() = default;
 
 void Stage::addListener(HWEventListener *Listener) {
   Listeners.insert(Listener);
 }
 
 } // namespace mca
 } // namespace llvm

lib/MCA/Support.cpp

 //===--------------------- Support.cpp --------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file implements a few helper functions used by various pipeline
 /// components.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "Support.h"
+#include "llvm/MCA/Support.h"
 #include "llvm/MC/MCSchedule.h"
 
 namespace llvm {
 namespace mca {
 
 void computeProcResourceMasks(const MCSchedModel &SM,
                               SmallVectorImpl<uint64_t> &Masks) {
   unsigned ProcResourceID = 0;

tools/llvm-mca/CMakeLists.txt

 include_directories(include)
 
 set(LLVM_LINK_COMPONENTS
   AllTargetsAsmPrinters
   AllTargetsAsmParsers
   AllTargetsDescs
   AllTargetsDisassemblers
   AllTargetsInfos
+  MCA
   MC
   MCParser
   Support
   )
 
 add_llvm_tool(llvm-mca
   llvm-mca.cpp
   CodeRegion.cpp
   CodeRegionGenerator.cpp
   PipelinePrinter.cpp
   Views/DispatchStatistics.cpp
   Views/InstructionInfoView.cpp
   Views/RegisterFileStatistics.cpp
   Views/ResourcePressureView.cpp
   Views/RetireControlUnitStatistics.cpp
   Views/SchedulerStatistics.cpp
   Views/SummaryView.cpp
   Views/TimelineView.cpp
   Views/View.cpp
   )
 
 set(LLVM_MCA_SOURCE_DIR ${CURRENT_SOURCE_DIR})
-add_subdirectory(lib)
-target_link_libraries(llvm-mca PRIVATE LLVMMCA)

tools/llvm-mca/LLVMBuild.txt

 ;   http://llvm.org/docs/LLVMBuild.html
 ;
 ;===------------------------------------------------------------------------===;
 
 [component_0]
 type = Tool
 name = llvm-mca
 parent = Tools
-required_libraries = MC MCParser Support all-targets
+required_libraries = MC MCA MCParser Support all-targets

tools/llvm-mca/PipelinePrinter.h

 ///
 /// PipelinePrinter allows the customization of the performance report.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_PIPELINEPRINTER_H
 #define LLVM_TOOLS_LLVM_MCA_PIPELINEPRINTER_H
 
-#include "Pipeline.h"
 #include "Views/View.h"
 #include "llvm/ADT/SmallVector.h"
+#include "llvm/MCA/Pipeline.h"
 #include "llvm/Support/raw_ostream.h"
 
 #define DEBUG_TYPE "llvm-mca"
 
 namespace llvm {
 namespace mca {
 
 /// A printer class that knows how to collects statistics on the

tools/llvm-mca/Views/SummaryView.cpp

 //===--------------------- SummaryView.cpp -------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file implements the functionalities used by the SummaryView to print
 /// the report information.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "Views/SummaryView.h"
-#include "Support.h"
 #include "llvm/ADT/SmallVector.h"
+#include "llvm/MCA/Support.h"
 #include "llvm/Support/Format.h"
 
 namespace llvm {
 namespace mca {
 
 #define DEBUG_TYPE "llvm-mca"
 
 SummaryView::SummaryView(const MCSchedModel &Model, ArrayRef<MCInst> S,

tools/llvm-mca/Views/View.h

 /// This file defines the main interface for Views. Each view contributes a
 /// portion of the final report generated by the tool.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_VIEW_H
 #define LLVM_TOOLS_LLVM_MCA_VIEW_H
 
-#include "HWEventListener.h"
+#include "llvm/MCA/HWEventListener.h"
 #include "llvm/Support/raw_ostream.h"
 
 namespace llvm {
 namespace mca {
 
 class View : public HWEventListener {
 public:
   virtual void printView(llvm::raw_ostream &OS) const = 0;
   virtual ~View() = default;
   void anchor() override;
 };
 } // namespace mca
 } // namespace llvm
 
 #endif

tools/llvm-mca/llvm-mca.cpp

 // The cpu defaults to the 'native' host cpu.
 // The output defaults to standard output.
 //
 //===----------------------------------------------------------------------===//
 
 #include "CodeRegion.h"
 #include "CodeRegionGenerator.h"
 #include "PipelinePrinter.h"
-#include "Stages/EntryStage.h"
-#include "Stages/InstructionTables.h"
 #include "Views/DispatchStatistics.h"
 #include "Views/InstructionInfoView.h"
 #include "Views/RegisterFileStatistics.h"
 #include "Views/ResourcePressureView.h"
 #include "Views/RetireControlUnitStatistics.h"
 #include "Views/SchedulerStatistics.h"
 #include "Views/SummaryView.h"
 #include "Views/TimelineView.h"
-#include "include/Context.h"
-#include "include/Pipeline.h"
-#include "include/Support.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCObjectFileInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MCA/Context.h"
+#include "llvm/MCA/Pipeline.h"
+#include "llvm/MCA/Stages/EntryStage.h"
+#include "llvm/MCA/Stages/InstructionTables.h"
+#include "llvm/MCA/Support.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/ErrorOr.h"
 #include "llvm/Support/FileSystem.h"
 #include "llvm/Support/Host.h"
 #include "llvm/Support/InitLLVM.h"
 #include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Support/SourceMgr.h"