[WebAssembly] replaced .param/.result by .functype

[aardappel]

Summary

This makes it easier/cleaner to generate a single signature from
this directive. Also:

• Adds the symbol name, such that we don't depend on the location of this directive anymore.
• Actually constructs the signature in the assembler, and make the assembler own it.
• Refactor the use of MVT vs ValType in the streamer and assembler to require less conversions overall.
• Changed 700 or so tests to use it.

[sbc100]

Nice! I wish we could do with without the lexer change and with a more asm-linux syntax.. but I guess that time for bikeshedding that is over.

lib/MC/MCParser/AsmLexer.cpp

653

Is there a risk we could break other asm backends with this?

[aardappel]

lib/MC/MCParser/AsmLexer.cpp

653

If there's other backend that allow parsing a - token followed by > token with no whitespace in between, then we will break them, yes. I think this is highly unlikely, as I don't know of any kind of expression where that could occur.

[dschuff]

otherwise LGTM!

lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp

189

at least the operator == overload on StringRef makes this code not as bad as it could be?

377

why set and then reset the symbol type? all of the intervening returns are error conditions, right?

[aardappel]

lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp

189

Yup, it's ok :)

377

That looks like a refactoring slip-up, will remove.

[aardappel]

Code review fixes: removed redundant setType()

[aardappel]

Fixes because of just introduced WebAssemblyTargetNullStreamer class.

include/llvm/MC/MCAsmMacro.h

enum TokenKind {
     Slash,     // '/'
     BackSlash, // '\'
     LParen, RParen, LBrac, RBrac, LCurly, RCurly,
     Star, Dot, Comma, Dollar, Equal, EqualEqual,
 
     Pipe, PipePipe, Caret,
     Amp, AmpAmp, Exclaim, ExclaimEqual, Percent, Hash,
     Less, LessEqual, LessLess, LessGreater,
-    Greater, GreaterEqual, GreaterGreater, At,
+    Greater, GreaterEqual, GreaterGreater, At, MinusGreater,
 
     // MIPS unary expression operators such as %neg.
     PercentCall16, PercentCall_Hi, PercentCall_Lo, PercentDtprel_Hi,
     PercentDtprel_Lo, PercentGot, PercentGot_Disp, PercentGot_Hi, PercentGot_Lo,
     PercentGot_Ofst, PercentGot_Page, PercentGottprel, PercentGp_Rel, PercentHi,
     PercentHigher, PercentHighest, PercentLo, PercentNeg, PercentPcrel_Hi,
     PercentPcrel_Lo, PercentTlsgd, PercentTlsldm, PercentTprel_Hi,
     PercentTprel_Lo

lib/MC/MCParser/AsmLexer.cpp

return AsmToken(AsmToken::EndOfStatement,
                     StringRef(TokStart, CurPtr - TokStart));
   }
   case '\n':
     IsAtStartOfLine = true;
     IsAtStartOfStatement = true;
     return AsmToken(AsmToken::EndOfStatement, StringRef(TokStart, 1));
   case ':': return AsmToken(AsmToken::Colon, StringRef(TokStart, 1));
   case '+': return AsmToken(AsmToken::Plus, StringRef(TokStart, 1));
-  case '-': return AsmToken(AsmToken::Minus, StringRef(TokStart, 1));
   case '~': return AsmToken(AsmToken::Tilde, StringRef(TokStart, 1));
   case '(': return AsmToken(AsmToken::LParen, StringRef(TokStart, 1));
   case ')': return AsmToken(AsmToken::RParen, StringRef(TokStart, 1));
   case '[': return AsmToken(AsmToken::LBrac, StringRef(TokStart, 1));
   case ']': return AsmToken(AsmToken::RBrac, StringRef(TokStart, 1));
   case '{': return AsmToken(AsmToken::LCurly, StringRef(TokStart, 1));
   case '}': return AsmToken(AsmToken::RCurly, StringRef(TokStart, 1));
   case '*': return AsmToken(AsmToken::Star, StringRef(TokStart, 1));
   case ',': return AsmToken(AsmToken::Comma, StringRef(TokStart, 1));
   case '$': return AsmToken(AsmToken::Dollar, StringRef(TokStart, 1));
   case '@': return AsmToken(AsmToken::At, StringRef(TokStart, 1));
   case '\\': return AsmToken(AsmToken::BackSlash, StringRef(TokStart, 1));
   case '=':
     if (*CurPtr == '=') {
       ++CurPtr;
       return AsmToken(AsmToken::EqualEqual, StringRef(TokStart, 2));
     }
     return AsmToken(AsmToken::Equal, StringRef(TokStart, 1));
+  case '-':
+    if (*CurPtr == '>') {
+      ++CurPtr;
+      return AsmToken(AsmToken::MinusGreater, StringRef(TokStart, 2));
+    }
+    return AsmToken(AsmToken::Minus, StringRef(TokStart, 1));
   case '|':
     if (*CurPtr == '|') {
       ++CurPtr;
       return AsmToken(AsmToken::PipePipe, StringRef(TokStart, 2));
     }
     return AsmToken(AsmToken::Pipe, StringRef(TokStart, 1));
   case '^': return AsmToken(AsmToken::Caret, StringRef(TokStart, 1));
   case '&':

lib/MC/MCParser/MCAsmLexer.cpp

void AsmToken::dump(raw_ostream &OS) const {
   case AsmToken::LBrac:              OS << "LBrac"; break;
   case AsmToken::LCurly:             OS << "LCurly"; break;
   case AsmToken::LParen:             OS << "LParen"; break;
   case AsmToken::Less:               OS << "Less"; break;
   case AsmToken::LessEqual:          OS << "LessEqual"; break;
   case AsmToken::LessGreater:        OS << "LessGreater"; break;
   case AsmToken::LessLess:           OS << "LessLess"; break;
   case AsmToken::Minus:              OS << "Minus"; break;
+  case AsmToken::MinusGreater:       OS << "MinusGreater"; break;
   case AsmToken::Percent:            OS << "Percent"; break;
   case AsmToken::Pipe:               OS << "Pipe"; break;
   case AsmToken::PipePipe:           OS << "PipePipe"; break;
   case AsmToken::Plus:               OS << "Plus"; break;
   case AsmToken::RBrac:              OS << "RBrac"; break;
   case AsmToken::RCurly:             OS << "RCurly"; break;
   case AsmToken::RParen:             OS << "RParen"; break;
   case AsmToken::Slash:              OS << "Slash"; break;

lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp

void print(raw_ostream &OS) const override {
     }
   }
 };
 
 class WebAssemblyAsmParser final : public MCTargetAsmParser {
   MCAsmParser &Parser;
   MCAsmLexer &Lexer;
 
+  // Much like WebAssemblyAsmPrinter in the backend, we have to own these.
+  std::vector<std::unique_ptr<wasm::WasmSignature>> Signatures;
+
 public:
   WebAssemblyAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
                        const MCInstrInfo &MII, const MCTargetOptions &Options)
       : MCTargetAsmParser(Options, STI, MII), Parser(Parser),
         Lexer(Parser.getLexer()) {
     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
   }
 
+  void addSignature(std::unique_ptr<wasm::WasmSignature> &&Sig) {
+    Signatures.push_back(std::move(Sig));
+  }
+
 #define GET_ASSEMBLER_HEADER
 #include "WebAssemblyGenAsmMatcher.inc"
 
   // TODO: This is required to be implemented, but appears unused.
   bool ParseRegister(unsigned & /*RegNo*/, SMLoc & /*StartLoc*/,
                      SMLoc & /*EndLoc*/) override {
     llvm_unreachable("ParseRegister is not implemented.");
   }
#include "WebAssemblyGenAsmMatcher.inc"
 
   bool Expect(AsmToken::TokenKind Kind, const char *KindName) {
     if (!IsNext(Kind))
       return Error(std::string("Expected ") + KindName + ", instead got: ",
                    Lexer.getTok());
     return false;
   }
 
+  StringRef ExpectIdent() {
+    if (!Lexer.is(AsmToken::Identifier)) {
+      Error("Expected identifier, got: ", Lexer.getTok());
+      return StringRef();
+    }
+    auto Name = Lexer.getTok().getString();
+    Parser.Lex();
+    return Name;
+  }
 
-  std::pair<MVT::SimpleValueType, unsigned>
-  ParseRegType(const StringRef &RegType) {
-    // Derive type from .param .local decls, or the instruction itself.
-    return StringSwitch<std::pair<MVT::SimpleValueType, unsigned>>(RegType)
-        .Case("i32", {MVT::i32, wasm::WASM_TYPE_I32})
-        .Case("i64", {MVT::i64, wasm::WASM_TYPE_I64})
-        .Case("f32", {MVT::f32, wasm::WASM_TYPE_F32})
-        .Case("f64", {MVT::f64, wasm::WASM_TYPE_F64})
-        .Case("i8x16", {MVT::v16i8, wasm::WASM_TYPE_V128})
-        .Case("i16x8", {MVT::v8i16, wasm::WASM_TYPE_V128})
-        .Case("i32x4", {MVT::v4i32, wasm::WASM_TYPE_V128})
-        .Case("i64x2", {MVT::v2i64, wasm::WASM_TYPE_V128})
-        .Case("f32x4", {MVT::v4f32, wasm::WASM_TYPE_V128})
-        .Case("f64x2", {MVT::v2f64, wasm::WASM_TYPE_V128})
-        // arbitrarily chosen vector type to associate with "v128"
-        // FIXME: should these be EVTs to avoid this arbitrary hack? Do we want
-        // to accept more specific SIMD register types?
-        .Case("v128", {MVT::v16i8, wasm::WASM_TYPE_V128})
-        .Default({MVT::INVALID_SIMPLE_VALUE_TYPE, wasm::WASM_TYPE_NORESULT});
+  Optional<wasm::ValType> ParseType(const StringRef &Type) {
+    // FIXME: can't use StringSwitch because wasm::ValType doesn't have a
+    // "invalid" value.
+    if (Type == "i32") return wasm::ValType::I32;
+    if (Type == "i64") return wasm::ValType::I64;
+    if (Type == "f32") return wasm::ValType::F32;
+    if (Type == "f64") return wasm::ValType::F64;
+    if (Type == "v128" || Type == "i8x16" || Type == "i16x8" ||
+        Type == "i32x4" || Type == "i64x2" || Type == "f32x4" ||
+        Type == "f64x2") return wasm::ValType::V128;
+    return Optional<wasm::ValType>();
   }
 
-  bool ParseRegTypeList(std::vector<MVT> &Types) {
+  bool ParseRegTypeList(SmallVectorImpl<wasm::ValType> &Types) {
     while (Lexer.is(AsmToken::Identifier)) {
-      auto RegType = ParseRegType(Lexer.getTok().getString()).first;
-      if (RegType == MVT::INVALID_SIMPLE_VALUE_TYPE)
+      auto Type = ParseType(Lexer.getTok().getString());
+      if (!Type)
         return true;
-      Types.push_back(RegType);
+      Types.push_back(Type.getValue());
       Parser.Lex();
       if (!IsNext(AsmToken::Comma))
         break;
     }
-    return Expect(AsmToken::EndOfStatement, "EOL");
+    return false;
   }
 
   void ParseSingleInteger(bool IsNegative, OperandVector &Operands) {
     auto &Int = Lexer.getTok();
     int64_t Val = Int.getIntVal();
     if (IsNegative)
       Val = -Val;
     Operands.push_back(make_unique<WebAssemblyOperand>(
bool ParseDirective(AsmToken DirectiveID) override {
     // - return false -> processed this directive successfully.
     assert(DirectiveID.getKind() == AsmToken::Identifier);
     auto &Out = getStreamer();
     auto &TOut =
         reinterpret_cast<WebAssemblyTargetStreamer &>(*Out.getTargetStreamer());
     // TODO: any time we return an error, at least one token must have been
     // consumed, otherwise this will not signal an error to the caller.
     if (DirectiveID.getString() == ".globaltype") {
-      if (!Lexer.is(AsmToken::Identifier))
-        return Error("Expected symbol name after .globaltype directive, got: ",
-                     Lexer.getTok());
-      auto Name = Lexer.getTok().getString();
-      Parser.Lex();
-      if (!IsNext(AsmToken::Comma))
-        return Error("Expected `,`, got: ", Lexer.getTok());
-      if (!Lexer.is(AsmToken::Identifier))
-        return Error("Expected type in .globaltype directive, got: ",
-                     Lexer.getTok());
-      auto Type = ParseRegType(Lexer.getTok().getString()).second;
-      if (Type == wasm::WASM_TYPE_NORESULT)
-        return Error("Unknown type in .globaltype directive: ",
-                     Lexer.getTok());
-      Parser.Lex();
+      auto SymName = ExpectIdent();
+      if (SymName.empty()) return true;
+      if (Expect(AsmToken::Comma, ",")) return true;
+      auto TypeTok = Lexer.getTok();
+      auto TypeName = ExpectIdent();
+      if (TypeName.empty()) return true;
+      auto Type = ParseType(TypeName);
+      if (!Type)
+        return Error("Unknown type in .globaltype directive: ", TypeTok);
       // Now set this symbol with the correct type.
       auto WasmSym = cast<MCSymbolWasm>(
-                       TOut.getStreamer().getContext().getOrCreateSymbol(Name));
+                    TOut.getStreamer().getContext().getOrCreateSymbol(SymName));
       WasmSym->setType(wasm::WASM_SYMBOL_TYPE_GLOBAL);
-      WasmSym->setGlobalType(wasm::WasmGlobalType{uint8_t(Type), true});
+      WasmSym->setGlobalType(
+            wasm::WasmGlobalType{uint8_t(Type.getValue()), true});
       // And emit the directive again.
       TOut.emitGlobalType(WasmSym);
       return Expect(AsmToken::EndOfStatement, "EOL");
-    } else if (DirectiveID.getString() == ".param") {
-      std::vector<MVT> Params;
-      if (ParseRegTypeList(Params)) return true;
-      TOut.emitParam(nullptr /* unused */, Params);
-      return false;
-    } else if (DirectiveID.getString() == ".result") {
-      std::vector<MVT> Results;
-      if (ParseRegTypeList(Results)) return true;
-      TOut.emitResult(nullptr /* unused */, Results);
-      return false;
+    } else if (DirectiveID.getString() == ".functype") {
+      auto SymName = ExpectIdent();
+      if (SymName.empty()) return true;
+      auto WasmSym = cast<MCSymbolWasm>(
+                    TOut.getStreamer().getContext().getOrCreateSymbol(SymName));
+      auto Signature = make_unique<wasm::WasmSignature>();
+      if (Expect(AsmToken::LParen, "(")) return true;
+      if (ParseRegTypeList(Signature->Params)) return true;
+      if (Expect(AsmToken::RParen, ")")) return true;
+      if (Expect(AsmToken::MinusGreater, "->")) return true;
+      if (Expect(AsmToken::LParen, "(")) return true;
+      if (ParseRegTypeList(Signature->Returns)) return true;
+      if (Expect(AsmToken::RParen, ")")) return true;
+      WasmSym->setSignature(Signature.get());
+      addSignature(std::move(Signature));
+      WasmSym->setType(wasm::WASM_SYMBOL_TYPE_FUNCTION);
+      TOut.emitFunctionType(WasmSym);
+      return Expect(AsmToken::EndOfStatement, "EOL");
     } else if (DirectiveID.getString() == ".local") {
-      std::vector<MVT> Locals;
+      SmallVector<wasm::ValType, 4> Locals;
       if (ParseRegTypeList(Locals)) return true;
       TOut.emitLocal(Locals);
-      return false;
+      return Expect(AsmToken::EndOfStatement, "EOL");
     }
     return true;  // We didn't process this directive.
   }
 
   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned & /*Opcode*/,
                                OperandVector &Operands, MCStreamer &Out,
                                uint64_t &ErrorInfo,
                                bool MatchingInlineAsm) override {

lib/Target/WebAssembly/MCTargetDesc/WebAssemblyTargetStreamer.h

 class MCSymbolWasm;
 
 /// WebAssembly-specific streamer interface, to implement support
 /// WebAssembly-specific assembly directives.
 class WebAssemblyTargetStreamer : public MCTargetStreamer {
 public:
   explicit WebAssemblyTargetStreamer(MCStreamer &S);
 
-  /// .param
-  virtual void emitParam(MCSymbol *Symbol, ArrayRef<MVT> Types) = 0;
-  /// .result
-  virtual void emitResult(MCSymbol *Symbol, ArrayRef<MVT> Types) = 0;
   /// .local
-  virtual void emitLocal(ArrayRef<MVT> Types) = 0;
+  virtual void emitLocal(ArrayRef<wasm::ValType> Types) = 0;
   /// .endfunc
   virtual void emitEndFunc() = 0;
   /// .functype
-  virtual void emitIndirectFunctionType(MCSymbolWasm *Symbol) = 0;
+  virtual void emitFunctionType(MCSymbolWasm *Symbol) = 0;
   /// .indidx
   virtual void emitIndIdx(const MCExpr *Value) = 0;
   /// .globaltype
   virtual void emitGlobalType(MCSymbolWasm *Sym) = 0;
   /// .import_module
   virtual void emitImportModule(MCSymbolWasm *Sym, StringRef ModuleName) = 0;
 
 protected:
   void emitValueType(wasm::ValType Type);
 };
 
 /// This part is for ascii assembly output
 class WebAssemblyTargetAsmStreamer final : public WebAssemblyTargetStreamer {
   formatted_raw_ostream &OS;
 
 public:
   WebAssemblyTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS);
 
-  void emitParam(MCSymbol *Symbol, ArrayRef<MVT> Types) override;
-  void emitResult(MCSymbol *Symbol, ArrayRef<MVT> Types) override;
-  void emitLocal(ArrayRef<MVT> Types) override;
+  void emitLocal(ArrayRef<wasm::ValType> Types) override;
   void emitEndFunc() override;
-  void emitIndirectFunctionType(MCSymbolWasm *Symbol) override;
+  void emitFunctionType(MCSymbolWasm *Symbol) override;
   void emitIndIdx(const MCExpr *Value) override;
   void emitGlobalType(MCSymbolWasm *Sym) override;
   void emitImportModule(MCSymbolWasm *Sym, StringRef ModuleName) override;
 };
 
 /// This part is for Wasm object output
 class WebAssemblyTargetWasmStreamer final : public WebAssemblyTargetStreamer {
 public:
   explicit WebAssemblyTargetWasmStreamer(MCStreamer &S);
 
-  void emitParam(MCSymbol *Symbol, ArrayRef<MVT> Types) override;
-  void emitResult(MCSymbol *Symbol, ArrayRef<MVT> Types) override;
-  void emitLocal(ArrayRef<MVT> Types) override;
+  void emitLocal(ArrayRef<wasm::ValType> Types) override;
   void emitEndFunc() override;
-  void emitIndirectFunctionType(MCSymbolWasm *Symbol) override;
+  void emitFunctionType(MCSymbolWasm *Symbol) override;
   void emitIndIdx(const MCExpr *Value) override;
   void emitGlobalType(MCSymbolWasm *Sym) override;
   void emitImportModule(MCSymbolWasm *Sym, StringRef ModuleName) override;
 };
 
 } // end namespace llvm
 
 #endif

lib/Target/WebAssembly/MCTargetDesc/WebAssemblyTargetStreamer.cpp

 
 WebAssemblyTargetAsmStreamer::WebAssemblyTargetAsmStreamer(
     MCStreamer &S, formatted_raw_ostream &OS)
     : WebAssemblyTargetStreamer(S), OS(OS) {}
 
 WebAssemblyTargetWasmStreamer::WebAssemblyTargetWasmStreamer(MCStreamer &S)
     : WebAssemblyTargetStreamer(S) {}
 
-static void PrintTypes(formatted_raw_ostream &OS, ArrayRef<MVT> Types) {
+static void PrintTypes(formatted_raw_ostream &OS, ArrayRef<wasm::ValType> Types) {
   bool First = true;
-  for (MVT Type : Types) {
+  for (auto Type : Types) {
     if (First)
       First = false;
     else
       OS << ", ";
-    OS << WebAssembly::TypeToString(WebAssembly::toValType(Type));
+    OS << WebAssembly::TypeToString(Type);
   }
   OS << '\n';
 }
 
-void WebAssemblyTargetAsmStreamer::emitParam(MCSymbol *Symbol,
-                                             ArrayRef<MVT> Types) {
-  if (!Types.empty()) {
-    OS << "\t.param  \t";
-
-    // FIXME: Currently this applies to the "current" function; it may
-    // be cleaner to specify an explicit symbol as part of the directive.
-
-    PrintTypes(OS, Types);
-  }
-}
-
-void WebAssemblyTargetAsmStreamer::emitResult(MCSymbol *Symbol,
-                                              ArrayRef<MVT> Types) {
-  if (!Types.empty()) {
-    OS << "\t.result \t";
-
-    // FIXME: Currently this applies to the "current" function; it may
-    // be cleaner to specify an explicit symbol as part of the directive.
-
-    PrintTypes(OS, Types);
-  }
-}
-
-void WebAssemblyTargetAsmStreamer::emitLocal(ArrayRef<MVT> Types) {
+void WebAssemblyTargetAsmStreamer::emitLocal(ArrayRef<wasm::ValType> Types) {
   if (!Types.empty()) {
     OS << "\t.local  \t";
     PrintTypes(OS, Types);
   }
 }
 
 void WebAssemblyTargetAsmStreamer::emitEndFunc() { OS << "\t.endfunc\n"; }
 
-void WebAssemblyTargetAsmStreamer::emitIndirectFunctionType(
-    MCSymbolWasm *Symbol) {
-  OS << "\t.functype\t" << Symbol->getName();
-  if (Symbol->getSignature()->Returns.empty())
-    OS << ", void";
-  else {
-    assert(Symbol->getSignature()->Returns.size() == 1);
-    OS << ", "
-       << WebAssembly::TypeToString(Symbol->getSignature()->Returns.front());
+void WebAssemblyTargetAsmStreamer::emitFunctionType(MCSymbolWasm *Symbol) {
+  OS << "\t.functype\t" << Symbol->getName() << " (";
+  auto &Params = Symbol->getSignature()->Params;
+  for (auto &Ty : Params) {
+    if (&Ty != &Params[0]) OS << ", ";
+    OS << WebAssembly::TypeToString(Ty);
+  }
+  OS << ") -> (";
+  auto &Returns = Symbol->getSignature()->Returns;
+  for (auto &Ty : Returns) {
+    if (&Ty != &Returns[0]) OS << ", ";
+    OS << WebAssembly::TypeToString(Ty);
   }
-  for (auto Ty : Symbol->getSignature()->Params)
-    OS << ", " << WebAssembly::TypeToString(Ty);
-  OS << '\n';
+  OS << ")\n";
 }
 
 void WebAssemblyTargetAsmStreamer::emitGlobalType(MCSymbolWasm *Sym) {
   OS << "\t.globaltype\t" << Sym->getName() << ", " <<
         WebAssembly::TypeToString(
           static_cast<wasm::ValType>(Sym->getGlobalType().Type)) <<
         '\n';
 }
 
 void WebAssemblyTargetAsmStreamer::emitImportModule(MCSymbolWasm *Sym,
                                                     StringRef ModuleName) {
   OS << "\t.import_module\t" << Sym->getName() << ", " << ModuleName << '\n';
 }
 
 void WebAssemblyTargetAsmStreamer::emitIndIdx(const MCExpr *Value) {
   OS << "\t.indidx  \t" << *Value << '\n';
 }
 
-void WebAssemblyTargetWasmStreamer::emitParam(MCSymbol *Symbol,
-                                              ArrayRef<MVT> Types) {
-  // The Symbol already has its signature
-}
-
-void WebAssemblyTargetWasmStreamer::emitResult(MCSymbol *Symbol,
-                                               ArrayRef<MVT> Types) {
-  // The Symbol already has its signature
-}
-
-void WebAssemblyTargetWasmStreamer::emitLocal(ArrayRef<MVT> Types) {
-  SmallVector<std::pair<MVT, uint32_t>, 4> Grouped;
-  for (MVT Type : Types) {
+void WebAssemblyTargetWasmStreamer::emitLocal(ArrayRef<wasm::ValType> Types) {
+  SmallVector<std::pair<wasm::ValType, uint32_t>, 4> Grouped;
+  for (auto Type : Types) {
     if (Grouped.empty() || Grouped.back().first != Type)
       Grouped.push_back(std::make_pair(Type, 1));
     else
       ++Grouped.back().second;
   }
 
   Streamer.EmitULEB128IntValue(Grouped.size());
   for (auto Pair : Grouped) {
     Streamer.EmitULEB128IntValue(Pair.second);
-    emitValueType(WebAssembly::toValType(Pair.first));
+    emitValueType(Pair.first);
   }
 }
 
 void WebAssemblyTargetWasmStreamer::emitEndFunc() {
   llvm_unreachable(".end_func is not needed for direct wasm output");
 }
 
 void WebAssemblyTargetWasmStreamer::emitIndIdx(const MCExpr *Value) {
   llvm_unreachable(".indidx encoding not yet implemented");
 }
 
-void WebAssemblyTargetWasmStreamer::emitIndirectFunctionType(
-    MCSymbolWasm *Symbol) {
+void WebAssemblyTargetWasmStreamer::emitFunctionType(MCSymbolWasm *Symbol) {
   // Symbol already has its arguments and result set.
   Symbol->setType(wasm::WASM_SYMBOL_TYPE_FUNCTION);
 }
 
 void WebAssemblyTargetWasmStreamer::emitGlobalType(MCSymbolWasm *Sym) {
   // Not needed.
 }
 
 void WebAssemblyTargetWasmStreamer::emitImportModule(MCSymbolWasm *Sym,
                                                      StringRef ModuleName) {
   Sym->setModuleName(ModuleName);
 }

lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp

if (F.isDeclarationForLinker() && !F.isIntrinsic()) {
         Sym->setSignature(Signature.get());
         addSignature(std::move(Signature));
       }
       // FIXME: this was originally intended for post-linking and was only used
       // for imports that were only called indirectly (i.e. s2wasm could not
       // infer the type from a call). With object files it applies to all
       // imports. so fix the names and the tests, or rethink how import
       // delcarations work in asm files.
-      getTargetStreamer()->emitIndirectFunctionType(Sym);
+      getTargetStreamer()->emitFunctionType(Sym);
 
       if (TM.getTargetTriple().isOSBinFormatWasm() &&
           F.hasFnAttribute("wasm-import-module")) {
         StringRef Name =
             F.getFnAttribute("wasm-import-module").getValueAsString();
         getTargetStreamer()->emitImportModule(Sym, Name);
       }
     }
void WebAssemblyAsmPrinter::EmitFunctionBodyStart() {
   SmallVector<MVT, 4> ParamVTs;
   ComputeSignatureVTs(F.getFunctionType(), F, TM, ParamVTs, ResultVTs);
   auto Signature = SignatureFromMVTs(ResultVTs, ParamVTs);
   auto *WasmSym = cast<MCSymbolWasm>(CurrentFnSym);
   WasmSym->setSignature(Signature.get());
   addSignature(std::move(Signature));
 
   // FIXME: clean up how params and results are emitted (use signatures)
-  getTargetStreamer()->emitParam(CurrentFnSym, ParamVTs);
+  getTargetStreamer()->emitFunctionType(WasmSym);
 
   // Emit the function index.
   if (MDNode *Idx = F.getMetadata("wasm.index")) {
     assert(Idx->getNumOperands() == 1);
 
     getTargetStreamer()->emitIndIdx(AsmPrinter::lowerConstant(
         cast<ConstantAsMetadata>(Idx->getOperand(0))->getValue()));
   }
 
-  getTargetStreamer()->emitResult(CurrentFnSym, ResultVTs);
-  getTargetStreamer()->emitLocal(MFI->getLocals());
+  SmallVector<wasm::ValType, 16> Locals;
+  ValTypesFromMVTs(MFI->getLocals(), Locals);
+  getTargetStreamer()->emitLocal(Locals);
 
   AsmPrinter::EmitFunctionBodyStart();
 }
 
 void WebAssemblyAsmPrinter::EmitInstruction(const MachineInstr *MI) {
   LLVM_DEBUG(dbgs() << "EmitInstruction: " << *MI << '\n');
 
   switch (MI->getOpcode()) {

lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h

void ComputeLegalValueVTs(const Function &F, const TargetMachine &TM, Type *Ty,
                           SmallVectorImpl<MVT> &ValueVTs);
 
 // Compute the signature for a given FunctionType (Ty). Note that it's not the
 // signature for F (F is just used to get varous context)
 void ComputeSignatureVTs(const FunctionType *Ty, const Function &F,
                          const TargetMachine &TM, SmallVectorImpl<MVT> &Params,
                          SmallVectorImpl<MVT> &Results);
 
+void ValTypesFromMVTs(const ArrayRef<MVT> &In,
+                      SmallVectorImpl<wasm::ValType> &Out);
+
 std::unique_ptr<wasm::WasmSignature>
 SignatureFromMVTs(const SmallVectorImpl<MVT> &Results,
                   const SmallVectorImpl<MVT> &Params);
 
 } // end namespace llvm
 
 #endif

lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.cpp

void llvm::ComputeSignatureVTs(const FunctionType *Ty, const Function &F,
   }
 
   for (auto *Param : Ty->params())
     ComputeLegalValueVTs(F, TM, Param, Params);
   if (Ty->isVarArg())
     Params.push_back(PtrVT);
 }
 
+void llvm::ValTypesFromMVTs(const ArrayRef<MVT> &In,
+                            SmallVectorImpl<wasm::ValType> &Out) {
+  for (MVT Ty : In)
+    Out.push_back(WebAssembly::toValType(Ty));
+}
+
 std::unique_ptr<wasm::WasmSignature>
 llvm::SignatureFromMVTs(const SmallVectorImpl<MVT> &Results,
                         const SmallVectorImpl<MVT> &Params) {
   auto Sig = make_unique<wasm::WasmSignature>();
-  for (MVT Ty : Results)
-    Sig->Returns.push_back(WebAssembly::toValType(Ty));
-  for (MVT Ty : Params)
-    Sig->Params.push_back(WebAssembly::toValType(Ty));
+  ValTypesFromMVTs(Results, Sig->Returns);
+  ValTypesFromMVTs(Params, Sig->Params);
   return Sig;
 }

test/CodeGen/WebAssembly/address-offsets.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
 
 ; Test folding constant offsets and symbols into load and store addresses under
 ; a variety of circumstances.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 @g = external global [0 x i32], align 4
 
 ; CHECK-LABEL: load_test0:
-; CHECK-NEXT: result    i32{{$}}
+; CHECK-NEXT: .functype load_test0 () -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, 0{{$}}
 ; CHECK-NEXT: i32.load  $push1=, g+40($pop0){{$}}
 ; CHECK-NEXT: return    $pop1{{$}}
 define i32 @load_test0() {
   %t = load i32, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @g, i32 0, i32 10), align 4
   ret i32 %t
 }
 
 ; CHECK-LABEL: load_test0_noinbounds:
-; CHECK-NEXT: result    i32{{$}}
+; CHECK-NEXT: .functype load_test0_noinbounds () -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, 0{{$}}
 ; CHECK-NEXT: i32.load  $push1=, g+40($pop0){{$}}
 ; CHECK-NEXT: return    $pop1{{$}}
 define i32 @load_test0_noinbounds() {
   %t = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @g, i32 0, i32 10), align 4
   ret i32 %t
 }
 
 ; TODO: load_test1 - load_test8 are disabled because folding GA+reg is disabled
 ; (there are cases where the value in the reg can be negative).
 ; Likewise for stores.
 
 ; CHECK-LABEL: load_test1:
-; CHECK-NEXT: param     i32{{$}}
-; CHECK-NEXT: result    i32{{$}}
+; CHECK-NEXT: .functype load_test1 (i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEX T: i32.shl   $push1=, $0, $pop0{{$}}
 ; CHECK-NEX T: i32.load  $push2=, g+40($pop1){{$}}
 ; CHECK-NEX T: return    $pop2{{$}}
 define i32 @load_test1(i32 %n) {
   %add = add nsw i32 %n, 10
   %arrayidx = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %add
   %t = load i32, i32* %arrayidx, align 4
   ret i32 %t
 }
 
 ; CHECK-LABEL: load_test2:
-; CHECK-NEXT: param     i32{{$}}
-; CHECK-NEXT: result    i32{{$}}
+; CHECK-NEXT: .functype load_test2 (i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEX T: i32.shl   $push1=, $0, $pop0{{$}}
 ; CHECK-NEX T: i32.load  $push2=, g+40($pop1){{$}}
 ; CHECK-NEX T: return    $pop2{{$}}
 define i32 @load_test2(i32 %n) {
   %add = add nsw i32 10, %n
   %arrayidx = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %add
   %t = load i32, i32* %arrayidx, align 4
   ret i32 %t
 }
 
 ; CHECK-LABEL: load_test3:
-; CHECK-NEXT: param     i32{{$}}
-; CHECK-NEXT: result    i32{{$}}
+; CHECK-NEXT: .functype load_test3 (i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEX T: i32.shl   $push1=, $0, $pop0{{$}}
 ; CHECK-NEX T: i32.load  $push2=, g+40($pop1){{$}}
 ; CHECK-NEX T: return    $pop2{{$}}
 define i32 @load_test3(i32 %n) {
   %add.ptr = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %n
   %add.ptr1 = getelementptr inbounds i32, i32* %add.ptr, i32 10
   %t = load i32, i32* %add.ptr1, align 4
   ret i32 %t
 }
 
 ; CHECK-LABEL: load_test4:
-; CHECK-NEXT: param     i32{{$}}
-; CHECK-NEXT: result    i32{{$}}
+; CHECK-NEXT: .functype load_test4 (i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEX T: i32.shl   $push1=, $0, $pop0{{$}}
 ; CHECK-NEX T: i32.load  $push2=, g+40($pop1){{$}}
 ; CHECK-NEX T: return    $pop2{{$}}
 define i32 @load_test4(i32 %n) {
   %add.ptr = getelementptr inbounds i32, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @g, i32 0, i32 10), i32 %n
   %t = load i32, i32* %add.ptr, align 4
   ret i32 %t
 }
 
 ; CHECK-LABEL: load_test5:
-; CHECK-NEXT: param     i32{{$}}
-; CHECK-NEXT: result    i32{{$}}
+; CHECK-NEXT: .functype load_test5 (i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEX T: i32.shl   $push1=, $0, $pop0{{$}}
 ; CHECK-NEX T: i32.load  $push2=, g+40($pop1){{$}}
 ; CHECK-NEX T: return    $pop2{{$}}
 define i32 @load_test5(i32 %n) {
   %add.ptr = getelementptr inbounds i32, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @g, i32 0, i32 10), i32 %n
   %t = load i32, i32* %add.ptr, align 4
   ret i32 %t
 }
 
 ; CHECK-LABEL: load_test6:
-; CHECK-NEXT: param     i32{{$}}
-; CHECK-NEXT: result    i32{{$}}
+; CHECK-NEXT: .functype load_test6 (i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEX T: i32.shl   $push1=, $0, $pop0{{$}}
 ; CHECK-NEX T: i32.load  $push2=, g+40($pop1){{$}}
 ; CHECK-NEX T: return    $pop2{{$}}
 define i32 @load_test6(i32 %n) {
   %add = add nsw i32 %n, 10
   %add.ptr = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %add
   %t = load i32, i32* %add.ptr, align 4
   ret i32 %t
 }
 
 ; CHECK-LABEL: load_test7:
-; CHECK-NEXT: param     i32{{$}}
-; CHECK-NEXT: result    i32{{$}}
+; CHECK-NEXT: .functype load_test7 (i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEX T: i32.shl   $push1=, $0, $pop0{{$}}
 ; CHECK-NEX T: i32.load  $push2=, g+40($pop1){{$}}
 ; CHECK-NEX T: return    $pop2{{$}}
 define i32 @load_test7(i32 %n) {
   %add.ptr = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %n
   %add.ptr1 = getelementptr inbounds i32, i32* %add.ptr, i32 10
   %t = load i32, i32* %add.ptr1, align 4
   ret i32 %t
 }
 
 ; CHECK-LABEL: load_test8:
-; CHECK-NEXT: param     i32{{$}}
-; CHECK-NEXT: result    i32{{$}}
+; CHECK-NEXT: .functype load_test8 (i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEX T: i32.shl   $push1=, $0, $pop0{{$}}
 ; CHECK-NEX T: i32.load  $push2=, g+40($pop1){{$}}
 ; CHECK-NEX T: return    $pop2{{$}}
 define i32 @load_test8(i32 %n) {
   %add = add nsw i32 10, %n
   %add.ptr = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %add
   %t = load i32, i32* %add.ptr, align 4
   ret i32 %t
 }
 
 ; CHECK-LABEL: load_test9:
-; CHECK-NEXT: result    i32{{$}}
+; CHECK-NEXT: .functype load_test9 () -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, 0{{$}}
 ; CHECK-NEXT: i32.load  $push1=, g-40($pop0){{$}}
 ; CHECK-NEXT: return    $pop1{{$}}
 define i32 @load_test9() {
   %t = load i32, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @g, i32 0, i32 1073741814), align 4
   ret i32 %t
 }
 
 ; CHECK-LABEL: load_test10:
-; CHECK-NEXT: param     i32{{$}}
-; CHECK-NEXT: result    i32{{$}}
+; CHECK-NEXT: .functype load_test10 (i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEXT: i32.shl   $push1=, $0, $pop0{{$}}
 ; CHECK-NEXT: i32.const $push2=, g-40{{$}}
 ; CHECK-NEXT: i32.add   $push3=, $pop1, $pop2{{$}}
 ; CHECK-NEXT: i32.load  $push4=, 0($pop3){{$}}
 ; CHECK-NEXT: return    $pop4{{$}}
 define i32 @load_test10(i32 %n) {
   %add = add nsw i32 %n, -10
   %arrayidx = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %add
   %t = load i32, i32* %arrayidx, align 4
   ret i32 %t
 }
 
 ; CHECK-LABEL: load_test11:
-; CHECK-NEXT: param     i32{{$}}
-; CHECK-NEXT: result    i32{{$}}
+; CHECK-NEXT: .functype load_test11 (i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.load  $push0=, 40($0){{$}}
 ; CHECK-NEXT: return    $pop0{{$}}
 define i32 @load_test11(i32* %p) {
   %arrayidx = getelementptr inbounds i32, i32* %p, i32 10
   %t = load i32, i32* %arrayidx, align 4
   ret i32 %t
 }
 
 ; CHECK-LABEL: load_test11_noinbounds:
-; CHECK-NEXT: param     i32{{$}}
-; CHECK-NEXT: result    i32{{$}}
+; CHECK-NEXT: .functype load_test11_noinbounds (i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, 40{{$}}
 ; CHECK-NEXT: i32.add   $push1=, $0, $pop0{{$}}
 ; CHECK-NEXT: i32.load  $push2=, 0($pop1){{$}}
 ; CHECK-NEXT: return    $pop2{{$}}
 define i32 @load_test11_noinbounds(i32* %p) {
   %arrayidx = getelementptr i32, i32* %p, i32 10
   %t = load i32, i32* %arrayidx, align 4
   ret i32 %t
 }
 
 ; CHECK-LABEL: load_test12:
-; CHECK-NEXT: param     i32, i32{{$}}
-; CHECK-NEXT: result    i32{{$}}
+; CHECK-NEXT: .functype load_test12 (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEXT: i32.shl   $push1=, $1, $pop0{{$}}
 ; CHECK-NEXT: i32.add   $push2=, $0, $pop1{{$}}
 ; CHECK-NEXT: i32.const $push3=, 40{{$}}
 ; CHECK-NEXT: i32.add   $push4=, $pop2, $pop3{{$}}
 ; CHECK-NEXT: i32.load  $push5=, 0($pop4){{$}}
 ; CHECK-NEXT: return    $pop5{{$}}
 define i32 @load_test12(i32* %p, i32 %n) {
   %add = add nsw i32 %n, 10
   %arrayidx = getelementptr inbounds i32, i32* %p, i32 %add
   %t = load i32, i32* %arrayidx, align 4
   ret i32 %t
 }
 
 ; CHECK-LABEL: load_test13:
-; CHECK-NEXT: param     i32, i32{{$}}
-; CHECK-NEXT: result    i32{{$}}
+; CHECK-NEXT: .functype load_test13 (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEXT: i32.shl   $push1=, $1, $pop0{{$}}
 ; CHECK-NEXT: i32.add   $push2=, $0, $pop1{{$}}
 ; CHECK-NEXT: i32.const $push3=, 40{{$}}
 ; CHECK-NEXT: i32.add   $push4=, $pop2, $pop3{{$}}
 ; CHECK-NEXT: i32.load  $push5=, 0($pop4){{$}}
 ; CHECK-NEXT: return    $pop5{{$}}
 define i32 @load_test13(i32* %p, i32 %n) {
   %add = add nsw i32 10, %n
   %arrayidx = getelementptr inbounds i32, i32* %p, i32 %add
   %t = load i32, i32* %arrayidx, align 4
   ret i32 %t
 }
 
 ; CHECK-LABEL: load_test14:
-; CHECK-NEXT: param     i32, i32{{$}}
-; CHECK-NEXT: result    i32{{$}}
+; CHECK-NEXT: .functype load_test14 (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEXT: i32.shl   $push1=, $1, $pop0{{$}}
 ; CHECK-NEXT: i32.add   $push2=, $0, $pop1{{$}}
 ; CHECK-NEXT: i32.load  $push3=, 40($pop2){{$}}
 ; CHECK-NEXT: return    $pop3{{$}}
 define i32 @load_test14(i32* %p, i32 %n) {
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 %n
   %add.ptr1 = getelementptr inbounds i32, i32* %add.ptr, i32 10
   %t = load i32, i32* %add.ptr1, align 4
   ret i32 %t
 }
 
 ; CHECK-LABEL: load_test15:
-; CHECK-NEXT: param     i32, i32{{$}}
-; CHECK-NEXT: result    i32{{$}}
+; CHECK-NEXT: .functype load_test15 (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEXT: i32.shl   $push1=, $1, $pop0{{$}}
 ; CHECK-NEXT: i32.add   $push2=, $0, $pop1{{$}}
 ; CHECK-NEXT: i32.const $push3=, 40{{$}}
 ; CHECK-NEXT: i32.add   $push4=, $pop2, $pop3{{$}}
 ; CHECK-NEXT: i32.load  $push5=, 0($pop4){{$}}
 ; CHECK-NEXT: return    $pop5{{$}}
 define i32 @load_test15(i32* %p, i32 %n) {
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 10
   %add.ptr1 = getelementptr inbounds i32, i32* %add.ptr, i32 %n
   %t = load i32, i32* %add.ptr1, align 4
   ret i32 %t
 }
 
 ; CHECK-LABEL: load_test16:
-; CHECK-NEXT: param     i32, i32{{$}}
-; CHECK-NEXT: result    i32{{$}}
+; CHECK-NEXT: .functype load_test16 (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEXT: i32.shl   $push1=, $1, $pop0{{$}}
 ; CHECK-NEXT: i32.add   $push2=, $0, $pop1{{$}}
 ; CHECK-NEXT: i32.const $push3=, 40{{$}}
 ; CHECK-NEXT: i32.add   $push4=, $pop2, $pop3{{$}}
 ; CHECK-NEXT: i32.load  $push5=, 0($pop4){{$}}
 ; CHECK-NEXT: return    $pop5{{$}}
 define i32 @load_test16(i32* %p, i32 %n) {
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 10
   %add.ptr1 = getelementptr inbounds i32, i32* %add.ptr, i32 %n
   %t = load i32, i32* %add.ptr1, align 4
   ret i32 %t
 }
 
 ; CHECK-LABEL: load_test17:
-; CHECK-NEXT: param     i32, i32{{$}}
-; CHECK-NEXT: result    i32{{$}}
+; CHECK-NEXT: .functype load_test17 (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEXT: i32.shl   $push1=, $1, $pop0{{$}}
 ; CHECK-NEXT: i32.add   $push2=, $0, $pop1{{$}}
 ; CHECK-NEXT: i32.const $push3=, 40{{$}}
 ; CHECK-NEXT: i32.add   $push4=, $pop2, $pop3{{$}}
 ; CHECK-NEXT: i32.load  $push5=, 0($pop4){{$}}
 ; CHECK-NEXT: return    $pop5{{$}}
 define i32 @load_test17(i32* %p, i32 %n) {
   %add = add nsw i32 %n, 10
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 %add
   %t = load i32, i32* %add.ptr, align 4
   ret i32 %t
 }
 
 ; CHECK-LABEL: load_test18:
-; CHECK-NEXT: param     i32, i32{{$}}
-; CHECK-NEXT: result    i32{{$}}
+; CHECK-NEXT: .functype load_test18 (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEXT: i32.shl   $push1=, $1, $pop0{{$}}
 ; CHECK-NEXT: i32.add   $push2=, $0, $pop1{{$}}
 ; CHECK-NEXT: i32.load  $push3=, 40($pop2){{$}}
 ; CHECK-NEXT: return    $pop3{{$}}
 define i32 @load_test18(i32* %p, i32 %n) {
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 %n
   %add.ptr1 = getelementptr inbounds i32, i32* %add.ptr, i32 10
   %t = load i32, i32* %add.ptr1, align 4
   ret i32 %t
 }
 
 ; CHECK-LABEL: load_test19:
-; CHECK-NEXT: param     i32, i32{{$}}
-; CHECK-NEXT: result    i32{{$}}
+; CHECK-NEXT: .functype load_test19 (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEXT: i32.shl   $push1=, $1, $pop0{{$}}
 ; CHECK-NEXT: i32.add   $push2=, $0, $pop1{{$}}
 ; CHECK-NEXT: i32.const $push3=, 40{{$}}
 ; CHECK-NEXT: i32.add   $push4=, $pop2, $pop3{{$}}
 ; CHECK-NEXT: i32.load  $push5=, 0($pop4){{$}}
 ; CHECK-NEXT: return    $pop5{{$}}
 define i32 @load_test19(i32* %p, i32 %n) {
   %add = add nsw i32 10, %n
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 %add
   %t = load i32, i32* %add.ptr, align 4
   ret i32 %t
 }
 
 ; CHECK-LABEL: load_test20:
-; CHECK-NEXT: param     i32{{$}}
-; CHECK-NEXT: result    i32{{$}}
+; CHECK-NEXT: .functype load_test20 (i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, -40{{$}}
 ; CHECK-NEXT: i32.add   $push1=, $0, $pop0{{$}}
 ; CHECK-NEXT: i32.load  $push2=, 0($pop1){{$}}
 ; CHECK-NEXT: return    $pop2{{$}}
 define i32 @load_test20(i32* %p) {
   %arrayidx = getelementptr inbounds i32, i32* %p, i32 -10
   %t = load i32, i32* %arrayidx, align 4
   ret i32 %t
 }
 
 ; CHECK-LABEL: load_test21:
-; CHECK-NEXT: param     i32, i32{{$}}
-; CHECK-NEXT: result    i32{{$}}
+; CHECK-NEXT: .functype load_test21 (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEXT: i32.shl   $push1=, $1, $pop0{{$}}
 ; CHECK-NEXT: i32.add   $push2=, $0, $pop1{{$}}
 ; CHECK-NEXT: i32.const $push3=, -40{{$}}
 ; CHECK-NEXT: i32.add   $push4=, $pop2, $pop3{{$}}
 ; CHECK-NEXT: i32.load  $push5=, 0($pop4){{$}}
 ; CHECK-NEXT: return    $pop5{{$}}
 define i32 @load_test21(i32* %p, i32 %n) {
   %add = add nsw i32 %n, -10
   %arrayidx = getelementptr inbounds i32, i32* %p, i32 %add
   %t = load i32, i32* %arrayidx, align 4
   ret i32 %t
 }
 
 ; CHECK-LABEL: store_test0:
-; CHECK-NEXT: param     i32{{$}}
+; CHECK-NEXT: .functype store_test0 (i32) -> (){{$}}
 ; CHECK-NEXT: i32.const $push0=, 0{{$}}
 ; CHECK-NEXT: i32.store g+40($pop0), $0{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_test0(i32 %i) {
   store i32 %i, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @g, i32 0, i32 10), align 4
   ret void
 }
 
 ; CHECK-LABEL: store_test0_noinbounds:
-; CHECK-NEXT: param     i32{{$}}
+; CHECK-NEXT: .functype store_test0_noinbounds (i32) -> (){{$}}
 ; CHECK-NEXT: i32.const $push0=, 0{{$}}
 ; CHECK-NEXT: i32.store g+40($pop0), $0{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_test0_noinbounds(i32 %i) {
   store i32 %i, i32* getelementptr ([0 x i32], [0 x i32]* @g, i32 0, i32 10), align 4
   ret void
 }
 
 ; CHECK-LABEL: store_test1:
-; CHECK-NEXT: param     i32, i32{{$}}
+; CHECK-NEXT: .functype store_test1 (i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEXT: i32.shl   $push1=, $0, $pop0{{$}}
 ; CHECK-NEX T: i32.store g+40($pop1), $1{{$}}
 ; CHECK-NEX T: return{{$}}
 define void @store_test1(i32 %n, i32 %i) {
   %add = add nsw i32 %n, 10
   %arrayidx = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %add
   store i32 %i, i32* %arrayidx, align 4
   ret void
 }
 
 ; CHECK-LABEL: store_test2:
-; CHECK-NEXT: param     i32, i32{{$}}
+; CHECK-NEXT: .functype store_test2 (i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEXT: i32.shl   $push1=, $0, $pop0{{$}}
 ; CHECK-NEX T: i32.store g+40($pop1), $1{{$}}
 ; CHECK-NEX T: return{{$}}
 define void @store_test2(i32 %n, i32 %i) {
   %add = add nsw i32 10, %n
   %arrayidx = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %add
   store i32 %i, i32* %arrayidx, align 4
   ret void
 }
 
 ; CHECK-LABEL: store_test3:
-; CHECK-NEXT: param     i32, i32{{$}}
+; CHECK-NEXT: .functype store_test3 (i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEXT: i32.shl   $push1=, $0, $pop0{{$}}
 ; CHECK-NEX T: i32.store g+40($pop1), $1{{$}}
 ; CHECK-NEX T: return{{$}}
 define void @store_test3(i32 %n, i32 %i) {
   %add.ptr = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %n
   %add.ptr1 = getelementptr inbounds i32, i32* %add.ptr, i32 10
   store i32 %i, i32* %add.ptr1, align 4
   ret void
 }
 
 ; CHECK-LABEL: store_test4:
-; CHECK-NEXT: param     i32, i32{{$}}
+; CHECK-NEXT: .functype store_test4 (i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEXT: i32.shl   $push1=, $0, $pop0{{$}}
 ; CHECK-NEX T: i32.store g+40($pop1), $1{{$}}
 ; CHECK-NEX T: return{{$}}
 define void @store_test4(i32 %n, i32 %i) {
   %add.ptr = getelementptr inbounds i32, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @g, i32 0, i32 10), i32 %n
   store i32 %i, i32* %add.ptr, align 4
   ret void
 }
 
 ; CHECK-LABEL: store_test5:
-; CHECK-NEXT: param     i32, i32{{$}}
+; CHECK-NEXT: .functype store_test5 (i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEXT: i32.shl   $push1=, $0, $pop0{{$}}
 ; CHECK-NEX T: i32.store g+40($pop1), $1{{$}}
 ; CHECK-NEX T: return{{$}}
 define void @store_test5(i32 %n, i32 %i) {
   %add.ptr = getelementptr inbounds i32, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @g, i32 0, i32 10), i32 %n
   store i32 %i, i32* %add.ptr, align 4
   ret void
 }
 
 ; CHECK-LABEL: store_test6:
-; CHECK-NEXT: param     i32, i32{{$}}
+; CHECK-NEXT: .functype store_test6 (i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEXT: i32.shl   $push1=, $0, $pop0{{$}}
 ; CHECK-NEX T: i32.store g+40($pop1), $1{{$}}
 ; CHECK-NEX T: return{{$}}
 define void @store_test6(i32 %n, i32 %i) {
   %add = add nsw i32 %n, 10
   %add.ptr = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %add
   store i32 %i, i32* %add.ptr, align 4
   ret void
 }
 
 ; CHECK-LABEL: store_test7:
-; CHECK-NEXT: param     i32, i32{{$}}
+; CHECK-NEXT: .functype store_test7 (i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEXT: i32.shl   $push1=, $0, $pop0{{$}}
 ; CHECK-NEX T: i32.store g+40($pop1), $1{{$}}
 ; CHECK-NEX T: return{{$}}
 define void @store_test7(i32 %n, i32 %i) {
   %add.ptr = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %n
   %add.ptr1 = getelementptr inbounds i32, i32* %add.ptr, i32 10
   store i32 %i, i32* %add.ptr1, align 4
   ret void
 }
 
 ; CHECK-LABEL: store_test8:
-; CHECK-NEXT: param     i32, i32{{$}}
+; CHECK-NEXT: .functype store_test8 (i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEXT: i32.shl   $push1=, $0, $pop0{{$}}
 ; CHECK-NEX T: i32.store g+40($pop1), $1{{$}}
 ; CHECK-NEX T: return{{$}}
 define void @store_test8(i32 %n, i32 %i) {
   %add = add nsw i32 10, %n
   %add.ptr = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %add
   store i32 %i, i32* %add.ptr, align 4
   ret void
 }
 
 ; CHECK-LABEL: store_test9:
-; CHECK-NEXT: param     i32{{$}}
+; CHECK-NEXT: .functype store_test9 (i32) -> (){{$}}
 ; CHECK-NEXT: i32.const $push0=, 0{{$}}
 ; CHECK-NEXT: i32.store g-40($pop0), $0{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_test9(i32 %i) {
   store i32 %i, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @g, i32 0, i32 1073741814), align 4
   ret void
 }
 
 ; CHECK-LABEL: store_test10:
-; CHECK-NEXT: param     i32, i32{{$}}
+; CHECK-NEXT: .functype store_test10 (i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEXT: i32.shl   $push1=, $0, $pop0{{$}}
 ; CHECK-NEXT: i32.const $push2=, g-40{{$}}
 ; CHECK-NEXT: i32.add   $push3=, $pop1, $pop2{{$}}
 ; CHECK-NEXT: i32.store 0($pop3), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_test10(i32 %n, i32 %i) {
   %add = add nsw i32 %n, -10
   %arrayidx = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %add
   store i32 %i, i32* %arrayidx, align 4
   ret void
 }
 
 ; CHECK-LABEL: store_test11:
-; CHECK-NEXT: param     i32, i32{{$}}
+; CHECK-NEXT: .functype store_test11 (i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.store 40($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_test11(i32* %p, i32 %i) {
   %arrayidx = getelementptr inbounds i32, i32* %p, i32 10
   store i32 %i, i32* %arrayidx, align 4
   ret void
 }
 
 ; CHECK-LABEL: store_test11_noinbounds:
-; CHECK-NEXT: param     i32, i32{{$}}
+; CHECK-NEXT: .functype store_test11_noinbounds (i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.const $push0=, 40{{$}}
 ; CHECK-NEXT: i32.add   $push1=, $0, $pop0{{$}}
 ; CHECK-NEXT: i32.store 0($pop1), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_test11_noinbounds(i32* %p, i32 %i) {
   %arrayidx = getelementptr i32, i32* %p, i32 10
   store i32 %i, i32* %arrayidx, align 4
   ret void
 }
 
 ; CHECK-LABEL: store_test12:
-; CHECK-NEXT: param     i32, i32, i32{{$}}
+; CHECK-NEXT: .functype store_test12 (i32, i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEXT: i32.shl   $push1=, $1, $pop0{{$}}
 ; CHECK-NEXT: i32.add   $push2=, $0, $pop1{{$}}
 ; CHECK-NEXT: i32.const $push3=, 40{{$}}
 ; CHECK-NEXT: i32.add   $push4=, $pop2, $pop3{{$}}
 ; CHECK-NEXT: i32.store 0($pop4), $2{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_test12(i32* %p, i32 %n, i32 %i) {
   %add = add nsw i32 %n, 10
   %arrayidx = getelementptr inbounds i32, i32* %p, i32 %add
   store i32 %i, i32* %arrayidx, align 4
   ret void
 }
 
 ; CHECK-LABEL: store_test13:
-; CHECK-NEXT: param     i32, i32, i32{{$}}
+; CHECK-NEXT: .functype store_test13 (i32, i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEXT: i32.shl   $push1=, $1, $pop0{{$}}
 ; CHECK-NEXT: i32.add   $push2=, $0, $pop1{{$}}
 ; CHECK-NEXT: i32.const $push3=, 40{{$}}
 ; CHECK-NEXT: i32.add   $push4=, $pop2, $pop3{{$}}
 ; CHECK-NEXT: i32.store 0($pop4), $2{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_test13(i32* %p, i32 %n, i32 %i) {
   %add = add nsw i32 10, %n
   %arrayidx = getelementptr inbounds i32, i32* %p, i32 %add
   store i32 %i, i32* %arrayidx, align 4
   ret void
 }
 
 ; CHECK-LABEL: store_test14:
-; CHECK-NEXT: param     i32, i32, i32{{$}}
+; CHECK-NEXT: .functype store_test14 (i32, i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEXT: i32.shl   $push1=, $1, $pop0{{$}}
 ; CHECK-NEXT: i32.add   $push2=, $0, $pop1{{$}}
 ; CHECK-NEXT: i32.store 40($pop2), $2{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_test14(i32* %p, i32 %n, i32 %i) {
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 %n
   %add.ptr1 = getelementptr inbounds i32, i32* %add.ptr, i32 10
   store i32 %i, i32* %add.ptr1, align 4
   ret void
 }
 
 ; CHECK-LABEL: store_test15:
-; CHECK-NEXT: param     i32, i32, i32{{$}}
+; CHECK-NEXT: .functype store_test15 (i32, i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEXT: i32.shl   $push1=, $1, $pop0{{$}}
 ; CHECK-NEXT: i32.add   $push2=, $0, $pop1{{$}}
 ; CHECK-NEXT: i32.const $push3=, 40{{$}}
 ; CHECK-NEXT: i32.add   $push4=, $pop2, $pop3{{$}}
 ; CHECK-NEXT: i32.store 0($pop4), $2{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_test15(i32* %p, i32 %n, i32 %i) {
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 10
   %add.ptr1 = getelementptr inbounds i32, i32* %add.ptr, i32 %n
   store i32 %i, i32* %add.ptr1, align 4
   ret void
 }
 
 ; CHECK-LABEL: store_test16:
-; CHECK-NEXT: param     i32, i32, i32{{$}}
+; CHECK-NEXT: .functype store_test16 (i32, i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEXT: i32.shl   $push1=, $1, $pop0{{$}}
 ; CHECK-NEXT: i32.add   $push2=, $0, $pop1{{$}}
 ; CHECK-NEXT: i32.const $push3=, 40{{$}}
 ; CHECK-NEXT: i32.add   $push4=, $pop2, $pop3{{$}}
 ; CHECK-NEXT: i32.store 0($pop4), $2{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_test16(i32* %p, i32 %n, i32 %i) {
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 10
   %add.ptr1 = getelementptr inbounds i32, i32* %add.ptr, i32 %n
   store i32 %i, i32* %add.ptr1, align 4
   ret void
 }
 
 ; CHECK-LABEL: store_test17:
-; CHECK-NEXT: param     i32, i32, i32{{$}}
+; CHECK-NEXT: .functype store_test17 (i32, i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEXT: i32.shl   $push1=, $1, $pop0{{$}}
 ; CHECK-NEXT: i32.add   $push2=, $0, $pop1{{$}}
 ; CHECK-NEXT: i32.const $push3=, 40{{$}}
 ; CHECK-NEXT: i32.add   $push4=, $pop2, $pop3{{$}}
 ; CHECK-NEXT: i32.store 0($pop4), $2{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_test17(i32* %p, i32 %n, i32 %i) {
   %add = add nsw i32 %n, 10
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 %add
   store i32 %i, i32* %add.ptr, align 4
   ret void
 }
 
 ; CHECK-LABEL: store_test18:
-; CHECK-NEXT: param     i32, i32, i32{{$}}
+; CHECK-NEXT: .functype store_test18 (i32, i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEXT: i32.shl   $push1=, $1, $pop0{{$}}
 ; CHECK-NEXT: i32.add   $push2=, $0, $pop1{{$}}
 ; CHECK-NEXT: i32.store 40($pop2), $2{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_test18(i32* %p, i32 %n, i32 %i) {
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 %n
   %add.ptr1 = getelementptr inbounds i32, i32* %add.ptr, i32 10
   store i32 %i, i32* %add.ptr1, align 4
   ret void
 }
 
 ; CHECK-LABEL: store_test19:
-; CHECK-NEXT: param     i32, i32, i32{{$}}
+; CHECK-NEXT: .functype store_test19 (i32, i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEXT: i32.shl   $push1=, $1, $pop0{{$}}
 ; CHECK-NEXT: i32.add   $push2=, $0, $pop1{{$}}
 ; CHECK-NEXT: i32.const $push3=, 40{{$}}
 ; CHECK-NEXT: i32.add   $push4=, $pop2, $pop3{{$}}
 ; CHECK-NEXT: i32.store 0($pop4), $2{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_test19(i32* %p, i32 %n, i32 %i) {
   %add = add nsw i32 10, %n
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 %add
   store i32 %i, i32* %add.ptr, align 4
   ret void
 }
 
 ; CHECK-LABEL: store_test20:
-; CHECK-NEXT: param     i32, i32{{$}}
+; CHECK-NEXT: .functype store_test20 (i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.const $push0=, -40{{$}}
 ; CHECK-NEXT: i32.add   $push1=, $0, $pop0{{$}}
 ; CHECK-NEXT: i32.store 0($pop1), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_test20(i32* %p, i32 %i) {
   %arrayidx = getelementptr inbounds i32, i32* %p, i32 -10
   store i32 %i, i32* %arrayidx, align 4
   ret void
 }
 
 ; CHECK-LABEL: store_test21:
-; CHECK-NEXT: param     i32, i32, i32{{$}}
+; CHECK-NEXT: .functype store_test21 (i32, i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEXT: i32.shl   $push1=, $1, $pop0{{$}}
 ; CHECK-NEXT: i32.add   $push2=, $0, $pop1{{$}}
 ; CHECK-NEXT: i32.const $push3=, -40{{$}}
 ; CHECK-NEXT: i32.add   $push4=, $pop2, $pop3{{$}}
 ; CHECK-NEXT: i32.store 0($pop4), $2{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_test21(i32* %p, i32 %n, i32 %i) {
   %add = add nsw i32 %n, -10
   %arrayidx = getelementptr inbounds i32, i32* %p, i32 %add
   store i32 %i, i32* %arrayidx, align 4
   ret void
 }

test/CodeGen/WebAssembly/atomic-mem-consistency.ll

 
 ;===----------------------------------------------------------------------------
 ; Atomic stores
 ;===----------------------------------------------------------------------------
 
 ; The 'acquire' and 'acq_rel' orderings aren’t valid on store instructions.
 
 ; CHECK-LABEL: store_i32_unordered:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype store_i32_unordered (i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.atomic.store 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_i32_unordered(i32 *%p, i32 %v) {
   store atomic i32 %v, i32* %p unordered, align 4
   ret void
 }
 
 ; CHECK-LABEL: store_i32_monotonic:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype store_i32_monotonic (i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.atomic.store 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_i32_monotonic(i32 *%p, i32 %v) {
   store atomic i32 %v, i32* %p monotonic, align 4
   ret void
 }
 
 ; CHECK-LABEL: store_i32_release:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype store_i32_release (i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.atomic.store 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_i32_release(i32 *%p, i32 %v) {
   store atomic i32 %v, i32* %p release, align 4
   ret void
 }
 
 ; CHECK-LABEL: store_i32_seq_cst:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype store_i32_seq_cst (i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.atomic.store 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_i32_seq_cst(i32 *%p, i32 %v) {
   store atomic i32 %v, i32* %p seq_cst, align 4
   ret void
 }
 
 ;===----------------------------------------------------------------------------
 ; Atomic read-modify-writes
 ;===----------------------------------------------------------------------------
 
 ; Out of several binary RMW instructions, here we test 'add' as an example.
 ; The 'unordered' ordering is not valid on atomicrmw instructions.
 
 ; CHECK-LABEL: add_i32_monotonic:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype add_i32_monotonic (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw.add $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @add_i32_monotonic(i32* %p, i32 %v) {
   %old = atomicrmw add i32* %p, i32 %v monotonic
   ret i32 %old
 }
 
 ; CHECK-LABEL: add_i32_acquire:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype add_i32_acquire (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw.add $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @add_i32_acquire(i32* %p, i32 %v) {
   %old = atomicrmw add i32* %p, i32 %v acquire
   ret i32 %old
 }
 
 ; CHECK-LABEL: add_i32_release:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype add_i32_release (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw.add $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @add_i32_release(i32* %p, i32 %v) {
   %old = atomicrmw add i32* %p, i32 %v release
   ret i32 %old
 }
 
 ; CHECK-LABEL: add_i32_acq_rel:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype add_i32_acq_rel (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw.add $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @add_i32_acq_rel(i32* %p, i32 %v) {
   %old = atomicrmw add i32* %p, i32 %v acq_rel
   ret i32 %old
 }
 
 ; CHECK-LABEL: add_i32_seq_cst:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype add_i32_seq_cst (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw.add $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @add_i32_seq_cst(i32* %p, i32 %v) {
   %old = atomicrmw add i32* %p, i32 %v seq_cst
   ret i32 %old
 }
 
 ; Ternary RMW instruction: cmpxchg
 ; The success and failure ordering arguments specify how this cmpxchg
 ; synchronizes with other atomic operations. Both ordering parameters must be at
 ; least monotonic, the ordering constraint on failure must be no stronger than
 ; that on success, and the failure ordering cannot be either release or acq_rel.
 
 ; CHECK-LABEL: cmpxchg_i32_monotonic_monotonic:
-; CHECK-NEXT: .param i32, i32, i32{{$}}
+; CHECK-NEXT: .functype cmpxchg_i32_monotonic_monotonic (i32, i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw.cmpxchg $push0=, 0($0), $1, $2{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @cmpxchg_i32_monotonic_monotonic(i32* %p, i32 %exp, i32 %new) {
   %pair = cmpxchg i32* %p, i32 %exp, i32 %new monotonic monotonic
   %old = extractvalue { i32, i1 } %pair, 0
   ret i32 %old
 }
 
 ; CHECK-LABEL: cmpxchg_i32_acquire_monotonic:
-; CHECK-NEXT: .param i32, i32, i32{{$}}
+; CHECK-NEXT: .functype cmpxchg_i32_acquire_monotonic (i32, i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw.cmpxchg $push0=, 0($0), $1, $2{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @cmpxchg_i32_acquire_monotonic(i32* %p, i32 %exp, i32 %new) {
   %pair = cmpxchg i32* %p, i32 %exp, i32 %new acquire monotonic
   %old = extractvalue { i32, i1 } %pair, 0
   ret i32 %old
 }
 
 ; CHECK-LABEL: cmpxchg_i32_release_monotonic:
-; CHECK-NEXT: .param i32, i32, i32{{$}}
+; CHECK-NEXT: .functype cmpxchg_i32_release_monotonic (i32, i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw.cmpxchg $push0=, 0($0), $1, $2{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @cmpxchg_i32_release_monotonic(i32* %p, i32 %exp, i32 %new) {
   %pair = cmpxchg i32* %p, i32 %exp, i32 %new release monotonic
   %old = extractvalue { i32, i1 } %pair, 0
   ret i32 %old
 }
 
 ; CHECK-LABEL: cmpxchg_i32_acq_rel_monotonic:
-; CHECK-NEXT: .param i32, i32, i32{{$}}
+; CHECK-NEXT: .functype cmpxchg_i32_acq_rel_monotonic (i32, i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw.cmpxchg $push0=, 0($0), $1, $2{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @cmpxchg_i32_acq_rel_monotonic(i32* %p, i32 %exp, i32 %new) {
   %pair = cmpxchg i32* %p, i32 %exp, i32 %new acq_rel monotonic
   %old = extractvalue { i32, i1 } %pair, 0
   ret i32 %old
 }
 
 ; CHECK-LABEL: cmpxchg_i32_seq_cst_monotonic:
-; CHECK-NEXT: .param i32, i32, i32{{$}}
+; CHECK-NEXT: .functype cmpxchg_i32_seq_cst_monotonic (i32, i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw.cmpxchg $push0=, 0($0), $1, $2{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @cmpxchg_i32_seq_cst_monotonic(i32* %p, i32 %exp, i32 %new) {
   %pair = cmpxchg i32* %p, i32 %exp, i32 %new seq_cst monotonic
   %old = extractvalue { i32, i1 } %pair, 0
   ret i32 %old
 }
 
 ; CHECK-LABEL: cmpxchg_i32_acquire_acquire:
-; CHECK-NEXT: .param i32, i32, i32{{$}}
+; CHECK-NEXT: .functype cmpxchg_i32_acquire_acquire (i32, i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw.cmpxchg $push0=, 0($0), $1, $2{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @cmpxchg_i32_acquire_acquire(i32* %p, i32 %exp, i32 %new) {
   %pair = cmpxchg i32* %p, i32 %exp, i32 %new acquire acquire
   %old = extractvalue { i32, i1 } %pair, 0
   ret i32 %old
 }
 
 ; CHECK-LABEL: cmpxchg_i32_release_acquire:
-; CHECK-NEXT: .param i32, i32, i32{{$}}
+; CHECK-NEXT: .functype cmpxchg_i32_release_acquire (i32, i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw.cmpxchg $push0=, 0($0), $1, $2{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @cmpxchg_i32_release_acquire(i32* %p, i32 %exp, i32 %new) {
   %pair = cmpxchg i32* %p, i32 %exp, i32 %new release acquire
   %old = extractvalue { i32, i1 } %pair, 0
   ret i32 %old
 }
 
 ; CHECK-LABEL: cmpxchg_i32_acq_rel_acquire:
-; CHECK-NEXT: .param i32, i32, i32{{$}}
+; CHECK-NEXT: .functype cmpxchg_i32_acq_rel_acquire (i32, i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw.cmpxchg $push0=, 0($0), $1, $2{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @cmpxchg_i32_acq_rel_acquire(i32* %p, i32 %exp, i32 %new) {
   %pair = cmpxchg i32* %p, i32 %exp, i32 %new acq_rel acquire
   %old = extractvalue { i32, i1 } %pair, 0
   ret i32 %old
 }
 
 ; CHECK-LABEL: cmpxchg_i32_seq_cst_acquire:
-; CHECK-NEXT: .param i32, i32, i32{{$}}
+; CHECK-NEXT: .functype cmpxchg_i32_seq_cst_acquire (i32, i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw.cmpxchg $push0=, 0($0), $1, $2{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @cmpxchg_i32_seq_cst_acquire(i32* %p, i32 %exp, i32 %new) {
   %pair = cmpxchg i32* %p, i32 %exp, i32 %new seq_cst acquire
   %old = extractvalue { i32, i1 } %pair, 0
   ret i32 %old
 }
 
 ; CHECK-LABEL: cmpxchg_i32_seq_cst_seq_cst:
-; CHECK-NEXT: .param i32, i32, i32{{$}}
+; CHECK-NEXT: .functype cmpxchg_i32_seq_cst_seq_cst (i32, i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw.cmpxchg $push0=, 0($0), $1, $2{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @cmpxchg_i32_seq_cst_seq_cst(i32* %p, i32 %exp, i32 %new) {
   %pair = cmpxchg i32* %p, i32 %exp, i32 %new seq_cst seq_cst
   %old = extractvalue { i32, i1 } %pair, 0
   ret i32 %old
 }

test/CodeGen/WebAssembly/atomic-rmw.ll

 ; RUN: not llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers
 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+atomics,+sign-ext | FileCheck %s
 
 ; Test atomic RMW (read-modify-write) instructions are assembled properly.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ;===----------------------------------------------------------------------------
 ; Atomic read-modify-writes: 32-bit
 ;===----------------------------------------------------------------------------
 
 ; CHECK-LABEL: add_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype add_i32 (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw.add $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @add_i32(i32* %p, i32 %v) {
   %old = atomicrmw add i32* %p, i32 %v seq_cst
   ret i32 %old
 }
 
 ; CHECK-LABEL: sub_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype sub_i32 (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw.sub $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @sub_i32(i32* %p, i32 %v) {
   %old = atomicrmw sub i32* %p, i32 %v seq_cst
   ret i32 %old
 }
 
 ; CHECK-LABEL: and_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype and_i32 (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw.and $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @and_i32(i32* %p, i32 %v) {
   %old = atomicrmw and i32* %p, i32 %v seq_cst
   ret i32 %old
 }
 
 ; CHECK-LABEL: or_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype or_i32 (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw.or $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @or_i32(i32* %p, i32 %v) {
   %old = atomicrmw or i32* %p, i32 %v seq_cst
   ret i32 %old
 }
 
 ; CHECK-LABEL: xor_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype xor_i32 (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw.xor $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @xor_i32(i32* %p, i32 %v) {
   %old = atomicrmw xor i32* %p, i32 %v seq_cst
   ret i32 %old
 }
 
 ; CHECK-LABEL: xchg_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype xchg_i32 (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw.xchg $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @xchg_i32(i32* %p, i32 %v) {
   %old = atomicrmw xchg i32* %p, i32 %v seq_cst
   ret i32 %old
 }
 
 ; CHECK-LABEL: cmpxchg_i32_loaded_value:
-; CHECK-NEXT: .param i32, i32, i32{{$}}
+; CHECK-NEXT: .functype cmpxchg_i32_loaded_value (i32, i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw.cmpxchg $push0=, 0($0), $1, $2{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @cmpxchg_i32_loaded_value(i32* %p, i32 %exp, i32 %new) {
   %pair = cmpxchg i32* %p, i32 %exp, i32 %new seq_cst seq_cst
   %old = extractvalue { i32, i1 } %pair, 0
   ret i32 %old
 }
 
 ; CHECK-LABEL: cmpxchg_i32_success:
-; CHECK-NEXT: .param i32, i32, i32{{$}}
+; CHECK-NEXT: .functype cmpxchg_i32_success (i32, i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw.cmpxchg $push0=, 0($0), $1, $2{{$}}
 ; CHECK-NEXT: i32.eq $push1=, $pop0, $1{{$}}
 ; CHECK-NEXT: return $pop1{{$}}
 define i1 @cmpxchg_i32_success(i32* %p, i32 %exp, i32 %new) {
   %pair = cmpxchg i32* %p, i32 %exp, i32 %new seq_cst seq_cst
   %succ = extractvalue { i32, i1 } %pair, 1
   ret i1 %succ
 }
define i32 @umin_i32(i32* %p, i32 %v) {
   ret i32 %old
 }
 
 ;===----------------------------------------------------------------------------
 ; Atomic read-modify-writes: 64-bit
 ;===----------------------------------------------------------------------------
 
 ; CHECK-LABEL: add_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype add_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw.add $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @add_i64(i64* %p, i64 %v) {
   %old = atomicrmw add i64* %p, i64 %v seq_cst
   ret i64 %old
 }
 
 ; CHECK-LABEL: sub_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype sub_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw.sub $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @sub_i64(i64* %p, i64 %v) {
   %old = atomicrmw sub i64* %p, i64 %v seq_cst
   ret i64 %old
 }
 
 ; CHECK-LABEL: and_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype and_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw.and $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @and_i64(i64* %p, i64 %v) {
   %old = atomicrmw and i64* %p, i64 %v seq_cst
   ret i64 %old
 }
 
 ; CHECK-LABEL: or_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype or_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw.or $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @or_i64(i64* %p, i64 %v) {
   %old = atomicrmw or i64* %p, i64 %v seq_cst
   ret i64 %old
 }
 
 ; CHECK-LABEL: xor_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype xor_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw.xor $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @xor_i64(i64* %p, i64 %v) {
   %old = atomicrmw xor i64* %p, i64 %v seq_cst
   ret i64 %old
 }
 
 ; CHECK-LABEL: xchg_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype xchg_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw.xchg $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @xchg_i64(i64* %p, i64 %v) {
   %old = atomicrmw xchg i64* %p, i64 %v seq_cst
   ret i64 %old
 }
 
 ; CHECK-LABEL: cmpxchg_i64_loaded_value:
-; CHECK-NEXT: .param i32, i64, i64{{$}}
+; CHECK-NEXT: .functype cmpxchg_i64_loaded_value (i32, i64, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw.cmpxchg $push0=, 0($0), $1, $2{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @cmpxchg_i64_loaded_value(i64* %p, i64 %exp, i64 %new) {
   %pair = cmpxchg i64* %p, i64 %exp, i64 %new seq_cst seq_cst
   %old = extractvalue { i64, i1 } %pair, 0
   ret i64 %old
 }
 
 ; CHECK-LABEL: cmpxchg_i64_success:
-; CHECK-NEXT: .param i32, i64, i64{{$}}
+; CHECK-NEXT: .functype cmpxchg_i64_success (i32, i64, i64) -> (i32){{$}}
 ; CHECK: i64.atomic.rmw.cmpxchg $push0=, 0($0), $1, $2{{$}}
 ; CHECK-NEXT: i64.eq $push1=, $pop0, $1{{$}}
 ; CHECK-NEXT: return $pop1{{$}}
 define i1 @cmpxchg_i64_success(i64* %p, i64 %exp, i64 %new) {
   %pair = cmpxchg i64* %p, i64 %exp, i64 %new seq_cst seq_cst
   %succ = extractvalue { i64, i1 } %pair, 1
   ret i1 %succ
 }

 
 ;===----------------------------------------------------------------------------
 ; Atomic truncating & sign-extending RMWs
 ;===----------------------------------------------------------------------------
 
 ; add
 
 ; CHECK-LABEL: add_sext_i8_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype add_sext_i8_i32 (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw8_u.add $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: i32.extend8_s $push1=, $pop0{{$}}
 ; CHECK-NEXT: return $pop1{{$}}
 define i32 @add_sext_i8_i32(i8* %p, i32 %v) {
   %t = trunc i32 %v to i8
   %old = atomicrmw add i8* %p, i8 %t seq_cst
   %e = sext i8 %old to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: add_sext_i16_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype add_sext_i16_i32 (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw16_u.add $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: i32.extend16_s $push1=, $pop0{{$}}
 ; CHECK-NEXT: return $pop1{{$}}
 define i32 @add_sext_i16_i32(i16* %p, i32 %v) {
   %t = trunc i32 %v to i16
   %old = atomicrmw add i16* %p, i16 %t seq_cst
   %e = sext i16 %old to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: add_sext_i8_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype add_sext_i8_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw8_u.add $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: i64.extend8_s $push1=, $pop0{{$}}
 ; CHECK-NEXT: return $pop1{{$}}
 define i64 @add_sext_i8_i64(i8* %p, i64 %v) {
   %t = trunc i64 %v to i8
   %old = atomicrmw add i8* %p, i8 %t seq_cst
   %e = sext i8 %old to i64
   ret i64 %e
 }
 
 ; CHECK-LABEL: add_sext_i16_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype add_sext_i16_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw16_u.add $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: i64.extend16_s $push1=, $pop0{{$}}
 ; CHECK-NEXT: return $pop1{{$}}
 define i64 @add_sext_i16_i64(i16* %p, i64 %v) {
   %t = trunc i64 %v to i16
   %old = atomicrmw add i16* %p, i16 %t seq_cst
   %e = sext i16 %old to i64
   ret i64 %e
 }
 
 ; 32->64 sext rmw gets selected as i32.atomic.rmw.add, i64_extend_s/i32
 ; CHECK-LABEL: add_sext_i32_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype add_sext_i32_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i32.wrap/i64 $push0=, $1{{$}}
 ; CHECK: i32.atomic.rmw.add $push1=, 0($0), $pop0{{$}}
 ; CHECK-NEXT: i64.extend_s/i32 $push2=, $pop1{{$}}
 ; CHECK-NEXT: return $pop2{{$}}
 define i64 @add_sext_i32_i64(i32* %p, i64 %v) {
   %t = trunc i64 %v to i32
   %old = atomicrmw add i32* %p, i32 %t seq_cst
   %e = sext i32 %old to i64
   ret i64 %e
 }
 
 ; sub
 
 ; CHECK-LABEL: sub_sext_i8_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype sub_sext_i8_i32 (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw8_u.sub $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: i32.extend8_s $push1=, $pop0{{$}}
 ; CHECK-NEXT: return $pop1{{$}}
 define i32 @sub_sext_i8_i32(i8* %p, i32 %v) {
   %t = trunc i32 %v to i8
   %old = atomicrmw sub i8* %p, i8 %t seq_cst
   %e = sext i8 %old to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: sub_sext_i16_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype sub_sext_i16_i32 (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw16_u.sub $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: i32.extend16_s $push1=, $pop0{{$}}
 ; CHECK-NEXT: return $pop1{{$}}
 define i32 @sub_sext_i16_i32(i16* %p, i32 %v) {
   %t = trunc i32 %v to i16
   %old = atomicrmw sub i16* %p, i16 %t seq_cst
   %e = sext i16 %old to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: sub_sext_i8_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype sub_sext_i8_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw8_u.sub $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: i64.extend8_s $push1=, $pop0{{$}}
 ; CHECK-NEXT: return $pop1{{$}}
 define i64 @sub_sext_i8_i64(i8* %p, i64 %v) {
   %t = trunc i64 %v to i8
   %old = atomicrmw sub i8* %p, i8 %t seq_cst
   %e = sext i8 %old to i64
   ret i64 %e
 }
 
 ; CHECK-LABEL: sub_sext_i16_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype sub_sext_i16_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw16_u.sub $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: i64.extend16_s $push1=, $pop0{{$}}
 ; CHECK-NEXT: return $pop1{{$}}
 define i64 @sub_sext_i16_i64(i16* %p, i64 %v) {
   %t = trunc i64 %v to i16
   %old = atomicrmw sub i16* %p, i16 %t seq_cst
   %e = sext i16 %old to i64
   ret i64 %e
 }
 
 ; 32->64 sext rmw gets selected as i32.atomic.rmw.sub, i64_extend_s/i32
 ; CHECK-LABEL: sub_sext_i32_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype sub_sext_i32_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i32.wrap/i64 $push0=, $1
 ; CHECK: i32.atomic.rmw.sub $push1=, 0($0), $pop0{{$}}
 ; CHECK-NEXT: i64.extend_s/i32 $push2=, $pop1{{$}}
 ; CHECK-NEXT: return $pop2{{$}}
 define i64 @sub_sext_i32_i64(i32* %p, i64 %v) {
   %t = trunc i64 %v to i32
   %old = atomicrmw sub i32* %p, i32 %t seq_cst
   %e = sext i32 %old to i64
   ret i64 %e
 }
 
 ; and
 
 ; CHECK-LABEL: and_sext_i8_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype and_sext_i8_i32 (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw8_u.and $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: i32.extend8_s $push1=, $pop0{{$}}
 ; CHECK-NEXT: return $pop1{{$}}
 define i32 @and_sext_i8_i32(i8* %p, i32 %v) {
   %t = trunc i32 %v to i8
   %old = atomicrmw and i8* %p, i8 %t seq_cst
   %e = sext i8 %old to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: and_sext_i16_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype and_sext_i16_i32 (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw16_u.and $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: i32.extend16_s $push1=, $pop0{{$}}
 ; CHECK-NEXT: return $pop1{{$}}
 define i32 @and_sext_i16_i32(i16* %p, i32 %v) {
   %t = trunc i32 %v to i16
   %old = atomicrmw and i16* %p, i16 %t seq_cst
   %e = sext i16 %old to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: and_sext_i8_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype and_sext_i8_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw8_u.and $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: i64.extend8_s $push1=, $pop0{{$}}
 ; CHECK-NEXT: return $pop1{{$}}
 define i64 @and_sext_i8_i64(i8* %p, i64 %v) {
   %t = trunc i64 %v to i8
   %old = atomicrmw and i8* %p, i8 %t seq_cst
   %e = sext i8 %old to i64
   ret i64 %e
 }
 
 ; CHECK-LABEL: and_sext_i16_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype and_sext_i16_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw16_u.and $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: i64.extend16_s $push1=, $pop0{{$}}
 ; CHECK-NEXT: return $pop1{{$}}
 define i64 @and_sext_i16_i64(i16* %p, i64 %v) {
   %t = trunc i64 %v to i16
   %old = atomicrmw and i16* %p, i16 %t seq_cst
   %e = sext i16 %old to i64
   ret i64 %e
 }
 
 ; 32->64 sext rmw gets selected as i32.atomic.rmw.and, i64_extend_s/i32
 ; CHECK-LABEL: and_sext_i32_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype and_sext_i32_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i32.wrap/i64 $push0=, $1{{$}}
 ; CHECK: i32.atomic.rmw.and $push1=, 0($0), $pop0{{$}}
 ; CHECK-NEXT: i64.extend_s/i32 $push2=, $pop1{{$}}
 ; CHECK-NEXT: return $pop2{{$}}
 define i64 @and_sext_i32_i64(i32* %p, i64 %v) {
   %t = trunc i64 %v to i32
   %old = atomicrmw and i32* %p, i32 %t seq_cst
   %e = sext i32 %old to i64
   ret i64 %e
 }
 
 ; or
 
 ; CHECK-LABEL: or_sext_i8_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype or_sext_i8_i32 (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw8_u.or $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: i32.extend8_s $push1=, $pop0{{$}}
 ; CHECK-NEXT: return $pop1{{$}}
 define i32 @or_sext_i8_i32(i8* %p, i32 %v) {
   %t = trunc i32 %v to i8
   %old = atomicrmw or i8* %p, i8 %t seq_cst
   %e = sext i8 %old to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: or_sext_i16_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype or_sext_i16_i32 (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw16_u.or $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: i32.extend16_s $push1=, $pop0{{$}}
 ; CHECK-NEXT: return $pop1{{$}}
 define i32 @or_sext_i16_i32(i16* %p, i32 %v) {
   %t = trunc i32 %v to i16
   %old = atomicrmw or i16* %p, i16 %t seq_cst
   %e = sext i16 %old to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: or_sext_i8_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype or_sext_i8_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw8_u.or $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: i64.extend8_s $push1=, $pop0{{$}}
 ; CHECK-NEXT: return $pop1{{$}}
 define i64 @or_sext_i8_i64(i8* %p, i64 %v) {
   %t = trunc i64 %v to i8
   %old = atomicrmw or i8* %p, i8 %t seq_cst
   %e = sext i8 %old to i64
   ret i64 %e
 }
 
 ; CHECK-LABEL: or_sext_i16_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype or_sext_i16_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw16_u.or $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: i64.extend16_s $push1=, $pop0{{$}}
 ; CHECK-NEXT: return $pop1{{$}}
 define i64 @or_sext_i16_i64(i16* %p, i64 %v) {
   %t = trunc i64 %v to i16
   %old = atomicrmw or i16* %p, i16 %t seq_cst
   %e = sext i16 %old to i64
   ret i64 %e
 }
 
 ; 32->64 sext rmw gets selected as i32.atomic.rmw.or, i64_extend_s/i32
 ; CHECK-LABEL: or_sext_i32_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype or_sext_i32_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i32.wrap/i64 $push0=, $1{{$}}
 ; CHECK: i32.atomic.rmw.or $push1=, 0($0), $pop0{{$}}
 ; CHECK-NEXT: i64.extend_s/i32 $push2=, $pop1{{$}}
 ; CHECK-NEXT: return $pop2{{$}}
 define i64 @or_sext_i32_i64(i32* %p, i64 %v) {
   %t = trunc i64 %v to i32
   %old = atomicrmw or i32* %p, i32 %t seq_cst
   %e = sext i32 %old to i64
   ret i64 %e
 }
 
 ; xor
 
 ; CHECK-LABEL: xor_sext_i8_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype xor_sext_i8_i32 (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw8_u.xor $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: i32.extend8_s $push1=, $pop0{{$}}
 ; CHECK-NEXT: return $pop1{{$}}
 define i32 @xor_sext_i8_i32(i8* %p, i32 %v) {
   %t = trunc i32 %v to i8
   %old = atomicrmw xor i8* %p, i8 %t seq_cst
   %e = sext i8 %old to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: xor_sext_i16_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype xor_sext_i16_i32 (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw16_u.xor $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: i32.extend16_s $push1=, $pop0{{$}}
 ; CHECK-NEXT: return $pop1{{$}}
 define i32 @xor_sext_i16_i32(i16* %p, i32 %v) {
   %t = trunc i32 %v to i16
   %old = atomicrmw xor i16* %p, i16 %t seq_cst
   %e = sext i16 %old to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: xor_sext_i8_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype xor_sext_i8_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw8_u.xor $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: i64.extend8_s $push1=, $pop0{{$}}
 ; CHECK-NEXT: return $pop1{{$}}
 define i64 @xor_sext_i8_i64(i8* %p, i64 %v) {
   %t = trunc i64 %v to i8
   %old = atomicrmw xor i8* %p, i8 %t seq_cst
   %e = sext i8 %old to i64
   ret i64 %e
 }
 
 ; CHECK-LABEL: xor_sext_i16_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype xor_sext_i16_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw16_u.xor $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: i64.extend16_s $push1=, $pop0{{$}}
 ; CHECK-NEXT: return $pop1{{$}}
 define i64 @xor_sext_i16_i64(i16* %p, i64 %v) {
   %t = trunc i64 %v to i16
   %old = atomicrmw xor i16* %p, i16 %t seq_cst
   %e = sext i16 %old to i64
   ret i64 %e
 }
 
 ; 32->64 sext rmw gets selected as i32.atomic.rmw.xor, i64_extend_s/i32
 ; CHECK-LABEL: xor_sext_i32_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype xor_sext_i32_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i32.wrap/i64 $push0=, $1{{$}}
 ; CHECK: i32.atomic.rmw.xor $push1=, 0($0), $pop0{{$}}
 ; CHECK-NEXT: i64.extend_s/i32 $push2=, $pop1{{$}}
 ; CHECK-NEXT: return $pop2{{$}}
 define i64 @xor_sext_i32_i64(i32* %p, i64 %v) {
   %t = trunc i64 %v to i32
   %old = atomicrmw xor i32* %p, i32 %t seq_cst
   %e = sext i32 %old to i64
   ret i64 %e
 }
 
 ; xchg
 
 ; CHECK-LABEL: xchg_sext_i8_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype xchg_sext_i8_i32 (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw8_u.xchg $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: i32.extend8_s $push1=, $pop0{{$}}
 ; CHECK-NEXT: return $pop1{{$}}
 define i32 @xchg_sext_i8_i32(i8* %p, i32 %v) {
   %t = trunc i32 %v to i8
   %old = atomicrmw xchg i8* %p, i8 %t seq_cst
   %e = sext i8 %old to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: xchg_sext_i16_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype xchg_sext_i16_i32 (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw16_u.xchg $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: i32.extend16_s $push1=, $pop0{{$}}
 ; CHECK-NEXT: return $pop1{{$}}
 define i32 @xchg_sext_i16_i32(i16* %p, i32 %v) {
   %t = trunc i32 %v to i16
   %old = atomicrmw xchg i16* %p, i16 %t seq_cst
   %e = sext i16 %old to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: xchg_sext_i8_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype xchg_sext_i8_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw8_u.xchg $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: i64.extend8_s $push1=, $pop0{{$}}
 ; CHECK-NEXT: return $pop1{{$}}
 define i64 @xchg_sext_i8_i64(i8* %p, i64 %v) {
   %t = trunc i64 %v to i8
   %old = atomicrmw xchg i8* %p, i8 %t seq_cst
   %e = sext i8 %old to i64
   ret i64 %e
 }
 
 ; CHECK-LABEL: xchg_sext_i16_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype xchg_sext_i16_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw16_u.xchg $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: i64.extend16_s $push1=, $pop0{{$}}
 ; CHECK-NEXT: return $pop1{{$}}
 define i64 @xchg_sext_i16_i64(i16* %p, i64 %v) {
   %t = trunc i64 %v to i16
   %old = atomicrmw xchg i16* %p, i16 %t seq_cst
   %e = sext i16 %old to i64
   ret i64 %e
 }
 
 ; 32->64 sext rmw gets selected as i32.atomic.rmw.xchg, i64_extend_s/i32
 ; CHECK-LABEL: xchg_sext_i32_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype xchg_sext_i32_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i32.wrap/i64 $push0=, $1{{$}}
 ; CHECK: i32.atomic.rmw.xchg $push1=, 0($0), $pop0{{$}}
 ; CHECK-NEXT: i64.extend_s/i32 $push2=, $pop1{{$}}
 ; CHECK-NEXT: return $pop2{{$}}
 define i64 @xchg_sext_i32_i64(i32* %p, i64 %v) {
   %t = trunc i64 %v to i32
   %old = atomicrmw xchg i32* %p, i32 %t seq_cst
   %e = sext i32 %old to i64
   ret i64 %e
 }
 
 ; cmpxchg
 
 ; CHECK-LABEL: cmpxchg_sext_i8_i32:
-; CHECK-NEXT: .param i32, i32, i32{{$}}
+; CHECK-NEXT: .functype cmpxchg_sext_i8_i32 (i32, i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw8_u.cmpxchg $push0=, 0($0), $1, $2{{$}}
 ; CHECK-NEXT: i32.extend8_s $push1=, $pop0{{$}}
 ; CHECK-NEXT: return $pop1{{$}}
 define i32 @cmpxchg_sext_i8_i32(i8* %p, i32 %exp, i32 %new) {
   %exp_t = trunc i32 %exp to i8
   %new_t = trunc i32 %new to i8
   %pair = cmpxchg i8* %p, i8 %exp_t, i8 %new_t seq_cst seq_cst
   %old = extractvalue { i8, i1 } %pair, 0
   %e = sext i8 %old to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: cmpxchg_sext_i16_i32:
-; CHECK-NEXT: .param i32, i32, i32{{$}}
+; CHECK-NEXT: .functype cmpxchg_sext_i16_i32 (i32, i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw16_u.cmpxchg $push0=, 0($0), $1, $2{{$}}
 ; CHECK-NEXT: i32.extend16_s $push1=, $pop0{{$}}
 ; CHECK-NEXT: return $pop1{{$}}
 define i32 @cmpxchg_sext_i16_i32(i16* %p, i32 %exp, i32 %new) {
   %exp_t = trunc i32 %exp to i16
   %new_t = trunc i32 %new to i16
   %pair = cmpxchg i16* %p, i16 %exp_t, i16 %new_t seq_cst seq_cst
   %old = extractvalue { i16, i1 } %pair, 0
   %e = sext i16 %old to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: cmpxchg_sext_i8_i64:
-; CHECK-NEXT: .param i32, i64, i64{{$}}
+; CHECK-NEXT: .functype cmpxchg_sext_i8_i64 (i32, i64, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw8_u.cmpxchg $push0=, 0($0), $1, $2{{$}}
 ; CHECK-NEXT: i64.extend8_s $push1=, $pop0{{$}}
 ; CHECK-NEXT: return $pop1{{$}}
 define i64 @cmpxchg_sext_i8_i64(i8* %p, i64 %exp, i64 %new) {
   %exp_t = trunc i64 %exp to i8
   %new_t = trunc i64 %new to i8
   %pair = cmpxchg i8* %p, i8 %exp_t, i8 %new_t seq_cst seq_cst
   %old = extractvalue { i8, i1 } %pair, 0
   %e = sext i8 %old to i64
   ret i64 %e
 }
 
 ; CHECK-LABEL: cmpxchg_sext_i16_i64:
-; CHECK-NEXT: .param i32, i64, i64{{$}}
+; CHECK-NEXT: .functype cmpxchg_sext_i16_i64 (i32, i64, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw16_u.cmpxchg $push0=, 0($0), $1, $2{{$}}
 ; CHECK-NEXT: i64.extend16_s $push1=, $pop0{{$}}
 ; CHECK-NEXT: return $pop1{{$}}
 define i64 @cmpxchg_sext_i16_i64(i16* %p, i64 %exp, i64 %new) {
   %exp_t = trunc i64 %exp to i16
   %new_t = trunc i64 %new to i16
   %pair = cmpxchg i16* %p, i16 %exp_t, i16 %new_t seq_cst seq_cst
   %old = extractvalue { i16, i1 } %pair, 0
   %e = sext i16 %old to i64
   ret i64 %e
 }
 
 ; 32->64 sext rmw gets selected as i32.atomic.rmw.cmpxchg, i64_extend_s/i32
 ; CHECK-LABEL: cmpxchg_sext_i32_i64:
-; CHECK-NEXT: .param i32, i64, i64{{$}}
+; CHECK-NEXT: .functype cmpxchg_sext_i32_i64 (i32, i64, i64) -> (i64){{$}}
 ; CHECK: i32.wrap/i64 $push1=, $1{{$}}
 ; CHECK-NEXT: i32.wrap/i64 $push0=, $2{{$}}
 ; CHECK-NEXT: i32.atomic.rmw.cmpxchg $push2=, 0($0), $pop1, $pop0{{$}}
 ; CHECK-NEXT: i64.extend_s/i32 $push3=, $pop2{{$}}
 ; CHECK-NEXT: return $pop3{{$}}
 define i64 @cmpxchg_sext_i32_i64(i32* %p, i64 %exp, i64 %new) {
   %exp_t = trunc i64 %exp to i32
   %new_t = trunc i64 %new to i32
   %pair = cmpxchg i32* %p, i32 %exp_t, i32 %new_t seq_cst seq_cst
   %old = extractvalue { i32, i1 } %pair, 0
   %e = sext i32 %old to i64
   ret i64 %e
 }
 
 ; Unsupported instructions are expanded using cmpxchg with a loop.
 ; Here we take a nand as an example.
 
 ; nand
 
 ; CHECK-LABEL: nand_sext_i8_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype nand_sext_i8_i32 (i32, i32) -> (i32){{$}}
 ; CHECK: loop
 ; CHECK: i32.atomic.rmw8_u.cmpxchg
 ; CHECK: i32.extend8_s
 define i32 @nand_sext_i8_i32(i8* %p, i32 %v) {
   %t = trunc i32 %v to i8
   %old = atomicrmw nand i8* %p, i8 %t seq_cst
   %e = sext i8 %old to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: nand_sext_i16_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype nand_sext_i16_i32 (i32, i32) -> (i32){{$}}
 ; CHECK: loop
 ; CHECK: i32.atomic.rmw16_u.cmpxchg
 ; CHECK: i32.extend16_s
 define i32 @nand_sext_i16_i32(i16* %p, i32 %v) {
   %t = trunc i32 %v to i16
   %old = atomicrmw nand i16* %p, i16 %t seq_cst
   %e = sext i16 %old to i32
   ret i32 %e
 }
 
 ; FIXME Currently this cannot make use of i64.atomic.rmw8_u.cmpxchg
 ; CHECK-LABEL: nand_sext_i8_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype nand_sext_i8_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: loop
 ; CHECK: i32.atomic.rmw8_u.cmpxchg
 ; CHECK: i64.extend_u/i32
 ; CHECK: i64.extend8_s
 define i64 @nand_sext_i8_i64(i8* %p, i64 %v) {
   %t = trunc i64 %v to i8
   %old = atomicrmw nand i8* %p, i8 %t seq_cst
   %e = sext i8 %old to i64
   ret i64 %e
 }
 
 ; FIXME Currently this cannot make use of i64.atomic.rmw16_u.cmpxchg
 ; CHECK-LABEL: nand_sext_i16_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype nand_sext_i16_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: loop
 ; CHECK: i32.atomic.rmw16_u.cmpxchg
 ; CHECK: i64.extend_u/i32
 ; CHECK: i64.extend16_s
 define i64 @nand_sext_i16_i64(i16* %p, i64 %v) {
   %t = trunc i64 %v to i16
   %old = atomicrmw nand i16* %p, i16 %t seq_cst
   %e = sext i16 %old to i64
   ret i64 %e
 }
 
 ; 32->64 sext rmw gets selected as i32.atomic.rmw.nand, i64_extend_s/i32
 ; CHECK-LABEL: nand_sext_i32_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype nand_sext_i32_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: loop
 ; CHECK: i32.atomic.rmw.cmpxchg
 ; CHECK: i64.extend_s/i32
 define i64 @nand_sext_i32_i64(i32* %p, i64 %v) {
   %t = trunc i64 %v to i32
   %old = atomicrmw nand i32* %p, i32 %t seq_cst
   %e = sext i32 %old to i64
   ret i64 %e
 }
 
 ;===----------------------------------------------------------------------------
 ; Atomic truncating & zero-extending RMWs
 ;===----------------------------------------------------------------------------
 
 ; add
 
 ; CHECK-LABEL: add_zext_i8_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype add_zext_i8_i32 (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw8_u.add $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @add_zext_i8_i32(i8* %p, i32 %v) {
   %t = trunc i32 %v to i8
   %old = atomicrmw add i8* %p, i8 %t seq_cst
   %e = zext i8 %old to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: add_zext_i16_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype add_zext_i16_i32 (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw16_u.add $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @add_zext_i16_i32(i16* %p, i32 %v) {
   %t = trunc i32 %v to i16
   %old = atomicrmw add i16* %p, i16 %t seq_cst
   %e = zext i16 %old to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: add_zext_i8_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype add_zext_i8_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw8_u.add $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @add_zext_i8_i64(i8* %p, i64 %v) {
   %t = trunc i64 %v to i8
   %old = atomicrmw add i8* %p, i8 %t seq_cst
   %e = zext i8 %old to i64
   ret i64 %e
 }
 
 ; CHECK-LABEL: add_zext_i16_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype add_zext_i16_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw16_u.add $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @add_zext_i16_i64(i16* %p, i64 %v) {
   %t = trunc i64 %v to i16
   %old = atomicrmw add i16* %p, i16 %t seq_cst
   %e = zext i16 %old to i64
   ret i64 %e
 }
 
 ; CHECK-LABEL: add_zext_i32_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype add_zext_i32_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw32_u.add $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @add_zext_i32_i64(i32* %p, i64 %v) {
   %t = trunc i64 %v to i32
   %old = atomicrmw add i32* %p, i32 %t seq_cst
   %e = zext i32 %old to i64
   ret i64 %e
 }
 
 ; sub
 
 ; CHECK-LABEL: sub_zext_i8_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype sub_zext_i8_i32 (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw8_u.sub $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @sub_zext_i8_i32(i8* %p, i32 %v) {
   %t = trunc i32 %v to i8
   %old = atomicrmw sub i8* %p, i8 %t seq_cst
   %e = zext i8 %old to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: sub_zext_i16_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype sub_zext_i16_i32 (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw16_u.sub $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @sub_zext_i16_i32(i16* %p, i32 %v) {
   %t = trunc i32 %v to i16
   %old = atomicrmw sub i16* %p, i16 %t seq_cst
   %e = zext i16 %old to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: sub_zext_i8_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype sub_zext_i8_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw8_u.sub $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @sub_zext_i8_i64(i8* %p, i64 %v) {
   %t = trunc i64 %v to i8
   %old = atomicrmw sub i8* %p, i8 %t seq_cst
   %e = zext i8 %old to i64
   ret i64 %e
 }
 
 ; CHECK-LABEL: sub_zext_i16_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype sub_zext_i16_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw16_u.sub $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @sub_zext_i16_i64(i16* %p, i64 %v) {
   %t = trunc i64 %v to i16
   %old = atomicrmw sub i16* %p, i16 %t seq_cst
   %e = zext i16 %old to i64
   ret i64 %e
 }
 
 ; CHECK-LABEL: sub_zext_i32_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype sub_zext_i32_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw32_u.sub $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @sub_zext_i32_i64(i32* %p, i64 %v) {
   %t = trunc i64 %v to i32
   %old = atomicrmw sub i32* %p, i32 %t seq_cst
   %e = zext i32 %old to i64
   ret i64 %e
 }
 
 ; and
 
 ; CHECK-LABEL: and_zext_i8_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype and_zext_i8_i32 (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw8_u.and $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @and_zext_i8_i32(i8* %p, i32 %v) {
   %t = trunc i32 %v to i8
   %old = atomicrmw and i8* %p, i8 %t seq_cst
   %e = zext i8 %old to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: and_zext_i16_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype and_zext_i16_i32 (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw16_u.and $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @and_zext_i16_i32(i16* %p, i32 %v) {
   %t = trunc i32 %v to i16
   %old = atomicrmw and i16* %p, i16 %t seq_cst
   %e = zext i16 %old to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: and_zext_i8_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype and_zext_i8_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw8_u.and $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @and_zext_i8_i64(i8* %p, i64 %v) {
   %t = trunc i64 %v to i8
   %old = atomicrmw and i8* %p, i8 %t seq_cst
   %e = zext i8 %old to i64
   ret i64 %e
 }
 
 ; CHECK-LABEL: and_zext_i16_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype and_zext_i16_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw16_u.and $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @and_zext_i16_i64(i16* %p, i64 %v) {
   %t = trunc i64 %v to i16
   %old = atomicrmw and i16* %p, i16 %t seq_cst
   %e = zext i16 %old to i64
   ret i64 %e
 }
 
 ; CHECK-LABEL: and_zext_i32_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype and_zext_i32_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw32_u.and $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @and_zext_i32_i64(i32* %p, i64 %v) {
   %t = trunc i64 %v to i32
   %old = atomicrmw and i32* %p, i32 %t seq_cst
   %e = zext i32 %old to i64
   ret i64 %e
 }
 
 ; or
 
 ; CHECK-LABEL: or_zext_i8_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype or_zext_i8_i32 (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw8_u.or $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @or_zext_i8_i32(i8* %p, i32 %v) {
   %t = trunc i32 %v to i8
   %old = atomicrmw or i8* %p, i8 %t seq_cst
   %e = zext i8 %old to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: or_zext_i16_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype or_zext_i16_i32 (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw16_u.or $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @or_zext_i16_i32(i16* %p, i32 %v) {
   %t = trunc i32 %v to i16
   %old = atomicrmw or i16* %p, i16 %t seq_cst
   %e = zext i16 %old to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: or_zext_i8_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype or_zext_i8_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw8_u.or $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @or_zext_i8_i64(i8* %p, i64 %v) {
   %t = trunc i64 %v to i8
   %old = atomicrmw or i8* %p, i8 %t seq_cst
   %e = zext i8 %old to i64
   ret i64 %e
 }
 
 ; CHECK-LABEL: or_zext_i16_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype or_zext_i16_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw16_u.or $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @or_zext_i16_i64(i16* %p, i64 %v) {
   %t = trunc i64 %v to i16
   %old = atomicrmw or i16* %p, i16 %t seq_cst
   %e = zext i16 %old to i64
   ret i64 %e
 }
 
 ; CHECK-LABEL: or_zext_i32_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype or_zext_i32_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw32_u.or $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @or_zext_i32_i64(i32* %p, i64 %v) {
   %t = trunc i64 %v to i32
   %old = atomicrmw or i32* %p, i32 %t seq_cst
   %e = zext i32 %old to i64
   ret i64 %e
 }
 
 ; xor
 
 ; CHECK-LABEL: xor_zext_i8_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype xor_zext_i8_i32 (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw8_u.xor $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @xor_zext_i8_i32(i8* %p, i32 %v) {
   %t = trunc i32 %v to i8
   %old = atomicrmw xor i8* %p, i8 %t seq_cst
   %e = zext i8 %old to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: xor_zext_i16_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype xor_zext_i16_i32 (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw16_u.xor $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @xor_zext_i16_i32(i16* %p, i32 %v) {
   %t = trunc i32 %v to i16
   %old = atomicrmw xor i16* %p, i16 %t seq_cst
   %e = zext i16 %old to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: xor_zext_i8_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype xor_zext_i8_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw8_u.xor $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @xor_zext_i8_i64(i8* %p, i64 %v) {
   %t = trunc i64 %v to i8
   %old = atomicrmw xor i8* %p, i8 %t seq_cst
   %e = zext i8 %old to i64
   ret i64 %e
 }
 
 ; CHECK-LABEL: xor_zext_i16_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype xor_zext_i16_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw16_u.xor $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @xor_zext_i16_i64(i16* %p, i64 %v) {
   %t = trunc i64 %v to i16
   %old = atomicrmw xor i16* %p, i16 %t seq_cst
   %e = zext i16 %old to i64
   ret i64 %e
 }
 
 ; CHECK-LABEL: xor_zext_i32_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype xor_zext_i32_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw32_u.xor $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @xor_zext_i32_i64(i32* %p, i64 %v) {
   %t = trunc i64 %v to i32
   %old = atomicrmw xor i32* %p, i32 %t seq_cst
   %e = zext i32 %old to i64
   ret i64 %e
 }
 
 ; xchg
 
 ; CHECK-LABEL: xchg_zext_i8_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype xchg_zext_i8_i32 (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw8_u.xchg $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @xchg_zext_i8_i32(i8* %p, i32 %v) {
   %t = trunc i32 %v to i8
   %old = atomicrmw xchg i8* %p, i8 %t seq_cst
   %e = zext i8 %old to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: xchg_zext_i16_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype xchg_zext_i16_i32 (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw16_u.xchg $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @xchg_zext_i16_i32(i16* %p, i32 %v) {
   %t = trunc i32 %v to i16
   %old = atomicrmw xchg i16* %p, i16 %t seq_cst
   %e = zext i16 %old to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: xchg_zext_i8_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype xchg_zext_i8_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw8_u.xchg $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @xchg_zext_i8_i64(i8* %p, i64 %v) {
   %t = trunc i64 %v to i8
   %old = atomicrmw xchg i8* %p, i8 %t seq_cst
   %e = zext i8 %old to i64
   ret i64 %e
 }
 
 ; CHECK-LABEL: xchg_zext_i16_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype xchg_zext_i16_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw16_u.xchg $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @xchg_zext_i16_i64(i16* %p, i64 %v) {
   %t = trunc i64 %v to i16
   %old = atomicrmw xchg i16* %p, i16 %t seq_cst
   %e = zext i16 %old to i64
   ret i64 %e
 }
 
 ; CHECK-LABEL: xchg_zext_i32_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype xchg_zext_i32_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw32_u.xchg $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @xchg_zext_i32_i64(i32* %p, i64 %v) {
   %t = trunc i64 %v to i32
   %old = atomicrmw xchg i32* %p, i32 %t seq_cst
   %e = zext i32 %old to i64
   ret i64 %e
 }
 
 ; cmpxchg
 
 ; CHECK-LABEL: cmpxchg_zext_i8_i32:
-; CHECK-NEXT: .param i32, i32, i32{{$}}
+; CHECK-NEXT: .functype cmpxchg_zext_i8_i32 (i32, i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw8_u.cmpxchg $push0=, 0($0), $1, $2{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @cmpxchg_zext_i8_i32(i8* %p, i32 %exp, i32 %new) {
   %exp_t = trunc i32 %exp to i8
   %new_t = trunc i32 %new to i8
   %pair = cmpxchg i8* %p, i8 %exp_t, i8 %new_t seq_cst seq_cst
   %old = extractvalue { i8, i1 } %pair, 0
   %e = zext i8 %old to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: cmpxchg_zext_i16_i32:
-; CHECK-NEXT: .param i32, i32, i32{{$}}
+; CHECK-NEXT: .functype cmpxchg_zext_i16_i32 (i32, i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw16_u.cmpxchg $push0=, 0($0), $1, $2{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @cmpxchg_zext_i16_i32(i16* %p, i32 %exp, i32 %new) {
   %exp_t = trunc i32 %exp to i16
   %new_t = trunc i32 %new to i16
   %pair = cmpxchg i16* %p, i16 %exp_t, i16 %new_t seq_cst seq_cst
   %old = extractvalue { i16, i1 } %pair, 0
   %e = zext i16 %old to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: cmpxchg_zext_i8_i64:
-; CHECK-NEXT: .param i32, i64, i64{{$}}
+; CHECK-NEXT: .functype cmpxchg_zext_i8_i64 (i32, i64, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw8_u.cmpxchg $push0=, 0($0), $1, $2{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @cmpxchg_zext_i8_i64(i8* %p, i64 %exp, i64 %new) {
   %exp_t = trunc i64 %exp to i8
   %new_t = trunc i64 %new to i8
   %pair = cmpxchg i8* %p, i8 %exp_t, i8 %new_t seq_cst seq_cst
   %old = extractvalue { i8, i1 } %pair, 0
   %e = zext i8 %old to i64
   ret i64 %e
 }
 
 ; CHECK-LABEL: cmpxchg_zext_i16_i64:
-; CHECK-NEXT: .param i32, i64, i64{{$}}
+; CHECK-NEXT: .functype cmpxchg_zext_i16_i64 (i32, i64, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw16_u.cmpxchg $push0=, 0($0), $1, $2{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @cmpxchg_zext_i16_i64(i16* %p, i64 %exp, i64 %new) {
   %exp_t = trunc i64 %exp to i16
   %new_t = trunc i64 %new to i16
   %pair = cmpxchg i16* %p, i16 %exp_t, i16 %new_t seq_cst seq_cst
   %old = extractvalue { i16, i1 } %pair, 0
   %e = zext i16 %old to i64
   ret i64 %e
 }
 
 ; CHECK-LABEL: cmpxchg_zext_i32_i64:
-; CHECK-NEXT: .param i32, i64, i64{{$}}
+; CHECK-NEXT: .functype cmpxchg_zext_i32_i64 (i32, i64, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw32_u.cmpxchg $push0=, 0($0), $1, $2{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @cmpxchg_zext_i32_i64(i32* %p, i64 %exp, i64 %new) {
   %exp_t = trunc i64 %exp to i32
   %new_t = trunc i64 %new to i32
   %pair = cmpxchg i32* %p, i32 %exp_t, i32 %new_t seq_cst seq_cst
   %old = extractvalue { i32, i1 } %pair, 0
   %e = zext i32 %old to i64
   ret i64 %e
 }
 
 ; Unsupported instructions are expanded using cmpxchg with a loop.
 ; Here we take a nand as an example.
 
 ; nand
 
 ; CHECK-LABEL: nand_zext_i8_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype nand_zext_i8_i32 (i32, i32) -> (i32){{$}}
 ; CHECK: loop
 ; CHECK: i32.atomic.rmw8_u.cmpxchg
 define i32 @nand_zext_i8_i32(i8* %p, i32 %v) {
   %t = trunc i32 %v to i8
   %old = atomicrmw nand i8* %p, i8 %t seq_cst
   %e = zext i8 %old to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: nand_zext_i16_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype nand_zext_i16_i32 (i32, i32) -> (i32){{$}}
 ; CHECK: loop
 ; CHECK: i32.atomic.rmw16_u.cmpxchg
 define i32 @nand_zext_i16_i32(i16* %p, i32 %v) {
   %t = trunc i32 %v to i16
   %old = atomicrmw nand i16* %p, i16 %t seq_cst
   %e = zext i16 %old to i32
   ret i32 %e
 }
 
 ; FIXME Currently this cannot make use of i64.atomic.rmw8_u.cmpxchg
 ; CHECK-LABEL: nand_zext_i8_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype nand_zext_i8_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: loop
 ; CHECK: i32.atomic.rmw8_u.cmpxchg
 ; CHECK: i64.extend_u/i32
 define i64 @nand_zext_i8_i64(i8* %p, i64 %v) {
   %t = trunc i64 %v to i8
   %old = atomicrmw nand i8* %p, i8 %t seq_cst
   %e = zext i8 %old to i64
   ret i64 %e
 }
 
 ; FIXME Currently this cannot make use of i64.atomic.rmw16_u.cmpxchg
 ; CHECK-LABEL: nand_zext_i16_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype nand_zext_i16_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: loop
 ; CHECK: i32.atomic.rmw16_u.cmpxchg
 ; CHECK: i64.extend_u/i32
 define i64 @nand_zext_i16_i64(i16* %p, i64 %v) {
   %t = trunc i64 %v to i16
   %old = atomicrmw nand i16* %p, i16 %t seq_cst
   %e = zext i16 %old to i64
   ret i64 %e
 }
 
 ; FIXME Currently this cannot make use of i64.atomic.rmw32_u.cmpxchg
 ; CHECK-LABEL: nand_zext_i32_i64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype nand_zext_i32_i64 (i32, i64) -> (i64){{$}}
 ; CHECK: loop
 ; CHECK: i32.atomic.rmw.cmpxchg
 ; CHECK: i64.extend_u/i32
 define i64 @nand_zext_i32_i64(i32* %p, i64 %v) {
   %t = trunc i64 %v to i32
   %old = atomicrmw nand i32* %p, i32 %t seq_cst
   %e = zext i32 %old to i64
   ret i64 %e
 }

test/CodeGen/WebAssembly/byval.ll

 declare void @ext_byval_func(%SmallStruct* byval)
 declare void @ext_byval_func_align8(%SmallStruct* byval align 8)
 declare void @ext_byval_func_alignedstruct(%AlignedStruct* byval)
 declare void @ext_byval_func_bigarray(%BigArray* byval)
 declare void @ext_byval_func_empty(%EmptyStruct* byval)
 
 ; CHECK-LABEL: byval_arg
 define void @byval_arg(%SmallStruct* %ptr) {
- ; CHECK: .param i32
+ ; CHECK: .functype byval_arg (i32) -> ()
  ; Subtract 16 from SP (SP is 16-byte aligned)
  ; CHECK-NEXT: get_global $push[[L2:.+]]=, __stack_pointer@GLOBAL
  ; CHECK-NEXT: i32.const $push[[L3:.+]]=, 16
  ; CHECK-NEXT: i32.sub $push[[L11:.+]]=, $pop[[L2]], $pop[[L3]]
  ; Ensure SP is stored back before the call
  ; CHECK-NEXT: tee_local $push[[L10:.+]]=, $[[SP:.+]]=, $pop[[L11]]{{$}}
  ; CHECK-NEXT: set_global __stack_pointer@GLOBAL, $pop[[L10]]{{$}}
  ; Copy the SmallStruct argument to the stack (SP+12, original SP-4)

  ; CHECK-NEXT: i32.add $push[[L8:.+]]=, $[[SP]], $pop[[L6]]
  ; CHECK-NEXT: set_global __stack_pointer@GLOBAL, $pop[[L8]]
  ; CHECK-NEXT: return
  ret void
 }
 
 ; CHECK-LABEL: byval_arg_align8
 define void @byval_arg_align8(%SmallStruct* %ptr) {
- ; CHECK: .param i32
+ ; CHECK: .functype byval_arg_align8 (i32) -> ()
  ; Don't check the entire SP sequence, just enough to get the alignment.
  ; CHECK: i32.const $push[[L1:.+]]=, 16
  ; CHECK-NEXT: i32.sub $push[[L11:.+]]=, {{.+}}, $pop[[L1]]
  ; CHECK-NEXT: tee_local $push[[L10:.+]]=, $[[SP:.+]]=, $pop[[L11]]{{$}}
  ; CHECK-NEXT: set_global __stack_pointer@GLOBAL, $pop[[L10]]{{$}}
  ; Copy the SmallStruct argument to the stack (SP+8, original SP-8)
  ; CHECK-NEXT: i32.load $push[[L0:.+]]=, 0($0){{$}}
  ; CHECK-NEXT: i32.store 8($[[SP]]), $pop[[L0]]{{$}}
  ; Pass a pointer to the stack slot to the function
  ; CHECK-NEXT: i32.const $push[[L5:.+]]=, 8{{$}}
  ; CHECK-NEXT: i32.add $push[[ARG:.+]]=, $[[SP]], $pop[[L5]]{{$}}
  ; CHECK-NEXT: call ext_byval_func_align8@FUNCTION, $pop[[ARG]]{{$}}
  call void @ext_byval_func_align8(%SmallStruct* byval align 8 %ptr)
  ret void
 }
 
 ; CHECK-LABEL: byval_arg_double
 define void @byval_arg_double(%AlignedStruct* %ptr) {
- ; CHECK: .param i32
+ ; CHECK: .functype byval_arg_double (i32) -> ()
  ; Subtract 16 from SP (SP is 16-byte aligned)
  ; CHECK: i32.const $push[[L1:.+]]=, 16
  ; CHECK-NEXT: i32.sub $push[[L14:.+]]=, {{.+}}, $pop[[L1]]
  ; CHECK-NEXT: tee_local $push[[L13:.+]]=, $[[SP:.+]]=, $pop[[L14]]
  ; CHECK-NEXT: set_global __stack_pointer@GLOBAL, $pop[[L13]]
  ; Copy the AlignedStruct argument to the stack (SP+0, original SP-16)
  ; Just check the last load/store pair of the memcpy
  ; CHECK: i64.load $push[[L4:.+]]=, 0($0)
  ; CHECK-NEXT: i64.store 0($[[SP]]), $pop[[L4]]
  ; Pass a pointer to the stack slot to the function
  ; CHECK-NEXT: call ext_byval_func_alignedstruct@FUNCTION, $[[SP]]
  tail call void @ext_byval_func_alignedstruct(%AlignedStruct* byval %ptr)
  ret void
 }
 
 ; CHECK-LABEL: byval_param
 define void @byval_param(%SmallStruct* byval align 32 %ptr) {
- ; CHECK: .param i32
+ ; CHECK: .functype byval_param (i32) -> ()
  ; %ptr is just a pointer to a struct, so pass it directly through
  ; CHECK: call ext_func@FUNCTION, $0
  call void @ext_func(%SmallStruct* %ptr)
  ret void
 }
 
 ; CHECK-LABEL: byval_empty_caller
 define void @byval_empty_caller(%EmptyStruct* %ptr) {
- ; CHECK: .param i32
+ ; CHECK: .functype byval_empty_caller (i32) -> ()
  ; CHECK: call ext_byval_func_empty@FUNCTION, $0
  call void @ext_byval_func_empty(%EmptyStruct* byval %ptr)
  ret void
 }
 
 ; CHECK-LABEL: byval_empty_callee
 define void @byval_empty_callee(%EmptyStruct* byval %ptr) {
- ; CHECK: .param i32
+ ; CHECK: .functype byval_empty_callee (i32) -> ()
  ; CHECK: call ext_func_empty@FUNCTION, $0
  call void @ext_func_empty(%EmptyStruct* %ptr)
  ret void
 }
 
 ; Call memcpy for "big" byvals.
 ; CHECK-LABEL: big_byval:
 ; CHECK:      get_global $push[[L2:.+]]=, __stack_pointer@GLOBAL{{$}}

test/CodeGen/WebAssembly/call.ll

 declare i32 @i32_binary(i32, i32)
 declare i64 @i64_nullary()
 declare float @float_nullary()
 declare double @double_nullary()
 declare <16 x i8> @v128_nullary()
 declare void @void_nullary()
 
 ; CHECK-LABEL: call_i32_nullary:
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype call_i32_nullary () -> (i32){{$}}
 ; CHECK-NEXT: {{^}} i32.call $push[[NUM:[0-9]+]]=, i32_nullary@FUNCTION{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i32 @call_i32_nullary() {
   %r = call i32 @i32_nullary()
   ret i32 %r
 }
 
 ; CHECK-LABEL: call_i64_nullary:
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype call_i64_nullary () -> (i64){{$}}
 ; CHECK-NEXT: {{^}} i64.call $push[[NUM:[0-9]+]]=, i64_nullary@FUNCTION{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @call_i64_nullary() {
   %r = call i64 @i64_nullary()
   ret i64 %r
 }
 
 ; CHECK-LABEL: call_float_nullary:
-; CHECK-NEXT: .result f32{{$}}
+; CHECK-NEXT: .functype call_float_nullary () -> (f32){{$}}
 ; CHECK-NEXT: {{^}} f32.call $push[[NUM:[0-9]+]]=, float_nullary@FUNCTION{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define float @call_float_nullary() {
   %r = call float @float_nullary()
   ret float %r
 }
 
 ; CHECK-LABEL: call_double_nullary:
-; CHECK-NEXT: .result f64{{$}}
+; CHECK-NEXT: .functype call_double_nullary () -> (f64){{$}}
 ; CHECK-NEXT: {{^}} f64.call $push[[NUM:[0-9]+]]=, double_nullary@FUNCTION{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define double @call_double_nullary() {
   %r = call double @double_nullary()
   ret double %r
 }
 
 ; CHECK-LABEL: call_v128_nullary:
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype call_v128_nullary () -> (v128){{$}}
 ; CHECK-NEXT: {{^}} v128.call $push[[NUM:[0-9]+]]=, v128_nullary@FUNCTION{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define <16 x i8> @call_v128_nullary() {
   %r = call <16 x i8> @v128_nullary()
   ret <16 x i8> %r
 }
 
 ; CHECK-LABEL: call_void_nullary:
+; CHECK-NEXT: .functype call_void_nullary () -> (){{$}}
 ; CHECK-NEXT: {{^}} call void_nullary@FUNCTION{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @call_void_nullary() {
   call void @void_nullary()
   ret void
 }
 
 ; CHECK-LABEL: call_i32_unary:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype call_i32_unary (i32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: {{^}} i32.call $push[[NUM:[0-9]+]]=, i32_unary@FUNCTION, $pop[[L0]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i32 @call_i32_unary(i32 %a) {
   %r = call i32 @i32_unary(i32 %a)
   ret i32 %r
 }
 
 ; CHECK-LABEL: call_i32_binary:
-; CHECK-NEXT: .param i32, i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype call_i32_binary (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: {{^}} i32.call $push[[NUM:[0-9]+]]=, i32_binary@FUNCTION, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i32 @call_i32_binary(i32 %a, i32 %b) {
   %r = call i32 @i32_binary(i32 %a, i32 %b)
   ret i32 %r
 }
 
 ; CHECK-LABEL: call_indirect_void:
-; CHECK-NEXT: .param i32{{$}}
+; CHECK-NEXT: .functype call_indirect_void (i32) -> (){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: {{^}} call_indirect $pop[[L0]]{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @call_indirect_void(void ()* %callee) {
   call void %callee()
   ret void
 }
 
 ; CHECK-LABEL: call_indirect_i32:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype call_indirect_i32 (i32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: {{^}} i32.call_indirect $push[[NUM:[0-9]+]]=, $pop[[L0]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i32 @call_indirect_i32(i32 ()* %callee) {
   %t = call i32 %callee()
   ret i32 %t
 }
 
 ; CHECK-LABEL: call_indirect_i64:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype call_indirect_i64 (i32) -> (i64){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: {{^}} i64.call_indirect $push[[NUM:[0-9]+]]=, $pop[[L0]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @call_indirect_i64(i64 ()* %callee) {
   %t = call i64 %callee()
   ret i64 %t
 }
 
 ; CHECK-LABEL: call_indirect_float:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result f32{{$}}
+; CHECK-NEXT: .functype call_indirect_float (i32) -> (f32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: {{^}} f32.call_indirect $push[[NUM:[0-9]+]]=, $pop[[L0]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define float @call_indirect_float(float ()* %callee) {
   %t = call float %callee()
   ret float %t
 }
 
 ; CHECK-LABEL: call_indirect_double:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result f64{{$}}
+; CHECK-NEXT: .functype call_indirect_double (i32) -> (f64){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: {{^}} f64.call_indirect $push[[NUM:[0-9]+]]=, $pop[[L0]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define double @call_indirect_double(double ()* %callee) {
   %t = call double %callee()
   ret double %t
 }
 
 ; CHECK-LABEL: call_indirect_v128:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype call_indirect_v128 (i32) -> (v128){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: {{^}} v128.call_indirect $push[[NUM:[0-9]+]]=, $pop[[L0]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define <16 x i8> @call_indirect_v128(<16 x i8> ()* %callee) {
   %t = call <16 x i8> %callee()
   ret <16 x i8> %t
 }
 
 ; CHECK-LABEL: call_indirect_arg:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype call_indirect_arg (i32, i32) -> (){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: {{^}} call_indirect $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @call_indirect_arg(void (i32)* %callee, i32 %arg) {
   call void %callee(i32 %arg)
   ret void
 }
 
 ; CHECK-LABEL: call_indirect_arg_2:
-; CHECK-NEXT: .param i32, i32, i32{{$}}
+; CHECK-NEXT: .functype call_indirect_arg_2 (i32, i32, i32) -> (){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 2{{$}}
 ; CHECK-NEXT: get_local $push[[L2:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: {{^}} i32.call_indirect $push[[NUM:[0-9]+]]=, $pop[[L0]], $pop[[L1]], $pop[[L2]]{{$}}
 ; CHECK-NEXT: drop $pop[[NUM]]{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @call_indirect_arg_2(i32 (i32, i32)* %callee, i32 %arg, i32 %arg2) {
   call i32 %callee(i32 %arg, i32 %arg2)
   ret void
 }
 
 ; CHECK-LABEL: tail_call_void_nullary:
+; CHECK-NEXT: .functype tail_call_void_nullary () -> (){{$}}
 ; CHECK-NEXT: {{^}} call void_nullary@FUNCTION{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @tail_call_void_nullary() {
   tail call void @void_nullary()
   ret void
 }
 
 ; CHECK-LABEL: fastcc_tail_call_void_nullary:
+; CHECK-NEXT: .functype fastcc_tail_call_void_nullary () -> (){{$}}
 ; CHECK-NEXT: {{^}} call void_nullary@FUNCTION{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @fastcc_tail_call_void_nullary() {
   tail call fastcc void @void_nullary()
   ret void
 }
 
 ; CHECK-LABEL: coldcc_tail_call_void_nullary:
+; CHECK-NEXT: .functype coldcc_tail_call_void_nullary () -> (){{$}}
 ; CHECK-NEXT: {{^}} call void_nullary@FUNCTION{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @coldcc_tail_call_void_nullary() {
   tail call coldcc void @void_nullary()
   ret void
 }
 
 ; CHECK-LABEL: call_constexpr:
+; CHECK-NEXT: .functype call_constexpr () -> (){{$}}
 ; CHECK-NEXT: i32.const $push[[L0:[0-9]+]]=, 2{{$}}
 ; CHECK-NEXT: i32.const $push[[L1:[0-9]+]]=, 3{{$}}
 ; CHECK-NEXT: call .Lvararg_func_bitcast@FUNCTION, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: call other_void_nullary@FUNCTION{{$}}
 ; CHECK-NEXT: call void_nullary@FUNCTION{{$}}
 ; CHECK-NEXT: return{{$}}
 declare void @vararg_func(...)
 declare void @other_void_nullary()

test/CodeGen/WebAssembly/cfg-stackify.ll

 if.end:
   call void @bar()
   br label %outer
 }
 
 ; Test switch lowering and block placement.
 
 ; CHECK-LABEL: test4:
-; CHECK-NEXT: .param       i32{{$}}
+; CHECK-NEXT: .functype test4 (i32) -> (){{$}}
 ; CHECK:      block   {{$}}
 ; CHECK-NEXT: block   {{$}}
 ; CHECK:      br_if       0, $pop{{[0-9]+}}{{$}}
 ; CHECK:      br_if       1, $pop{{[0-9]+}}{{$}}
 ; CHECK:      br          1{{$}}
 ; CHECK-NEXT: .LBB13_3:
 ; CHECK-NEXT: end_block{{$}}
 ; CHECK-NEXT: block   {{$}}
 ; CHECK:      br_if 0, $pop{{[0-9]+}}{{$}}
 ; CHECK:      br_if 1, $pop{{[0-9]+}}{{$}}
 ; CHECK-NEXT: .LBB13_5:
 ; CHECK-NEXT: end_block{{$}}
 ; CHECK-NEXT: return{{$}}
 ; CHECK-NEXT: .LBB13_6:
 ; CHECK-NEXT: end_block{{$}}
 ; CHECK-NEXT: return{{$}}
 ; OPT-LABEL: test4:
-; OPT-NEXT: .param       i32{{$}}
+; OPT-NEXT: .functype test4 (i32) -> (){{$}}
 ; OPT:      block   {{$}}
 ; OPT-NEXT: block   {{$}}
 ; OPT:      br_if       0, $pop{{[0-9]+}}{{$}}
 ; OPT:      br_if       1, $pop{{[0-9]+}}{{$}}
 ; OPT:      br          1{{$}}
 ; OPT-NEXT: .LBB13_3:
 ; OPT-NEXT: end_block{{$}}
 ; OPT-NEXT: block   {{$}}
bb7:
   ret void
 }
 
 ; A block can be "branched to" from another even if it is also reachable via
 ; fallthrough from the other. This would normally be optimized away, so use
 ; optnone to disable optimizations to test this case.
 
 ; CHECK-LABEL: test13:
-; CHECK-NEXT:  block   {{$}}
+; CHECK:       block   {{$}}
 ; CHECK-NEXT:  block   {{$}}
 ; CHECK:       br_if 0, $pop0{{$}}
 ; CHECK:       block   {{$}}
 ; CHECK:       br_if 0, $pop3{{$}}
 ; CHECK:       .LBB22_3:
 ; CHECK-NEXT:  end_block{{$}}
 ; CHECK:       br_if 1, $pop{{[0-9]+}}{{$}}
 ; CHECK-NEXT:  br 1{{$}}
 ; CHECK-NEXT:  .LBB22_4:
 ; CHECK-NEXT:  end_block{{$}}
 ; CHECK-NEXT:  return{{$}}
 ; CHECK-NEXT:  .LBB22_5:
 ; CHECK-NEXT:  end_block{{$}}
 ; CHECK-NEXT:  unreachable{{$}}
 ; OPT-LABEL: test13:
-; OPT-NEXT:  block   {{$}}
+; OPT:       block   {{$}}
 ; OPT-NEXT:  block   {{$}}
 ; OPT:       br_if 0, $pop0{{$}}
 ; OPT:       block   {{$}}
 ; OPT:       br_if 0, $pop3{{$}}
 ; OPT:       .LBB22_3:
 ; OPT-NEXT:  end_block{{$}}
 ; OPT:       br_if 1, $pop{{[0-9]+}}{{$}}
 ; OPT-NEXT:  br 1{{$}}
bb5:
   ret void
 }
 
 ; Test a case with a single-block loop that has another loop
 ; as a successor. The end_loop for the first loop should go
 ; before the loop for the second.
 
 ; CHECK-LABEL: test14:
-; CHECK-NEXT: .LBB23_1:{{$}}
+; CHECK:      .LBB23_1:{{$}}
 ; CHECK-NEXT:     loop    {{$}}
 ; CHECK-NEXT:     i32.const   $push0=, 0{{$}}
 ; CHECK-NEXT:     br_if       0, $pop0{{$}}
 ; CHECK-NEXT:     end_loop{{$}}
 ; CHECK-NEXT: .LBB23_3:{{$}}
 ; CHECK-NEXT:     loop    {{$}}
 ; CHECK-NEXT:     i32.const   $push1=, 0{{$}}
 ; CHECK-NEXT:     br_if       0, $pop1{{$}}

test/CodeGen/WebAssembly/comparisons-f32.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
 
 ; Test that basic 32-bit floating-point comparison operations assemble as
 ; expected.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: ord_f32:
-; CHECK-NEXT: .param f32, f32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype ord_f32 (f32, f32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: f32.eq $push[[NUM0:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: get_local $push[[L2:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: get_local $push[[L3:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: f32.eq $push[[NUM1:[0-9]+]]=, $pop[[L2]], $pop[[L3]]{{$}}
 ; CHECK-NEXT: i32.and $push[[NUM2:[0-9]+]]=, $pop[[NUM0]], $pop[[NUM1]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM2]]{{$}}
 define i32 @ord_f32(float %x, float %y) {
   %a = fcmp ord float %x, %y
   %b = zext i1 %a to i32
   ret i32 %b
 }
 
 ; CHECK-LABEL: uno_f32:
-; CHECK-NEXT: .param f32, f32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype uno_f32 (f32, f32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: f32.ne $push[[NUM0:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: get_local $push[[L2:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: get_local $push[[L3:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: f32.ne $push[[NUM1:[0-9]+]]=, $pop[[L2]], $pop[[L3]]{{$}}
 ; CHECK-NEXT: i32.or $push[[NUM2:[0-9]+]]=, $pop[[NUM0]], $pop[[NUM1]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM2]]{{$}}
 define i32 @uno_f32(float %x, float %y) {
   %a = fcmp uno float %x, %y
   %b = zext i1 %a to i32
   ret i32 %b
 }
 
 ; CHECK-LABEL: oeq_f32:
-; CHECK-NEXT: .param f32, f32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype oeq_f32 (f32, f32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: f32.eq $push[[NUM:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i32 @oeq_f32(float %x, float %y) {
   %a = fcmp oeq float %x, %y
   %b = zext i1 %a to i32
   ret i32 %b
define i32 @oge_f32(float %x, float %y) {
   %b = zext i1 %a to i32
   ret i32 %b
 }
 
 ; Expanded comparisons, which also check for NaN.
 ; These simply rely on SDAG's Expand cond code action.
 
 ; CHECK-LABEL: ueq_f32:
-; CHECK-NEXT: .param f32, f32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype ueq_f32 (f32, f32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: f32.eq $push[[NUM0:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: get_local $push[[L2:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L3:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: f32.ne $push[[NUM1:[0-9]+]]=, $pop[[L2]], $pop[[L3]]{{$}}
 ; CHECK-NEXT: get_local $push[[L4:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: get_local $push[[L5:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: f32.ne $push[[NUM2:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}}
 ; CHECK-NEXT: i32.or $push[[NUM3:[0-9]+]]=, $pop[[NUM1]], $pop[[NUM2]]{{$}}
 ; CHECK-NEXT: i32.or $push[[NUM4:[0-9]+]]=, $pop[[NUM0]], $pop[[NUM3]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM4]]{{$}}
 define i32 @ueq_f32(float %x, float %y) {
   %a = fcmp ueq float %x, %y
   %b = zext i1 %a to i32
   ret i32 %b
 }
 
 ; CHECK-LABEL: one_f32:
-; CHECK-NEXT: .param f32, f32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype one_f32 (f32, f32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: f32.ne $push[[NUM0:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: get_local $push[[L2:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L3:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: f32.eq $push[[NUM1:[0-9]+]]=, $pop[[L2]], $pop[[L3]]{{$}}
 ; CHECK-NEXT: get_local $push[[L4:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: get_local $push[[L5:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: f32.eq $push[[NUM2:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}}
 ; CHECK-NEXT: i32.and $push[[NUM3:[0-9]+]]=, $pop[[NUM1]], $pop[[NUM2]]{{$}}
 ; CHECK-NEXT: i32.and $push[[NUM4:[0-9]+]]=, $pop[[NUM0]], $pop[[NUM3]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM4]]
 define i32 @one_f32(float %x, float %y) {
   %a = fcmp one float %x, %y
   %b = zext i1 %a to i32
   ret i32 %b
 }
 
 ; CHECK-LABEL: ult_f32:
-; CHECK-NEXT: .param f32, f32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype ult_f32 (f32, f32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: f32.ge $push[[NUM0:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: i32.const $push[[C0:[0-9]+]]=, 1
 ; CHECK-NEXT: i32.xor $push[[NUM2:[0-9]+]]=, $pop[[NUM0]], $pop[[C0]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM2]]{{$}}
 define i32 @ult_f32(float %x, float %y) {
   %a = fcmp ult float %x, %y
   %b = zext i1 %a to i32
   ret i32 %b
 }
 
 ; CHECK-LABEL: ule_f32:
-; CHECK-NEXT: .param f32, f32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype ule_f32 (f32, f32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: f32.gt $push[[NUM0:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: i32.const $push[[C0:[0-9]+]]=, 1
 ; CHECK-NEXT: i32.xor $push[[NUM2:[0-9]+]]=, $pop[[NUM0]], $pop[[C0]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM2]]{{$}}
 define i32 @ule_f32(float %x, float %y) {
   %a = fcmp ule float %x, %y
   %b = zext i1 %a to i32
   ret i32 %b
 }
 
 ; CHECK-LABEL: ugt_f32:
-; CHECK-NEXT: .param f32, f32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype ugt_f32 (f32, f32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: f32.le $push[[NUM0:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: i32.const $push[[C0:[0-9]+]]=, 1
 ; CHECK-NEXT: i32.xor $push[[NUM2:[0-9]+]]=, $pop[[NUM0]], $pop[[C0]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM2]]{{$}}
 define i32 @ugt_f32(float %x, float %y) {
   %a = fcmp ugt float %x, %y
   %b = zext i1 %a to i32
   ret i32 %b
 }
 
 ; CHECK-LABEL: uge_f32:
-; CHECK-NEXT: .param f32, f32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype uge_f32 (f32, f32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: f32.lt $push[[NUM0:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: i32.const $push[[C0:[0-9]+]]=, 1
 ; CHECK-NEXT: i32.xor $push[[NUM2:[0-9]+]]=, $pop[[NUM0]], $pop[[C0]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM2]]{{$}}
 define i32 @uge_f32(float %x, float %y) {
   %a = fcmp uge float %x, %y
   %b = zext i1 %a to i32
   ret i32 %b
 }

test/CodeGen/WebAssembly/comparisons-f64.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
 
 ; Test that basic 64-bit floating-point comparison operations assemble as
 ; expected.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: ord_f64:
-; CHECK-NEXT: .param f64, f64{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype ord_f64 (f64, f64) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: f64.eq $push[[NUM0:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: get_local $push[[L2:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: get_local $push[[L3:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: f64.eq $push[[NUM1:[0-9]+]]=, $pop[[L2]], $pop[[L3]]{{$}}
 ; CHECK-NEXT: i32.and $push[[NUM2:[0-9]+]]=, $pop[[NUM0]], $pop[[NUM1]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM2]]{{$}}
 define i32 @ord_f64(double %x, double %y) {
   %a = fcmp ord double %x, %y
   %b = zext i1 %a to i32
   ret i32 %b
 }
 
 ; CHECK-LABEL: uno_f64:
-; CHECK-NEXT: .param f64, f64{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype uno_f64 (f64, f64) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: f64.ne $push[[NUM0:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: get_local $push[[L2:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: get_local $push[[L3:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: f64.ne $push[[NUM1:[0-9]+]]=, $pop[[L2]], $pop[[L3]]{{$}}
 ; CHECK-NEXT: i32.or $push[[NUM2:[0-9]+]]=, $pop[[NUM0]], $pop[[NUM1]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM2]]{{$}}
 define i32 @uno_f64(double %x, double %y) {
   %a = fcmp uno double %x, %y
   %b = zext i1 %a to i32
   ret i32 %b
 }
 
 ; CHECK-LABEL: oeq_f64:
-; CHECK-NEXT: .param f64, f64{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype oeq_f64 (f64, f64) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: f64.eq $push[[NUM:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i32 @oeq_f64(double %x, double %y) {
   %a = fcmp oeq double %x, %y
   %b = zext i1 %a to i32
   ret i32 %b
define i32 @oge_f64(double %x, double %y) {
   %a = fcmp oge double %x, %y
   %b = zext i1 %a to i32
   ret i32 %b
 }
 
 ; Expanded comparisons, which also check for NaN.
 
 ; CHECK-LABEL: ueq_f64:
-; CHECK-NEXT: .param f64, f64{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype ueq_f64 (f64, f64) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: f64.eq $push[[NUM0:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: get_local $push[[L2:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L3:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: f64.ne $push[[NUM1:[0-9]+]]=, $pop[[L2]], $pop[[L3]]{{$}}
 ; CHECK-NEXT: get_local $push[[L4:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: get_local $push[[L5:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: f64.ne $push[[NUM2:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}}
 ; CHECK-NEXT: i32.or $push[[NUM3:[0-9]+]]=, $pop[[NUM1]], $pop[[NUM2]]{{$}}
 ; CHECK-NEXT: i32.or $push[[NUM4:[0-9]+]]=, $pop[[NUM0]], $pop[[NUM3]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM4]]{{$}}
 define i32 @ueq_f64(double %x, double %y) {
   %a = fcmp ueq double %x, %y
   %b = zext i1 %a to i32
   ret i32 %b
 }
 
 ; CHECK-LABEL: one_f64:
-; CHECK-NEXT: .param f64, f64{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype one_f64 (f64, f64) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: f64.ne $push[[NUM0:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: get_local $push[[L2:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L3:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: f64.eq $push[[NUM1:[0-9]+]]=, $pop[[L2]], $pop[[L3]]{{$}}
 ; CHECK-NEXT: get_local $push[[L4:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: get_local $push[[L5:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: f64.eq $push[[NUM2:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}}
 ; CHECK-NEXT: i32.and $push[[NUM3:[0-9]+]]=, $pop[[NUM1]], $pop[[NUM2]]{{$}}
 ; CHECK-NEXT: i32.and $push[[NUM4:[0-9]+]]=, $pop[[NUM0]], $pop[[NUM3]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM4]]
 define i32 @one_f64(double %x, double %y) {
   %a = fcmp one double %x, %y
   %b = zext i1 %a to i32
   ret i32 %b
 }
 
 ; CHECK-LABEL: ult_f64:
-; CHECK-NEXT: .param f64, f64{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype ult_f64 (f64, f64) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: f64.ge $push[[NUM0:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: i32.const $push[[C0:[0-9]+]]=, 1
 ; CHECK-NEXT: i32.xor $push[[NUM2:[0-9]+]]=, $pop[[NUM0]], $pop[[C0]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM2]]{{$}}
 define i32 @ult_f64(double %x, double %y) {
   %a = fcmp ult double %x, %y
   %b = zext i1 %a to i32
   ret i32 %b
 }
 
 ; CHECK-LABEL: ule_f64:
-; CHECK-NEXT: .param f64, f64{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype ule_f64 (f64, f64) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: f64.gt $push[[NUM0:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: i32.const $push[[C0:[0-9]+]]=, 1
 ; CHECK-NEXT: i32.xor $push[[NUM2:[0-9]+]]=, $pop[[NUM0]], $pop[[C0]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM2]]{{$}}
 define i32 @ule_f64(double %x, double %y) {
   %a = fcmp ule double %x, %y
   %b = zext i1 %a to i32
   ret i32 %b
 }
 
 ; CHECK-LABEL: ugt_f64:
-; CHECK-NEXT: .param f64, f64{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype ugt_f64 (f64, f64) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: f64.le $push[[NUM0:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: i32.const $push[[C0:[0-9]+]]=, 1
 ; CHECK-NEXT: i32.xor $push[[NUM2:[0-9]+]]=, $pop[[NUM0]], $pop[[C0]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM2]]{{$}}
 define i32 @ugt_f64(double %x, double %y) {
   %a = fcmp ugt double %x, %y
   %b = zext i1 %a to i32
   ret i32 %b
 }
 
 ; CHECK-LABEL: uge_f64:
-; CHECK-NEXT: .param f64, f64{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype uge_f64 (f64, f64) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: f64.lt $push[[NUM0:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: i32.const $push[[C0:[0-9]+]]=, 1
 ; CHECK-NEXT: i32.xor $push[[NUM2:[0-9]+]]=, $pop[[NUM0]], $pop[[C0]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM2]]{{$}}
 define i32 @uge_f64(double %x, double %y) {
   %a = fcmp uge double %x, %y
   %b = zext i1 %a to i32
   ret i32 %b
 }

test/CodeGen/WebAssembly/comparisons-i32.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -fast-isel -fast-isel-abort=1 | FileCheck %s
 
 ; Test that basic 32-bit integer comparison operations assemble as expected.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: eq_i32:
-; CHECK-NEXT: .param i32, i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype eq_i32 (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i32.eq $push[[NUM:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i32 @eq_i32(i32 %x, i32 %y) {
   %a = icmp eq i32 %x, %y
   %b = zext i1 %a to i32
   ret i32 %b

test/CodeGen/WebAssembly/comparisons-i64.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -fast-isel -fast-isel-abort=1 | FileCheck %s
 
 ; Test that basic 64-bit integer comparison operations assemble as expected.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: eq_i64:
-; CHECK-NEXT: .param i64, i64{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype eq_i64 (i64, i64) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i64.eq $push[[NUM:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i32 @eq_i64(i64 %x, i64 %y) {
   %a = icmp eq i64 %x, %y
   %b = zext i1 %a to i32
   ret i32 %b

test/CodeGen/WebAssembly/conv-trap.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=-nontrapping-fptoint | FileCheck %s
 
 ; Test that basic conversion operations assemble as expected using
 ; the trapping opcodes and explicit code to suppress the trapping.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: i32_trunc_s_f32:
-; CHECK-NEXT: .param f32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype i32_trunc_s_f32 (f32) -> (i32){{$}}
 ; CHECK-NEXT: block
 ; CHECK-NEXT: f32.abs $push[[ABS:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: f32.const $push[[LIMIT:[0-9]+]]=, 0x1p31{{$}}
 ; CHECK-NEXT: f32.lt $push[[LT:[0-9]+]]=, $pop[[ABS]], $pop[[LIMIT]]{{$}}
 ; CHECK-NEXT: br_if 0, $pop[[LT]]{{$}}
 ; CHECK-NEXT: i32.const $push[[ALT:[0-9]+]]=, -2147483648{{$}}
 ; CHECK-NEXT: return $pop[[ALT]]{{$}}
 ; CHECK-NEXT: BB
 ; CHECK-NEXT: end_block
 ; CHECK-NEXT: i32.trunc_s/f32 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i32 @i32_trunc_s_f32(float %x) {
   %a = fptosi float %x to i32
   ret i32 %a
 }
 
 ; CHECK-LABEL: i32_trunc_u_f32:
-; CHECK-NEXT: .param f32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype i32_trunc_u_f32 (f32) -> (i32){{$}}
 ; CHECK-NEXT: block
 ; CHECK-NEXT: f32.const $push[[LIMIT:[0-9]+]]=, 0x1p32{{$}}
 ; CHECK-NEXT: f32.lt $push[[LT:[0-9]+]]=, $0, $pop[[LIMIT]]{{$}}
 ; CHECK-NEXT: f32.const $push[[ZERO:[0-9]+]]=, 0x0p0{{$}}
 ; CHECK-NEXT: f32.ge $push[[GE:[0-9]+]]=, $0, $pop[[ZERO]]{{$}}
 ; CHECK-NEXT: i32.and $push[[AND:[0-9]+]]=, $pop[[LT]], $pop[[GE]]{{$}}
 ; CHECK-NEXT: br_if 0, $pop[[AND]]{{$}}
 ; CHECK-NEXT: i32.const $push[[ALT:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: return $pop[[ALT]]{{$}}
 ; CHECK-NEXT: BB
 ; CHECK-NEXT: end_block
 ; CHECK-NEXT: i32.trunc_u/f32 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i32 @i32_trunc_u_f32(float %x) {
   %a = fptoui float %x to i32
   ret i32 %a
 }
 
 ; CHECK-LABEL: i32_trunc_s_f64:
-; CHECK-NEXT: .param f64{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype i32_trunc_s_f64 (f64) -> (i32){{$}}
 ; CHECK-NEXT: block
 ; CHECK-NEXT: f64.abs $push[[ABS:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: f64.const $push[[LIMIT:[0-9]+]]=, 0x1p31{{$}}
 ; CHECK-NEXT: f64.lt $push[[LT:[0-9]+]]=, $pop[[ABS]], $pop[[LIMIT]]{{$}}
 ; CHECK-NEXT: br_if 0, $pop[[LT]]{{$}}
 ; CHECK-NEXT: i32.const $push[[ALT:[0-9]+]]=, -2147483648{{$}}
 ; CHECK-NEXT: return $pop[[ALT]]{{$}}
 ; CHECK-NEXT: BB
 ; CHECK-NEXT: end_block
 ; CHECK-NEXT: i32.trunc_s/f64 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i32 @i32_trunc_s_f64(double %x) {
   %a = fptosi double %x to i32
   ret i32 %a
 }
 
 ; CHECK-LABEL: i32_trunc_u_f64:
-; CHECK-NEXT: .param f64{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype i32_trunc_u_f64 (f64) -> (i32){{$}}
 ; CHECK-NEXT: block
 ; CHECK-NEXT: f64.const $push[[LIMIT:[0-9]+]]=, 0x1p32{{$}}
 ; CHECK-NEXT: f64.lt $push[[LT:[0-9]+]]=, $0, $pop[[LIMIT]]{{$}}
 ; CHECK-NEXT: f64.const $push[[ZERO:[0-9]+]]=, 0x0p0{{$}}
 ; CHECK-NEXT: f64.ge $push[[GE:[0-9]+]]=, $0, $pop[[ZERO]]{{$}}
 ; CHECK-NEXT: i32.and $push[[AND:[0-9]+]]=, $pop[[LT]], $pop[[GE]]{{$}}
 ; CHECK-NEXT: br_if 0, $pop[[AND]]{{$}}
 ; CHECK-NEXT: i32.const $push[[ALT:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: return $pop[[ALT]]{{$}}
 ; CHECK-NEXT: BB
 ; CHECK-NEXT: end_block
 ; CHECK-NEXT: i32.trunc_u/f64 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i32 @i32_trunc_u_f64(double %x) {
   %a = fptoui double %x to i32
   ret i32 %a
 }
 
 ; CHECK-LABEL: i64_trunc_s_f32:
-; CHECK-NEXT: .param f32{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype i64_trunc_s_f32 (f32) -> (i64){{$}}
 ; CHECK-NEXT: block
 ; CHECK-NEXT: f32.abs $push[[ABS:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: f32.const $push[[LIMIT:[0-9]+]]=, 0x1p63{{$}}
 ; CHECK-NEXT: f32.lt $push[[LT:[0-9]+]]=, $pop[[ABS]], $pop[[LIMIT]]{{$}}
 ; CHECK-NEXT: br_if 0, $pop[[LT]]{{$}}
 ; CHECK-NEXT: i64.const $push[[ALT:[0-9]+]]=, -9223372036854775808{{$}}
 ; CHECK-NEXT: return $pop[[ALT]]{{$}}
 ; CHECK-NEXT: BB
 ; CHECK-NEXT: end_block
 ; CHECK-NEXT: i64.trunc_s/f32 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @i64_trunc_s_f32(float %x) {
   %a = fptosi float %x to i64
   ret i64 %a
 }
 
 ; CHECK-LABEL: i64_trunc_u_f32:
-; CHECK-NEXT: .param f32{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype i64_trunc_u_f32 (f32) -> (i64){{$}}
 ; CHECK-NEXT: block
 ; CHECK-NEXT: f32.const $push[[LIMIT:[0-9]+]]=, 0x1p64{{$}}
 ; CHECK-NEXT: f32.lt $push[[LT:[0-9]+]]=, $0, $pop[[LIMIT]]{{$}}
 ; CHECK-NEXT: f32.const $push[[ZERO:[0-9]+]]=, 0x0p0{{$}}
 ; CHECK-NEXT: f32.ge $push[[GE:[0-9]+]]=, $0, $pop[[ZERO]]{{$}}
 ; CHECK-NEXT: i32.and $push[[AND:[0-9]+]]=, $pop[[LT]], $pop[[GE]]{{$}}
 ; CHECK-NEXT: br_if 0, $pop[[AND]]{{$}}
 ; CHECK-NEXT: i64.const $push[[ALT:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: return $pop[[ALT]]{{$}}
 ; CHECK-NEXT: BB
 ; CHECK-NEXT: end_block
 ; CHECK-NEXT: i64.trunc_u/f32 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @i64_trunc_u_f32(float %x) {
   %a = fptoui float %x to i64
   ret i64 %a
 }
 
 ; CHECK-LABEL: i64_trunc_s_f64:
-; CHECK-NEXT: .param f64{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype i64_trunc_s_f64 (f64) -> (i64){{$}}
 ; CHECK-NEXT: block
 ; CHECK-NEXT: f64.abs $push[[ABS:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: f64.const $push[[LIMIT:[0-9]+]]=, 0x1p63{{$}}
 ; CHECK-NEXT: f64.lt $push[[LT:[0-9]+]]=, $pop[[ABS]], $pop[[LIMIT]]{{$}}
 ; CHECK-NEXT: br_if 0, $pop[[LT]]{{$}}
 ; CHECK-NEXT: i64.const $push[[ALT:[0-9]+]]=, -9223372036854775808{{$}}
 ; CHECK-NEXT: return $pop[[ALT]]{{$}}
 ; CHECK-NEXT: BB
 ; CHECK-NEXT: end_block
 ; CHECK-NEXT: i64.trunc_s/f64 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @i64_trunc_s_f64(double %x) {
   %a = fptosi double %x to i64
   ret i64 %a
 }
 
 ; CHECK-LABEL: i64_trunc_u_f64:
-; CHECK-NEXT: .param f64{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype i64_trunc_u_f64 (f64) -> (i64){{$}}
 ; CHECK-NEXT: block
 ; CHECK-NEXT: f64.const $push[[LIMIT:[0-9]+]]=, 0x1p64{{$}}
 ; CHECK-NEXT: f64.lt $push[[LT:[0-9]+]]=, $0, $pop[[LIMIT]]{{$}}
 ; CHECK-NEXT: f64.const $push[[ZERO:[0-9]+]]=, 0x0p0{{$}}
 ; CHECK-NEXT: f64.ge $push[[GE:[0-9]+]]=, $0, $pop[[ZERO]]{{$}}
 ; CHECK-NEXT: i32.and $push[[AND:[0-9]+]]=, $pop[[LT]], $pop[[GE]]{{$}}
 ; CHECK-NEXT: br_if 0, $pop[[AND]]{{$}}
 ; CHECK-NEXT: i64.const $push[[ALT:[0-9]+]]=, 0{{$}}

test/CodeGen/WebAssembly/conv.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+nontrapping-fptoint | FileCheck %s
 
 ; Test that basic conversion operations assemble as expected.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: i32_wrap_i64:
-; CHECK-NEXT: .param i64{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype i32_wrap_i64 (i64) -> (i32){{$}}
 ; CHECK-NEXT: i32.wrap/i64 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i32 @i32_wrap_i64(i64 %x) {
   %a = trunc i64 %x to i32
   ret i32 %a
 }
 
 ; CHECK-LABEL: i64_extend_s_i32:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype i64_extend_s_i32 (i32) -> (i64){{$}}
 ; CHECK-NEXT: i64.extend_s/i32 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @i64_extend_s_i32(i32 %x) {
   %a = sext i32 %x to i64
   ret i64 %a
 }
 
 ; CHECK-LABEL: i64_extend_u_i32:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype i64_extend_u_i32 (i32) -> (i64){{$}}
 ; CHECK-NEXT: i64.extend_u/i32 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @i64_extend_u_i32(i32 %x) {
   %a = zext i32 %x to i64
   ret i64 %a
 }
 
 ; CHECK-LABEL: i32_trunc_s_f32:
-; CHECK-NEXT: .param f32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype i32_trunc_s_f32 (f32) -> (i32){{$}}
 ; CHECK-NEXT: i32.trunc_s:sat/f32 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i32 @i32_trunc_s_f32(float %x) {
   %a = fptosi float %x to i32
   ret i32 %a
 }
 
 ; CHECK-LABEL: i32_trunc_sat_s_f32:
-; CHECK-NEXT: .param f32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype i32_trunc_sat_s_f32 (f32) -> (i32){{$}}
 ; CHECK-NEXT: i32.trunc_s:sat/f32 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 declare i32 @llvm.wasm.trunc.saturate.signed.i32.f32(float)
 define i32 @i32_trunc_sat_s_f32(float %x) {
   %a = call i32 @llvm.wasm.trunc.saturate.signed.i32.f32(float %x)
   ret i32 %a
 }
 
 ; CHECK-LABEL: i32_trunc_u_f32:
-; CHECK-NEXT: .param f32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype i32_trunc_u_f32 (f32) -> (i32){{$}}
 ; CHECK-NEXT: i32.trunc_u:sat/f32 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i32 @i32_trunc_u_f32(float %x) {
   %a = fptoui float %x to i32
   ret i32 %a
 }
 
 ; CHECK-LABEL: i32_trunc_sat_u_f32:
-; CHECK-NEXT: .param f32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype i32_trunc_sat_u_f32 (f32) -> (i32){{$}}
 ; CHECK-NEXT: i32.trunc_u:sat/f32 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 declare i32 @llvm.wasm.trunc.saturate.unsigned.i32.f32(float)
 define i32 @i32_trunc_sat_u_f32(float %x) {
   %a = call i32 @llvm.wasm.trunc.saturate.unsigned.i32.f32(float %x)
   ret i32 %a
 }
 
 ; CHECK-LABEL: i32_trunc_s_f64:
-; CHECK-NEXT: .param f64{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype i32_trunc_s_f64 (f64) -> (i32){{$}}
 ; CHECK-NEXT: i32.trunc_s:sat/f64 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i32 @i32_trunc_s_f64(double %x) {
   %a = fptosi double %x to i32
   ret i32 %a
 }
 
 ; CHECK-LABEL: i32_trunc_sat_s_f64:
-; CHECK-NEXT: .param f64{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype i32_trunc_sat_s_f64 (f64) -> (i32){{$}}
 ; CHECK-NEXT: i32.trunc_s:sat/f64 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 declare i32 @llvm.wasm.trunc.saturate.signed.i32.f64(double)
 define i32 @i32_trunc_sat_s_f64(double %x) {
   %a = call i32 @llvm.wasm.trunc.saturate.signed.i32.f64(double %x)
   ret i32 %a
 }
 
 ; CHECK-LABEL: i32_trunc_u_f64:
-; CHECK-NEXT: .param f64{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype i32_trunc_u_f64 (f64) -> (i32){{$}}
 ; CHECK-NEXT: i32.trunc_u:sat/f64 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i32 @i32_trunc_u_f64(double %x) {
   %a = fptoui double %x to i32
   ret i32 %a
 }
 
 ; CHECK-LABEL: i32_trunc_sat_u_f64:
-; CHECK-NEXT: .param f64{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype i32_trunc_sat_u_f64 (f64) -> (i32){{$}}
 ; CHECK-NEXT: i32.trunc_u:sat/f64 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 declare i32 @llvm.wasm.trunc.saturate.unsigned.i32.f64(double)
 define i32 @i32_trunc_sat_u_f64(double %x) {
   %a = call i32 @llvm.wasm.trunc.saturate.unsigned.i32.f64(double %x)
   ret i32 %a
 }
 
 ; CHECK-LABEL: i64_trunc_s_f32:
-; CHECK-NEXT: .param f32{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype i64_trunc_s_f32 (f32) -> (i64){{$}}
 ; CHECK-NEXT: i64.trunc_s:sat/f32 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @i64_trunc_s_f32(float %x) {
   %a = fptosi float %x to i64
   ret i64 %a
 }
 
 ; CHECK-LABEL: i64_trunc_sat_s_f32:
-; CHECK-NEXT: .param f32{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype i64_trunc_sat_s_f32 (f32) -> (i64){{$}}
 ; CHECK-NEXT: i64.trunc_s:sat/f32 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 declare i64 @llvm.wasm.trunc.saturate.signed.i64.f32(float)
 define i64 @i64_trunc_sat_s_f32(float %x) {
   %a = call i64 @llvm.wasm.trunc.saturate.signed.i64.f32(float %x)
   ret i64 %a
 }
 
 ; CHECK-LABEL: i64_trunc_u_f32:
-; CHECK-NEXT: .param f32{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype i64_trunc_u_f32 (f32) -> (i64){{$}}
 ; CHECK-NEXT: i64.trunc_u:sat/f32 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @i64_trunc_u_f32(float %x) {
   %a = fptoui float %x to i64
   ret i64 %a
 }
 
 ; CHECK-LABEL: i64_trunc_sat_u_f32:
-; CHECK-NEXT: .param f32{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype i64_trunc_sat_u_f32 (f32) -> (i64){{$}}
 ; CHECK-NEXT: i64.trunc_u:sat/f32 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 declare i64 @llvm.wasm.trunc.saturate.unsigned.i64.f32(float)
 define i64 @i64_trunc_sat_u_f32(float %x) {
   %a = call i64 @llvm.wasm.trunc.saturate.unsigned.i64.f32(float %x)
   ret i64 %a
 }
 
 ; CHECK-LABEL: i64_trunc_s_f64:
-; CHECK-NEXT: .param f64{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype i64_trunc_s_f64 (f64) -> (i64){{$}}
 ; CHECK-NEXT: i64.trunc_s:sat/f64 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @i64_trunc_s_f64(double %x) {
   %a = fptosi double %x to i64
   ret i64 %a
 }
 
 ; CHECK-LABEL: i64_trunc_sat_s_f64:
-; CHECK-NEXT: .param f64{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype i64_trunc_sat_s_f64 (f64) -> (i64){{$}}
 ; CHECK-NEXT: i64.trunc_s:sat/f64 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 declare i64 @llvm.wasm.trunc.saturate.signed.i64.f64(double)
 define i64 @i64_trunc_sat_s_f64(double %x) {
   %a = call i64 @llvm.wasm.trunc.saturate.signed.i64.f64(double %x)
   ret i64 %a
 }
 
 ; CHECK-LABEL: i64_trunc_u_f64:
-; CHECK-NEXT: .param f64{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype i64_trunc_u_f64 (f64) -> (i64){{$}}
 ; CHECK-NEXT: i64.trunc_u:sat/f64 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @i64_trunc_u_f64(double %x) {
   %a = fptoui double %x to i64
   ret i64 %a
 }
 
 ; CHECK-LABEL: i64_trunc_sat_u_f64:
-; CHECK-NEXT: .param f64{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype i64_trunc_sat_u_f64 (f64) -> (i64){{$}}
 ; CHECK-NEXT: i64.trunc_u:sat/f64 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 declare i64 @llvm.wasm.trunc.saturate.unsigned.i64.f64(double)
 define i64 @i64_trunc_sat_u_f64(double %x) {
   %a = call i64 @llvm.wasm.trunc.saturate.unsigned.i64.f64(double %x)
   ret i64 %a
 }
 
 ; CHECK-LABEL: f32_convert_s_i32:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result f32{{$}}
+; CHECK-NEXT: .functype f32_convert_s_i32 (i32) -> (f32){{$}}
 ; CHECK-NEXT: f32.convert_s/i32 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define float @f32_convert_s_i32(i32 %x) {
   %a = sitofp i32 %x to float
   ret float %a
 }
 
 ; CHECK-LABEL: f32_convert_u_i32:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result f32{{$}}
+; CHECK-NEXT: .functype f32_convert_u_i32 (i32) -> (f32){{$}}
 ; CHECK-NEXT: f32.convert_u/i32 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define float @f32_convert_u_i32(i32 %x) {
   %a = uitofp i32 %x to float
   ret float %a
 }
 
 ; CHECK-LABEL: f64_convert_s_i32:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result f64{{$}}
+; CHECK-NEXT: .functype f64_convert_s_i32 (i32) -> (f64){{$}}
 ; CHECK-NEXT: f64.convert_s/i32 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define double @f64_convert_s_i32(i32 %x) {
   %a = sitofp i32 %x to double
   ret double %a
 }
 
 ; CHECK-LABEL: f64_convert_u_i32:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result f64{{$}}
+; CHECK-NEXT: .functype f64_convert_u_i32 (i32) -> (f64){{$}}
 ; CHECK-NEXT: f64.convert_u/i32 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define double @f64_convert_u_i32(i32 %x) {
   %a = uitofp i32 %x to double
   ret double %a
 }
 
 ; CHECK-LABEL: f32_convert_s_i64:
-; CHECK-NEXT: .param i64{{$}}
-; CHECK-NEXT: .result f32{{$}}
+; CHECK-NEXT: .functype f32_convert_s_i64 (i64) -> (f32){{$}}
 ; CHECK-NEXT: f32.convert_s/i64 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define float @f32_convert_s_i64(i64 %x) {
   %a = sitofp i64 %x to float
   ret float %a
 }
 
 ; CHECK-LABEL: f32_convert_u_i64:
-; CHECK-NEXT: .param i64{{$}}
-; CHECK-NEXT: .result f32{{$}}
+; CHECK-NEXT: .functype f32_convert_u_i64 (i64) -> (f32){{$}}
 ; CHECK-NEXT: f32.convert_u/i64 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define float @f32_convert_u_i64(i64 %x) {
   %a = uitofp i64 %x to float
   ret float %a
 }
 
 ; CHECK-LABEL: f64_convert_s_i64:
-; CHECK-NEXT: .param i64{{$}}
-; CHECK-NEXT: .result f64{{$}}
+; CHECK-NEXT: .functype f64_convert_s_i64 (i64) -> (f64){{$}}
 ; CHECK-NEXT: f64.convert_s/i64 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define double @f64_convert_s_i64(i64 %x) {
   %a = sitofp i64 %x to double
   ret double %a
 }
 
 ; CHECK-LABEL: f64_convert_u_i64:
-; CHECK-NEXT: .param i64{{$}}
-; CHECK-NEXT: .result f64{{$}}
+; CHECK-NEXT: .functype f64_convert_u_i64 (i64) -> (f64){{$}}
 ; CHECK-NEXT: f64.convert_u/i64 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define double @f64_convert_u_i64(i64 %x) {
   %a = uitofp i64 %x to double
   ret double %a
 }
 
 ; CHECK-LABEL: f64_promote_f32:
-; CHECK-NEXT: .param f32{{$}}
-; CHECK-NEXT: .result f64{{$}}
+; CHECK-NEXT: .functype f64_promote_f32 (f32) -> (f64){{$}}
 ; CHECK-NEXT: f64.promote/f32 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define double @f64_promote_f32(float %x) {
   %a = fpext float %x to double
   ret double %a
 }
 
 ; CHECK-LABEL: f32_demote_f64:
-; CHECK-NEXT: .param f64{{$}}
-; CHECK-NEXT: .result f32{{$}}
+; CHECK-NEXT: .functype f32_demote_f64 (f64) -> (f32){{$}}
 ; CHECK-NEXT: f32.demote/f64 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define float @f32_demote_f64(double %x) {
   %a = fptrunc double %x to float
   ret float %a
 }
 
 ; If the high its are unused, LLVM will optimize sext/zext into anyext, which

test/CodeGen/WebAssembly/dead-vreg.ll

 ; RUN: llc < %s -asm-verbose=false -verify-machineinstrs | FileCheck %s
 
 ; Check that unused vregs aren't assigned registers.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 define void @foo(i32* nocapture %a, i32 %w, i32 %h) {
 ; CHECK-LABEL: foo:
-; CHECK-NEXT: .param i32, i32, i32{{$}}
+; CHECK-NEXT: .functype foo (i32, i32, i32) -> (){{$}}
 ; CHECK-NEXT: .local i32, i32, i32, i32, i32, i32{{$}}
 entry:
   %cmp.19 = icmp sgt i32 %h, 0
   br i1 %cmp.19, label %for.cond.1.preheader.lr.ph, label %for.end.7
 
 for.cond.1.preheader.lr.ph:
   %cmp2.17 = icmp sgt i32 %w, 0
   br label %for.cond.1.preheader

test/CodeGen/WebAssembly/exception.ll

 ; RUN: not llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -exception-model=wasm
 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -exception-model=wasm -mattr=+exception-handling | FileCheck -allow-deprecated-dag-overlap %s
 ; RUN: llc < %s -disable-wasm-fallthrough-return-opt -wasm-keep-registers -exception-model=wasm -mattr=+exception-handling
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 %struct.Cleanup = type { i8 }
 
 @_ZTIi = external constant i8*
 
 declare void @llvm.wasm.throw(i32, i8*)
 
 ; CHECK-LABEL: test_throw:
-; CHECK-NEXT: i32.const $push0=, 0
+; CHECK:      i32.const $push0=, 0
 ; CHECK-NEXT: throw 0, $pop0
 define void @test_throw() {
   call void @llvm.wasm.throw(i32 0, i8* null)
   ret void
 }
 
 ; CHECK-LABEL: test_catch_rethrow:
 ; CHECK:   get_global  $push{{.+}}=, __stack_pointer@GLOBAL

test/CodeGen/WebAssembly/f16.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -fast-isel | FileCheck %s
 
 ; Test that f16 is expanded.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: demote:
-; CHECK-NEXT: .param    f32{{$}}
-; CHECK-NEXT: .result   f32{{$}}
+; CHECK-NEXT: .functype demote (f32) -> (f32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i32.call  $push[[L1:[0-9]+]]=, __gnu_f2h_ieee@FUNCTION, $pop[[L0]]{{$}}
 ; CHECK-NEXT: f32.call  $push[[L2:[0-9]+]]=, __gnu_h2f_ieee@FUNCTION, $pop[[L1]]{{$}}
 ; CHECK-NEXT: return    $pop[[L2]]{{$}}
 define half @demote(float %f) {
     %t = fptrunc float %f to half
     ret half %t
 }
 
 ; CHECK-LABEL: promote:
-; CHECK-NEXT: .param    f32{{$}}
-; CHECK-NEXT: .result   f32{{$}}
+; CHECK-NEXT: .functype promote (f32) -> (f32){{$}}
 ; CHECK-NEXT: get_local $push0=, 0{{$}}
 ; CHECK-NEXT: return    $pop0{{$}}
 define float @promote(half %f) {
     %t = fpext half %f to float
     ret float %t
 }

test/CodeGen/WebAssembly/f32.ll

 declare float @llvm.ceil.f32(float)
 declare float @llvm.floor.f32(float)
 declare float @llvm.trunc.f32(float)
 declare float @llvm.nearbyint.f32(float)
 declare float @llvm.rint.f32(float)
 declare float @llvm.fma.f32(float, float, float)
 
 ; CHECK-LABEL: fadd32:
-; CHECK-NEXT: .param f32, f32{{$}}
-; CHECK-NEXT: .result f32{{$}}
+; CHECK-NEXT: .functype fadd32 (f32, f32) -> (f32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: f32.add $push[[LR:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: return $pop[[LR]]{{$}}
 define float @fadd32(float %x, float %y) {
   %a = fadd float %x, %y
   ret float %a
 }

test/CodeGen/WebAssembly/f64.ll

 declare double @llvm.ceil.f64(double)
 declare double @llvm.floor.f64(double)
 declare double @llvm.trunc.f64(double)
 declare double @llvm.nearbyint.f64(double)
 declare double @llvm.rint.f64(double)
 declare double @llvm.fma.f64(double, double, double)
 
 ; CHECK-LABEL: fadd64:
-; CHECK-NEXT: .param f64, f64{{$}}
-; CHECK-NEXT: .result f64{{$}}
+; CHECK-NEXT: .functype fadd64 (f64, f64) -> (f64){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: f64.add $push[[LR:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: return $pop[[LR]]{{$}}
 define double @fadd64(double %x, double %y) {
   %a = fadd double %x, %y
   ret double %a
 }

test/CodeGen/WebAssembly/fast-isel-i24.ll

 ; RUN: llc < %s -O0 -wasm-keep-registers
 ; PR36564
 ; PR37546
 
 ; Test that fast-isel properly copes with i24 arguments and return types.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: add:
-; CHECK-NEXT: .param    i32, i32{{$}}
-; CHECK-NEXT: .result   i32{{$}}
+; CHECK-NEXT: .functype add (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push2=, 0{{$}}
 ; CHECK-NEXT: get_local $push1=, 1{{$}}
 ; CHECK-NEXT: i32.add   $push0=, $pop2, $pop1{{$}}
 ; CHECK-NEXT: end_function
 define i24 @add(i24 %x, i24 %y) {
     %z = add i24 %x, %y
     ret i24 %z
 }
 
 ; CHECK-LABEL: return_zero:
-; CHECK-NEXT: .result   i32{{$}}
+; CHECK-NEXT: .functype return_zero () -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, 0{{$}}
 ; CHECK-NEXT: end_function
 define i24 @return_zero() {
     ret i24 0
 }

test/CodeGen/WebAssembly/fast-isel-i256.ll

 ; RUN: llc < %s -O0 -wasm-keep-registers
 ; PR36564
 ; PR37546
 
 ; Test that fast-isel properly copes with i256 arguments and return types.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: add:
-; CHECK-NEXT: .param      i32, i64, i64, i64, i64, i64, i64, i64, i64{{$}}
+; CHECK-NEXT: .functype add (i32, i64, i64, i64, i64, i64, i64, i64, i64) -> (){{$}}
 ; CHECK-NOT:  .result
 ; CHECK: end_function
 define i256 @add(i256 %x, i256 %y) {
     %z = add i256 %x, %y
     ret i256 %z
 }
 
 ; CHECK-LABEL: return_zero:
-; CHECK-NEXT: .param      i32{{$}}
-; CHECK-NOT: .result
+; CHECK-NEXT: .functype return_zero (i32) -> (){{$}}
 ; CHECK: end_function
 define i256 @return_zero() {
     ret i256 0
 }
 
 ; CHECK-LABEL: return_zero_with_params:
-; CHECK-NEXT: .param      i32, f32{{$}}
-; CHECK-NOT: .result
+; CHECK-NEXT: .functype return_zero_with_params (i32, f32) -> (){{$}}
 ; CHECK: end_function
 define i256 @return_zero_with_params(float %x) {
     ret i256 0
 }

test/CodeGen/WebAssembly/frem.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
 
 ; Test that the frem instruction works.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: frem32:
-; CHECK-NEXT: .param f32, f32{{$}}
-; CHECK-NEXT: .result f32{{$}}
+; CHECK-NEXT: .functype frem32 (f32, f32) -> (f32){{$}}
 ; CHECK-NEXT: {{^}} f32.call $push0=, fmodf@FUNCTION, $0, $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define float @frem32(float %x, float %y) {
   %a = frem float %x, %y
   ret float %a
 }
 
 ; CHECK-LABEL: frem64:
-; CHECK-NEXT: .param f64, f64{{$}}
-; CHECK-NEXT: .result f64{{$}}
+; CHECK-NEXT: .functype frem64 (f64, f64) -> (f64){{$}}
 ; CHECK-NEXT: {{^}} f64.call $push0=, fmod@FUNCTION, $0, $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define double @frem64(double %x, double %y) {
   %a = frem double %x, %y
   ret double %a
 }

test/CodeGen/WebAssembly/func.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
 
 ; Test that basic functions assemble as expected.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: f0:
 ; CHECK: return{{$}}
 ; CHECK: end_function{{$}}
 ; CHECK: .size f0,
 define void @f0() {
   ret void
 }
 
 ; CHECK-LABEL: f1:
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype f1 () -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push[[NUM:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 ; CHECK: .size f1,
 define i32 @f1() {
   ret i32 0
 }
 
 ; CHECK-LABEL: f2:
-; CHECK-NEXT: .param i32, f32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype f2 (i32, f32) -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push[[NUM:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 ; CHECK: .size f2,
 define i32 @f2(i32 %p1, float %p2) {
   ret i32 0
 }
 
 ; CHECK-LABEL: f3:
-; CHECK-NEXT: .param i32, f32{{$}}
+; CHECK-NEXT: .functype f3 (i32, f32) -> (){{$}}
 ; CHECK-NOT: local
 ; CHECK-NEXT: return{{$}}
 ; CHECK: .size f3,
 define void @f3(i32 %p1, float %p2) {
   ret void
 }
 
 ; CHECK-LABEL: f4:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype f4 (i32) -> (i32){{$}}
 ; CHECK-NOT: local
 ; CHECK: .size f4,
 define i32 @f4(i32 %x) {
 entry:
    %c = trunc i32 %x to i1
    br i1 %c, label %true, label %false
 true:
    ret i32 0
 false:
    ret i32 1
 }
 
 ; CHECK-LABEL: f5:
-; CHECK-NEXT: .result f32{{$}}
+; CHECK-NEXT: .functype f5 () -> (f32){{$}}
 ; CHECK-NEXT: unreachable
 define float @f5()  {
  unreachable
 }

test/CodeGen/WebAssembly/function-bitcasts-varargs.ll

 
 ; CHECK: callWithArgs:
 ; CHECK: i32.const  $push1=, 0
 ; CHECK-NEXT: i32.const $push0=, 1
 ; CHECK-NEXT: call      .Lunderspecified_bitcast@FUNCTION, $pop1, $pop0
 ; CHECK: call     .Lspecified_bitcast@FUNCTION, $pop{{[0-9]+$}}
 
 ; CHECK: .Lunderspecified_bitcast:
-; CHECK-NEXT: .param    i32, i32{{$}}
+; CHECK-NEXT: .functype .Lunderspecified_bitcast (i32, i32) -> (){{$}}
 ; CHECK: call     underspecified@FUNCTION, $pop{{[0-9]+$}}
 
 ; CHECK: .Lspecified_bitcast:
-; CHECK-NEXT: .param    i32{{$}}
+; CHECK-NEXT: .functype .Lspecified_bitcast (i32) -> (){{$}}
 ; CHECK: call     specified@FUNCTION, $pop{{[0-9]+}}, $pop{{[0-9]+$}}

test/CodeGen/WebAssembly/function-bitcasts.ll

 declare void @plain(i32)
 
 declare void @foo0()
 declare void @foo1()
 declare void @foo2()
 declare void @foo3()
 
 ; CHECK-LABEL: test:
-; CHECK-NEXT: call        .Lhas_i32_arg_bitcast.2@FUNCTION{{$}}
+; CHECK:      call        .Lhas_i32_arg_bitcast.2@FUNCTION{{$}}
 ; CHECK-NEXT: call        .Lhas_i32_arg_bitcast.2@FUNCTION{{$}}
 ; CHECK-NEXT: call        .Lhas_i32_ret_bitcast@FUNCTION{{$}}
 ; CHECK-NEXT: i32.call     $drop=, has_i32_ret@FUNCTION
 ; CHECK-NEXT: i32.const   $push[[L0:[0-9]+]]=, 0
 ; CHECK-NEXT: call        .Lfoo0_bitcast@FUNCTION, $pop[[L0]]{{$}}
 ; CHECK-NEXT: i32.const   $push[[L1:[0-9]+]]=, 0
 ; CHECK-NEXT: call        .Lfoo0_bitcast@FUNCTION, $pop[[L1]]{{$}}
 ; CHECK-NEXT: i32.const   $push[[L2:[0-9]+]]=, 0
define void @test_varargs() {
   ret void
 }
 
 ; Don't use wrappers when the value is stored in memory
 
 @global_func = hidden local_unnamed_addr global void ()* null
 
 ; CHECK-LABEL: test_store:
-; CHECK-NEXT: i32.const   $push[[L0:[0-9]+]]=, 0{{$}}
+; CHECK:      i32.const   $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i32.const   $push[[L1:[0-9]+]]=, has_i32_ret@FUNCTION{{$}}
 ; CHECK-NEXT: i32.store   global_func($pop[[L0]]), $pop[[L1]]{{$}}
 define void @test_store() {
   %1 = bitcast i32 ()* @has_i32_ret to void ()*
   store void ()* %1, void ()** @global_func
   ret void
 }
 
 ; CHECK-LABEL: test_load:
-; CHECK-NEXT: result      i32{{$}}
+; CHECK-NEXT: .functype test_load () -> (i32){{$}}
 ; CHECK-NEXT: i32.const   $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i32.load    $push[[L1:[0-9]+]]=, global_func($pop[[L0]]){{$}}
 ; CHECK-NEXT: i32.call_indirect $push{{[0-9]+}}=, $pop[[L1]]{{$}}
 define i32 @test_load() {
   %1 = load i32 ()*, i32 ()** bitcast (void ()** @global_func to i32 ()**)
   %2 = call i32 %1()
   ret i32 %2
 }
 
 ; Don't use wrappers when the value is passed to a function call
 
 declare void @call_func(i32 ()*)
 
 ; CHECK-LABEL: test_argument:
-; CHECK-NEXT: i32.const   $push[[L0:[0-9]+]]=, has_i32_ret@FUNCTION{{$}}
+; CHECK:      i32.const   $push[[L0:[0-9]+]]=, has_i32_ret@FUNCTION{{$}}
 ; CHECK-NEXT: call        call_func@FUNCTION, $pop[[L0]]{{$}}
 ; CHECK-NEXT: i32.const   $push[[L1:[0-9]+]]=, has_i32_arg@FUNCTION{{$}}
 ; CHECK-NEXT: call        call_func@FUNCTION, $pop[[L1]]{{$}}
 define void @test_argument() {
   call void @call_func(i32 ()* @has_i32_ret)
   call void @call_func(i32 ()* bitcast (void (i32)* @has_i32_arg to i32 ()*))
   ret void
 }
%0 = landingpad { i8*, i32 }
           catch i8* null
   br label %end
 
 end:
   ret void
 }
 
 ; CHECK-LABEL: .Lhas_i32_arg_bitcast:
-; CHECK-NEXT: .param      i32, i32
+; CHECK-NEXT: .functype .Lhas_i32_arg_bitcast (i32, i32) -> ()
 ; CHECK-NEXT: call        has_i32_arg@FUNCTION, $1{{$}}
 ; CHECK-NEXT: end_function
 
 ; CHECK-LABEL: .Lhas_i32_arg_bitcast.1:
-; CHECK-NEXT: .param      i32, i32
+; CHECK-NEXT: .functype .Lhas_i32_arg_bitcast.1 (i32, i32) -> ()
 ; CHECK-NEXT: call        has_i32_arg@FUNCTION, $0{{$}}
 ; CHECK-NEXT: end_function
 
 ; CHECK-LABEL: .Lhas_i32_arg_bitcast.2:
-; CHECK-NEXT: call        has_i32_arg@FUNCTION, $0{{$}}
+; CHECK:      call        has_i32_arg@FUNCTION, $0{{$}}
 ; CHECK-NEXT: end_function
 
 ; CHECK-LABEL: .Lhas_i32_ret_bitcast:
-; CHECK-NEXT: call        $drop=, has_i32_ret@FUNCTION{{$}}
+; CHECK:      call        $drop=, has_i32_ret@FUNCTION{{$}}
 ; CHECK-NEXT: end_function
 
 ; CHECK-LABEL: .Lvararg_bitcast:
 ; CHECK: call        vararg@FUNCTION, $1{{$}}
 ; CHECK: end_function
 
 ; CHECK-LABEL: .Lplain_bitcast:
 ; CHECK: call        plain@FUNCTION, $1{{$}}
 ; CHECK: end_function
 
 ; CHECK-LABEL: .Lfoo0_bitcast:
-; CHECK-NEXT: .param      i32
+; CHECK-NEXT: .functype .Lfoo0_bitcast (i32) -> ()
 ; CHECK-NEXT: call        foo0@FUNCTION{{$}}
 ; CHECK-NEXT: end_function
 
 ; CHECK-LABEL: .Lfoo1_bitcast:
-; CHECK-NEXT: .result     i32
+; CHECK-NEXT: .functype .Lfoo1_bitcast () -> (i32)
 ; CHECK-NEXT: call        foo1@FUNCTION{{$}}
 ; CHECK-NEXT: copy_local  $push0=, $0
 ; CHECK-NEXT: end_function

test/CodeGen/WebAssembly/global.ll

 ; CHECK-NEXT: i32.load $push1=, answer($pop0){{$}}
 ; CHECK-NEXT: return $pop1{{$}}
 define i32 @foo() {
   %a = load i32, i32* @answer
   ret i32 %a
 }
 
 ; CHECK-LABEL: call_memcpy:
-; CHECK-NEXT: .param          i32, i32, i32{{$}}
-; CHECK-NEXT: .result         i32{{$}}
+; CHECK-NEXT: .functype call_memcpy (i32, i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.call        $push0=, memcpy@FUNCTION, $0, $1, $2{{$}}
 ; CHECK-NEXT: return          $pop0{{$}}
 declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i1)
 define i8* @call_memcpy(i8* %p, i8* nocapture readonly %q, i32 %n) {
   tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %p, i8* %q, i32 %n, i1 false)
   ret i8* %p
 }
 

test/CodeGen/WebAssembly/i128-returned.ll

 ; RUN: llc < %s -asm-verbose=false | FileCheck %s
 
 ; Test that the "returned" attribute works with i128 types.
 ; PR36128
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 declare i128 @bar(i128 returned)
 
 define i128 @foo(i128) {
   %r = tail call i128 @bar(i128 %0)
   ret i128 %r
 }
 
 ; CHECK-LABEL: foo:
-; CHECK-NEXT: .param    i32, i64, i64
-; CHECK-NOT:  .result
+; CHECK-NEXT: .functype foo (i32, i64, i64) -> ()
 
-; CHECK: .functype  bar, void, i32, i64, i64
+; CHECK: .functype bar (i32, i64, i64) -> ()

test/CodeGen/WebAssembly/i128.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
 
 ; Test that basic 128-bit integer operations assemble as expected.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 declare i128 @llvm.ctlz.i128(i128, i1)
 declare i128 @llvm.cttz.i128(i128, i1)
 declare i128 @llvm.ctpop.i128(i128)
 
 ; CHECK-LABEL: add128:
-; CHECK-NEXT: .param i32, i64, i64, i64, i64{{$}}
+; CHECK-NEXT: .functype add128 (i32, i64, i64, i64, i64) -> (){{$}}
 ; CHECK-NOT:  .result
 ; CHECK:      i64.add
 ; CHECK:      i64.store
 ; CHECK:      i64.add
 ; CHECK:      i64.store
 ; CHECK-NEXT: return{{$}}
 define i128 @add128(i128 %x, i128 %y) {
   %a = add i128 %x, %y
   ret i128 %a
 }
 
 ; CHECK-LABEL: sub128:
-; CHECK-NEXT: .param i32, i64, i64, i64, i64{{$}}
-; CHECK-NOT: .result
+; CHECK-NEXT: .functype sub128 (i32, i64, i64, i64, i64) -> (){{$}}
 ; CHECK:      i64.sub
 ; CHECK:      i64.store
 ; CHECK:      i64.sub
 ; CHECK:      i64.store
 ; CHECK-NEXT: return{{$}}
 define i128 @sub128(i128 %x, i128 %y) {
   %a = sub i128 %x, %y
   ret i128 %a
 }
 
 ; CHECK-LABEL: mul128:
-; CHECK-NEXT: .param i32, i64, i64, i64, i64{{$}}
-; CHECK-NOT: .result
+; CHECK-NEXT: .functype mul128 (i32, i64, i64, i64, i64) -> (){{$}}
 ; CHECK: call __multi3@FUNCTION, ${{.+}}, ${{.+}}, ${{.+}}, ${{.+}}, ${{.+}}{{$}}
 ; CHECK: return{{$}}
 define i128 @mul128(i128 %x, i128 %y) {
   %a = mul i128 %x, %y
   ret i128 %a
 }
 
 ; CHECK-LABEL: sdiv128:
-; CHECK-NEXT: .param i32, i64, i64, i64, i64{{$}}
-; CHECK-NOT: .result
+; CHECK-NEXT: .functype sdiv128 (i32, i64, i64, i64, i64) -> (){{$}}
 ; CHECK: call __divti3@FUNCTION, ${{.+}}, ${{.+}}, ${{.+}}, ${{.+}}, ${{.+}}{{$}}
 ; CHECK: return{{$}}
 define i128 @sdiv128(i128 %x, i128 %y) {
   %a = sdiv i128 %x, %y
   ret i128 %a
 }
 
 ; CHECK-LABEL: udiv128:
-; CHECK-NEXT: .param i32, i64, i64, i64, i64{{$}}
-; CHECK-NOT: .result
+; CHECK-NEXT: .functype udiv128 (i32, i64, i64, i64, i64) -> (){{$}}
 ; CHECK: call __udivti3@FUNCTION, ${{.+}}, ${{.+}}, ${{.+}}, ${{.+}}, ${{.+}}{{$}}
 ; CHECK: return{{$}}
 define i128 @udiv128(i128 %x, i128 %y) {
   %a = udiv i128 %x, %y
   ret i128 %a
 }
 
 ; CHECK-LABEL: srem128:
-; CHECK-NEXT: .param i32, i64, i64, i64, i64{{$}}
-; CHECK-NOT: .result
+; CHECK-NEXT: .functype srem128 (i32, i64, i64, i64, i64) -> (){{$}}
 ; CHECK: call __modti3@FUNCTION, ${{.+}}, ${{.+}}, ${{.+}}, ${{.+}}, ${{.+}}{{$}}
 ; CHECK: return{{$}}
 define i128 @srem128(i128 %x, i128 %y) {
   %a = srem i128 %x, %y
   ret i128 %a
 }
 
 ; CHECK-LABEL: urem128:
-; CHECK-NEXT: .param i32, i64, i64, i64, i64{{$}}
-; CHECK-NOT: .result
+; CHECK-NEXT: .functype urem128 (i32, i64, i64, i64, i64) -> (){{$}}
 ; CHECK: call __umodti3@FUNCTION, ${{.+}}, ${{.+}}, ${{.+}}, ${{.+}}, ${{.+}}{{$}}
 ; CHECK: return{{$}}
 define i128 @urem128(i128 %x, i128 %y) {
   %a = urem i128 %x, %y
   ret i128 %a
 }
 
 ; CHECK-LABEL: and128:
-; CHECK-NEXT: .param i32, i64, i64, i64, i64{{$}}
+; CHECK-NEXT: .functype and128 (i32, i64, i64, i64, i64) -> (){{$}}
 ; CHECK-NOT:  .result
 ; CHECK:      i64.and
 ; CHECK:      i64.store
 ; CHECK:      i64.and
 ; CHECK:      i64.store
 ; CHECK-NEXT: return{{$}}
 define i128 @and128(i128 %x, i128 %y) {
   %a = and i128 %x, %y
   ret i128 %a
 }
 
 ; CHECK-LABEL: or128:
-; CHECK-NEXT: .param i32, i64, i64, i64, i64{{$}}
-; CHECK-NOT: .result
+; CHECK-NEXT: .functype or128 (i32, i64, i64, i64, i64) -> (){{$}}
 ; CHECK:      i64.or
 ; CHECK:      i64.store
 ; CHECK:      i64.or
 ; CHECK:      i64.store
 ; CHECK-NEXT: return{{$}}
 define i128 @or128(i128 %x, i128 %y) {
   %a = or i128 %x, %y
   ret i128 %a
 }
 
 ; CHECK-LABEL: xor128:
-; CHECK-NEXT: .param i32, i64, i64, i64, i64{{$}}
-; CHECK-NOT: .result
+; CHECK-NEXT: .functype xor128 (i32, i64, i64, i64, i64) -> (){{$}}
 ; CHECK:      i64.xor
 ; CHECK:      i64.store
 ; CHECK:      i64.xor
 ; CHECK:      i64.store
 ; CHECK-NEXT: return{{$}}
 define i128 @xor128(i128 %x, i128 %y) {
   %a = xor i128 %x, %y
   ret i128 %a
 }
 
 ; CHECK-LABEL: shl128:
-; CHECK-NEXT: .param i32, i64, i64, i64, i64{{$}}
-; CHECK-NOT: .result
+; CHECK-NEXT: .functype shl128 (i32, i64, i64, i64, i64) -> (){{$}}
 ; CHECK: call __ashlti3@FUNCTION, ${{.+}}, ${{.+}}, ${{.+}}, ${{.+}}{{$}}
 ; CHECK: return{{$}}
 define i128 @shl128(i128 %x, i128 %y) {
   %a = shl i128 %x, %y
   ret i128 %a
 }
 
 ; CHECK-LABEL: shr128:
-; CHECK-NEXT: .param i32, i64, i64, i64, i64{{$}}
-; CHECK-NOT: .result
+; CHECK-NEXT: .functype shr128 (i32, i64, i64, i64, i64) -> (){{$}}
 ; CHECK: call __lshrti3@FUNCTION, ${{.+}}, ${{.+}}, ${{.+}}, ${{.+}}{{$}}
 ; CHECK: return{{$}}
 define i128 @shr128(i128 %x, i128 %y) {
   %a = lshr i128 %x, %y
   ret i128 %a
 }
 
 ; CHECK-LABEL: sar128:
-; CHECK-NEXT: .param i32, i64, i64, i64, i64{{$}}
-; CHECK-NOT: .result
+; CHECK-NEXT: .functype sar128 (i32, i64, i64, i64, i64) -> (){{$}}
 ; CHECK: call __ashrti3@FUNCTION, ${{.+}}, ${{.+}}, ${{.+}}, ${{.+}}{{$}}
 ; CHECK: return{{$}}
 define i128 @sar128(i128 %x, i128 %y) {
   %a = ashr i128 %x, %y
   ret i128 %a
 }
 
 ; CHECK-LABEL: clz128:
-; CHECK-NEXT: .param i32, i64, i64{{$}}
+; CHECK-NEXT: .functype clz128 (i32, i64, i64) -> (){{$}}
 ; CHECK-NOT:  .result
 ; CHECK:      i64.clz
 ; CHECK:      i64.clz
 ; CHECK:      return{{$}}
 define i128 @clz128(i128 %x) {
   %a = call i128 @llvm.ctlz.i128(i128 %x, i1 false)
   ret i128 %a
 }
 
 ; CHECK-LABEL: clz128_zero_undef:
-; CHECK-NEXT: .param i32, i64, i64{{$}}
-; CHECK-NOT: .result
+; CHECK-NEXT: .functype clz128_zero_undef (i32, i64, i64) -> (){{$}}
 ; CHECK:      i64.clz
 ; CHECK:      i64.clz
 ; CHECK:      return{{$}}
 define i128 @clz128_zero_undef(i128 %x) {
   %a = call i128 @llvm.ctlz.i128(i128 %x, i1 true)
   ret i128 %a
 }
 
 ; CHECK-LABEL: ctz128:
-; CHECK-NEXT: .param i32, i64, i64{{$}}
-; CHECK-NOT: .result
+; CHECK-NEXT: .functype ctz128 (i32, i64, i64) -> (){{$}}
 ; CHECK:      i64.ctz
 ; CHECK:      i64.ctz
 ; CHECK:      return{{$}}
 define i128 @ctz128(i128 %x) {
   %a = call i128 @llvm.cttz.i128(i128 %x, i1 false)
   ret i128 %a
 }
 
 ; CHECK-LABEL: ctz128_zero_undef:
-; CHECK-NEXT: .param i32, i64, i64{{$}}
-; CHECK-NOT: .result
+; CHECK-NEXT: .functype ctz128_zero_undef (i32, i64, i64) -> (){{$}}
 ; CHECK:      i64.ctz
 ; CHECK:      i64.ctz
 ; CHECK:      return{{$}}
 define i128 @ctz128_zero_undef(i128 %x) {
   %a = call i128 @llvm.cttz.i128(i128 %x, i1 true)
   ret i128 %a
 }
 
 ; CHECK-LABEL: popcnt128:
-; CHECK-NEXT: .param i32, i64, i64{{$}}
-; CHECK-NOT: .result
+; CHECK-NEXT: .functype popcnt128 (i32, i64, i64) -> (){{$}}
 ; CHECK:      i64.popcnt
 ; CHECK:      i64.popcnt
 ; CHECK:      return{{$}}
 define i128 @popcnt128(i128 %x) {
   %a = call i128 @llvm.ctpop.i128(i128 %x)
   ret i128 %a
 }
 
 ; CHECK-LABEL: eqz128:
-; CHECK-NEXT: .param i64, i64{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype eqz128 (i64, i64) -> (i32){{$}}
 ; CHECK:     i64.or
 ; CHECK:     i64.eqz
 ; CHECK:     return $
 define i32 @eqz128(i128 %x) {
   %a = icmp eq i128 %x, 0
   %b = zext i1 %a to i32
   ret i32 %b
 }
 
 ; CHECK-LABEL: rotl:
-; CHECK-NEXT: .param i32, i64, i64, i64, i64{{$}}
-; CHECK-NOT: .result
+; CHECK-NEXT: .functype rotl (i32, i64, i64, i64, i64) -> (){{$}}
 ; CHECK: call __ashlti3@FUNCTION, ${{.+}}, ${{.+}}, ${{.+}}, ${{.+}}{{$}}
 ; CHECK: call __lshrti3@FUNCTION, ${{.+}}, ${{.+}}, ${{.+}}, ${{.+}}{{$}}
 ; CHECK: return{{$}}
 define i128 @rotl(i128 %x, i128 %y) {
   %z = sub i128 128, %y
   %b = shl i128 %x, %y
   %c = lshr i128 %x, %z
   %d = or i128 %b, %c
   ret i128 %d
 }
 
 ; CHECK-LABEL: masked_rotl:
-; CHECK-NEXT: .param i32, i64, i64, i64, i64{{$}}
-; CHECK-NOT: .result
+; CHECK-NEXT: .functype masked_rotl (i32, i64, i64, i64, i64) -> (){{$}}
 ; CHECK: call __ashlti3@FUNCTION, ${{.+}}, ${{.+}}, ${{.+}}, ${{.+}}{{$}}
 ; CHECK: call __lshrti3@FUNCTION, ${{.+}}, ${{.+}}, ${{.+}}, ${{.+}}{{$}}
 ; CHECK: return{{$}}
 define i128 @masked_rotl(i128 %x, i128 %y) {
   %a = and i128 %y, 127
   %z = sub i128 128, %a
   %b = shl i128 %x, %a
   %c = lshr i128 %x, %z
   %d = or i128 %b, %c
   ret i128 %d
 }
 
 ; CHECK-LABEL: rotr:
-; CHECK-NEXT: .param i32, i64, i64, i64, i64{{$}}
-; CHECK-NOT: .result
+; CHECK-NEXT: .functype rotr (i32, i64, i64, i64, i64) -> (){{$}}
 ; CHECK: call __lshrti3@FUNCTION, ${{.+}}, ${{.+}}, ${{.+}}, ${{.+}}{{$}}
 ; CHECK: call __ashlti3@FUNCTION, ${{.+}}, ${{.+}}, ${{.+}}, ${{.+}}{{$}}
 ; CHECK: return{{$}}
 define i128 @rotr(i128 %x, i128 %y) {
   %z = sub i128 128, %y
   %b = lshr i128 %x, %y
   %c = shl i128 %x, %z
   %d = or i128 %b, %c
   ret i128 %d
 }
 
 ; CHECK-LABEL: masked_rotr:
-; CHECK-NEXT: .param i32, i64, i64, i64, i64{{$}}
-; CHECK-NOT: .result
+; CHECK-NEXT: .functype masked_rotr (i32, i64, i64, i64, i64) -> (){{$}}
 ; CHECK: call __lshrti3@FUNCTION, ${{.+}}, ${{.+}}, ${{.+}}, ${{.+}}{{$}}
 ; CHECK: call __ashlti3@FUNCTION, ${{.+}}, ${{.+}}, ${{.+}}, ${{.+}}{{$}}
 ; CHECK: return{{$}}
 define i128 @masked_rotr(i128 %x, i128 %y) {
   %a = and i128 %y, 127
   %z = sub i128 128, %a
   %b = lshr i128 %x, %a
   %c = shl i128 %x, %z
   %d = or i128 %b, %c
   ret i128 %d
 }

test/CodeGen/WebAssembly/i32-load-store-alignment.ll

 ; RUN: llc < %s -mattr=+atomics -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
 
 ; Test loads and stores with custom alignment values.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ;===----------------------------------------------------------------------------
 ; Loads
 ;===----------------------------------------------------------------------------
 
 ; CHECK-LABEL: ldi32_a1:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype ldi32_a1 (i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.load $push[[NUM:[0-9]+]]=, 0($0):p2align=0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i32 @ldi32_a1(i32 *%p) {
   %v = load i32, i32* %p, align 1
   ret i32 %v
 }
 
 ; CHECK-LABEL: ldi32_a2:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype ldi32_a2 (i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.load $push[[NUM:[0-9]+]]=, 0($0):p2align=1{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i32 @ldi32_a2(i32 *%p) {
   %v = load i32, i32* %p, align 2
   ret i32 %v
 }
 
 ; 4 is the default alignment for i32 so no attribute is needed.
 
 ; CHECK-LABEL: ldi32_a4:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype ldi32_a4 (i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.load $push[[NUM:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i32 @ldi32_a4(i32 *%p) {
   %v = load i32, i32* %p, align 4
   ret i32 %v
 }
 
 ; The default alignment in LLVM is the same as the defualt alignment in wasm.
 
 ; CHECK-LABEL: ldi32:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype ldi32 (i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.load $push[[NUM:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i32 @ldi32(i32 *%p) {
   %v = load i32, i32* %p
   ret i32 %v
 }
 
 ; 8 is greater than the default alignment so it is ignored.
 
 ; CHECK-LABEL: ldi32_a8:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype ldi32_a8 (i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.load $push[[NUM:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i32 @ldi32_a8(i32 *%p) {
   %v = load i32, i32* %p, align 8
   ret i32 %v
 }
 
 ;===----------------------------------------------------------------------------
 ; Extending loads
 ;===----------------------------------------------------------------------------
 
 ; CHECK-LABEL: ldi8_a1:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype ldi8_a1 (i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.load8_u $push[[NUM:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i8 @ldi8_a1(i8 *%p) {
   %v = load i8, i8* %p, align 1
   ret i8 %v
 }
 
 ; CHECK-LABEL: ldi8_a2:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype ldi8_a2 (i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.load8_u $push[[NUM:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i8 @ldi8_a2(i8 *%p) {
   %v = load i8, i8* %p, align 2
   ret i8 %v
 }
 
 ; CHECK-LABEL: ldi16_a1:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype ldi16_a1 (i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.load16_u $push[[NUM:[0-9]+]]=, 0($0):p2align=0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i16 @ldi16_a1(i16 *%p) {
   %v = load i16, i16* %p, align 1
   ret i16 %v
 }
 
 ; CHECK-LABEL: ldi16_a2:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype ldi16_a2 (i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.load16_u $push[[NUM:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i16 @ldi16_a2(i16 *%p) {
   %v = load i16, i16* %p, align 2
   ret i16 %v
 }
 
 ; CHECK-LABEL: ldi16_a4:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype ldi16_a4 (i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.load16_u $push[[NUM:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i16 @ldi16_a4(i16 *%p) {
   %v = load i16, i16* %p, align 4
   ret i16 %v
 }
 
 ;===----------------------------------------------------------------------------
 ; Stores
 ;===----------------------------------------------------------------------------
 
 ; CHECK-LABEL: sti32_a1:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype sti32_a1 (i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.store 0($0):p2align=0, $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti32_a1(i32 *%p, i32 %v) {
   store i32 %v, i32* %p, align 1
   ret void
 }
 
 ; CHECK-LABEL: sti32_a2:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype sti32_a2 (i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.store 0($0):p2align=1, $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti32_a2(i32 *%p, i32 %v) {
   store i32 %v, i32* %p, align 2
   ret void
 }
 
 ; 4 is the default alignment for i32 so no attribute is needed.
 
 ; CHECK-LABEL: sti32_a4:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype sti32_a4 (i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.store 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti32_a4(i32 *%p, i32 %v) {
   store i32 %v, i32* %p, align 4
   ret void
 }
 
 ; The default alignment in LLVM is the same as the defualt alignment in wasm.
 
 ; CHECK-LABEL: sti32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype sti32 (i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.store 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti32(i32 *%p, i32 %v) {
   store i32 %v, i32* %p
   ret void
 }
 
 ; CHECK-LABEL: sti32_a8:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype sti32_a8 (i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.store 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti32_a8(i32 *%p, i32 %v) {
   store i32 %v, i32* %p, align 8
   ret void
 }
 
 ;===----------------------------------------------------------------------------
 ; Truncating stores
 ;===----------------------------------------------------------------------------
 
 ; CHECK-LABEL: sti8_a1:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype sti8_a1 (i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.store8 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti8_a1(i8 *%p, i8 %v) {
   store i8 %v, i8* %p, align 1
   ret void
 }
 
 ; CHECK-LABEL: sti8_a2:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype sti8_a2 (i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.store8 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti8_a2(i8 *%p, i8 %v) {
   store i8 %v, i8* %p, align 2
   ret void
 }
 
 ; CHECK-LABEL: sti16_a1:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype sti16_a1 (i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.store16 0($0):p2align=0, $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti16_a1(i16 *%p, i16 %v) {
   store i16 %v, i16* %p, align 1
   ret void
 }
 
 ; CHECK-LABEL: sti16_a2:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype sti16_a2 (i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.store16 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti16_a2(i16 *%p, i16 %v) {
   store i16 %v, i16* %p, align 2
   ret void
 }
 
 ; CHECK-LABEL: sti16_a4:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype sti16_a4 (i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.store16 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti16_a4(i16 *%p, i16 %v) {
   store i16 %v, i16* %p, align 4
   ret void
 }
 
 ;===----------------------------------------------------------------------------
 ; Atomic loads
 ;===----------------------------------------------------------------------------
 
 ; Wasm atomics have the alignment field, but it must always have the type's
 ; natural alignment.
 
 ; CHECK-LABEL: ldi32_atomic_a4:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype ldi32_atomic_a4 (i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.atomic.load $push[[NUM:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i32 @ldi32_atomic_a4(i32 *%p) {
   %v = load atomic i32, i32* %p seq_cst, align 4
   ret i32 %v
 }
 
 ; 8 is greater than the default alignment so it is ignored.
 
 ; CHECK-LABEL: ldi32_atomic_a8:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype ldi32_atomic_a8 (i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.atomic.load $push[[NUM:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i32 @ldi32_atomic_a8(i32 *%p) {
   %v = load atomic i32, i32* %p seq_cst, align 8
   ret i32 %v
 }
 
 ;===----------------------------------------------------------------------------
 ; Atomic stores
 ;===----------------------------------------------------------------------------
 
 ; CHECK-LABEL: sti32_atomic_a4:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype sti32_atomic_a4 (i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.atomic.store 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti32_atomic_a4(i32 *%p, i32 %v) {
  store atomic i32 %v, i32* %p seq_cst, align 4
  ret void
 }
 
 ; 8 is greater than the default alignment so it is ignored.
 
 ; CHECK-LABEL: sti32_atomic_a8:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype sti32_atomic_a8 (i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.atomic.store 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti32_atomic_a8(i32 *%p, i32 %v) {
  store atomic i32 %v, i32* %p seq_cst, align 8
  ret void
 }

test/CodeGen/WebAssembly/i32.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
 
 ; Test that basic 32-bit integer operations assemble as expected.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 declare i32 @llvm.ctlz.i32(i32, i1)
 declare i32 @llvm.cttz.i32(i32, i1)
 declare i32 @llvm.ctpop.i32(i32)
 
 ; CHECK-LABEL: add32:
-; CHECK-NEXT: .param i32, i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype add32 (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i32.add $push0=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @add32(i32 %x, i32 %y) {
   %a = add i32 %x, %y
   ret i32 %a
 }
 
 ; CHECK-LABEL: sub32:
-; CHECK-NEXT: .param i32, i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype sub32 (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i32.sub $push0=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @sub32(i32 %x, i32 %y) {
   %a = sub i32 %x, %y
   ret i32 %a
 }
 
 ; CHECK-LABEL: mul32:
-; CHECK-NEXT: .param i32, i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype mul32 (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i32.mul $push0=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @mul32(i32 %x, i32 %y) {
   %a = mul i32 %x, %y
   ret i32 %a
 }
 
 ; CHECK-LABEL: sdiv32:
-; CHECK-NEXT: .param i32, i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype sdiv32 (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i32.div_s $push0=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @sdiv32(i32 %x, i32 %y) {
   %a = sdiv i32 %x, %y
   ret i32 %a
 }
 
 ; CHECK-LABEL: udiv32:
-; CHECK-NEXT: .param i32, i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype udiv32 (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i32.div_u $push0=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @udiv32(i32 %x, i32 %y) {
   %a = udiv i32 %x, %y
   ret i32 %a
 }
 
 ; CHECK-LABEL: srem32:
-; CHECK-NEXT: .param i32, i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype srem32 (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i32.rem_s $push0=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @srem32(i32 %x, i32 %y) {
   %a = srem i32 %x, %y
   ret i32 %a
 }
 
 ; CHECK-LABEL: urem32:
-; CHECK-NEXT: .param i32, i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype urem32 (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i32.rem_u $push0=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @urem32(i32 %x, i32 %y) {
   %a = urem i32 %x, %y
   ret i32 %a
 }
 
 ; CHECK-LABEL: and32:
-; CHECK-NEXT: .param i32, i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype and32 (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i32.and $push0=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @and32(i32 %x, i32 %y) {
   %a = and i32 %x, %y
   ret i32 %a
 }
 
 ; CHECK-LABEL: or32:
-; CHECK-NEXT: .param i32, i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype or32 (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i32.or $push0=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @or32(i32 %x, i32 %y) {
   %a = or i32 %x, %y
   ret i32 %a
 }
 
 ; CHECK-LABEL: xor32:
-; CHECK-NEXT: .param i32, i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype xor32 (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i32.xor $push0=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @xor32(i32 %x, i32 %y) {
   %a = xor i32 %x, %y
   ret i32 %a
 }
 
 ; CHECK-LABEL: shl32:
-; CHECK-NEXT: .param i32, i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype shl32 (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i32.shl $push0=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @shl32(i32 %x, i32 %y) {
   %a = shl i32 %x, %y
   ret i32 %a
 }
 
 ; CHECK-LABEL: shr32:
-; CHECK-NEXT: .param i32, i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype shr32 (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i32.shr_u $push0=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @shr32(i32 %x, i32 %y) {
   %a = lshr i32 %x, %y
   ret i32 %a
 }
 
 ; CHECK-LABEL: sar32:
-; CHECK-NEXT: .param i32, i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype sar32 (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i32.shr_s $push0=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @sar32(i32 %x, i32 %y) {
   %a = ashr i32 %x, %y
   ret i32 %a
 }
 
 ; CHECK-LABEL: clz32:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype clz32 (i32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i32.clz $push0=, $pop[[L0]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @clz32(i32 %x) {
   %a = call i32 @llvm.ctlz.i32(i32 %x, i1 false)
   ret i32 %a
 }
 
 ; CHECK-LABEL: clz32_zero_undef:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype clz32_zero_undef (i32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i32.clz $push0=, $pop[[L0]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @clz32_zero_undef(i32 %x) {
   %a = call i32 @llvm.ctlz.i32(i32 %x, i1 true)
   ret i32 %a
 }
 
 ; CHECK-LABEL: ctz32:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype ctz32 (i32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i32.ctz $push0=, $pop[[L0]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @ctz32(i32 %x) {
   %a = call i32 @llvm.cttz.i32(i32 %x, i1 false)
   ret i32 %a
 }
 
 ; CHECK-LABEL: ctz32_zero_undef:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype ctz32_zero_undef (i32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i32.ctz $push0=, $pop[[L0]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @ctz32_zero_undef(i32 %x) {
   %a = call i32 @llvm.cttz.i32(i32 %x, i1 true)
   ret i32 %a
 }
 
 ; CHECK-LABEL: popcnt32:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype popcnt32 (i32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i32.popcnt $push0=, $pop[[L0]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @popcnt32(i32 %x) {
   %a = call i32 @llvm.ctpop.i32(i32 %x)
   ret i32 %a
 }
 
 ; CHECK-LABEL: eqz32:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype eqz32 (i32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i32.eqz $push0=, $pop[[L0]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @eqz32(i32 %x) {
   %a = icmp eq i32 %x, 0
   %b = zext i1 %a to i32
   ret i32 %b
 }
 
 ; CHECK-LABEL: rotl:
-; CHECK-NEXT: .param i32, i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype rotl (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i32.rotl $push0=, $pop[[L0]], $pop[[L1]]
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @rotl(i32 %x, i32 %y) {
   %z = sub i32 32, %y
   %b = shl i32 %x, %y
   %c = lshr i32 %x, %z
   %d = or i32 %b, %c
   ret i32 %d
 }
 
 ; CHECK-LABEL: masked_rotl:
-; CHECK-NEXT: .param i32, i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype masked_rotl (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i32.rotl $push0=, $pop[[L0]], $pop[[L1]]
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @masked_rotl(i32 %x, i32 %y) {
   %a = and i32 %y, 31
   %z = sub i32 32, %a
   %b = shl i32 %x, %a
   %c = lshr i32 %x, %z
   %d = or i32 %b, %c
   ret i32 %d
 }
 
 ; CHECK-LABEL: rotr:
-; CHECK-NEXT: .param i32, i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype rotr (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i32.rotr $push0=, $pop[[L0]], $pop[[L1]]
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @rotr(i32 %x, i32 %y) {
   %z = sub i32 32, %y
   %b = lshr i32 %x, %y
   %c = shl i32 %x, %z
   %d = or i32 %b, %c
   ret i32 %d
 }
 
 ; CHECK-LABEL: masked_rotr:
-; CHECK-NEXT: .param i32, i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype masked_rotr (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i32.rotr $push0=, $pop[[L0]], $pop[[L1]]
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @masked_rotr(i32 %x, i32 %y) {
   %a = and i32 %y, 31
   %z = sub i32 32, %a
   %b = lshr i32 %x, %a
   %c = shl i32 %x, %z
   %d = or i32 %b, %c
   ret i32 %d
 }

test/CodeGen/WebAssembly/i64-load-store-alignment.ll

 ; RUN: llc < %s -mattr=+atomics -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
 
 ; Test loads and stores with custom alignment values.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ;===----------------------------------------------------------------------------
 ; Loads
 ;===----------------------------------------------------------------------------
 
 ; CHECK-LABEL: ldi64_a1:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype ldi64_a1 (i32) -> (i64){{$}}
 ; CHECK-NEXT: i64.load $push[[NUM:[0-9]+]]=, 0($0):p2align=0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @ldi64_a1(i64 *%p) {
   %v = load i64, i64* %p, align 1
   ret i64 %v
 }
 
 ; CHECK-LABEL: ldi64_a2:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype ldi64_a2 (i32) -> (i64){{$}}
 ; CHECK-NEXT: i64.load $push[[NUM:[0-9]+]]=, 0($0):p2align=1{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @ldi64_a2(i64 *%p) {
   %v = load i64, i64* %p, align 2
   ret i64 %v
 }
 
 ; CHECK-LABEL: ldi64_a4:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype ldi64_a4 (i32) -> (i64){{$}}
 ; CHECK-NEXT: i64.load $push[[NUM:[0-9]+]]=, 0($0):p2align=2{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @ldi64_a4(i64 *%p) {
   %v = load i64, i64* %p, align 4
   ret i64 %v
 }
 
 ; 8 is the default alignment for i64 so no attribute is needed.
 
 ; CHECK-LABEL: ldi64_a8:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype ldi64_a8 (i32) -> (i64){{$}}
 ; CHECK-NEXT: i64.load $push[[NUM:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @ldi64_a8(i64 *%p) {
   %v = load i64, i64* %p, align 8
   ret i64 %v
 }
 
 ; The default alignment in LLVM is the same as the defualt alignment in wasm.
 
 ; CHECK-LABEL: ldi64:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype ldi64 (i32) -> (i64){{$}}
 ; CHECK-NEXT: i64.load $push[[NUM:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @ldi64(i64 *%p) {
   %v = load i64, i64* %p
   ret i64 %v
 }
 
 ; 16 is greater than the default alignment so it is ignored.
 
 ; CHECK-LABEL: ldi64_a16:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype ldi64_a16 (i32) -> (i64){{$}}
 ; CHECK-NEXT: i64.load $push[[NUM:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @ldi64_a16(i64 *%p) {
   %v = load i64, i64* %p, align 16
   ret i64 %v
 }
 
 ;===----------------------------------------------------------------------------
 ; Extending loads
 ;===----------------------------------------------------------------------------
 
 ; CHECK-LABEL: ldi8_a1:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype ldi8_a1 (i32) -> (i64){{$}}
 ; CHECK-NEXT: i64.load8_u $push[[NUM:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @ldi8_a1(i8 *%p) {
   %v = load i8, i8* %p, align 1
   %w = zext i8 %v to i64
   ret i64 %w
 }
 
 ; CHECK-LABEL: ldi8_a2:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype ldi8_a2 (i32) -> (i64){{$}}
 ; CHECK-NEXT: i64.load8_u $push[[NUM:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @ldi8_a2(i8 *%p) {
   %v = load i8, i8* %p, align 2
   %w = zext i8 %v to i64
   ret i64 %w
 }
 
 ; CHECK-LABEL: ldi16_a1:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype ldi16_a1 (i32) -> (i64){{$}}
 ; CHECK-NEXT: i64.load16_u $push[[NUM:[0-9]+]]=, 0($0):p2align=0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @ldi16_a1(i16 *%p) {
   %v = load i16, i16* %p, align 1
   %w = zext i16 %v to i64
   ret i64 %w
 }
 
 ; CHECK-LABEL: ldi16_a2:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype ldi16_a2 (i32) -> (i64){{$}}
 ; CHECK-NEXT: i64.load16_u $push[[NUM:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @ldi16_a2(i16 *%p) {
   %v = load i16, i16* %p, align 2
   %w = zext i16 %v to i64
   ret i64 %w
 }
 
 ; CHECK-LABEL: ldi16_a4:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype ldi16_a4 (i32) -> (i64){{$}}
 ; CHECK-NEXT: i64.load16_u $push[[NUM:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @ldi16_a4(i16 *%p) {
   %v = load i16, i16* %p, align 4
   %w = zext i16 %v to i64
   ret i64 %w
 }
 
 ; CHECK-LABEL: ldi32_a1:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype ldi32_a1 (i32) -> (i64){{$}}
 ; CHECK-NEXT: i64.load32_u $push[[NUM:[0-9]+]]=, 0($0):p2align=0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @ldi32_a1(i32 *%p) {
   %v = load i32, i32* %p, align 1
   %w = zext i32 %v to i64
   ret i64 %w
 }
 
 ; CHECK-LABEL: ldi32_a2:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype ldi32_a2 (i32) -> (i64){{$}}
 ; CHECK-NEXT: i64.load32_u $push[[NUM:[0-9]+]]=, 0($0):p2align=1{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @ldi32_a2(i32 *%p) {
   %v = load i32, i32* %p, align 2
   %w = zext i32 %v to i64
   ret i64 %w
 }
 
 ; CHECK-LABEL: ldi32_a4:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype ldi32_a4 (i32) -> (i64){{$}}
 ; CHECK-NEXT: i64.load32_u $push[[NUM:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @ldi32_a4(i32 *%p) {
   %v = load i32, i32* %p, align 4
   %w = zext i32 %v to i64
   ret i64 %w
 }
 
 ; CHECK-LABEL: ldi32_a8:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype ldi32_a8 (i32) -> (i64){{$}}
 ; CHECK-NEXT: i64.load32_u $push[[NUM:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @ldi32_a8(i32 *%p) {
   %v = load i32, i32* %p, align 8
   %w = zext i32 %v to i64
   ret i64 %w
 }
 
 ;===----------------------------------------------------------------------------
 ; Stores
 ;===----------------------------------------------------------------------------
 
 ; CHECK-LABEL: sti64_a1:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype sti64_a1 (i32, i64) -> (){{$}}
 ; CHECK-NEXT: i64.store 0($0):p2align=0, $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti64_a1(i64 *%p, i64 %v) {
   store i64 %v, i64* %p, align 1
   ret void
 }
 
 ; CHECK-LABEL: sti64_a2:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype sti64_a2 (i32, i64) -> (){{$}}
 ; CHECK-NEXT: i64.store 0($0):p2align=1, $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti64_a2(i64 *%p, i64 %v) {
   store i64 %v, i64* %p, align 2
   ret void
 }
 
 ; CHECK-LABEL: sti64_a4:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype sti64_a4 (i32, i64) -> (){{$}}
 ; CHECK-NEXT: i64.store 0($0):p2align=2, $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti64_a4(i64 *%p, i64 %v) {
   store i64 %v, i64* %p, align 4
   ret void
 }
 
 ; 8 is the default alignment for i32 so no attribute is needed.
 
 ; CHECK-LABEL: sti64_a8:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype sti64_a8 (i32, i64) -> (){{$}}
 ; CHECK-NEXT: i64.store 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti64_a8(i64 *%p, i64 %v) {
   store i64 %v, i64* %p, align 8
   ret void
 }
 
 ; The default alignment in LLVM is the same as the defualt alignment in wasm.
 
 ; CHECK-LABEL: sti64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype sti64 (i32, i64) -> (){{$}}
 ; CHECK-NEXT: i64.store 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti64(i64 *%p, i64 %v) {
   store i64 %v, i64* %p
   ret void
 }
 
 ; CHECK-LABEL: sti64_a16:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype sti64_a16 (i32, i64) -> (){{$}}
 ; CHECK-NEXT: i64.store 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti64_a16(i64 *%p, i64 %v) {
   store i64 %v, i64* %p, align 16
   ret void
 }
 
 ;===----------------------------------------------------------------------------
 ; Truncating stores
 ;===----------------------------------------------------------------------------
 
 ; CHECK-LABEL: sti8_a1:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype sti8_a1 (i32, i64) -> (){{$}}
 ; CHECK-NEXT: i64.store8 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti8_a1(i8 *%p, i64 %w) {
   %v = trunc i64 %w to i8
   store i8 %v, i8* %p, align 1
   ret void
 }
 
 ; CHECK-LABEL: sti8_a2:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype sti8_a2 (i32, i64) -> (){{$}}
 ; CHECK-NEXT: i64.store8 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti8_a2(i8 *%p, i64 %w) {
   %v = trunc i64 %w to i8
   store i8 %v, i8* %p, align 2
   ret void
 }
 
 ; CHECK-LABEL: sti16_a1:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype sti16_a1 (i32, i64) -> (){{$}}
 ; CHECK-NEXT: i64.store16 0($0):p2align=0, $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti16_a1(i16 *%p, i64 %w) {
   %v = trunc i64 %w to i16
   store i16 %v, i16* %p, align 1
   ret void
 }
 
 ; CHECK-LABEL: sti16_a2:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype sti16_a2 (i32, i64) -> (){{$}}
 ; CHECK-NEXT: i64.store16 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti16_a2(i16 *%p, i64 %w) {
   %v = trunc i64 %w to i16
   store i16 %v, i16* %p, align 2
   ret void
 }
 
 ; CHECK-LABEL: sti16_a4:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype sti16_a4 (i32, i64) -> (){{$}}
 ; CHECK-NEXT: i64.store16 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti16_a4(i16 *%p, i64 %w) {
   %v = trunc i64 %w to i16
   store i16 %v, i16* %p, align 4
   ret void
 }
 
 ; CHECK-LABEL: sti32_a1:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype sti32_a1 (i32, i64) -> (){{$}}
 ; CHECK-NEXT: i64.store32 0($0):p2align=0, $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti32_a1(i32 *%p, i64 %w) {
   %v = trunc i64 %w to i32
   store i32 %v, i32* %p, align 1
   ret void
 }
 
 ; CHECK-LABEL: sti32_a2:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype sti32_a2 (i32, i64) -> (){{$}}
 ; CHECK-NEXT: i64.store32 0($0):p2align=1, $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti32_a2(i32 *%p, i64 %w) {
   %v = trunc i64 %w to i32
   store i32 %v, i32* %p, align 2
   ret void
 }
 
 ; CHECK-LABEL: sti32_a4:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype sti32_a4 (i32, i64) -> (){{$}}
 ; CHECK-NEXT: i64.store32 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti32_a4(i32 *%p, i64 %w) {
   %v = trunc i64 %w to i32
   store i32 %v, i32* %p, align 4
   ret void
 }
 
 ; CHECK-LABEL: sti32_a8:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype sti32_a8 (i32, i64) -> (){{$}}
 ; CHECK-NEXT: i64.store32 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti32_a8(i32 *%p, i64 %w) {
   %v = trunc i64 %w to i32
   store i32 %v, i32* %p, align 8
   ret void
 }
 
 ;===----------------------------------------------------------------------------
 ; Atomic loads
 ;===----------------------------------------------------------------------------
 
 ; Wasm atomics have the alignment field, but it must always have the type's
 ; natural alignment.
 
 ; CHECK-LABEL: ldi64_atomic_a8:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype ldi64_atomic_a8 (i32) -> (i64){{$}}
 ; CHECK-NEXT: i64.atomic.load $push[[NUM:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @ldi64_atomic_a8(i64 *%p) {
   %v = load atomic i64, i64* %p seq_cst, align 8
   ret i64 %v
 }
 
 ; 16 is greater than the default alignment so it is ignored.
 
 ; CHECK-LABEL: ldi64_atomic_a16:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype ldi64_atomic_a16 (i32) -> (i64){{$}}
 ; CHECK-NEXT: i64.atomic.load $push[[NUM:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @ldi64_atomic_a16(i64 *%p) {
   %v = load atomic i64, i64* %p seq_cst, align 16
   ret i64 %v
 }
 
 ;===----------------------------------------------------------------------------
 ; Atomic stores
 ;===----------------------------------------------------------------------------
 
 ; CHECK-LABEL: sti64_atomic_a4:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype sti64_atomic_a4 (i32, i64) -> (){{$}}
 ; CHECK-NEXT: i64.atomic.store 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti64_atomic_a4(i64 *%p, i64 %v) {
  store atomic i64 %v, i64* %p seq_cst, align 8
  ret void
 }
 
 ; 16 is greater than the default alignment so it is ignored.
 
 ; CHECK-LABEL: sti64_atomic_a8:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype sti64_atomic_a8 (i32, i64) -> (){{$}}
 ; CHECK-NEXT: i64.atomic.store 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti64_atomic_a8(i64 *%p, i64 %v) {
  store atomic i64 %v, i64* %p seq_cst, align 16
  ret void
 }

test/CodeGen/WebAssembly/i64.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
 
 ; Test that basic 64-bit integer operations assemble as expected.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 declare i64 @llvm.ctlz.i64(i64, i1)
 declare i64 @llvm.cttz.i64(i64, i1)
 declare i64 @llvm.ctpop.i64(i64)
 
 ; CHECK-LABEL: add64:
-; CHECK-NEXT: .param i64, i64{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype add64 (i64, i64) -> (i64){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i64.add $push0=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @add64(i64 %x, i64 %y) {
   %a = add i64 %x, %y
   ret i64 %a
 }
 
 ; CHECK-LABEL: sub64:
-; CHECK-NEXT: .param i64, i64{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype sub64 (i64, i64) -> (i64){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i64.sub $push0=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @sub64(i64 %x, i64 %y) {
   %a = sub i64 %x, %y
   ret i64 %a
 }
 
 ; CHECK-LABEL: mul64:
-; CHECK-NEXT: .param i64, i64{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype mul64 (i64, i64) -> (i64){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i64.mul $push0=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @mul64(i64 %x, i64 %y) {
   %a = mul i64 %x, %y
   ret i64 %a
 }
 
 ; CHECK-LABEL: sdiv64:
-; CHECK-NEXT: .param i64, i64{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype sdiv64 (i64, i64) -> (i64){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i64.div_s $push0=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @sdiv64(i64 %x, i64 %y) {
   %a = sdiv i64 %x, %y
   ret i64 %a
 }
 
 ; CHECK-LABEL: udiv64:
-; CHECK-NEXT: .param i64, i64{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype udiv64 (i64, i64) -> (i64){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i64.div_u $push0=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @udiv64(i64 %x, i64 %y) {
   %a = udiv i64 %x, %y
   ret i64 %a
 }
 
 ; CHECK-LABEL: srem64:
-; CHECK-NEXT: .param i64, i64{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype srem64 (i64, i64) -> (i64){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i64.rem_s $push0=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @srem64(i64 %x, i64 %y) {
   %a = srem i64 %x, %y
   ret i64 %a
 }
 
 ; CHECK-LABEL: urem64:
-; CHECK-NEXT: .param i64, i64{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype urem64 (i64, i64) -> (i64){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i64.rem_u $push0=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @urem64(i64 %x, i64 %y) {
   %a = urem i64 %x, %y
   ret i64 %a
 }
 
 ; CHECK-LABEL: and64:
-; CHECK-NEXT: .param i64, i64{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype and64 (i64, i64) -> (i64){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i64.and $push0=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @and64(i64 %x, i64 %y) {
   %a = and i64 %x, %y
   ret i64 %a
 }
 
 ; CHECK-LABEL: or64:
-; CHECK-NEXT: .param i64, i64{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype or64 (i64, i64) -> (i64){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i64.or $push0=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @or64(i64 %x, i64 %y) {
   %a = or i64 %x, %y
   ret i64 %a
 }
 
 ; CHECK-LABEL: xor64:
-; CHECK-NEXT: .param i64, i64{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype xor64 (i64, i64) -> (i64){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i64.xor $push0=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @xor64(i64 %x, i64 %y) {
   %a = xor i64 %x, %y
   ret i64 %a
 }
 
 ; CHECK-LABEL: shl64:
-; CHECK-NEXT: .param i64, i64{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype shl64 (i64, i64) -> (i64){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i64.shl $push0=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @shl64(i64 %x, i64 %y) {
   %a = shl i64 %x, %y
   ret i64 %a
 }
 
 ; CHECK-LABEL: shr64:
-; CHECK-NEXT: .param i64, i64{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype shr64 (i64, i64) -> (i64){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i64.shr_u $push0=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @shr64(i64 %x, i64 %y) {
   %a = lshr i64 %x, %y
   ret i64 %a
 }
 
 ; CHECK-LABEL: sar64:
-; CHECK-NEXT: .param i64, i64{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype sar64 (i64, i64) -> (i64){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i64.shr_s $push0=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @sar64(i64 %x, i64 %y) {
   %a = ashr i64 %x, %y
   ret i64 %a
 }
 
 ; CHECK-LABEL: clz64:
-; CHECK-NEXT: .param i64{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype clz64 (i64) -> (i64){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i64.clz $push0=, $pop[[L0]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @clz64(i64 %x) {
   %a = call i64 @llvm.ctlz.i64(i64 %x, i1 false)
   ret i64 %a
 }
 
 ; CHECK-LABEL: clz64_zero_undef:
-; CHECK-NEXT: .param i64{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype clz64_zero_undef (i64) -> (i64){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i64.clz $push0=, $pop[[L0]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @clz64_zero_undef(i64 %x) {
   %a = call i64 @llvm.ctlz.i64(i64 %x, i1 true)
   ret i64 %a
 }
 
 ; CHECK-LABEL: ctz64:
-; CHECK-NEXT: .param i64{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype ctz64 (i64) -> (i64){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i64.ctz $push0=, $pop[[L0]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @ctz64(i64 %x) {
   %a = call i64 @llvm.cttz.i64(i64 %x, i1 false)
   ret i64 %a
 }
 
 ; CHECK-LABEL: ctz64_zero_undef:
-; CHECK-NEXT: .param i64{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype ctz64_zero_undef (i64) -> (i64){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i64.ctz $push0=, $pop[[L0]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @ctz64_zero_undef(i64 %x) {
   %a = call i64 @llvm.cttz.i64(i64 %x, i1 true)
   ret i64 %a
 }
 
 ; CHECK-LABEL: popcnt64:
-; CHECK-NEXT: .param i64{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype popcnt64 (i64) -> (i64){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i64.popcnt $push0=, $pop[[L0]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @popcnt64(i64 %x) {
   %a = call i64 @llvm.ctpop.i64(i64 %x)
   ret i64 %a
 }
 
 ; CHECK-LABEL: eqz64:
-; CHECK-NEXT: .param i64{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype eqz64 (i64) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i64.eqz $push0=, $pop[[L0]]{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @eqz64(i64 %x) {
   %a = icmp eq i64 %x, 0
   %b = zext i1 %a to i32
   ret i32 %b
 }
 
 ; CHECK-LABEL: rotl:
-; CHECK-NEXT: .param i64, i64{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype rotl (i64, i64) -> (i64){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i64.rotl $push0=, $pop[[L0]], $pop[[L1]]
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @rotl(i64 %x, i64 %y) {
   %z = sub i64 64, %y
   %b = shl i64 %x, %y
   %c = lshr i64 %x, %z
   %d = or i64 %b, %c
   ret i64 %d
 }
 
 ; CHECK-LABEL: masked_rotl:
-; CHECK-NEXT: .param i64, i64{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype masked_rotl (i64, i64) -> (i64){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i64.rotl $push0=, $pop[[L0]], $pop[[L1]]
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @masked_rotl(i64 %x, i64 %y) {
   %a = and i64 %y, 63
   %z = sub i64 64, %a
   %b = shl i64 %x, %a
   %c = lshr i64 %x, %z
   %d = or i64 %b, %c
   ret i64 %d
 }
 
 ; CHECK-LABEL: rotr:
-; CHECK-NEXT: .param i64, i64{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype rotr (i64, i64) -> (i64){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i64.rotr $push0=, $pop[[L0]], $pop[[L1]]
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @rotr(i64 %x, i64 %y) {
   %z = sub i64 64, %y
   %b = lshr i64 %x, %y
   %c = shl i64 %x, %z
   %d = or i64 %b, %c
   ret i64 %d
 }
 
 ; CHECK-LABEL: masked_rotr:
-; CHECK-NEXT: .param i64, i64{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype masked_rotr (i64, i64) -> (i64){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i64.rotr $push0=, $pop[[L0]], $pop[[L1]]
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @masked_rotr(i64 %x, i64 %y) {
   %a = and i64 %y, 63
   %z = sub i64 64, %a
   %b = lshr i64 %x, %a
   %c = shl i64 %x, %z
   %d = or i64 %b, %c
   ret i64 %d
 }

test/CodeGen/WebAssembly/immediates.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
 
 ; Test that basic immediates assemble as expected.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: zero_i32:
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype zero_i32 () -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push[[NUM:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i32 @zero_i32() {
   ret i32 0
 }
 
 ; CHECK-LABEL: one_i32:
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype one_i32 () -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push[[NUM:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i32 @one_i32() {
   ret i32 1
 }
 
 ; CHECK-LABEL: max_i32:
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype max_i32 () -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push[[NUM:[0-9]+]]=, 2147483647{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i32 @max_i32() {
   ret i32 2147483647
 }
 
 ; CHECK-LABEL: min_i32:
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype min_i32 () -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push[[NUM:[0-9]+]]=, -2147483648{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i32 @min_i32() {
   ret i32 -2147483648
 }
 
 ; CHECK-LABEL: zero_i64:
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype zero_i64 () -> (i64){{$}}
 ; CHECK-NEXT: i64.const $push[[NUM:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @zero_i64() {
   ret i64 0
 }
 
 ; CHECK-LABEL: one_i64:
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype one_i64 () -> (i64){{$}}
 ; CHECK-NEXT: i64.const $push[[NUM:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @one_i64() {
   ret i64 1
 }
 
 ; CHECK-LABEL: max_i64:
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype max_i64 () -> (i64){{$}}
 ; CHECK-NEXT: i64.const $push[[NUM:[0-9]+]]=, 9223372036854775807{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @max_i64() {
   ret i64 9223372036854775807
 }
 
 ; CHECK-LABEL: min_i64:
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype min_i64 () -> (i64){{$}}
 ; CHECK-NEXT: i64.const $push[[NUM:[0-9]+]]=, -9223372036854775808{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @min_i64() {
   ret i64 -9223372036854775808
 }
 
 ; CHECK-LABEL: negzero_f32:
-; CHECK-NEXT: .result f32{{$}}
+; CHECK-NEXT: .functype negzero_f32 () -> (f32){{$}}
 ; CHECK-NEXT: f32.const $push[[NUM:[0-9]+]]=, -0x0p0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define float @negzero_f32() {
   ret float -0.0
 }
 
 ; CHECK-LABEL: zero_f32:
-; CHECK-NEXT: .result f32{{$}}
+; CHECK-NEXT: .functype zero_f32 () -> (f32){{$}}
 ; CHECK-NEXT: f32.const $push[[NUM:[0-9]+]]=, 0x0p0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define float @zero_f32() {
   ret float 0.0
 }
 
 ; CHECK-LABEL: one_f32:
-; CHECK-NEXT: .result f32{{$}}
+; CHECK-NEXT: .functype one_f32 () -> (f32){{$}}
 ; CHECK-NEXT: f32.const $push[[NUM:[0-9]+]]=, 0x1p0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define float @one_f32() {
   ret float 1.0
 }
 
 ; CHECK-LABEL: two_f32:
-; CHECK-NEXT: .result f32{{$}}
+; CHECK-NEXT: .functype two_f32 () -> (f32){{$}}
 ; CHECK-NEXT: f32.const $push[[NUM:[0-9]+]]=, 0x1p1{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define float @two_f32() {
   ret float 2.0
 }
 
 ; CHECK-LABEL: nan_f32:
-; CHECK-NEXT: .result f32{{$}}
+; CHECK-NEXT: .functype nan_f32 () -> (f32){{$}}
 ; CHECK-NEXT: f32.const $push[[NUM:[0-9]+]]=, nan{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define float @nan_f32() {
   ret float 0x7FF8000000000000
 }
 
 ; CHECK-LABEL: negnan_f32:
-; CHECK-NEXT: .result f32{{$}}
+; CHECK-NEXT: .functype negnan_f32 () -> (f32){{$}}
 ; CHECK-NEXT: f32.const $push[[NUM:[0-9]+]]=, -nan{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define float @negnan_f32() {
   ret float 0xFFF8000000000000
 }
 
 ; CHECK-LABEL: inf_f32:
-; CHECK-NEXT: .result f32{{$}}
+; CHECK-NEXT: .functype inf_f32 () -> (f32){{$}}
 ; CHECK-NEXT: f32.const $push[[NUM:[0-9]+]]=, infinity{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define float @inf_f32() {
   ret float 0x7FF0000000000000
 }
 
 ; CHECK-LABEL: neginf_f32:
-; CHECK-NEXT: .result f32{{$}}
+; CHECK-NEXT: .functype neginf_f32 () -> (f32){{$}}
 ; CHECK-NEXT: f32.const $push[[NUM:[0-9]+]]=, -infinity{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define float @neginf_f32() {
   ret float 0xFFF0000000000000
 }
 
 ; CHECK-LABEL: custom_nan_f32:
-; CHECK-NEXT: .result f32{{$}}
+; CHECK-NEXT: .functype custom_nan_f32 () -> (f32){{$}}
 ; CHECK-NEXT: f32.const $push[[NUM:[0-9]+]]=, -nan:0x6bcdef{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define float @custom_nan_f32() {
   ret float 0xFFFD79BDE0000000
 }
 
 ; TODO: LLVM's MC layer stores f32 operands as host doubles, requiring a
 ; conversion, so the bits of the NaN are not fully preserved.
 
 ; CHECK-LABEL: custom_nans_f32:
-; CHECK-NEXT: .result f32{{$}}
+; CHECK-NEXT: .functype custom_nans_f32 () -> (f32){{$}}
 ; CHECK-NEXT: f32.const $push[[NUM:[0-9]+]]=, -nan:0x6bcdef{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define float @custom_nans_f32() {
   ret float 0xFFF579BDE0000000
 }
 
 ; CHECK-LABEL: negzero_f64:
-; CHECK-NEXT: .result f64{{$}}
+; CHECK-NEXT: .functype negzero_f64 () -> (f64){{$}}
 ; CHECK-NEXT: f64.const $push[[NUM:[0-9]+]]=, -0x0p0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define double @negzero_f64() {
   ret double -0.0
 }
 
 ; CHECK-LABEL: zero_f64:
-; CHECK-NEXT: .result f64{{$}}
+; CHECK-NEXT: .functype zero_f64 () -> (f64){{$}}
 ; CHECK-NEXT: f64.const $push[[NUM:[0-9]+]]=, 0x0p0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define double @zero_f64() {
   ret double 0.0
 }
 
 ; CHECK-LABEL: one_f64:
-; CHECK-NEXT: .result f64{{$}}
+; CHECK-NEXT: .functype one_f64 () -> (f64){{$}}
 ; CHECK-NEXT: f64.const $push[[NUM:[0-9]+]]=, 0x1p0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define double @one_f64() {
   ret double 1.0
 }
 
 ; CHECK-LABEL: two_f64:
-; CHECK-NEXT: .result f64{{$}}
+; CHECK-NEXT: .functype two_f64 () -> (f64){{$}}
 ; CHECK-NEXT: f64.const $push[[NUM:[0-9]+]]=, 0x1p1{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define double @two_f64() {
   ret double 2.0
 }
 
 ; CHECK-LABEL: nan_f64:
-; CHECK-NEXT: .result f64{{$}}
+; CHECK-NEXT: .functype nan_f64 () -> (f64){{$}}
 ; CHECK-NEXT: f64.const $push[[NUM:[0-9]+]]=, nan{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define double @nan_f64() {
   ret double 0x7FF8000000000000
 }
 
 ; CHECK-LABEL: negnan_f64:
-; CHECK-NEXT: .result f64{{$}}
+; CHECK-NEXT: .functype negnan_f64 () -> (f64){{$}}
 ; CHECK-NEXT: f64.const $push[[NUM:[0-9]+]]=, -nan{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define double @negnan_f64() {
   ret double 0xFFF8000000000000
 }
 
 ; CHECK-LABEL: inf_f64:
-; CHECK-NEXT: .result f64{{$}}
+; CHECK-NEXT: .functype inf_f64 () -> (f64){{$}}
 ; CHECK-NEXT: f64.const $push[[NUM:[0-9]+]]=, infinity{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define double @inf_f64() {
   ret double 0x7FF0000000000000
 }
 
 ; CHECK-LABEL: neginf_f64:
-; CHECK-NEXT: .result f64{{$}}
+; CHECK-NEXT: .functype neginf_f64 () -> (f64){{$}}
 ; CHECK-NEXT: f64.const $push[[NUM:[0-9]+]]=, -infinity{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define double @neginf_f64() {
   ret double 0xFFF0000000000000
 }
 
 ;; Custom NaN playloads are currently not always preserved because of the use of
 ;; native doubles in the MC layer. TODO: fix this problem or decide we don't
 ;; care about preserving NaN payloads.
 
 ; XXX-CHECK-LABEL: custom_nan_f64:
-; XXX-CHECK-NEXT: .result f64{{$}}
+; XXX-CHECK-NEXT: .functype custom_nan_f64 () -> (f64){{$}}
 ; XXX-CHECK-NEXT: f64.const $push[[NUM:[0-9]+]]=, -nan:0xabcdef0123456{{$}}
 ; XXX-CHECK-NEXT: return $pop[[NUM]]{{$}}
 ; define double @custom_nan_f64() {
 ;   ret double 0xFFFABCDEF0123456
 ; }
 
 ; XXX-CHECK-LABEL: custom_nans_f64:
-; XXX-CHECK-NEXT: .result f64{{$}}
+; XXX-CHECK-NEXT: .functype custom_nans_f64 () -> (f64){{$}}
 ; XXX-CHECK-NEXT: f64.const $push[[NUM:[0-9]+]]=, -nan:0x2bcdef0123456{{$}}
 ; XXX-CHECK-NEXT: return $pop[[NUM]]{{$}}
 ; define double @custom_nans_f64() {
 ;   ret double 0xFFF2BCDEF0123456
 ; }

test/CodeGen/WebAssembly/indirect-import.ll

 declare void @extern_sret(%struct.big* sret) #1
 
 declare i128 @extern_i128ret(i64) #1
 
 attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="generic" "unsafe-fp-math"="false" "use-soft-float"="false" }
 attributes #1 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="generic" "unsafe-fp-math"="false" "use-soft-float"="false" }
 
 
-; CHECK: .functype       extern_fd, f32, f64
-; CHECK: .functype       extern_vj, void, i64
-; CHECK: .functype       extern_v, void
-; CHECK: .functype       extern_ijidf, i32, i64, i32, f64, f32
-; CHECK: .functype       extern_struct, void, i32
-; CHECK: .functype       extern_sret, void, i32
-; CHECK: .functype       extern_i128ret, void, i32, i64
+; CHECK: .functype extern_fd (f64) -> (f32)
+; CHECK: .functype extern_vj (i64) -> ()
+; CHECK: .functype extern_v () -> ()
+; CHECK: .functype extern_ijidf  (i64, i32, f64, f32) -> (i32)
+; CHECK: .functype extern_struct (i32) -> ()
+; CHECK: .functype extern_sret (i32) -> ()
+; CHECK: .functype extern_i128ret (i32, i64) -> ()

test/CodeGen/WebAssembly/inline-asm-roundtrip.ll

 ;        : "r" (src));
 ;   return dst != 3;
 ; }
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: main:
-; CHECK-NEXT: .param    i32, i32
-; CHECK-NEXT: .result   i32
+; CHECK-NEXT: .functype main (i32, i32) -> (i32)
 ; CHECK-NEXT: .local    i32
 ; CHECK-NEXT: i32.const 1
 ; CHECK-NEXT: set_local [[SRC:[0-9]+]]
 ; CHECK-NEXT: i32.const 2
 ; CHECK-NEXT: get_local [[SRC]]
 ; CHECK-NEXT: i32.add
 ; CHECK-NEXT: set_local [[DST:[0-9]+]]
 ; CHECK-NEXT: get_local [[DST]]

test/CodeGen/WebAssembly/inline-asm.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -no-integrated-as -verify-machineinstrs | FileCheck %s
 
 ; Test basic inline assembly. Pass -no-integrated-as since these aren't
 ; actually valid assembly syntax.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: foo:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype foo (i32) -> (i32){{$}}
 ; CHECK-NEXT: #APP{{$}}
 ; CHECK-NEXT: # 0 = aaa(0){{$}}
 ; CHECK-NEXT: #NO_APP{{$}}
 ; CHECK-NEXT: get_local $push0=, 0{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @foo(i32 %r) {
 entry:
   %0 = tail call i32 asm sideeffect "# $0 = aaa($1)", "=r,r"(i32 %r) #0, !srcloc !0
   ret i32 %0
 }
 
 ; CHECK-LABEL: imm:
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype imm () -> (i32){{$}}
 ; CHECK-NEXT: .local i32{{$}}
 ; CHECK-NEXT: #APP{{$}}
 ; CHECK-NEXT: # 0 = ccc(42){{$}}
 ; CHECK-NEXT: #NO_APP{{$}}
 ; CHECK-NEXT: get_local $push0=, 0{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @imm() {
 entry:
   %0 = tail call i32 asm sideeffect "# $0 = ccc($1)", "=r,i"(i32 42) #0, !srcloc !2
   ret i32 %0
 }
 
 ; CHECK-LABEL: foo_i64:
-; CHECK-NEXT: .param i64{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype foo_i64 (i64) -> (i64){{$}}
 ; CHECK-NEXT: #APP{{$}}
 ; CHECK-NEXT: # 0 = aaa(0){{$}}
 ; CHECK-NEXT: #NO_APP{{$}}
 ; CHECK-NEXT: get_local $push0=, 0{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @foo_i64(i64 %r) {
 entry:
   %0 = tail call i64 asm sideeffect "# $0 = aaa($1)", "=r,r"(i64 %r) #0, !srcloc !0

test/CodeGen/WebAssembly/load.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -fast-isel -fast-isel-abort=1 | FileCheck %s
 
 ; Test that basic loads are assembled properly.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: ldi32:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype ldi32 (i32) -> (i32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i32.load $push[[NUM:[0-9]+]]=, 0($pop[[L0]]){{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i32 @ldi32(i32 *%p) {
   %v = load i32, i32* %p
   ret i32 %v
 }
 
 ; CHECK-LABEL: ldi64:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype ldi64 (i32) -> (i64){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i64.load $push[[NUM:[0-9]+]]=, 0($pop[[L0]]){{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @ldi64(i64 *%p) {
   %v = load i64, i64* %p
   ret i64 %v
 }
 
 ; CHECK-LABEL: ldf32:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result f32{{$}}
+; CHECK-NEXT: .functype ldf32 (i32) -> (f32){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: f32.load $push[[NUM:[0-9]+]]=, 0($pop[[L0]]){{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define float @ldf32(float *%p) {
   %v = load float, float* %p
   ret float %v
 }
 
 ; CHECK-LABEL: ldf64:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result f64{{$}}
+; CHECK-NEXT: .functype ldf64 (i32) -> (f64){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: f64.load $push[[NUM:[0-9]+]]=, 0($pop[[L0]]){{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define double @ldf64(double *%p) {
   %v = load double, double* %p
   ret double %v
 }

test/CodeGen/WebAssembly/lower-global-dtors.ll

[
   { i32, void ()*, i8* } { i32 1, void ()* @orig_dtor1c1a, i8* @associated1c1 },
   { i32, void ()*, i8* } { i32 1, void ()* @orig_dtor1c1b, i8* @associated1c1 },
   { i32, void ()*, i8* } { i32 65535, void ()* @orig_dtor65536, i8* null },
   { i32, void ()*, i8* } { i32 65535, void ()* null, i8* null },
   { i32, void ()*, i8* } { i32 65535, void ()* @after_the_null, i8* null }
 ]
 
 ; CHECK-LABEL: .Lcall_dtors.0:
-; CHECK-NEXT: .param          i32{{$}}
+; CHECK-NEXT: .functype .Lcall_dtors.0 (i32) -> (){{$}}
 ; CHECK-NEXT: call            orig_dtor0@FUNCTION{{$}}
 
 ; CHECK-LABEL: .Lregister_call_dtors.0:
-; CHECK-NEXT: block
+; CHECK:      block
 ; CHECK-NEXT: i32.const       $push2=, .Lcall_dtors.0@FUNCTION{{$}}
 ; CHECK-NEXT: i32.const       $push1=, 0
 ; CHECK-NEXT: i32.const       $push0=, __dso_handle
 ; CHECK-NEXT: i32.call        $push3=, __cxa_atexit@FUNCTION, $pop2, $pop1, $pop0{{$}}
 ; CHECK-NEXT: br_if           0, $pop3
 ; CHECK-NEXT: return
 ;      CHECK: end_block
 ; CHECK-NEXT: unreachable
 
 ; CHECK-LABEL: .Lcall_dtors.1:
-; CHECK-NEXT: .param          i32{{$}}
+; CHECK-NEXT: .functype .Lcall_dtors.1 (i32) -> (){{$}}
 ; CHECK-NEXT: call            orig_dtor1a@FUNCTION{{$}}
 ; CHECK-NEXT: call            orig_dtor1b@FUNCTION{{$}}
 
 ; CHECK-LABEL: .Lregister_call_dtors.1:
-; CHECK-NEXT: block
+; CHECK:      block
 ; CHECK-NEXT: i32.const       $push2=, .Lcall_dtors.1@FUNCTION{{$}}
 ; CHECK-NEXT: i32.const       $push1=, 0
 ; CHECK-NEXT: i32.const       $push0=, __dso_handle
 ; CHECK-NEXT: i32.call        $push3=, __cxa_atexit@FUNCTION, $pop2, $pop1, $pop0{{$}}
 ; CHECK-NEXT: br_if           0, $pop3
 ; CHECK-NEXT: return
 ;      CHECK: end_block
 ; CHECK-NEXT: unreachable
 
 ; CHECK-LABEL: .Lcall_dtors.1.associated1c0:
-; CHECK-NEXT: .param          i32{{$}}
+; CHECK-NEXT: .functype .Lcall_dtors.1.associated1c0 (i32) -> (){{$}}
 ; CHECK-NEXT: call            orig_dtor1c0@FUNCTION{{$}}
 
 ; CHECK-LABEL: .Lregister_call_dtors.1.associated1c0:
-; CHECK-NEXT: block
+; CHECK:      block
 ; CHECK-NEXT: i32.const       $push2=, .Lcall_dtors.1.associated1c0@FUNCTION{{$}}
 ; CHECK-NEXT: i32.const       $push1=, 0
 ; CHECK-NEXT: i32.const       $push0=, __dso_handle
 ; CHECK-NEXT: i32.call        $push3=, __cxa_atexit@FUNCTION, $pop2, $pop1, $pop0{{$}}
 ; CHECK-NEXT: br_if           0, $pop3
 ; CHECK-NEXT: return
 ;      CHECK: end_block
 ; CHECK-NEXT: unreachable
 
 ; CHECK-LABEL: .Lcall_dtors.1.associated1c1:
-; CHECK-NEXT: .param          i32{{$}}
+; CHECK-NEXT: .functype .Lcall_dtors.1.associated1c1 (i32) -> (){{$}}
 ; CHECK-NEXT: call            orig_dtor1c1a@FUNCTION{{$}}
 ; CHECK-NEXT: call            orig_dtor1c1b@FUNCTION{{$}}
 
 ; CHECK-LABEL: .Lregister_call_dtors.1.associated1c1:
-; CHECK-NEXT: block
+; CHECK:      block
 ; CHECK-NEXT: i32.const       $push2=, .Lcall_dtors.1.associated1c1@FUNCTION{{$}}
 ; CHECK-NEXT: i32.const       $push1=, 0
 ; CHECK-NEXT: i32.const       $push0=, __dso_handle
 ; CHECK-NEXT: i32.call        $push3=, __cxa_atexit@FUNCTION, $pop2, $pop1, $pop0{{$}}
 ; CHECK-NEXT: br_if           0, $pop3
 ; CHECK-NEXT: return
 ;      CHECK: end_block
 ; CHECK-NEXT: unreachable
 
 ; CHECK-LABEL: .Lcall_dtors:
-; CHECK-NEXT: .param          i32{{$}}
+; CHECK-NEXT: .functype .Lcall_dtors (i32) -> (){{$}}
 ; CHECK-NEXT: call            orig_dtor65536@FUNCTION{{$}}
 
 ; CHECK-LABEL: .Lregister_call_dtors:
-; CHECK-NEXT: block
+; CHECK:      block
 ; CHECK-NEXT: i32.const       $push2=, .Lcall_dtors@FUNCTION{{$}}
 ; CHECK-NEXT: i32.const       $push1=, 0
 ; CHECK-NEXT: i32.const       $push0=, __dso_handle
 ; CHECK-NEXT: i32.call        $push3=, __cxa_atexit@FUNCTION, $pop2, $pop1, $pop0{{$}}
 ; CHECK-NEXT: br_if           0, $pop3
 ; CHECK-NEXT: return
 ;      CHECK: end_block
 ; CHECK-NEXT: unreachable
 
 ; CHECK-LABEL: .section .init_array.0,"",@
 ;      CHECK: .int32  .Lregister_call_dtors.0@FUNCTION{{$}}
 ; CHECK-LABEL: .section .init_array.1,"",@
 ;      CHECK: .int32  .Lregister_call_dtors.1@FUNCTION{{$}}
 ; CHECK-LABEL: .section .init_array.200,"",@
 ;      CHECK: .int32  orig_ctor@FUNCTION{{$}}
 ; CHECK-LABEL: .section .init_array,"",@
 ;      CHECK: .int32  .Lregister_call_dtors@FUNCTION{{$}}
 
 ; CHECK-LABEL: .weak __dso_handle
 
-; CHECK-LABEL: .functype __cxa_atexit, i32, i32, i32, i32{{$}}
+; CHECK-LABEL: .functype __cxa_atexit (i32, i32, i32) -> (i32){{$}}
 
 ; We shouldn't make use of a .fini_array section.
 
 ; FINI-NOT: fini_array
 
 ; This function is listed after the null terminator, so it should
 ; be excluded.
 
 ; NULL-NOT: after_the_null

test/CodeGen/WebAssembly/main-declaration.ll

 ; RUN: llc < %s -asm-verbose=false -wasm-temporary-workarounds=false | FileCheck %s
 
 ; Test main functions with alternate signatures.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 declare void @main()
 
 define void @foo() {
   call void @main()
   ret void
 }
 
 ; CHECK-NOT:   __original_main
 ; CHECK-LABEL: foo:
+; CHECK-NEXT:    .functype foo () -> ()
 ; CHECK-NEXT:    call main@FUNCTION
 ; CHECK-NEXT:    end_function
 ; CHECK-NOT:   __original_main

test/CodeGen/WebAssembly/main-no-args.ll

 ; RUN: llc < %s -asm-verbose=false -wasm-temporary-workarounds=false | FileCheck %s
 
 ; Test main functions with alternate signatures.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 define void @main() {
   ret void
 }
 
 ; CHECK-LABEL: .L__original_main:
+; CHECK-NEXT: .functype .L__original_main () -> ()
 ; CHECK-NEXT: end_function
 
 ; CHECK-LABEL: main:
-; CHECK-NEXT: .param i32, i32
-; CHECK-NEXT: .result i32
+; CHECK-NEXT: .functype main (i32, i32) -> (i32)
 ; CHECK:      call .L__original_main@FUNCTION

test/CodeGen/WebAssembly/main-with-args.ll

 ; RUN: llc < %s -asm-verbose=false -wasm-temporary-workarounds=false | FileCheck %s
 
 ; Test that main function with expected signature is not wrapped
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 define i32 @main(i32 %a, i8** %b) {
   ret i32 0
 }
 
 ; CHECK-LABEL: main:
-; CHECK-NEXT: .param i32, i32
-; CHECK-NEXT: .result i32
+; CHECK-NEXT: .functype main (i32, i32) -> (i32)
 
 ; CHECK-NOT: __original_main:

test/CodeGen/WebAssembly/memory-addr32.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
 
 ; Test that basic memory operations assemble as expected with 32-bit addresses.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 declare i32 @llvm.wasm.memory.size.i32(i32) nounwind readonly
 declare i32 @llvm.wasm.memory.grow.i32(i32, i32) nounwind
 declare i32 @llvm.wasm.mem.size.i32(i32) nounwind readonly
 declare i32 @llvm.wasm.mem.grow.i32(i32, i32) nounwind
 declare i32 @llvm.wasm.current.memory.i32() nounwind readonly
 declare i32 @llvm.wasm.grow.memory.i32(i32) nounwind
 
 ; CHECK-LABEL: memory_size:
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype memory_size () -> (i32){{$}}
 ; CHECK-NEXT: memory.size $push0=, 0{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @memory_size() {
   %a = call i32 @llvm.wasm.memory.size.i32(i32 0)
   ret i32 %a
 }
 
 ; CHECK-LABEL: memory_grow:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype memory_grow (i32) -> (i32){{$}}
 ; CHECK: memory.grow $push0=, 0, $0{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @memory_grow(i32 %n) {
   %a = call i32 @llvm.wasm.memory.grow.i32(i32 0, i32 %n)
   ret i32 %a
 }
 
 ; CHECK-LABEL: mem_size:
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype mem_size () -> (i32){{$}}
 ; CHECK-NEXT: mem.size $push0=, 0{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @mem_size() {
   %a = call i32 @llvm.wasm.mem.size.i32(i32 0)
   ret i32 %a
 }
 
 ; CHECK-LABEL: mem_grow:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype mem_grow (i32) -> (i32){{$}}
 ; CHECK: mem.grow $push0=, 0, $0{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @mem_grow(i32 %n) {
   %a = call i32 @llvm.wasm.mem.grow.i32(i32 0, i32 %n)
   ret i32 %a
 }
 
 ; CHECK-LABEL: current_memory:
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype current_memory () -> (i32){{$}}
 ; CHECK-NEXT: current_memory $push0={{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @current_memory() {
   %a = call i32 @llvm.wasm.current.memory.i32()
   ret i32 %a
 }
 
 ; CHECK-LABEL: grow_memory:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype grow_memory (i32) -> (i32){{$}}
 ; CHECK: grow_memory $push0=, $0{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @grow_memory(i32 %n) {
   %a = call i32 @llvm.wasm.grow.memory.i32(i32 %n)
   ret i32 %a
 }

test/CodeGen/WebAssembly/offset-atomics.ll

 
 ;===----------------------------------------------------------------------------
 ; Atomic stores: 32-bit
 ;===----------------------------------------------------------------------------
 
 ; Basic store.
 
 ; CHECK-LABEL: store_i32_no_offset:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype store_i32_no_offset (i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.atomic.store 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_i32_no_offset(i32 *%p, i32 %v) {
   store atomic i32 %v, i32* %p seq_cst, align 4
   ret void
 }
 
 ; With an nuw add, we can fold an offset.
define void @store_i32_with_unfolded_gep_offset(i32* %p) {
   %s = getelementptr i32, i32* %p, i32 6
   store atomic i32 0, i32* %s seq_cst, align 4
   ret void
 }
 
 ; When storing from a fixed address, materialize a zero.
 
 ; CHECK-LABEL: store_i32_to_numeric_address:
-; CHECK-NEXT: i32.const $push0=, 0{{$}}
+; CHECK:      i32.const $push0=, 0{{$}}
 ; CHECK-NEXT: i32.const $push1=, 0{{$}}
 ; CHECK-NEXT: i32.atomic.store 42($pop0), $pop1{{$}}
 define void @store_i32_to_numeric_address() {
   %s = inttoptr i32 42 to i32*
   store atomic i32 0, i32* %s seq_cst, align 4
   ret void
 }
 
 ; CHECK-LABEL: store_i32_to_global_address:
 ; CHECK: i32.const $push0=, 0{{$}}
 ; CHECK: i32.const $push1=, 0{{$}}
 ; CHECK: i32.atomic.store gv($pop0), $pop1{{$}}
 define void @store_i32_to_global_address() {
   store atomic i32 0, i32* @gv seq_cst, align 4
   ret void
 }
 
 ;===----------------------------------------------------------------------------
 ; Atomic stores: 64-bit
 ;===----------------------------------------------------------------------------
 
 ; Basic store.
 
 ; CHECK-LABEL: store_i64_no_offset:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype store_i64_no_offset (i32, i64) -> (){{$}}
 ; CHECK-NEXT: i64.atomic.store 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_i64_no_offset(i64 *%p, i64 %v) {
   store atomic i64 %v, i64* %p seq_cst, align 8
   ret void
 }
 
 ; With an nuw add, we can fold an offset.

 ; Atomic binary read-modify-writes: 32-bit
 ;===----------------------------------------------------------------------------
 
 ; There are several RMW instructions, but here we only test 'add' as an example.
 
 ; Basic RMW.
 
 ; CHECK-LABEL: rmw_add_i32_no_offset:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype rmw_add_i32_no_offset (i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw.add $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @rmw_add_i32_no_offset(i32* %p, i32 %v) {
   %old = atomicrmw add i32* %p, i32 %v seq_cst
   ret i32 %old
 }
 
 ; With an nuw add, we can fold an offset.

 
 ;===----------------------------------------------------------------------------
 ; Atomic binary read-modify-writes: 64-bit
 ;===----------------------------------------------------------------------------
 
 ; Basic RMW.
 
 ; CHECK-LABEL: rmw_add_i64_no_offset:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype rmw_add_i64_no_offset (i32, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw.add $push0=, 0($0), $1{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @rmw_add_i64_no_offset(i64* %p, i64 %v) {
   %old = atomicrmw add i64* %p, i64 %v seq_cst
   ret i64 %old
 }
 
 ; With an nuw add, we can fold an offset.

 
 ;===----------------------------------------------------------------------------
 ; Atomic ternary read-modify-writes: 32-bit
 ;===----------------------------------------------------------------------------
 
 ; Basic RMW.
 
 ; CHECK-LABEL: cmpxchg_i32_no_offset:
-; CHECK-NEXT: .param i32, i32, i32{{$}}
+; CHECK-NEXT: .functype cmpxchg_i32_no_offset (i32, i32, i32) -> (i32){{$}}
 ; CHECK: i32.atomic.rmw.cmpxchg $push0=, 0($0), $1, $2{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @cmpxchg_i32_no_offset(i32* %p, i32 %exp, i32 %new) {
   %pair = cmpxchg i32* %p, i32 %exp, i32 %new seq_cst seq_cst
   %old = extractvalue { i32, i1 } %pair, 0
   ret i32 %old
 }
 

 
 ;===----------------------------------------------------------------------------
 ; Atomic ternary read-modify-writes: 64-bit
 ;===----------------------------------------------------------------------------
 
 ; Basic RMW.
 
 ; CHECK-LABEL: cmpxchg_i64_no_offset:
-; CHECK-NEXT: .param i32, i64, i64{{$}}
+; CHECK-NEXT: .functype cmpxchg_i64_no_offset (i32, i64, i64) -> (i64){{$}}
 ; CHECK: i64.atomic.rmw.cmpxchg $push0=, 0($0), $1, $2{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @cmpxchg_i64_no_offset(i64* %p, i64 %exp, i64 %new) {
   %pair = cmpxchg i64* %p, i64 %exp, i64 %new seq_cst seq_cst
   %old = extractvalue { i64, i1 } %pair, 0
   ret i64 %old
 }
 

test/CodeGen/WebAssembly/offset-folding.ll

 ; RUN: llc < %s -asm-verbose=false -wasm-keep-registers | FileCheck %s
 
 ; Test that constant offsets can be folded into global addresses.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 @x = external global [0 x i32]
 @y = global [50 x i32] zeroinitializer
 
 ; Test basic constant offsets of both defined and external symbols.
 
 ; CHECK-LABEL: test0:
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype test0 () -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, x+188{{$}}
 ; CHECK=NEXT: return $pop0{{$}}
 define i32* @test0() {
   ret i32* getelementptr ([0 x i32], [0 x i32]* @x, i32 0, i32 47)
 }
 
 ; CHECK-LABEL: test1:
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype test1 () -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, y+188{{$}}
 ; CHECK=NEXT: return $pop0{{$}}
 define i32* @test1() {
   ret i32* getelementptr ([50 x i32], [50 x i32]* @y, i32 0, i32 47)
 }
 
 ; Test zero offsets.
 
 ; CHECK-LABEL: test2:
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype test2 () -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, x{{$}}
 ; CHECK=NEXT: return $pop0{{$}}
 define i32* @test2() {
   ret i32* getelementptr ([0 x i32], [0 x i32]* @x, i32 0, i32 0)
 }
 
 ; CHECK-LABEL: test3:
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype test3 () -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, y{{$}}
 ; CHECK=NEXT: return $pop0{{$}}
 define i32* @test3() {
   ret i32* getelementptr ([50 x i32], [50 x i32]* @y, i32 0, i32 0)
 }
 
 ; Test negative offsets.
 
 ; CHECK-LABEL: test4:
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype test4 () -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, x-188{{$}}
 ; CHECK=NEXT: return $pop0{{$}}
 define i32* @test4() {
   ret i32* getelementptr ([0 x i32], [0 x i32]* @x, i32 0, i32 -47)
 }
 
 ; CHECK-LABEL: test5:
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype test5 () -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, y-188{{$}}
 ; CHECK=NEXT: return $pop0{{$}}
 define i32* @test5() {
   ret i32* getelementptr ([50 x i32], [50 x i32]* @y, i32 0, i32 -47)
 }

test/CodeGen/WebAssembly/offset.ll

 
 ;===----------------------------------------------------------------------------
 ; Stores: 32-bit
 ;===----------------------------------------------------------------------------
 
 ; Basic store.
 
 ; CHECK-LABEL: store_i32_no_offset:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype store_i32_no_offset (i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.store 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_i32_no_offset(i32 *%p, i32 %v) {
   store i32 %v, i32* %p
   ret void
 }
 
 ; With an nuw add, we can fold an offset.
define void @store_i32_with_unfolded_gep_offset(i32* %p) {
   %s = getelementptr i32, i32* %p, i32 6
   store i32 0, i32* %s
   ret void
 }
 
 ; When storing from a fixed address, materialize a zero.
 
 ; CHECK-LABEL: store_i32_to_numeric_address:
-; CHECK-NEXT: i32.const $push0=, 0{{$}}
+; CHECK:      i32.const $push0=, 0{{$}}
 ; CHECK-NEXT: i32.const $push1=, 0{{$}}
 ; CHECK-NEXT: i32.store 42($pop0), $pop1{{$}}
 define void @store_i32_to_numeric_address() {
   %s = inttoptr i32 42 to i32*
   store i32 0, i32* %s
   ret void
 }
 

test/CodeGen/WebAssembly/reg-stackify.ll

 }
 
 ; Don't schedule stack uses into the stack. To reduce register pressure, the
 ; scheduler might be tempted to move the definition of $2 down. However, this
 ; would risk getting incorrect liveness if the instructions are later
 ; rearranged to make the stack contiguous.
 
 ; CHECK-LABEL: stack_uses:
-; CHECK: .param i32, i32, i32, i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK: .functype stack_uses (i32, i32, i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: block   {{$}}
 ; CHECK-NEXT: i32.const   $push[[L13:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i32.lt_s    $push[[L0:[0-9]+]]=, $0, $pop[[L13]]{{$}}
 ; CHECK-NEXT: i32.const   $push[[L1:[0-9]+]]=, 2{{$}}
 ; CHECK-NEXT: i32.lt_s    $push[[L2:[0-9]+]]=, $1, $pop[[L1]]{{$}}
 ; CHECK-NEXT: i32.xor     $push[[L5:[0-9]+]]=, $pop[[L0]], $pop[[L2]]{{$}}
 ; CHECK-NEXT: i32.const   $push[[L12:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i32.lt_s    $push[[L3:[0-9]+]]=, $2, $pop[[L12]]{{$}}
 ; CHECK-NEXT: i32.const   $push[[L11:[0-9]+]]=, 2{{$}}
 ; CHECK-NEXT: i32.lt_s    $push[[L4:[0-9]+]]=, $3, $pop[[L11]]{{$}}
 ; CHECK-NEXT: i32.xor     $push[[L6:[0-9]+]]=, $pop[[L3]], $pop[[L4]]{{$}}
 ; CHECK-NEXT: i32.xor     $push[[L7:[0-9]+]]=, $pop[[L5]], $pop[[L6]]{{$}}
 ; CHECK-NEXT: i32.const   $push10=, 1{{$}}
 ; CHECK-NEXT: i32.ne      $push8=, $pop7, $pop10{{$}}
 ; CHECK-NEXT: br_if       0, $pop8{{$}}
 ; CHECK-NEXT: i32.const   $push9=, 0{{$}}
 ; CHECK-NEXT: return      $pop9{{$}}
 ; CHECK-NEXT: .LBB7_2:
 ; CHECK-NEXT: end_block{{$}}
 ; CHECK-NEXT: i32.const   $push14=, 1{{$}}
 ; CHECK-NEXT: return      $pop14{{$}}
 ; NOREGS-LABEL: stack_uses:
-; NOREGS: .param i32, i32, i32, i32{{$}}
-; NOREGS-NEXT: .result i32{{$}}
+; NOREGS: .functype stack_uses (i32, i32, i32, i32) -> (i32){{$}}
 ; NOREGS-NEXT: block {{$}}
 ; NOREGS-NEXT: get_local 0{{$}}
 ; NOREGS-NEXT: i32.const   1{{$}}
 ; NOREGS-NEXT: i32.lt_s
 ; NOREGS-NEXT: get_local 1{{$}}
 ; NOREGS-NEXT: i32.const   2{{$}}
 ; NOREGS-NEXT: i32.lt_s
 ; NOREGS-NEXT: i32.xor {{$}}

 false:
   ret i32 1
 }
 
 ; Test an interesting case where the load has multiple uses and cannot
 ; be trivially stackified. However, it can be stackified with a tee_local.
 
 ; CHECK-LABEL: multiple_uses:
-; CHECK: .param       i32, i32, i32{{$}}
+; CHECK: .functype multiple_uses (i32, i32, i32) -> (){{$}}
 ; CHECK-NEXT: block   {{$}}
 ; CHECK-NEXT: i32.load    $push[[NUM0:[0-9]+]]=, 0($2){{$}}
 ; CHECK-NEXT: tee_local   $push[[NUM1:[0-9]+]]=, $3=, $pop[[NUM0]]{{$}}
 ; CHECK-NEXT: i32.ge_u    $push[[NUM2:[0-9]+]]=, $pop[[NUM1]], $1{{$}}
 ; CHECK-NEXT: br_if       0, $pop[[NUM2]]{{$}}
 ; CHECK-NEXT: i32.lt_u    $push[[NUM3:[0-9]+]]=, $3, $0{{$}}
 ; CHECK-NEXT: br_if       0, $pop[[NUM3]]{{$}}
 ; CHECK-NEXT: i32.store   0($2), $3{{$}}
 ; CHECK-NEXT: .LBB8_3:
 ; CHECK-NEXT: end_block{{$}}
 ; CHECK-NEXT: return{{$}}
 ; NOREGS-LABEL: multiple_uses:
-; NOREGS: .param       i32, i32, i32{{$}}
+; NOREGS: .functype multiple_uses (i32, i32, i32) -> (){{$}}
 ; NOREGS: .local i32{{$}}
 ; NOREGS-NEXT: block {{$}}
 ; NOREGS-NEXT: get_local   2{{$}}
 ; NOREGS-NEXT: i32.load    0{{$}}
 ; NOREGS-NEXT: tee_local   3{{$}}
 ; NOREGS-NEXT: get_local   1{{$}}
 ; NOREGS-NEXT: i32.ge_u
 ; NOREGS-NEXT: br_if       0{{$}}

 return:
   ret void
 }
 
 ; Don't stackify stores effects across other instructions with side effects.
 
 ; CHECK:      side_effects:
 ; CHECK:      store
-; CHECK-NEXT: call
+; CHECK:      call
 ; CHECK:      store
 ; CHECK-NEXT: call
 ; NOREGS:      side_effects:
 ; NOREGS:      store
-; NOREGS-NEXT: call
+; NOREGS:      call
 ; NOREGS:      store
 ; NOREGS-NEXT: call
 declare void @evoke_side_effects()
 define hidden void @stackify_store_across_side_effects(double* nocapture %d) {
 entry:
   store double 2.0, double* %d
   call void @evoke_side_effects()
   store double 2.0, double* %d
   call void @evoke_side_effects()
   ret void
 }
 
 ; Div instructions have side effects and can't be reordered, but this entire
 ; function should still be able to be stackified because it's already in
 ; tree order.
 
 ; CHECK-LABEL: div_tree:
-; CHECK: .param i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32{{$}}
-; CHECK-NEXT: .result     i32{{$}}
+; CHECK: .functype div_tree (i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.div_s   $push[[L0:[0-9]+]]=, $0, $1{{$}}
 ; CHECK-NEXT: i32.div_s   $push[[L1:[0-9]+]]=, $2, $3{{$}}
 ; CHECK-NEXT: i32.div_s   $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; CHECK-NEXT: i32.div_s   $push[[L3:[0-9]+]]=, $4, $5{{$}}
 ; CHECK-NEXT: i32.div_s   $push[[L4:[0-9]+]]=, $6, $7{{$}}
 ; CHECK-NEXT: i32.div_s   $push[[L5:[0-9]+]]=, $pop[[L3]], $pop[[L4]]{{$}}
 ; CHECK-NEXT: i32.div_s   $push[[L6:[0-9]+]]=, $pop[[L2]], $pop[[L5]]{{$}}
 ; CHECK-NEXT: i32.div_s   $push[[L7:[0-9]+]]=, $8, $9{{$}}
 ; CHECK-NEXT: i32.div_s   $push[[L8:[0-9]+]]=, $10, $11{{$}}
 ; CHECK-NEXT: i32.div_s   $push[[L9:[0-9]+]]=, $pop[[L7]], $pop[[L8]]{{$}}
 ; CHECK-NEXT: i32.div_s   $push[[L10:[0-9]+]]=, $12, $13{{$}}
 ; CHECK-NEXT: i32.div_s   $push[[L11:[0-9]+]]=, $14, $15{{$}}
 ; CHECK-NEXT: i32.div_s   $push[[L12:[0-9]+]]=, $pop[[L10]], $pop[[L11]]{{$}}
 ; CHECK-NEXT: i32.div_s   $push[[L13:[0-9]+]]=, $pop[[L9]], $pop[[L12]]{{$}}
 ; CHECK-NEXT: i32.div_s   $push[[L14:[0-9]+]]=, $pop[[L6]], $pop[[L13]]{{$}}
 ; CHECK-NEXT: return      $pop[[L14]]{{$}}
 ; NOREGS-LABEL: div_tree:
-; NOREGS: .param i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32{{$}}
-; NOREGS-NEXT: .result     i32{{$}}
+; NOREGS: .functype div_tree (i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) -> (i32){{$}}
 ; NOREGS-NEXT: get_local 0{{$}}
 ; NOREGS-NEXT: get_local 1{{$}}
 ; NOREGS-NEXT: i32.div_s{{$}}
 ; NOREGS-NEXT: get_local 2{{$}}
 ; NOREGS-NEXT: get_local 3{{$}}
 ; NOREGS-NEXT: i32.div_s{{$}}
 ; NOREGS-NEXT: i32.div_s{{$}}
 ; NOREGS-NEXT: get_local 4{{$}}
entry:
   %div13 = sdiv i32 %div9, %div12
   %div14 = sdiv i32 %div6, %div13
   ret i32 %div14
 }
 
 ; A simple multiple-use case.
 
 ; CHECK-LABEL: simple_multiple_use:
-; CHECK:  .param      i32, i32{{$}}
+; CHECK:       .functype simple_multiple_use (i32, i32) -> (){{$}}
 ; CHECK-NEXT:  i32.mul     $push[[NUM0:[0-9]+]]=, $1, $0{{$}}
 ; CHECK-NEXT:  tee_local   $push[[NUM1:[0-9]+]]=, $[[NUM2:[0-9]+]]=, $pop[[NUM0]]{{$}}
 ; CHECK-NEXT:  call        use_a@FUNCTION, $pop[[NUM1]]{{$}}
 ; CHECK-NEXT:  call        use_b@FUNCTION, $[[NUM2]]{{$}}
 ; CHECK-NEXT:  return{{$}}
 ; NOREGS-LABEL: simple_multiple_use:
-; NOREGS:  .param      i32, i32{{$}}
+; NOREGS:       .functype simple_multiple_use (i32, i32) -> (){{$}}
 ; NOREGS-NEXT:  get_local 1{{$}}
 ; NOREGS-NEXT:  get_local 0{{$}}
 ; NOREGS-NEXT:  i32.mul
 ; NOREGS-NEXT:  tee_local   1{{$}}
 ; NOREGS-NEXT:  call        use_a@FUNCTION{{$}}
 ; NOREGS-NEXT:  get_local   1{{$}}
 ; NOREGS-NEXT:  call        use_b@FUNCTION{{$}}
 ; NOREGS-NEXT:  return{{$}}
 declare void @use_a(i32)
 declare void @use_b(i32)
 define void @simple_multiple_use(i32 %x, i32 %y) {
   %mul = mul i32 %y, %x
   call void @use_a(i32 %mul)
   call void @use_b(i32 %mul)
   ret void
 }
 
 ; Multiple uses of the same value in one instruction.
 
 ; CHECK-LABEL: multiple_uses_in_same_insn:
-; CHECK:  .param      i32, i32{{$}}
+; CHECK:       .functype multiple_uses_in_same_insn (i32, i32) -> (){{$}}
 ; CHECK-NEXT:  i32.mul     $push[[NUM0:[0-9]+]]=, $1, $0{{$}}
 ; CHECK-NEXT:  tee_local   $push[[NUM1:[0-9]+]]=, $[[NUM2:[0-9]+]]=, $pop[[NUM0]]{{$}}
 ; CHECK-NEXT:  call        use_2@FUNCTION, $pop[[NUM1]], $[[NUM2]]{{$}}
 ; CHECK-NEXT:  return{{$}}
 ; NOREGS-LABEL: multiple_uses_in_same_insn:
-; NOREGS:  .param      i32, i32{{$}}
+; NOREGS:       .functype multiple_uses_in_same_insn (i32, i32) -> (){{$}}
 ; NOREGS-NEXT:  get_local 1{{$}}
 ; NOREGS-NEXT:  get_local 0{{$}}
 ; NOREGS-NEXT:  i32.mul
 ; NOREGS-NEXT:  tee_local   1{{$}}
 ; NOREGS-NEXT:  get_local   1{{$}}
 ; NOREGS-NEXT:  call        use_2@FUNCTION{{$}}
 ; NOREGS-NEXT:  return{{$}}
 declare void @use_2(i32, i32)
 define void @multiple_uses_in_same_insn(i32 %x, i32 %y) {
   %mul = mul i32 %y, %x
   call void @use_2(i32 %mul, i32 %mul)
   ret void
 }
 
 ; Commute operands to achieve better stackifying.
 
 ; CHECK-LABEL: commute:
-; CHECK-NOT: param
-; CHECK:  .result     i32{{$}}
+; CHECK:  .functype commute () -> (i32){{$}}
 ; CHECK-NEXT:  i32.call    $push0=, red@FUNCTION{{$}}
 ; CHECK-NEXT:  i32.call    $push1=, green@FUNCTION{{$}}
 ; CHECK-NEXT:  i32.add     $push2=, $pop0, $pop1{{$}}
 ; CHECK-NEXT:  i32.call    $push3=, blue@FUNCTION{{$}}
 ; CHECK-NEXT:  i32.add     $push4=, $pop2, $pop3{{$}}
 ; CHECK-NEXT:  return      $pop4{{$}}
 ; NOREGS-LABEL: commute:
-; NOREGS-NOT: param
-; NOREGS:  .result     i32{{$}}
+; NOREGS:  .functype commute () -> (i32){{$}}
 ; NOREGS-NEXT:  i32.call    red@FUNCTION{{$}}
 ; NOREGS-NEXT:  i32.call    green@FUNCTION{{$}}
 ; NOREGS-NEXT:  i32.add {{$}}
 ; NOREGS-NEXT:  i32.call    blue@FUNCTION{{$}}
 ; NOREGS-NEXT:  i32.add {{$}}
 ; NOREGS-NEXT:  return{{$}}
 declare i32 @red()
 declare i32 @green()

 define i32 @store_past_invar_load(i32 %a, i32* %p1, i32* dereferenceable(4) %p2) {
   store i32 %a, i32* %p1
   %b = load i32, i32* %p2, !invariant.load !0
   call i32 @callee(i32 %a)
   ret i32 %b
 }
 
 ; CHECK-LABEL: ignore_dbg_value:
-; CHECK-NEXT: .Lfunc_begin
-; CHECK-NEXT: unreachable
+; CHECK:      .Lfunc_begin
+; CHECK:       unreachable
 ; NOREGS-LABEL: ignore_dbg_value:
-; NOREGS-NEXT: .Lfunc_begin
-; NOREGS-NEXT: unreachable
+; NOREGS:      .Lfunc_begin
+; NOREGS:       unreachable
 declare void @llvm.dbg.value(metadata, i64, metadata, metadata)
 define void @ignore_dbg_value() {
   call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !7, metadata !9), !dbg !10
   unreachable
 }
 
 ; Don't stackify an expression that might use the stack into a return, since we
 ; might insert a prologue before the return.

test/CodeGen/WebAssembly/return-int32.ll

 ; RUN: llc < %s -asm-verbose=false -wasm-keep-registers | FileCheck %s
 ; RUN: llc < %s -asm-verbose=false -wasm-keep-registers -fast-isel -fast-isel-abort=1 | FileCheck %s
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: return_i32:
-; CHECK-NEXT:  .param i32{{$}}
-; CHECK-NEXT:  .result i32{{$}}
+; CHECK-NEXT:  .functype return_i32 (i32) -> (i32){{$}}
 ; CHECK-NEXT:  get_local  $push0=, 0
 ; CHECK-NEXT:  end_function{{$}}
 define i32 @return_i32(i32 %p) {
   ret i32 %p
 }
 
 ; CHECK-LABEL: return_i32_twice:
 ; CHECK:      store

test/CodeGen/WebAssembly/return-void.ll

 ; RUN: llc < %s -asm-verbose=false | FileCheck %s
 ; RUN: llc < %s -asm-verbose=false -fast-isel -fast-isel-abort=1 | FileCheck %s
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: return_void:
-; CHECK-NEXT: end_function{{$}}
+; CHECK: end_function{{$}}
 define void @return_void() {
   ret void
 }
 
 ; CHECK-LABEL: return_void_twice:
 ; CHECK:      store
 ; CHECK-NEXT: return{{$}}
 ; CHECK:      store

test/CodeGen/WebAssembly/returned.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
 
 ; Test that the "returned" attribute is optimized effectively.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: _Z3foov:
-; CHECK-NEXT: .result   i32{{$}}
+; CHECK-NEXT: .functype _Z3foov () -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, 1{{$}}
 ; CHECK-NEXT: {{^}} i32.call      $push1=, _Znwm@FUNCTION, $pop0{{$}}
 ; CHECK-NEXT: {{^}} i32.call      $push2=, _ZN5AppleC1Ev@FUNCTION, $pop1{{$}}
 ; CHECK-NEXT: return    $pop2{{$}}
 %class.Apple = type { i8 }
 declare noalias i8* @_Znwm(i32)
 declare %class.Apple* @_ZN5AppleC1Ev(%class.Apple* returned)
 define %class.Apple* @_Z3foov() {
 entry:
   %call = tail call noalias i8* @_Znwm(i32 1)
   %0 = bitcast i8* %call to %class.Apple*
   %call1 = tail call %class.Apple* @_ZN5AppleC1Ev(%class.Apple* %0)
   ret %class.Apple* %0
 }
 
 ; CHECK-LABEL: _Z3barPvS_l:
-; CHECK-NEXT: .param   i32, i32, i32{{$}}
-; CHECK-NEXT: .result  i32{{$}}
+; CHECK-NEXT: .functype _Z3barPvS_l (i32, i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: {{^}} i32.call     $push0=, memcpy@FUNCTION, $0, $1, $2{{$}}
 ; CHECK-NEXT: return   $pop0{{$}}
 declare i8* @memcpy(i8* returned, i8*, i32)
 define i8* @_Z3barPvS_l(i8* %p, i8* %s, i32 %n) {
 entry:
   %call = tail call i8* @memcpy(i8* %p, i8* %s, i32 %n)
   ret i8* %p
 }
 
 ; Test that the optimization isn't performed on constant arguments.
 
 ; CHECK-LABEL: test_constant_arg:
-; CHECK-NEXT: i32.const   $push0=, global{{$}}
+; CHECK:      i32.const   $push0=, global{{$}}
 ; CHECK-NEXT: {{^}} i32.call        $drop=, returns_arg@FUNCTION, $pop0{{$}}
 ; CHECK-NEXT: return{{$}}
 @global = external global i32
 @addr = global i32* @global
 define void @test_constant_arg() {
   %call = call i32* @returns_arg(i32* @global)
   ret void
 }
 declare i32* @returns_arg(i32* returned)
 
 ; Test that the optimization isn't performed on arguments without the
 ; "returned" attribute.
 
 ; CHECK-LABEL: test_other_skipped:
-; CHECK-NEXT: .param   i32, i32, f64{{$}}
+; CHECK-NEXT: .functype test_other_skipped (i32, i32, f64) -> (){{$}}
 ; CHECK-NEXT: {{^}} i32.call     $drop=, do_something@FUNCTION, $0, $1, $2{{$}}
 ; CHECK-NEXT: {{^}} call     do_something_with_i32@FUNCTION, $1{{$}}
 ; CHECK-NEXT: {{^}} call     do_something_with_double@FUNCTION, $2{{$}}
 declare i32 @do_something(i32 returned, i32, double)
 declare void @do_something_with_i32(i32)
 declare void @do_something_with_double(double)
 define void @test_other_skipped(i32 %a, i32 %b, double %c) {
     %call = call i32 @do_something(i32 %a, i32 %b, double %c)
     call void @do_something_with_i32(i32 %b)
     call void @do_something_with_double(double %c)
     ret void
 }
 
 ; Test that the optimization is performed on arguments other than the first.
 
 ; CHECK-LABEL: test_second_arg:
-; CHECK-NEXT: .param   i32, i32{{$}}
-; CHECK-NEXT: .result  i32{{$}}
+; CHECK-NEXT: .functype test_second_arg (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: {{^}} i32.call     $push0=, do_something_else@FUNCTION, $0, $1{{$}}
 ; CHECK-NEXT: return   $pop0{{$}}
 declare i32 @do_something_else(i32, i32 returned)
 define i32 @test_second_arg(i32 %a, i32 %b) {
     %call = call i32 @do_something_else(i32 %a, i32 %b)
     ret i32 %b
 }

test/CodeGen/WebAssembly/select.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s --check-prefixes CHECK,SLOW
 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -fast-isel -fast-isel-abort=1 | FileCheck %s
 
 ; Test that wasm select instruction is selected from LLVM select instruction.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: select_i32_bool:
-; CHECK-NEXT: .param     i32, i32, i32{{$}}
-; CHECK-NEXT: .result    i32{{$}}
+; CHECK-NEXT: .functype select_i32_bool (i32, i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.select $push0=, $1, $2, $0{{$}}
 ; CHECK-NEXT: return     $pop0{{$}}
 define i32 @select_i32_bool(i1 zeroext %a, i32 %b, i32 %c) {
   %cond = select i1 %a, i32 %b, i32 %c
   ret i32 %cond
 }
 
 ; CHECK-LABEL: select_i32_bool_nozext:
-; CHECK-NEXT: .param     i32, i32, i32{{$}}
-; CHECK-NEXT: .result    i32{{$}}
+; CHECK-NEXT: .functype select_i32_bool_nozext (i32, i32, i32) -> (i32){{$}}
 ; SLOW-NEXT: i32.select $push0=, $1, $2, $0{{$}}
 ; SLOW-NEXT: return     $pop0{{$}}
 define i32 @select_i32_bool_nozext(i1 %a, i32 %b, i32 %c) {
   %cond = select i1 %a, i32 %b, i32 %c
   ret i32 %cond
 }
 
 ; CHECK-LABEL: select_i32_eq:
-; CHECK-NEXT: .param     i32, i32, i32{{$}}
-; CHECK-NEXT: .result    i32{{$}}
+; CHECK-NEXT: .functype select_i32_eq (i32, i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.select $push0=, $2, $1, $0{{$}}
 ; CHECK-NEXT: return     $pop0{{$}}
 define i32 @select_i32_eq(i32 %a, i32 %b, i32 %c) {
   %cmp = icmp eq i32 %a, 0
   %cond = select i1 %cmp, i32 %b, i32 %c
   ret i32 %cond
 }
 
 ; CHECK-LABEL: select_i32_ne:
-; CHECK-NEXT: .param     i32, i32, i32{{$}}
-; CHECK-NEXT: .result    i32{{$}}
+; CHECK-NEXT: .functype select_i32_ne (i32, i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.select $push0=, $1, $2, $0{{$}}
 ; CHECK-NEXT: return     $pop0{{$}}
 define i32 @select_i32_ne(i32 %a, i32 %b, i32 %c) {
   %cmp = icmp ne i32 %a, 0
   %cond = select i1 %cmp, i32 %b, i32 %c
   ret i32 %cond
 }
 
 ; CHECK-LABEL: select_i64_bool:
-; CHECK-NEXT: .param     i32, i64, i64{{$}}
-; CHECK-NEXT: .result    i64{{$}}
+; CHECK-NEXT: .functype select_i64_bool (i32, i64, i64) -> (i64){{$}}
 ; CHECK-NEXT: i64.select $push0=, $1, $2, $0{{$}}
 ; CHECK-NEXT: return     $pop0{{$}}
 define i64 @select_i64_bool(i1 zeroext %a, i64 %b, i64 %c) {
   %cond = select i1 %a, i64 %b, i64 %c
   ret i64 %cond
 }
 
 ; CHECK-LABEL: select_i64_bool_nozext:
-; CHECK-NEXT: .param     i32, i64, i64{{$}}
-; CHECK-NEXT: .result    i64{{$}}
+; CHECK-NEXT: .functype select_i64_bool_nozext (i32, i64, i64) -> (i64){{$}}
 ; SLOW-NEXT: i64.select $push0=, $1, $2, $0{{$}}
 ; SLOW-NEXT: return     $pop0{{$}}
 define i64 @select_i64_bool_nozext(i1 %a, i64 %b, i64 %c) {
   %cond = select i1 %a, i64 %b, i64 %c
   ret i64 %cond
 }
 
 ; CHECK-LABEL: select_i64_eq:
-; CHECK-NEXT: .param     i32, i64, i64{{$}}
-; CHECK-NEXT: .result    i64{{$}}
+; CHECK-NEXT: .functype select_i64_eq (i32, i64, i64) -> (i64){{$}}
 ; CHECK-NEXT: i64.select $push0=, $2, $1, $0{{$}}
 ; CHECK-NEXT: return     $pop0{{$}}
 define i64 @select_i64_eq(i32 %a, i64 %b, i64 %c) {
   %cmp = icmp eq i32 %a, 0
   %cond = select i1 %cmp, i64 %b, i64 %c
   ret i64 %cond
 }
 
 ; CHECK-LABEL: select_i64_ne:
-; CHECK-NEXT: .param     i32, i64, i64{{$}}
-; CHECK-NEXT: .result    i64{{$}}
+; CHECK-NEXT: .functype select_i64_ne (i32, i64, i64) -> (i64){{$}}
 ; CHECK-NEXT: i64.select $push0=, $1, $2, $0{{$}}
 ; CHECK-NEXT: return     $pop0{{$}}
 define i64 @select_i64_ne(i32 %a, i64 %b, i64 %c) {
   %cmp = icmp ne i32 %a, 0
   %cond = select i1 %cmp, i64 %b, i64 %c
   ret i64 %cond
 }
 
 ; CHECK-LABEL: select_f32_bool:
-; CHECK-NEXT: .param     i32, f32, f32{{$}}
-; CHECK-NEXT: .result    f32{{$}}
+; CHECK-NEXT: .functype select_f32_bool (i32, f32, f32) -> (f32){{$}}
 ; CHECK-NEXT: f32.select $push0=, $1, $2, $0{{$}}
 ; CHECK-NEXT: return     $pop0{{$}}
 define float @select_f32_bool(i1 zeroext %a, float %b, float %c) {
   %cond = select i1 %a, float %b, float %c
   ret float %cond
 }
 
 ; CHECK-LABEL: select_f32_bool_nozext:
-; CHECK-NEXT: .param     i32, f32, f32{{$}}
-; CHECK-NEXT: .result    f32{{$}}
+; CHECK-NEXT: .functype select_f32_bool_nozext (i32, f32, f32) -> (f32){{$}}
 ; SLOW-NEXT: f32.select $push0=, $1, $2, $0{{$}}
 ; SLOW-NEXT: return     $pop0{{$}}
 define float @select_f32_bool_nozext(i1 %a, float %b, float %c) {
   %cond = select i1 %a, float %b, float %c
   ret float %cond
 }
 
 ; CHECK-LABEL: select_f32_eq:
-; CHECK-NEXT: .param     i32, f32, f32{{$}}
-; CHECK-NEXT: .result    f32{{$}}
+; CHECK-NEXT: .functype select_f32_eq (i32, f32, f32) -> (f32){{$}}
 ; CHECK-NEXT: f32.select $push0=, $2, $1, $0{{$}}
 ; CHECK-NEXT: return     $pop0{{$}}
 define float @select_f32_eq(i32 %a, float %b, float %c) {
   %cmp = icmp eq i32 %a, 0
   %cond = select i1 %cmp, float %b, float %c
   ret float %cond
 }
 
 ; CHECK-LABEL: select_f32_ne:
-; CHECK-NEXT: .param     i32, f32, f32{{$}}
-; CHECK-NEXT: .result    f32{{$}}
+; CHECK-NEXT: .functype select_f32_ne (i32, f32, f32) -> (f32){{$}}
 ; CHECK-NEXT: f32.select $push0=, $1, $2, $0{{$}}
 ; CHECK-NEXT: return     $pop0{{$}}
 define float @select_f32_ne(i32 %a, float %b, float %c) {
   %cmp = icmp ne i32 %a, 0
   %cond = select i1 %cmp, float %b, float %c
   ret float %cond
 }
 
 ; CHECK-LABEL: select_f64_bool:
-; CHECK-NEXT: .param     i32, f64, f64{{$}}
-; CHECK-NEXT: .result    f64{{$}}
+; CHECK-NEXT: .functype select_f64_bool (i32, f64, f64) -> (f64){{$}}
 ; CHECK-NEXT: f64.select $push0=, $1, $2, $0{{$}}
 ; CHECK-NEXT: return     $pop0{{$}}
 define double @select_f64_bool(i1 zeroext %a, double %b, double %c) {
   %cond = select i1 %a, double %b, double %c
   ret double %cond
 }
 
 ; CHECK-LABEL: select_f64_bool_nozext:
-; CHECK-NEXT: .param     i32, f64, f64{{$}}
-; CHECK-NEXT: .result    f64{{$}}
+; CHECK-NEXT: .functype select_f64_bool_nozext (i32, f64, f64) -> (f64){{$}}
 ; SLOW-NEXT: f64.select $push0=, $1, $2, $0{{$}}
 ; SLOW-NEXT: return     $pop0{{$}}
 define double @select_f64_bool_nozext(i1 %a, double %b, double %c) {
   %cond = select i1 %a, double %b, double %c
   ret double %cond
 }
 
 ; CHECK-LABEL: select_f64_eq:
-; CHECK-NEXT: .param     i32, f64, f64{{$}}
-; CHECK-NEXT: .result    f64{{$}}
+; CHECK-NEXT: .functype select_f64_eq (i32, f64, f64) -> (f64){{$}}
 ; CHECK-NEXT: f64.select $push0=, $2, $1, $0{{$}}
 ; CHECK-NEXT: return     $pop0{{$}}
 define double @select_f64_eq(i32 %a, double %b, double %c) {
   %cmp = icmp eq i32 %a, 0
   %cond = select i1 %cmp, double %b, double %c
   ret double %cond
 }
 
 ; CHECK-LABEL: select_f64_ne:
-; CHECK-NEXT: .param     i32, f64, f64{{$}}
-; CHECK-NEXT: .result    f64{{$}}
+; CHECK-NEXT: .functype select_f64_ne (i32, f64, f64) -> (f64){{$}}
 ; CHECK-NEXT: f64.select $push0=, $1, $2, $0{{$}}
 ; CHECK-NEXT: return     $pop0{{$}}
 define double @select_f64_ne(i32 %a, double %b, double %c) {
   %cmp = icmp ne i32 %a, 0
   %cond = select i1 %cmp, double %b, double %c
   ret double %cond
 }

test/CodeGen/WebAssembly/signext-inreg.ll

 ; RUN: llc < %s -mattr=+sign-ext -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s --check-prefix=NOSIGNEXT
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: i32_extend8_s:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype i32_extend8_s (i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.extend8_s $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 
 ; NOSIGNEXT-LABEL: i32_extend8_s
 ; NOSIGNEXT-NOT: i32.extend8_s
 define i32 @i32_extend8_s(i8 %x) {
   %a = sext i8 %x to i32
   ret i32 %a
 }
 
 ; CHECK-LABEL: i32_extend16_s:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype i32_extend16_s (i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.extend16_s $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 
 ; NOSIGNEXT-LABEL: i32_extend16_s
 ; NOSIGNEXT-NOT: i32.extend16_s
 define i32 @i32_extend16_s(i16 %x) {
   %a = sext i16 %x to i32
   ret i32 %a
 }
 
 ; CHECK-LABEL: i64_extend8_s:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype i64_extend8_s (i32) -> (i64){{$}}
 ; CHECK-NEXT: i64.extend_u/i32 $push[[NUM1:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: i64.extend8_s $push[[NUM2:[0-9]+]]=, $pop[[NUM1]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM2]]{{$}}
 
 ; NOSIGNEXT-LABEL: i64_extend8_s
 ; NOSIGNEXT-NOT: i64.extend8_s
 define i64 @i64_extend8_s(i8 %x) {
   %a = sext i8 %x to i64
   ret i64 %a
 }
 
 ; CHECK-LABEL: i64_extend16_s:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype i64_extend16_s (i32) -> (i64){{$}}
 ; CHECK-NEXT: i64.extend_u/i32 $push[[NUM1:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: i64.extend16_s $push[[NUM2:[0-9]+]]=, $pop[[NUM1]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM2]]{{$}}
 
 ; NOSIGNEXT-LABEL: i64_extend16_s
 ; NOSIGNEXT-NOT: i16.extend16_s
 define i64 @i64_extend16_s(i16 %x) {
   %a = sext i16 %x to i64
   ret i64 %a
 }
 
 ; No SIGN_EXTEND_INREG is needed for 32->64 extension.
 ; CHECK-LABEL: i64_extend32_s:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: .functype i64_extend32_s (i32) -> (i64){{$}}
 ; CHECK-NEXT: i64.extend_s/i32 $push[[NUM:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @i64_extend32_s(i32 %x) {
   %a = sext i32 %x to i64
   ret i64 %a
 }
 

test/CodeGen/WebAssembly/signext-zeroext.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
 
 ; Test zeroext and signext ABI keywords
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: z2s_func:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype z2s_func (i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push[[NUM0:[0-9]+]]=, 24{{$}}
 ; CHECK-NEXT: i32.shl $push[[NUM2:[0-9]+]]=, $0, $pop[[NUM0]]{{$}}
 ; CHECK-NEXT: i32.const $push[[NUM1:[0-9]+]]=, 24{{$}}
 ; CHECK-NEXT: i32.shr_s $push[[NUM3:[0-9]+]]=, $pop[[NUM2]], $pop[[NUM1]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM3]]{{$}}
 define signext i8 @z2s_func(i8 zeroext %t) {
   ret i8 %t
 }
 
 ; CHECK-LABEL: s2z_func:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype s2z_func (i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push[[NUM0:[0-9]+]]=, 255{{$}}
 ; CHECK-NEXT: i32.and $push[[NUM1:[0-9]+]]=, $0, $pop[[NUM0]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM1]]{{$}}
 define zeroext i8 @s2z_func(i8 signext %t) {
   ret i8 %t
 }
 
 ; CHECK-LABEL: z2s_call:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype z2s_call (i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push[[NUM0:[0-9]+]]=, 255{{$}}
 ; CHECK-NEXT: i32.and $push[[NUM1:[0-9]+]]=, $0, $pop[[NUM0]]{{$}}
 ; CHECK-NEXT: call $push[[NUM2:[0-9]+]]=, z2s_func@FUNCTION, $pop[[NUM1]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM2]]{{$}}
 define i32 @z2s_call(i32 %t) {
   %s = trunc i32 %t to i8
   %u = call signext i8 @z2s_func(i8 zeroext %s)
   %v = sext i8 %u to i32
   ret i32 %v
 }
 
 ; CHECK-LABEL: s2z_call:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype s2z_call (i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push[[NUM0:[0-9]+]]=, 24{{$}}
 ; CHECK-NEXT: i32.shl $push[[NUM1:[0-9]+]]=, $0, $pop[[NUM0]]{{$}}
 ; CHECK-NEXT: i32.const $push[[NUM6:[0-9]+]]=, 24{{$}}
 ; CHECK-NEXT: i32.shr_s $push[[NUM2:[0-9]+]]=, $pop[[NUM1]], $pop[[NUM6]]{{$}}
 ; CHECK-NEXT: call $push[[NUM3:[0-9]]]=, s2z_func@FUNCTION, $pop[[NUM2]]{{$}}
 ; CHECK-NEXT: i32.const $push[[NUM7:[0-9]+]]=, 24{{$}}
 ; CHECK-NEXT: i32.shl $push[[NUM4:[0-9]+]]=, $pop[[NUM3]], $pop[[NUM7]]{{$}}
 ; CHECK-NEXT: i32.const $push[[NUM8:[0-9]+]]=, 24{{$}}
 ; CHECK-NEXT: i32.shr_s $push[[NUM5:[0-9]+]]=, $pop[[NUM4]], $pop[[NUM8]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM5]]{{$}}
 define i32 @s2z_call(i32 %t) {
   %s = trunc i32 %t to i8
   %u = call zeroext i8 @s2z_func(i8 signext %s)
   %v = sext i8 %u to i32
   ret i32 %v
 }

test/CodeGen/WebAssembly/simd-arith.ll

 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; ==============================================================================
 ; 16 x i8
 ; ==============================================================================
 ; CHECK-LABEL: add_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype add_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.add $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @add_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = add <16 x i8> %x, %y
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: sub_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype sub_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.sub $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @sub_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = sub <16 x i8> %x, %y
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: mul_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype mul_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.mul $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @mul_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = mul <16 x i8> %x, %y
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: neg_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype neg_v16i8 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.neg $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @neg_v16i8(<16 x i8> %x) {
   %a = sub <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0,
                       i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>,
                      %x
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: shl_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shl_v16i8 (v128, i32) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.shl $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @shl_v16i8(<16 x i8> %v, i8 %x) {
   %t = insertelement <16 x i8> undef, i8 %x, i32 0
   %s = shufflevector <16 x i8> %t, <16 x i8> undef,
     <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0,
                 i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   %a = shl <16 x i8> %v, %s
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: shl_const_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shl_const_v16i8 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 5
 ; SIMD128-NEXT: i8x16.shl $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @shl_const_v16i8(<16 x i8> %v) {
   %a = shl <16 x i8> %v,
     <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5,
      i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: shl_vec_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shl_vec_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.extract_lane_u $push[[L0:[0-9]+]]=, $0, 0{{$}}
 ; SIMD128-NEXT: i8x16.extract_lane_u $push[[L1:[0-9]+]]=, $1, 0{{$}}
 ; SIMD128-NEXT: i32.shl $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; SIMD128-NEXT: i8x16.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
 ; Skip 14 lanes
 ; SIMD128:      i8x16.extract_lane_u $push[[L4:[0-9]+]]=, $0, 15{{$}}
 ; SIMD128-NEXT: i8x16.extract_lane_u $push[[L5:[0-9]+]]=, $1, 15{{$}}
 ; SIMD128-NEXT: i32.shl $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}}
 ; SIMD128-NEXT: i8x16.replace_lane $push[[R:[0-9]+]]=, $pop[[L7:[0-9]+]], 15, $pop[[L6]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @shl_vec_v16i8(<16 x i8> %v, <16 x i8> %x) {
   %a = shl <16 x i8> %v, %x
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: shr_s_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shr_s_v16i8 (v128, i32) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.shr_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @shr_s_v16i8(<16 x i8> %v, i8 %x) {
   %t = insertelement <16 x i8> undef, i8 %x, i32 0
   %s = shufflevector <16 x i8> %t, <16 x i8> undef,
     <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0,
                 i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   %a = ashr <16 x i8> %v, %s
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: shr_s_vec_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shr_s_vec_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.extract_lane_u $push[[L0:[0-9]+]]=, $0, 0{{$}}
 ; SIMD128-NEXT: i32.const $push[[L1:[0-9]+]]=, 24{{$}}
 ; SIMD128-NEXT: i32.shl $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; SIMD128-NEXT: i32.const $push[[L3:[0-9]+]]=, 24{{$}}
 ; SIMD128-NEXT: i32.shr_s $push[[L4:[0-9]+]]=, $pop[[L2]], $pop[[L3]]{{$}}
 ; SIMD128-NEXT: i8x16.extract_lane_u $push[[L5:[0-9]+]]=, $1, 0{{$}}
 ; SIMD128-NEXT: i32.shr_s $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}}
 ; SIMD128-NEXT: i8x16.splat $push[[L7:[0-9]+]]=, $pop[[L6]]{{$}}

 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @shr_s_vec_v16i8(<16 x i8> %v, <16 x i8> %x) {
   %a = ashr <16 x i8> %v, %x
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: shr_u_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shr_u_v16i8 (v128, i32) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.shr_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @shr_u_v16i8(<16 x i8> %v, i8 %x) {
   %t = insertelement <16 x i8> undef, i8 %x, i32 0
   %s = shufflevector <16 x i8> %t, <16 x i8> undef,
     <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0,
                 i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   %a = lshr <16 x i8> %v, %s
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: shr_u_vec_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shr_u_vec_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.extract_lane_u $push[[L0:[0-9]+]]=, $0, 0{{$}}
 ; SIMD128-NEXT: i8x16.extract_lane_u $push[[L1:[0-9]+]]=, $1, 0{{$}}
 ; SIMD128-NEXT: i32.shr_u $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; SIMD128-NEXT: i8x16.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
 ; Skip 14 lanes
 ; SIMD128:      i8x16.extract_lane_u $push[[L4:[0-9]+]]=, $0, 15{{$}}
 ; SIMD128-NEXT: i8x16.extract_lane_u $push[[L5:[0-9]+]]=, $1, 15{{$}}
 ; SIMD128-NEXT: i32.shr_u $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}}
 ; SIMD128-NEXT: i8x16.replace_lane $push[[R:[0-9]+]]=, $pop[[L7:[0-9]+]], 15, $pop[[L6]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @shr_u_vec_v16i8(<16 x i8> %v, <16 x i8> %x) {
   %a = lshr <16 x i8> %v, %x
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: and_v16i8:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype and_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @and_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = and <16 x i8> %x, %y
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: or_v16i8:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype or_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @or_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = or <16 x i8> %x, %y
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: xor_v16i8:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype xor_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.xor $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @xor_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = xor <16 x i8> %x, %y
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: not_v16i8:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype not_v16i8 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @not_v16i8(<16 x i8> %x) {
   %a = xor <16 x i8> %x, <i8 -1, i8 -1, i8 -1, i8 -1,
                           i8 -1, i8 -1, i8 -1, i8 -1,
                           i8 -1, i8 -1, i8 -1, i8 -1,
                           i8 -1, i8 -1, i8 -1, i8 -1>
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: bitselect_v16i8:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype bitselect_v16i8 (v128, v128, v128) -> (v128){{$}}
 ; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
 ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
 ; SIMD128-FAST-NEXT: v128.and
 ; SIMD128-FAST-NEXT: v128.not
 ; SIMD128-FAST-NEXT: v128.and
 ; SIMD128-FAST-NEXT: v128.or
 ; SIMD128-FAST-NEXT: return
 define <16 x i8> @bitselect_v16i8(<16 x i8> %c, <16 x i8> %v1, <16 x i8> %v2) {
   %masked_v1 = and <16 x i8> %c, %v1
   %inv_mask = xor <16 x i8> %c,
     <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
      i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
   %masked_v2 = and <16 x i8> %inv_mask, %v2
   %a = or <16 x i8> %masked_v1, %masked_v2
   ret <16 x i8> %a
 }
 
 ; ==============================================================================
 ; 8 x i16
 ; ==============================================================================
 ; CHECK-LABEL: add_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype add_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.add $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @add_v8i16(<8 x i16> %x, <8 x i16> %y) {
   %a = add <8 x i16> %x, %y
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: sub_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype sub_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.sub $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @sub_v8i16(<8 x i16> %x, <8 x i16> %y) {
   %a = sub <8 x i16> %x, %y
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: mul_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype mul_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.mul $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @mul_v8i16(<8 x i16> %x, <8 x i16> %y) {
   %a = mul <8 x i16> %x, %y
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: neg_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype neg_v8i16 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.neg $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @neg_v8i16(<8 x i16> %x) {
   %a = sub <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>,
                      %x
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: shl_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shl_v8i16 (v128, i32) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.shl $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @shl_v8i16(<8 x i16> %v, i16 %x) {
   %t = insertelement <8 x i16> undef, i16 %x, i32 0
   %s = shufflevector <8 x i16> %t, <8 x i16> undef,
     <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   %a = shl <8 x i16> %v, %s
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: shl_const_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shl_const_v8i16 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 5
 ; SIMD128-NEXT: i16x8.shl $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @shl_const_v8i16(<8 x i16> %v) {
   %a = shl <8 x i16> %v,
     <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: shl_vec_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shl_vec_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.extract_lane_u $push[[L0:[0-9]+]]=, $0, 0{{$}}
 ; SIMD128-NEXT: i16x8.extract_lane_u $push[[L1:[0-9]+]]=, $1, 0{{$}}
 ; SIMD128-NEXT: i32.shl $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; SIMD128-NEXT: i16x8.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
 ; Skip 6 lanes
 ; SIMD128:      i16x8.extract_lane_u $push[[L4:[0-9]+]]=, $0, 7{{$}}
 ; SIMD128-NEXT: i16x8.extract_lane_u $push[[L5:[0-9]+]]=, $1, 7{{$}}
 ; SIMD128-NEXT: i32.shl $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}}
 ; SIMD128-NEXT: i16x8.replace_lane $push[[R:[0-9]+]]=, $pop[[L7:[0-9]+]], 7, $pop[[L6]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @shl_vec_v8i16(<8 x i16> %v, <8 x i16> %x) {
   %a = shl <8 x i16> %v, %x
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: shr_s_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shr_s_v8i16 (v128, i32) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.shr_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @shr_s_v8i16(<8 x i16> %v, i16 %x) {
   %t = insertelement <8 x i16> undef, i16 %x, i32 0
   %s = shufflevector <8 x i16> %t, <8 x i16> undef,
     <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   %a = ashr <8 x i16> %v, %s
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: shr_s_vec_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shr_s_vec_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.extract_lane_u $push[[L0:[0-9]+]]=, $0, 0{{$}}
 ; SIMD128-NEXT: i32.const $push[[L1:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.shl $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; SIMD128-NEXT: i32.const $push[[L3:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.shr_s $push[[L4:[0-9]+]]=, $pop[[L2]], $pop[[L3]]{{$}}
 ; SIMD128-NEXT: i16x8.extract_lane_u $push[[L5:[0-9]+]]=, $1, 0{{$}}
 ; SIMD128-NEXT: i32.shr_s $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}}
 ; SIMD128-NEXT: i16x8.splat $push[[L7:[0-9]+]]=, $pop[[L6]]{{$}}

 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @shr_s_vec_v8i16(<8 x i16> %v, <8 x i16> %x) {
   %a = ashr <8 x i16> %v, %x
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: shr_u_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shr_u_v8i16 (v128, i32) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.shr_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @shr_u_v8i16(<8 x i16> %v, i16 %x) {
   %t = insertelement <8 x i16> undef, i16 %x, i32 0
   %s = shufflevector <8 x i16> %t, <8 x i16> undef,
     <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   %a = lshr <8 x i16> %v, %s
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: shr_u_vec_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shr_u_vec_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.extract_lane_u $push[[L0:[0-9]+]]=, $0, 0{{$}}
 ; SIMD128-NEXT: i16x8.extract_lane_u $push[[L1:[0-9]+]]=, $1, 0{{$}}
 ; SIMD128-NEXT: i32.shr_u $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; SIMD128-NEXT: i16x8.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
 ; Skip 6 lanes
 ; SIMD128:      i16x8.extract_lane_u $push[[L4:[0-9]+]]=, $0, 7{{$}}
 ; SIMD128-NEXT: i16x8.extract_lane_u $push[[L5:[0-9]+]]=, $1, 7{{$}}
 ; SIMD128-NEXT: i32.shr_u $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}}
 ; SIMD128-NEXT: i16x8.replace_lane $push[[R:[0-9]+]]=, $pop[[L7:[0-9]+]], 7, $pop[[L6]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @shr_u_vec_v8i16(<8 x i16> %v, <8 x i16> %x) {
   %a = lshr <8 x i16> %v, %x
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: and_v8i16:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype and_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @and_v8i16(<8 x i16> %x, <8 x i16> %y) {
   %a = and <8 x i16> %x, %y
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: or_v8i16:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype or_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @or_v8i16(<8 x i16> %x, <8 x i16> %y) {
   %a = or <8 x i16> %x, %y
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: xor_v8i16:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype xor_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.xor $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @xor_v8i16(<8 x i16> %x, <8 x i16> %y) {
   %a = xor <8 x i16> %x, %y
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: not_v8i16:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype not_v8i16 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @not_v8i16(<8 x i16> %x) {
   %a = xor <8 x i16> %x, <i16 -1, i16 -1, i16 -1, i16 -1,
                           i16 -1, i16 -1, i16 -1, i16 -1>
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: bitselect_v8i16:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype bitselect_v8i16 (v128, v128, v128) -> (v128){{$}}
 ; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
 ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
 ; SIMD128-FAST-NEXT: v128.and
 ; SIMD128-FAST-NEXT: v128.not
 ; SIMD128-FAST-NEXT: v128.and
 ; SIMD128-FAST-NEXT: v128.or
 ; SIMD128-FAST-NEXT: return
 define <8 x i16> @bitselect_v8i16(<8 x i16> %c, <8 x i16> %v1, <8 x i16> %v2) {
   %masked_v1 = and <8 x i16> %v1, %c
   %inv_mask = xor <8 x i16>
     <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>,
     %c
   %masked_v2 = and <8 x i16> %v2, %inv_mask
   %a = or <8 x i16> %masked_v1, %masked_v2
   ret <8 x i16> %a
 }
 
 ; ==============================================================================
 ; 4 x i32
 ; ==============================================================================
 ; CHECK-LABEL: add_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype add_v4i32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.add $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @add_v4i32(<4 x i32> %x, <4 x i32> %y) {
   %a = add <4 x i32> %x, %y
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: sub_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype sub_v4i32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.sub $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @sub_v4i32(<4 x i32> %x, <4 x i32> %y) {
   %a = sub <4 x i32> %x, %y
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: mul_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype mul_v4i32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.mul $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @mul_v4i32(<4 x i32> %x, <4 x i32> %y) {
   %a = mul <4 x i32> %x, %y
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: neg_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype neg_v4i32 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.neg $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @neg_v4i32(<4 x i32> %x) {
   %a = sub <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %x
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: shl_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128, i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shl_v4i32 (v128, i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.shl $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @shl_v4i32(<4 x i32> %v, i32 %x) {
   %t = insertelement <4 x i32> undef, i32 %x, i32 0
   %s = shufflevector <4 x i32> %t, <4 x i32> undef,
     <4 x i32> <i32 0, i32 0, i32 0, i32 0>
   %a = shl <4 x i32> %v, %s
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: shl_const_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shl_const_v4i32 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 5
 ; SIMD128-NEXT: i32x4.shl $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @shl_const_v4i32(<4 x i32> %v) {
   %a = shl <4 x i32> %v, <i32 5, i32 5, i32 5, i32 5>
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: shl_vec_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shl_vec_v4i32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.extract_lane $push[[L0:[0-9]+]]=, $0, 0{{$}}
 ; SIMD128-NEXT: i32x4.extract_lane $push[[L1:[0-9]+]]=, $1, 0{{$}}
 ; SIMD128-NEXT: i32.shl $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; SIMD128-NEXT: i32x4.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
 ; Skip 2 lanes
 ; SIMD128:      i32x4.extract_lane $push[[L4:[0-9]+]]=, $0, 3{{$}}
 ; SIMD128-NEXT: i32x4.extract_lane $push[[L5:[0-9]+]]=, $1, 3{{$}}
 ; SIMD128-NEXT: i32.shl $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}}
 ; SIMD128-NEXT: i32x4.replace_lane $push[[R:[0-9]+]]=, $pop[[L7:[0-9]+]], 3, $pop[[L6]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @shl_vec_v4i32(<4 x i32> %v, <4 x i32> %x) {
   %a = shl <4 x i32> %v, %x
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: shr_s_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128, i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shr_s_v4i32 (v128, i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.shr_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @shr_s_v4i32(<4 x i32> %v, i32 %x) {
   %t = insertelement <4 x i32> undef, i32 %x, i32 0
   %s = shufflevector <4 x i32> %t, <4 x i32> undef,
     <4 x i32> <i32 0, i32 0, i32 0, i32 0>
   %a = ashr <4 x i32> %v, %s
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: shr_s_vec_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shr_s_vec_v4i32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.extract_lane $push[[L0:[0-9]+]]=, $0, 0{{$}}
 ; SIMD128-NEXT: i32x4.extract_lane $push[[L1:[0-9]+]]=, $1, 0{{$}}
 ; SIMD128-NEXT: i32.shr_s $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; SIMD128-NEXT: i32x4.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
 ; Skip 2 lanes
 ; SIMD128:      i32x4.extract_lane $push[[L4:[0-9]+]]=, $0, 3{{$}}
 ; SIMD128-NEXT: i32x4.extract_lane $push[[L5:[0-9]+]]=, $1, 3{{$}}
 ; SIMD128-NEXT: i32.shr_s $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}}
 ; SIMD128-NEXT: i32x4.replace_lane $push[[R:[0-9]+]]=, $pop[[L7:[0-9]+]], 3, $pop[[L6]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @shr_s_vec_v4i32(<4 x i32> %v, <4 x i32> %x) {
   %a = ashr <4 x i32> %v, %x
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: shr_u_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128, i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shr_u_v4i32 (v128, i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.shr_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @shr_u_v4i32(<4 x i32> %v, i32 %x) {
   %t = insertelement <4 x i32> undef, i32 %x, i32 0
   %s = shufflevector <4 x i32> %t, <4 x i32> undef,
     <4 x i32> <i32 0, i32 0, i32 0, i32 0>
   %a = lshr <4 x i32> %v, %s
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: shr_u_vec_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shr_u_vec_v4i32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.extract_lane $push[[L0:[0-9]+]]=, $0, 0{{$}}
 ; SIMD128-NEXT: i32x4.extract_lane $push[[L1:[0-9]+]]=, $1, 0{{$}}
 ; SIMD128-NEXT: i32.shr_u $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; SIMD128-NEXT: i32x4.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
 ; Skip 2 lanes
 ; SIMD128:      i32x4.extract_lane $push[[L4:[0-9]+]]=, $0, 3{{$}}
 ; SIMD128-NEXT: i32x4.extract_lane $push[[L5:[0-9]+]]=, $1, 3{{$}}
 ; SIMD128-NEXT: i32.shr_u $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}}
 ; SIMD128-NEXT: i32x4.replace_lane $push[[R:[0-9]+]]=, $pop[[L7:[0-9]+]], 3, $pop[[L6]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @shr_u_vec_v4i32(<4 x i32> %v, <4 x i32> %x) {
   %a = lshr <4 x i32> %v, %x
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: and_v4i32:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype and_v4i32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @and_v4i32(<4 x i32> %x, <4 x i32> %y) {
   %a = and <4 x i32> %x, %y
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: or_v4i32:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype or_v4i32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @or_v4i32(<4 x i32> %x, <4 x i32> %y) {
   %a = or <4 x i32> %x, %y
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: xor_v4i32:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype xor_v4i32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.xor $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @xor_v4i32(<4 x i32> %x, <4 x i32> %y) {
   %a = xor <4 x i32> %x, %y
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: not_v4i32:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype not_v4i32 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @not_v4i32(<4 x i32> %x) {
   %a = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: bitselect_v4i32:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype bitselect_v4i32 (v128, v128, v128) -> (v128){{$}}
 ; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
 ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
 ; SIMD128-FAST-NEXT: v128.not
 ; SIMD128-FAST-NEXT: v128.and
 ; SIMD128-FAST-NEXT: v128.and
 ; SIMD128-FAST-NEXT: v128.or
 ; SIMD128-FAST-NEXT: return
 define <4 x i32> @bitselect_v4i32(<4 x i32> %c, <4 x i32> %v1, <4 x i32> %v2) {
   %masked_v1 = and <4 x i32> %c, %v1
   %inv_mask = xor <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, %c
   %masked_v2 = and <4 x i32> %inv_mask, %v2
   %a = or <4 x i32> %masked_v2, %masked_v1
   ret <4 x i32> %a
 }
 
 ; ==============================================================================
 ; 2 x i64
 ; ==============================================================================
 ; CHECK-LABEL: add_v2i64:
 ; NO-SIMD128-NOT: i64x2
 ; SIMD128-VM-NOT: i64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype add_v2i64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.add $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @add_v2i64(<2 x i64> %x, <2 x i64> %y) {
   %a = add <2 x i64> %x, %y
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: sub_v2i64:
 ; NO-SIMD128-NOT: i64x2
 ; SIMD128-VM-NOT: i64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype sub_v2i64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.sub $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @sub_v2i64(<2 x i64> %x, <2 x i64> %y) {
   %a = sub <2 x i64> %x, %y
   ret <2 x i64> %a
 }
 
 ; v2i64.mul is not in spec
 ; CHECK-LABEL: mul_v2i64:
 ; NO-SIMD128-NOT: i64x2
 ; SIMD128-VM-NOT: i64x2
 ; SIMD128-NOT: i64x2.mul
 ; SIMD128: i64x2.extract_lane
 ; SIMD128: i64.mul
 define <2 x i64> @mul_v2i64(<2 x i64> %x, <2 x i64> %y) {
   %a = mul <2 x i64> %x, %y
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: neg_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype neg_v2i64 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.neg $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @neg_v2i64(<2 x i64> %x) {
   %a = sub <2 x i64> <i64 0, i64 0>, %x
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: shl_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-NEXT: .param v128, i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shl_v2i64 (v128, i32) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.shl $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @shl_v2i64(<2 x i64> %v, i32 %x) {
   %x2 = zext i32 %x to i64
   %t = insertelement <2 x i64> undef, i64 %x2, i32 0
   %s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
   %a = shl <2 x i64> %v, %s
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: shl_nozext_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-NEXT: .param v128, i64{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shl_nozext_v2i64 (v128, i64) -> (v128){{$}}
 ; SIMD128-NEXT: i32.wrap/i64 $push[[L0:[0-9]+]]=, $1{{$}}
 ; SIMD128-NEXT: i64x2.shl $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @shl_nozext_v2i64(<2 x i64> %v, i64 %x) {
   %t = insertelement <2 x i64> undef, i64 %x, i32 0
   %s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
   %a = shl <2 x i64> %v, %s
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: shl_const_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shl_const_v2i64 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 5{{$}}
 ; SIMD128-NEXT: i64x2.shl $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @shl_const_v2i64(<2 x i64> %v) {
   %a = shl <2 x i64> %v, <i64 5, i64 5>
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: shl_vec_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shl_vec_v2i64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.extract_lane $push[[L0:[0-9]+]]=, $0, 0{{$}}
 ; SIMD128-NEXT: i64x2.extract_lane $push[[L1:[0-9]+]]=, $1, 0{{$}}
 ; SIMD128-NEXT: i64.shl $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; SIMD128-NEXT: i64x2.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
 ; SIMD128-NEXT: i64x2.extract_lane $push[[L4:[0-9]+]]=, $0, 1{{$}}
 ; SIMD128-NEXT: i64x2.extract_lane $push[[L5:[0-9]+]]=, $1, 1{{$}}
 ; SIMD128-NEXT: i64.shl $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}}
 ; SIMD128-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L3]], 1, $pop[[L6]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @shl_vec_v2i64(<2 x i64> %v, <2 x i64> %x) {
   %a = shl <2 x i64> %v, %x
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: shr_s_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-NEXT: .param v128, i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shr_s_v2i64 (v128, i32) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.shr_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @shr_s_v2i64(<2 x i64> %v, i32 %x) {
   %x2 = zext i32 %x to i64
   %t = insertelement <2 x i64> undef, i64 %x2, i32 0
   %s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
   %a = ashr <2 x i64> %v, %s
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: shr_s_nozext_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-NEXT: .param v128, i64{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shr_s_nozext_v2i64 (v128, i64) -> (v128){{$}}
 ; SIMD128-NEXT: i32.wrap/i64 $push[[L0:[0-9]+]]=, $1{{$}}
 ; SIMD128-NEXT: i64x2.shr_s $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @shr_s_nozext_v2i64(<2 x i64> %v, i64 %x) {
   %t = insertelement <2 x i64> undef, i64 %x, i32 0
   %s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
   %a = ashr <2 x i64> %v, %s
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: shr_s_const_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shr_s_const_v2i64 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 5{{$}}
 ; SIMD128-NEXT: i64x2.shr_s $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @shr_s_const_v2i64(<2 x i64> %v) {
   %a = ashr <2 x i64> %v, <i64 5, i64 5>
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: shr_s_vec_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shr_s_vec_v2i64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.extract_lane $push[[L0:[0-9]+]]=, $0, 0{{$}}
 ; SIMD128-NEXT: i64x2.extract_lane $push[[L1:[0-9]+]]=, $1, 0{{$}}
 ; SIMD128-NEXT: i64.shr_s $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; SIMD128-NEXT: i64x2.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
 ; SIMD128-NEXT: i64x2.extract_lane $push[[L4:[0-9]+]]=, $0, 1{{$}}
 ; SIMD128-NEXT: i64x2.extract_lane $push[[L5:[0-9]+]]=, $1, 1{{$}}
 ; SIMD128-NEXT: i64.shr_s $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}}
 ; SIMD128-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L3]], 1, $pop[[L6]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @shr_s_vec_v2i64(<2 x i64> %v, <2 x i64> %x) {
   %a = ashr <2 x i64> %v, %x
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: shr_u_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-NEXT: .param v128, i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shr_u_v2i64 (v128, i32) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.shr_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @shr_u_v2i64(<2 x i64> %v, i32 %x) {
   %x2 = zext i32 %x to i64
   %t = insertelement <2 x i64> undef, i64 %x2, i32 0
   %s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
   %a = lshr <2 x i64> %v, %s
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: shr_u_nozext_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-NEXT: .param v128, i64{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shr_u_nozext_v2i64 (v128, i64) -> (v128){{$}}
 ; SIMD128-NEXT: i32.wrap/i64 $push[[L0:[0-9]+]]=, $1{{$}}
 ; SIMD128-NEXT: i64x2.shr_u $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @shr_u_nozext_v2i64(<2 x i64> %v, i64 %x) {
   %t = insertelement <2 x i64> undef, i64 %x, i32 0
   %s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
   %a = lshr <2 x i64> %v, %s
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: shr_u_const_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shr_u_const_v2i64 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 5{{$}}
 ; SIMD128-NEXT: i64x2.shr_u $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @shr_u_const_v2i64(<2 x i64> %v) {
   %a = lshr <2 x i64> %v, <i64 5, i64 5>
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: shr_u_vec_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shr_u_vec_v2i64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.extract_lane $push[[L0:[0-9]+]]=, $0, 0{{$}}
 ; SIMD128-NEXT: i64x2.extract_lane $push[[L1:[0-9]+]]=, $1, 0{{$}}
 ; SIMD128-NEXT: i64.shr_u $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; SIMD128-NEXT: i64x2.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
 ; SIMD128-NEXT: i64x2.extract_lane $push[[L4:[0-9]+]]=, $0, 1{{$}}
 ; SIMD128-NEXT: i64x2.extract_lane $push[[L5:[0-9]+]]=, $1, 1{{$}}
 ; SIMD128-NEXT: i64.shr_u $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}}
 ; SIMD128-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L3]], 1, $pop[[L6]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @shr_u_vec_v2i64(<2 x i64> %v, <2 x i64> %x) {
   %a = lshr <2 x i64> %v, %x
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: and_v2i64:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype and_v2i64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @and_v2i64(<2 x i64> %x, <2 x i64> %y) {
   %a = and <2 x i64> %x, %y
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: or_v2i64:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype or_v2i64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @or_v2i64(<2 x i64> %x, <2 x i64> %y) {
   %a = or <2 x i64> %x, %y
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: xor_v2i64:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype xor_v2i64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.xor $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @xor_v2i64(<2 x i64> %x, <2 x i64> %y) {
   %a = xor <2 x i64> %x, %y
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: not_v2i64:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype not_v2i64 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @not_v2i64(<2 x i64> %x) {
   %a = xor <2 x i64> %x, <i64 -1, i64 -1>
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: bitselect_v2i64:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .param v128, v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype bitselect_v2i64 (v128, v128, v128) -> (v128){{$}}
 ; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
 ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
 ; SIMD128-FAST-NEXT: v128.not
 ; SIMD128-FAST-NEXT: v128.and
 ; SIMD128-FAST-NEXT: v128.and
 ; SIMD128-FAST-NEXT: v128.or
 ; SIMD128-FAST-NEXT: return
 define <2 x i64> @bitselect_v2i64(<2 x i64> %c, <2 x i64> %v1, <2 x i64> %v2) {
   %masked_v1 = and <2 x i64> %v1, %c
   %inv_mask = xor <2 x i64> <i64 -1, i64 -1>, %c
   %masked_v2 = and <2 x i64> %v2, %inv_mask
   %a = or <2 x i64> %masked_v2, %masked_v1
   ret <2 x i64> %a
 }
 
 ; ==============================================================================
 ; 4 x float
 ; ==============================================================================
 ; CHECK-LABEL: neg_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype neg_v4f32 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.neg $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @neg_v4f32(<4 x float> %x) {
   ; nsz makes this semantically equivalent to flipping sign bit
   %a = fsub nsz <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>, %x
   ret <4 x float> %a
 }
 
 ; CHECK-LABEL: abs_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype abs_v4f32 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.abs $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare <4 x float> @llvm.fabs.v4f32(<4 x float>) nounwind readnone
 define <4 x float> @abs_v4f32(<4 x float> %x) {
   %a = call <4 x float> @llvm.fabs.v4f32(<4 x float> %x)
   ret <4 x float> %a
 }
 
 ; CHECK-LABEL: min_unordered_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype min_unordered_v4f32 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32.const $push[[L0:[0-9]+]]=, 0x1.4p2
 ; SIMD128-NEXT: f32x4.splat $push[[L1:[0-9]+]]=, $pop[[L0]]
 ; SIMD128-NEXT: f32x4.min $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @min_unordered_v4f32(<4 x float> %x) {
   %cmps = fcmp ule <4 x float> %x, <float 5., float 5., float 5., float 5.>
   %a = select <4 x i1> %cmps, <4 x float> %x,
     <4 x float> <float 5., float 5., float 5., float 5.>
   ret <4 x float> %a
 }
 
 ; CHECK-LABEL: max_unordered_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype max_unordered_v4f32 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32.const $push[[L0:[0-9]+]]=, 0x1.4p2
 ; SIMD128-NEXT: f32x4.splat $push[[L1:[0-9]+]]=, $pop[[L0]]
 ; SIMD128-NEXT: f32x4.max $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @max_unordered_v4f32(<4 x float> %x) {
   %cmps = fcmp uge <4 x float> %x, <float 5., float 5., float 5., float 5.>
   %a = select <4 x i1> %cmps, <4 x float> %x,
     <4 x float> <float 5., float 5., float 5., float 5.>
   ret <4 x float> %a
 }
 
 ; CHECK-LABEL: min_ordered_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype min_ordered_v4f32 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32.const $push[[L0:[0-9]+]]=, 0x1.4p2
 ; SIMD128-NEXT: f32x4.splat $push[[L1:[0-9]+]]=, $pop[[L0]]
 ; SIMD128-NEXT: f32x4.min $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @min_ordered_v4f32(<4 x float> %x) {
   %cmps = fcmp ole <4 x float> <float 5., float 5., float 5., float 5.>, %x
   %a = select <4 x i1> %cmps,
     <4 x float> <float 5., float 5., float 5., float 5.>, <4 x float> %x
   ret <4 x float> %a
 }
 
 ; CHECK-LABEL: max_ordered_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype max_ordered_v4f32 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32.const $push[[L0:[0-9]+]]=, 0x1.4p2
 ; SIMD128-NEXT: f32x4.splat $push[[L1:[0-9]+]]=, $pop[[L0]]
 ; SIMD128-NEXT: f32x4.max $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @max_ordered_v4f32(<4 x float> %x) {
   %cmps = fcmp oge <4 x float> <float 5., float 5., float 5., float 5.>, %x
   %a = select <4 x i1> %cmps,
     <4 x float> <float 5., float 5., float 5., float 5.>, <4 x float> %x
   ret <4 x float> %a
 }
 
 ; CHECK-LABEL: min_intrinsic_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype min_intrinsic_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.min $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare <4 x float> @llvm.minimum.v4f32(<4 x float>, <4 x float>)
 define <4 x float> @min_intrinsic_v4f32(<4 x float> %x, <4 x float> %y) {
   %a = call <4 x float> @llvm.minimum.v4f32(<4 x float> %x, <4 x float> %y)
   ret <4 x float> %a
 }
 
 ; CHECK-LABEL: max_intrinsic_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype max_intrinsic_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.max $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare <4 x float> @llvm.maximum.v4f32(<4 x float>, <4 x float>)
 define <4 x float> @max_intrinsic_v4f32(<4 x float> %x, <4 x float> %y) {
   %a = call <4 x float> @llvm.maximum.v4f32(<4 x float> %x, <4 x float> %y)
   ret <4 x float> %a
 }
 
 ; CHECK-LABEL: min_const_intrinsic_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype min_const_intrinsic_v4f32 () -> (v128){{$}}
 ; SIMD128-NEXT: f32.const $push[[L:[0-9]+]]=, 0x1.4p2{{$}}
 ; SIMD128-NEXT: f32x4.splat $push[[R:[0-9]+]]=, $pop[[L]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @min_const_intrinsic_v4f32() {
   %a = call <4 x float> @llvm.minimum.v4f32(
     <4 x float> <float 42., float 42., float 42., float 42.>,
     <4 x float> <float 5., float 5., float 5., float 5.>
   )
   ret <4 x float> %a
 }
 
 ; CHECK-LABEL: max_const_intrinsic_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype max_const_intrinsic_v4f32 () -> (v128){{$}}
 ; SIMD128-NEXT: f32.const $push[[L:[0-9]+]]=, 0x1.5p5{{$}}
 ; SIMD128-NEXT: f32x4.splat $push[[R:[0-9]+]]=, $pop[[L]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @max_const_intrinsic_v4f32() {
   %a = call <4 x float> @llvm.maximum.v4f32(
     <4 x float> <float 42., float 42., float 42., float 42.>,
     <4 x float> <float 5., float 5., float 5., float 5.>
   )
   ret <4 x float> %a
 }
 
 ; CHECK-LABEL: add_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype add_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.add $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @add_v4f32(<4 x float> %x, <4 x float> %y) {
   %a = fadd <4 x float> %x, %y
   ret <4 x float> %a
 }
 
 ; CHECK-LABEL: sub_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype sub_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.sub $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @sub_v4f32(<4 x float> %x, <4 x float> %y) {
   %a = fsub <4 x float> %x, %y
   ret <4 x float> %a
 }
 
 ; CHECK-LABEL: div_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype div_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.div $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @div_v4f32(<4 x float> %x, <4 x float> %y) {
   %a = fdiv <4 x float> %x, %y
   ret <4 x float> %a
 }
 
 ; CHECK-LABEL: mul_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype mul_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.mul $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @mul_v4f32(<4 x float> %x, <4 x float> %y) {
   %a = fmul <4 x float> %x, %y
   ret <4 x float> %a
 }
 
 ; CHECK-LABEL: sqrt_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype sqrt_v4f32 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.sqrt $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare <4 x float> @llvm.sqrt.v4f32(<4 x float> %x)
 define <4 x float> @sqrt_v4f32(<4 x float> %x) {
   %a = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %x)
   ret <4 x float> %a
 }
 
 ; ==============================================================================
 ; 2 x double
 ; ==============================================================================
 ; CHECK-LABEL: neg_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype neg_v2f64 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.neg $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @neg_v2f64(<2 x double> %x) {
   ; nsz makes this semantically equivalent to flipping sign bit
   %a = fsub nsz <2 x double> <double 0., double 0.>, %x
   ret <2 x double> %a
 }
 
 ; CHECK-LABEL: abs_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype abs_v2f64 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.abs $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare <2 x double> @llvm.fabs.v2f64(<2 x double>) nounwind readnone
 define <2 x double> @abs_v2f64(<2 x double> %x) {
   %a = call <2 x double> @llvm.fabs.v2f64(<2 x double> %x)
   ret <2 x double> %a
 }
 
 ; CHECK-LABEL: min_unordered_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype min_unordered_v2f64 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64.const $push[[L0:[0-9]+]]=, 0x1.4p2
 ; SIMD128-NEXT: f64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]]
 ; SIMD128-NEXT: f64x2.min $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @min_unordered_v2f64(<2 x double> %x) {
   %cmps = fcmp ule <2 x double> %x, <double 5., double 5.>
   %a = select <2 x i1> %cmps, <2 x double> %x,
     <2 x double> <double 5., double 5.>
   ret <2 x double> %a
 }
 
 ; CHECK-LABEL: max_unordered_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype max_unordered_v2f64 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64.const $push[[L0:[0-9]+]]=, 0x1.4p2
 ; SIMD128-NEXT: f64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]]
 ; SIMD128-NEXT: f64x2.max $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @max_unordered_v2f64(<2 x double> %x) {
   %cmps = fcmp uge <2 x double> %x, <double 5., double 5.>
   %a = select <2 x i1> %cmps, <2 x double> %x,
     <2 x double> <double 5., double 5.>
   ret <2 x double> %a
 }
 
 ; CHECK-LABEL: min_ordered_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype min_ordered_v2f64 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64.const $push[[L0:[0-9]+]]=, 0x1.4p2
 ; SIMD128-NEXT: f64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]]
 ; SIMD128-NEXT: f64x2.min $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @min_ordered_v2f64(<2 x double> %x) {
   %cmps = fcmp ole <2 x double> <double 5., double 5.>, %x
   %a = select <2 x i1> %cmps, <2 x double> <double 5., double 5.>,
     <2 x double> %x
   ret <2 x double> %a
 }
 
 ; CHECK-LABEL: max_ordered_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype max_ordered_v2f64 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64.const $push[[L0:[0-9]+]]=, 0x1.4p2
 ; SIMD128-NEXT: f64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]]
 ; SIMD128-NEXT: f64x2.max $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @max_ordered_v2f64(<2 x double> %x) {
   %cmps = fcmp oge <2 x double> <double 5., double 5.>, %x
   %a = select <2 x i1> %cmps, <2 x double> <double 5., double 5.>,
     <2 x double> %x
   ret <2 x double> %a
 }
 
 ; CHECK-LABEL: min_intrinsic_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype min_intrinsic_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.min $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare <2 x double> @llvm.minimum.v2f64(<2 x double>, <2 x double>)
 define <2 x double> @min_intrinsic_v2f64(<2 x double> %x, <2 x double> %y) {
   %a = call <2 x double> @llvm.minimum.v2f64(<2 x double> %x, <2 x double> %y)
   ret <2 x double> %a
 }
 
 ; CHECK-LABEL: max_intrinsic_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype max_intrinsic_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.max $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare <2 x double> @llvm.maximum.v2f64(<2 x double>, <2 x double>)
 define <2 x double> @max_intrinsic_v2f64(<2 x double> %x, <2 x double> %y) {
   %a = call <2 x double> @llvm.maximum.v2f64(<2 x double> %x, <2 x double> %y)
   ret <2 x double> %a
 }
 
 ; CHECK-LABEL: min_const_intrinsic_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype min_const_intrinsic_v2f64 () -> (v128){{$}}
 ; SIMD128-NEXT: f64.const $push[[L:[0-9]+]]=, 0x1.4p2{{$}}
 ; SIMD128-NEXT: f64x2.splat $push[[R:[0-9]+]]=, $pop[[L]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @min_const_intrinsic_v2f64() {
   %a = call <2 x double> @llvm.minimum.v2f64(
     <2 x double> <double 42., double 42.>,
     <2 x double> <double 5., double 5.>
   )
   ret <2 x double> %a
 }
 
 ; CHECK-LABEL: max_const_intrinsic_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype max_const_intrinsic_v2f64 () -> (v128){{$}}
 ; SIMD128-NEXT: f64.const $push[[L:[0-9]+]]=, 0x1.5p5{{$}}
 ; SIMD128-NEXT: f64x2.splat $push[[R:[0-9]+]]=, $pop[[L]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @max_const_intrinsic_v2f64() {
   %a = call <2 x double> @llvm.maximum.v2f64(
     <2 x double> <double 42., double 42.>,
     <2 x double> <double 5., double 5.>
   )
   ret <2 x double> %a
 }
 
 ; CHECK-LABEL: add_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f62x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype add_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.add $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @add_v2f64(<2 x double> %x, <2 x double> %y) {
   %a = fadd <2 x double> %x, %y
   ret <2 x double> %a
 }
 
 ; CHECK-LABEL: sub_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f62x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype sub_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.sub $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @sub_v2f64(<2 x double> %x, <2 x double> %y) {
   %a = fsub <2 x double> %x, %y
   ret <2 x double> %a
 }
 
 ; CHECK-LABEL: div_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f62x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype div_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.div $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @div_v2f64(<2 x double> %x, <2 x double> %y) {
   %a = fdiv <2 x double> %x, %y
   ret <2 x double> %a
 }
 
 ; CHECK-LABEL: mul_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f62x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype mul_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.mul $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @mul_v2f64(<2 x double> %x, <2 x double> %y) {
   %a = fmul <2 x double> %x, %y
   ret <2 x double> %a
 }
 
 ; CHECK-LABEL: sqrt_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype sqrt_v2f64 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.sqrt $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare <2 x double> @llvm.sqrt.v2f64(<2 x double> %x)
 define <2 x double> @sqrt_v2f64(<2 x double> %x) {
   %a = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %x)
   ret <2 x double> %a
 }

test/CodeGen/WebAssembly/simd-comparisons.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128
 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128-VM
 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=-simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,NO-SIMD128
 
 ; Test SIMD comparison operators
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: compare_eq_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_eq_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i1> @compare_eq_v16i8 (<16 x i8> %x, <16 x i8> %y) {
   %res = icmp eq <16 x i8> %x, %y
   ret <16 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_eq_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_eq_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @compare_sext_eq_v16i8 (<16 x i8> %x, <16 x i8> %y) {
   %cmp = icmp eq <16 x i8> %x, %y
   %res = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %res
 }
 
 ; CHECK-LABEL: compare_ne_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_ne_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.ne $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i1> @compare_ne_v16i8 (<16 x i8> %x, <16 x i8> %y) {
   %res = icmp ne <16 x i8> %x, %y
   ret <16 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ne_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_ne_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.ne $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @compare_sext_ne_v16i8 (<16 x i8> %x, <16 x i8> %y) {
   %cmp = icmp ne <16 x i8> %x, %y
   %res = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %res
 }
 
 ; CHECK-LABEL: compare_slt_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_slt_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.lt_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i1> @compare_slt_v16i8 (<16 x i8> %x, <16 x i8> %y) {
   %res = icmp slt <16 x i8> %x, %y
   ret <16 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_slt_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_slt_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.lt_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @compare_sext_slt_v16i8 (<16 x i8> %x, <16 x i8> %y) {
   %cmp = icmp slt <16 x i8> %x, %y
   %res = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %res
 }
 
 ; CHECK-LABEL: compare_ult_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_ult_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.lt_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i1> @compare_ult_v16i8 (<16 x i8> %x, <16 x i8> %y) {
   %res = icmp ult <16 x i8> %x, %y
   ret <16 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ult_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_ult_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.lt_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @compare_sext_ult_v16i8 (<16 x i8> %x, <16 x i8> %y) {
   %cmp = icmp ult <16 x i8> %x, %y
   %res = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %res
 }
 
 ; CHECK-LABEL: compare_sle_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sle_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.le_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i1> @compare_sle_v16i8 (<16 x i8> %x, <16 x i8> %y) {
   %res = icmp sle <16 x i8> %x, %y
   ret <16 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_sle_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_sle_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.le_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @compare_sext_sle_v16i8 (<16 x i8> %x, <16 x i8> %y) {
   %cmp = icmp sle <16 x i8> %x, %y
   %res = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %res
 }
 
 ; CHECK-LABEL: compare_ule_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_ule_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.le_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i1> @compare_ule_v16i8 (<16 x i8> %x, <16 x i8> %y) {
   %res = icmp ule <16 x i8> %x, %y
   ret <16 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ule_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_ule_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.le_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @compare_sext_ule_v16i8 (<16 x i8> %x, <16 x i8> %y) {
   %cmp = icmp ule <16 x i8> %x, %y
   %res = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %res
 }
 
 ; CHECK-LABEL: compare_sgt_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sgt_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.gt_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i1> @compare_sgt_v16i8 (<16 x i8> %x, <16 x i8> %y) {
   %res = icmp sgt <16 x i8> %x, %y
   ret <16 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_sgt_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_sgt_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.gt_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @compare_sext_sgt_v16i8 (<16 x i8> %x, <16 x i8> %y) {
   %cmp = icmp sgt <16 x i8> %x, %y
   %res = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %res
 }
 
 ; CHECK-LABEL: compare_ugt_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_ugt_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.gt_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i1> @compare_ugt_v16i8 (<16 x i8> %x, <16 x i8> %y) {
   %res = icmp ugt <16 x i8> %x, %y
   ret <16 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ugt_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_ugt_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.gt_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @compare_sext_ugt_v16i8 (<16 x i8> %x, <16 x i8> %y) {
   %cmp = icmp ugt <16 x i8> %x, %y
   %res = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %res
 }
 
 ; CHECK-LABEL: compare_sge_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sge_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.ge_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i1> @compare_sge_v16i8 (<16 x i8> %x, <16 x i8> %y) {
   %res = icmp sge <16 x i8> %x, %y
   ret <16 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_sge_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_sge_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.ge_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @compare_sext_sge_v16i8 (<16 x i8> %x, <16 x i8> %y) {
   %cmp = icmp sge <16 x i8> %x, %y
   %res = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %res
 }
 
 ; CHECK-LABEL: compare_uge_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_uge_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.ge_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i1> @compare_uge_v16i8 (<16 x i8> %x, <16 x i8> %y) {
   %res = icmp uge <16 x i8> %x, %y
   ret <16 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_uge_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_uge_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.ge_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @compare_sext_uge_v16i8 (<16 x i8> %x, <16 x i8> %y) {
   %cmp = icmp uge <16 x i8> %x, %y
   %res = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %res
 }
 
 ; CHECK-LABEL: compare_eq_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_eq_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i1> @compare_eq_v8i16 (<8 x i16> %x, <8 x i16> %y) {
   %res = icmp eq <8 x i16> %x, %y
   ret <8 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_eq_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_eq_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @compare_sext_eq_v8i16 (<8 x i16> %x, <8 x i16> %y) {
   %cmp = icmp eq <8 x i16> %x, %y
   %res = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %res
 }
 
 ; CHECK-LABEL: compare_ne_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_ne_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.ne $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i1> @compare_ne_v8i16 (<8 x i16> %x, <8 x i16> %y) {
   %res = icmp ne <8 x i16> %x, %y
   ret <8 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ne_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_ne_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.ne $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @compare_sext_ne_v8i16 (<8 x i16> %x, <8 x i16> %y) {
   %cmp = icmp ne <8 x i16> %x, %y
   %res = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %res
 }
 
 ; CHECK-LABEL: compare_slt_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_slt_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.lt_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i1> @compare_slt_v8i16 (<8 x i16> %x, <8 x i16> %y) {
   %res = icmp slt <8 x i16> %x, %y
   ret <8 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_slt_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_slt_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.lt_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @compare_sext_slt_v8i16 (<8 x i16> %x, <8 x i16> %y) {
   %cmp = icmp slt <8 x i16> %x, %y
   %res = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %res
 }
 
 ; CHECK-LABEL: compare_ult_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_ult_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.lt_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i1> @compare_ult_v8i16 (<8 x i16> %x, <8 x i16> %y) {
   %res = icmp ult <8 x i16> %x, %y
   ret <8 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ult_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_ult_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.lt_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @compare_sext_ult_v8i16 (<8 x i16> %x, <8 x i16> %y) {
   %cmp = icmp ult <8 x i16> %x, %y
   %res = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %res
 }
 
 ; CHECK-LABEL: compare_sle_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sle_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.le_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i1> @compare_sle_v8i16 (<8 x i16> %x, <8 x i16> %y) {
   %res = icmp sle <8 x i16> %x, %y
   ret <8 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_sle_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_sle_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.le_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @compare_sext_sle_v8i16 (<8 x i16> %x, <8 x i16> %y) {
   %cmp = icmp sle <8 x i16> %x, %y
   %res = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %res
 }
 
 ; CHECK-LABEL: compare_ule_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_ule_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.le_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i1> @compare_ule_v8i16 (<8 x i16> %x, <8 x i16> %y) {
   %res = icmp ule <8 x i16> %x, %y
   ret <8 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ule_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_ule_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.le_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @compare_sext_ule_v8i16 (<8 x i16> %x, <8 x i16> %y) {
   %cmp = icmp ule <8 x i16> %x, %y
   %res = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %res
 }
 
 ; CHECK-LABEL: compare_sgt_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sgt_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.gt_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i1> @compare_sgt_v8i16 (<8 x i16> %x, <8 x i16> %y) {
   %res = icmp sgt <8 x i16> %x, %y
   ret <8 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_sgt_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_sgt_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.gt_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @compare_sext_sgt_v8i16 (<8 x i16> %x, <8 x i16> %y) {
   %cmp = icmp sgt <8 x i16> %x, %y
   %res = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %res
 }
 
 ; CHECK-LABEL: compare_ugt_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_ugt_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.gt_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i1> @compare_ugt_v8i16 (<8 x i16> %x, <8 x i16> %y) {
   %res = icmp ugt <8 x i16> %x, %y
   ret <8 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ugt_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_ugt_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.gt_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @compare_sext_ugt_v8i16 (<8 x i16> %x, <8 x i16> %y) {
   %cmp = icmp ugt <8 x i16> %x, %y
   %res = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %res
 }
 
 ; CHECK-LABEL: compare_sge_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sge_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.ge_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i1> @compare_sge_v8i16 (<8 x i16> %x, <8 x i16> %y) {
   %res = icmp sge <8 x i16> %x, %y
   ret <8 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_sge_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_sge_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.ge_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @compare_sext_sge_v8i16 (<8 x i16> %x, <8 x i16> %y) {
   %cmp = icmp sge <8 x i16> %x, %y
   %res = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %res
 }
 
 ; CHECK-LABEL: compare_uge_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_uge_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.ge_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i1> @compare_uge_v8i16 (<8 x i16> %x, <8 x i16> %y) {
   %res = icmp uge <8 x i16> %x, %y
   ret <8 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_uge_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_uge_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.ge_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @compare_sext_uge_v8i16 (<8 x i16> %x, <8 x i16> %y) {
   %cmp = icmp uge <8 x i16> %x, %y
   %res = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %res
 }
 
 ; CHECK-LABEL: compare_eq_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_eq_v4i32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i1> @compare_eq_v4i32 (<4 x i32> %x, <4 x i32> %y) {
   %res = icmp eq <4 x i32> %x, %y
   ret <4 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_eq_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_eq_v4i32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @compare_sext_eq_v4i32 (<4 x i32> %x, <4 x i32> %y) {
   %cmp = icmp eq <4 x i32> %x, %y
   %res = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: compare_ne_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_ne_v4i32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.ne $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i1> @compare_ne_v4i32 (<4 x i32> %x, <4 x i32> %y) {
   %res = icmp ne <4 x i32> %x, %y
   ret <4 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ne_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_ne_v4i32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.ne $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @compare_sext_ne_v4i32 (<4 x i32> %x, <4 x i32> %y) {
   %cmp = icmp ne <4 x i32> %x, %y
   %res = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: compare_slt_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_slt_v4i32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.lt_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i1> @compare_slt_v4i32 (<4 x i32> %x, <4 x i32> %y) {
   %res = icmp slt <4 x i32> %x, %y
   ret <4 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_slt_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_slt_v4i32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.lt_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @compare_sext_slt_v4i32 (<4 x i32> %x, <4 x i32> %y) {
   %cmp = icmp slt <4 x i32> %x, %y
   %res = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: compare_ult_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_ult_v4i32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.lt_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i1> @compare_ult_v4i32 (<4 x i32> %x, <4 x i32> %y) {
   %res = icmp ult <4 x i32> %x, %y
   ret <4 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ult_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_ult_v4i32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.lt_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @compare_sext_ult_v4i32 (<4 x i32> %x, <4 x i32> %y) {
   %cmp = icmp ult <4 x i32> %x, %y
   %res = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: compare_sle_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sle_v4i32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.le_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i1> @compare_sle_v4i32 (<4 x i32> %x, <4 x i32> %y) {
   %res = icmp sle <4 x i32> %x, %y
   ret <4 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_sle_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_sle_v4i32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.le_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @compare_sext_sle_v4i32 (<4 x i32> %x, <4 x i32> %y) {
   %cmp = icmp sle <4 x i32> %x, %y
   %res = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: compare_ule_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_ule_v4i32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.le_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i1> @compare_ule_v4i32 (<4 x i32> %x, <4 x i32> %y) {
   %res = icmp ule <4 x i32> %x, %y
   ret <4 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ule_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_ule_v4i32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.le_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @compare_sext_ule_v4i32 (<4 x i32> %x, <4 x i32> %y) {
   %cmp = icmp ule <4 x i32> %x, %y
   %res = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: compare_sgt_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sgt_v4i32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.gt_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i1> @compare_sgt_v4i32 (<4 x i32> %x, <4 x i32> %y) {
   %res = icmp sgt <4 x i32> %x, %y
   ret <4 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_sgt_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_sgt_v4i32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.gt_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @compare_sext_sgt_v4i32 (<4 x i32> %x, <4 x i32> %y) {
   %cmp = icmp sgt <4 x i32> %x, %y
   %res = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: compare_ugt_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_ugt_v4i32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.gt_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i1> @compare_ugt_v4i32 (<4 x i32> %x, <4 x i32> %y) {
   %res = icmp ugt <4 x i32> %x, %y
   ret <4 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ugt_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_ugt_v4i32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.gt_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @compare_sext_ugt_v4i32 (<4 x i32> %x, <4 x i32> %y) {
   %cmp = icmp ugt <4 x i32> %x, %y
   %res = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: compare_sge_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sge_v4i32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.ge_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i1> @compare_sge_v4i32 (<4 x i32> %x, <4 x i32> %y) {
   %res = icmp sge <4 x i32> %x, %y
   ret <4 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_sge_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_sge_v4i32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.ge_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @compare_sext_sge_v4i32 (<4 x i32> %x, <4 x i32> %y) {
   %cmp = icmp sge <4 x i32> %x, %y
   %res = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: compare_uge_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_uge_v4i32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.ge_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i1> @compare_uge_v4i32 (<4 x i32> %x, <4 x i32> %y) {
   %res = icmp uge <4 x i32> %x, %y
   ret <4 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_uge_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_uge_v4i32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.ge_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @compare_sext_uge_v4i32 (<4 x i32> %x, <4 x i32> %y) {
   %cmp = icmp uge <4 x i32> %x, %y
   %res = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: compare_oeq_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_oeq_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i1> @compare_oeq_v4f32 (<4 x float> %x, <4 x float> %y) {
   %res = fcmp oeq <4 x float> %x, %y
   ret <4 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_oeq_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_oeq_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @compare_sext_oeq_v4f32 (<4 x float> %x, <4 x float> %y) {
   %cmp = fcmp oeq <4 x float> %x, %y
   %res = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: compare_ogt_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_ogt_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.gt $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i1> @compare_ogt_v4f32 (<4 x float> %x, <4 x float> %y) {
   %res = fcmp ogt <4 x float> %x, %y
   ret <4 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ogt_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_ogt_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.gt $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @compare_sext_ogt_v4f32 (<4 x float> %x, <4 x float> %y) {
   %cmp = fcmp ogt <4 x float> %x, %y
   %res = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: compare_oge_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_oge_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.ge $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i1> @compare_oge_v4f32 (<4 x float> %x, <4 x float> %y) {
   %res = fcmp oge <4 x float> %x, %y
   ret <4 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_oge_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_oge_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.ge $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @compare_sext_oge_v4f32 (<4 x float> %x, <4 x float> %y) {
   %cmp = fcmp oge <4 x float> %x, %y
   %res = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: compare_olt_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_olt_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.lt $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i1> @compare_olt_v4f32 (<4 x float> %x, <4 x float> %y) {
   %res = fcmp olt <4 x float> %x, %y
   ret <4 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_olt_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_olt_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.lt $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @compare_sext_olt_v4f32 (<4 x float> %x, <4 x float> %y) {
   %cmp = fcmp olt <4 x float> %x, %y
   %res = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: compare_ole_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_ole_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.le $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i1> @compare_ole_v4f32 (<4 x float> %x, <4 x float> %y) {
   %res = fcmp ole <4 x float> %x, %y
   ret <4 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ole_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_ole_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.le $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @compare_sext_ole_v4f32 (<4 x float> %x, <4 x float> %y) {
   %cmp = fcmp ole <4 x float> %x, %y
   %res = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: compare_one_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_one_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.ne $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: f32x4.eq $push[[T1:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f32x4.eq $push[[T2:[0-9]+]]=, $1, $1{{$}}
 ; SIMD128-NEXT: v128.and $push[[T3:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
 ; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T3]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i1> @compare_one_v4f32 (<4 x float> %x, <4 x float> %y) {
   %res = fcmp one <4 x float> %x, %y
   ret <4 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_one_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_one_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.ne $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: f32x4.eq $push[[T1:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f32x4.eq $push[[T2:[0-9]+]]=, $1, $1{{$}}
 ; SIMD128-NEXT: v128.and $push[[T3:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
 ; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T3]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @compare_sext_one_v4f32 (<4 x float> %x, <4 x float> %y) {
   %cmp = fcmp one <4 x float> %x, %y
   %res = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: compare_ord_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_ord_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.eq $push[[T0:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f32x4.eq $push[[T1:[0-9]+]]=, $1, $1{{$}}
 ; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
 ; SIMD128-NEXT: return   $pop[[R]]{{$}}
 define <4 x i1> @compare_ord_v4f32 (<4 x float> %x, <4 x float> %y) {
   %res = fcmp ord <4 x float> %x, %y
   ret <4 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ord_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_ord_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.eq $push[[T0:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f32x4.eq $push[[T1:[0-9]+]]=, $1, $1{{$}}
 ; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
 ; SIMD128-NEXT: return   $pop[[R]]{{$}}
 define <4 x i32> @compare_sext_ord_v4f32 (<4 x float> %x, <4 x float> %y) {
   %cmp = fcmp ord <4 x float> %x, %y
   %res = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: compare_ueq_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_ueq_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.eq $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: f32x4.ne $push[[T1:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f32x4.ne $push[[T2:[0-9]+]]=, $1, $1{{$}}
 ; SIMD128-NEXT: v128.or $push[[T3:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
 ; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T3]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i1> @compare_ueq_v4f32 (<4 x float> %x, <4 x float> %y) {
   %res = fcmp ueq <4 x float> %x, %y
   ret <4 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ueq_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_ueq_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.eq $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: f32x4.ne $push[[T1:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f32x4.ne $push[[T2:[0-9]+]]=, $1, $1{{$}}
 ; SIMD128-NEXT: v128.or $push[[T3:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
 ; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T3]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]
 define <4 x i32> @compare_sext_ueq_v4f32 (<4 x float> %x, <4 x float> %y) {
   %cmp = fcmp ueq <4 x float> %x, %y
   %res = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: compare_ugt_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_ugt_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.le $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i1> @compare_ugt_v4f32 (<4 x float> %x, <4 x float> %y) {
   %res = fcmp ugt <4 x float> %x, %y
   ret <4 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ugt_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_ugt_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.le $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @compare_sext_ugt_v4f32 (<4 x float> %x, <4 x float> %y) {
   %cmp = fcmp ugt <4 x float> %x, %y
   %res = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: compare_uge_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_uge_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.lt $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i1> @compare_uge_v4f32 (<4 x float> %x, <4 x float> %y) {
   %res = fcmp uge <4 x float> %x, %y
   ret <4 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_uge_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_uge_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.lt $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @compare_sext_uge_v4f32 (<4 x float> %x, <4 x float> %y) {
   %cmp = fcmp uge <4 x float> %x, %y
   %res = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: compare_ult_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_ult_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.ge $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i1> @compare_ult_v4f32 (<4 x float> %x, <4 x float> %y) {
   %res = fcmp ult <4 x float> %x, %y
   ret <4 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ult_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_ult_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.ge $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @compare_sext_ult_v4f32 (<4 x float> %x, <4 x float> %y) {
   %cmp = fcmp ult <4 x float> %x, %y
   %res = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: compare_ule_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_ule_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.gt $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i1> @compare_ule_v4f32 (<4 x float> %x, <4 x float> %y) {
   %res = fcmp ule <4 x float> %x, %y
   ret <4 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ule_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_ule_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.gt $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @compare_sext_ule_v4f32 (<4 x float> %x, <4 x float> %y) {
   %cmp = fcmp ule <4 x float> %x, %y
   %res = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: compare_une_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_une_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.ne $push[[R:[0-9]+]]=, $0, $1{{$}}{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i1> @compare_une_v4f32 (<4 x float> %x, <4 x float> %y) {
   %res = fcmp une <4 x float> %x, %y
   ret <4 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_une_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_une_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.ne $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @compare_sext_une_v4f32 (<4 x float> %x, <4 x float> %y) {
   %cmp = fcmp une <4 x float> %x, %y
   %res = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: compare_uno_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_uno_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.ne $push[[T0:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f32x4.ne $push[[T1:[0-9]+]]=, $1, $1{{$}}
 ; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i1> @compare_uno_v4f32 (<4 x float> %x, <4 x float> %y) {
   %res = fcmp uno <4 x float> %x, %y
   ret <4 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_uno_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_uno_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.ne $push[[T0:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f32x4.ne $push[[T1:[0-9]+]]=, $1, $1{{$}}
 ; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @compare_sext_uno_v4f32 (<4 x float> %x, <4 x float> %y) {
   %cmp = fcmp uno <4 x float> %x, %y
   %res = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: compare_oeq_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_oeq_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_oeq_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp oeq <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_oeq_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_oeq_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_oeq_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp oeq <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_ogt_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_ogt_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.gt $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_ogt_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp ogt <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ogt_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_ogt_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.gt $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_ogt_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp ogt <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_oge_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_oge_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ge $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_oge_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp oge <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_oge_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_oge_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ge $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_oge_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp oge <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_olt_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_olt_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.lt $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_olt_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp olt <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_olt_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_olt_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.lt $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_olt_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp olt <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_ole_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_ole_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.le $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_ole_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp ole <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ole_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_ole_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.le $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_ole_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp ole <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_one_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_one_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T1:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T2:[0-9]+]]=, $1, $1{{$}}
 ; SIMD128-NEXT: v128.and $push[[T3:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
 ; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T3]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_one_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp one <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_one_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_one_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T1:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T2:[0-9]+]]=, $1, $1{{$}}
 ; SIMD128-NEXT: v128.and $push[[T3:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
 ; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T3]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_one_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp one <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_ord_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_ord_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T0:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T1:[0-9]+]]=, $1, $1{{$}}
 ; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
 ; SIMD128-NEXT: return   $pop[[R]]{{$}}
 define <2 x i1> @compare_ord_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp ord <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ord_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_ord_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T0:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T1:[0-9]+]]=, $1, $1{{$}}
 ; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
 ; SIMD128-NEXT: return   $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_ord_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp ord <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_ueq_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_ueq_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T1:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T2:[0-9]+]]=, $1, $1{{$}}
 ; SIMD128-NEXT: v128.or $push[[T3:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
 ; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T3]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_ueq_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp ueq <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ueq_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_ueq_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T1:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T2:[0-9]+]]=, $1, $1{{$}}
 ; SIMD128-NEXT: v128.or $push[[T3:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
 ; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T3]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_ueq_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp ueq <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_ugt_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_ugt_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.le $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_ugt_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp ugt <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ugt_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_ugt_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.le $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_ugt_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp ugt <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_uge_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_uge_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.lt $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_uge_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp uge <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_uge_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_uge_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.lt $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_uge_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp uge <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_ult_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_ult_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ge $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_ult_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp ult <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ult_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_ult_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ge $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_ult_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp ult <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_ule_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_ule_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.gt $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_ule_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp ule <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ule_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_ule_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.gt $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_ule_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp ule <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_une_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_une_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_une_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp une <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_une_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_une_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_une_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp une <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_uno_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_uno_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T0:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T1:[0-9]+]]=, $1, $1{{$}}
 ; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_uno_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp uno <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_uno_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype compare_sext_uno_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T0:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T1:[0-9]+]]=, $1, $1{{$}}
 ; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_uno_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp uno <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }

test/CodeGen/WebAssembly/simd-conversions.ll

 ; RUN: llc < %s -asm-verbose=false -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128
 ; RUN: llc < %s -asm-verbose=false -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128-VM
 ; RUN: llc < %s -asm-verbose=false -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=-simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,NO-SIMD128
 
 ; Test that vector float-to-int and int-to-float instructions lower correctly
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: convert_s_v4f32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype convert_s_v4f32 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.convert_s/i32x4 $push[[R:[0-9]+]]=, $0
 ; SIMD128-NEXT: return $pop[[R]]
 define <4 x float> @convert_s_v4f32(<4 x i32> %x) {
   %a = sitofp <4 x i32> %x to <4 x float>
   ret <4 x float> %a
 }
 
 ; CHECK-LABEL: convert_u_v4f32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype convert_u_v4f32 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.convert_u/i32x4 $push[[R:[0-9]+]]=, $0
 ; SIMD128-NEXT: return $pop[[R]]
 define <4 x float> @convert_u_v4f32(<4 x i32> %x) {
   %a = uitofp <4 x i32> %x to <4 x float>
   ret <4 x float> %a
 }
 
 ; CHECK-LABEL: convert_s_v2f64:
 ; NO-SIMD128-NOT: i64x2
 ; SIMD128-VM-NOT: f64x2.convert_s/i64x2
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype convert_s_v2f64 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.convert_s/i64x2 $push[[R:[0-9]+]]=, $0
 ; SIMD128-NEXT: return $pop[[R]]
 define <2 x double> @convert_s_v2f64(<2 x i64> %x) {
   %a = sitofp <2 x i64> %x to <2 x double>
   ret <2 x double> %a
 }
 
 ; CHECK-LABEL: convert_u_v2f64:
 ; NO-SIMD128-NOT: i64x2
 ; SIMD128-VM-NOT: f64x2.convert_u/i64x2
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype convert_u_v2f64 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.convert_u/i64x2 $push[[R:[0-9]+]]=, $0
 ; SIMD128-NEXT: return $pop[[R]]
 define <2 x double> @convert_u_v2f64(<2 x i64> %x) {
   %a = uitofp <2 x i64> %x to <2 x double>
   ret <2 x double> %a
 }
 
 ; CHECK-LABEL: trunc_sat_s_v4i32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype trunc_sat_s_v4i32 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.trunc_sat_s/f32x4 $push[[R:[0-9]+]]=, $0
 ; SIMD128-NEXT: return $pop[[R]]
 define <4 x i32> @trunc_sat_s_v4i32(<4 x float> %x) {
   %a = fptosi <4 x float> %x to <4 x i32>
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: trunc_sat_u_v4i32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype trunc_sat_u_v4i32 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.trunc_sat_u/f32x4 $push[[R:[0-9]+]]=, $0
 ; SIMD128-NEXT: return $pop[[R]]
 define <4 x i32> @trunc_sat_u_v4i32(<4 x float> %x) {
   %a = fptoui <4 x float> %x to <4 x i32>
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: trunc_sat_s_v2i64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: i64x2.trunc_sat_s/f64x2
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype trunc_sat_s_v2i64 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.trunc_sat_s/f64x2 $push[[R:[0-9]+]]=, $0
 ; SIMD128-NEXT: return $pop[[R]]
 define <2 x i64> @trunc_sat_s_v2i64(<2 x double> %x) {
   %a = fptosi <2 x double> %x to <2 x i64>
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: trunc_sat_u_v2i64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: i64x2.trunc_sat_u/f64x2
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype trunc_sat_u_v2i64 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.trunc_sat_u/f64x2 $push[[R:[0-9]+]]=, $0
 ; SIMD128-NEXT: return $pop[[R]]
 define <2 x i64> @trunc_sat_u_v2i64(<2 x double> %x) {
   %a = fptoui <2 x double> %x to <2 x i64>
   ret <2 x i64> %a
 }

test/CodeGen/WebAssembly/simd-ext-load-trunc-store.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128 | FileCheck %s
 
 ; Check that store in memory with smaller lanes are loaded and stored
 ; as expected. This is a regression test for part of bug 39275.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: load_ext_2xi32:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype load_ext_2xi32 (i32) -> (v128){{$}}
 ; CHECK-NEXT: i64.load32_u $push[[L0:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: i64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]]{{$}}
 ; CHECK-NEXT: i64.load32_u $push[[L2:[0-9]+]]=, 4($0){{$}}
 ; CHECK-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L1]], 1, $pop[[L2]]{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <2 x i32> @load_ext_2xi32(<2 x i32>* %p) {
   %1 = load <2 x i32>, <2 x i32>* %p, align 4
   ret <2 x i32> %1
 }
 
 ; CHECK-LABEL: load_zext_2xi32:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype load_zext_2xi32 (i32) -> (v128){{$}}
 ; CHECK-NEXT: i64.load32_u $push[[L0:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: i64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]]{{$}}
 ; CHECK-NEXT: i64.load32_u $push[[L2:[0-9]+]]=, 4($0){{$}}
 ; CHECK-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L1]], 1, $pop[[L2]]{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_zext_2xi32(<2 x i32>* %p) {
   %1 = load <2 x i32>, <2 x i32>* %p, align 4
   %2 = zext <2 x i32> %1 to <2 x i64>
   ret <2 x i64> %2
 }
 
 ; CHECK-LABEL: load_sext_2xi32:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype load_sext_2xi32 (i32) -> (v128){{$}}
 ; CHECK-NEXT: i64.load32_s $push[[L0:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: i64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]]{{$}}
 ; CHECK-NEXT: i64.load32_s $push[[L2:[0-9]+]]=, 4($0){{$}}
 ; CHECK-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L1]], 1, $pop[[L2]]{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_sext_2xi32(<2 x i32>* %p) {
   %1 = load <2 x i32>, <2 x i32>* %p, align 4
   %2 = sext <2 x i32> %1 to <2 x i64>
   ret <2 x i64> %2
 }
 
 ; CHECK-LABEL: store_trunc_2xi32:
-; CHECK-NEXT: .param i32, v128{{$}}
+; CHECK-NEXT: .functype store_trunc_2xi32 (i32, v128) -> (){{$}}
 ; CHECK-NEXT: i64x2.extract_lane $push[[L0:[0-9]+]]=, $1, 1
 ; CHECK-NEXT: i64.store32 4($0), $pop[[L0]]
 ; CHECK-NEXT: i64x2.extract_lane $push[[L1:[0-9]+]]=, $1, 0
 ; CHECK-NEXT: i64.store32 0($0), $pop[[L1]]
 ; CHECK-NEXT: return
 define void @store_trunc_2xi32(<2 x i32>* %p, <2 x i32> %x) {
   store <2 x i32> %x, <2 x i32>* %p, align 4
   ret void
 }

test/CodeGen/WebAssembly/simd-intrinsics.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128
 
 ; Test that SIMD128 intrinsics lower as expected. These intrinsics are
 ; only expected to lower successfully if the simd128 attribute is
 ; enabled and legal types are used.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; ==============================================================================
 ; 16 x i8
 ; ==============================================================================
 ; CHECK-LABEL: add_sat_s_v16i8:
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype add_sat_s_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.add_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8>, <16 x i8>)
 define <16 x i8> @add_sat_s_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y)
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: add_sat_u_v16i8:
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype add_sat_u_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.add_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8>, <16 x i8>)
 define <16 x i8> @add_sat_u_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y)
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: sub_sat_s_v16i8:
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype sub_sat_s_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.sub_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare <16 x i8> @llvm.wasm.sub.saturate.signed.v16i8(<16 x i8>, <16 x i8>)
 define <16 x i8> @sub_sat_s_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = call <16 x i8> @llvm.wasm.sub.saturate.signed.v16i8(
     <16 x i8> %x, <16 x i8> %y
   )
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: sub_sat_u_v16i8:
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype sub_sat_u_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.sub_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare <16 x i8> @llvm.wasm.sub.saturate.unsigned.v16i8(<16 x i8>, <16 x i8>)
 define <16 x i8> @sub_sat_u_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = call <16 x i8> @llvm.wasm.sub.saturate.unsigned.v16i8(
     <16 x i8> %x, <16 x i8> %y
   )
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: any_v16i8:
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: .functype any_v16i8 (v128) -> (i32){{$}}
 ; SIMD128-NEXT: i8x16.any_true $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.anytrue.v16i8(<16 x i8>)
 define i32 @any_v16i8(<16 x i8> %x) {
   %a = call i32 @llvm.wasm.anytrue.v16i8(<16 x i8> %x)
   ret i32 %a
 }
 
 ; CHECK-LABEL: all_v16i8:
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: .functype all_v16i8 (v128) -> (i32){{$}}
 ; SIMD128-NEXT: i8x16.all_true $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.alltrue.v16i8(<16 x i8>)
 define i32 @all_v16i8(<16 x i8> %x) {
   %a = call i32 @llvm.wasm.alltrue.v16i8(<16 x i8> %x)
   ret i32 %a
 }
 
 ; CHECK-LABEL: bitselect_v16i8:
-; SIMD128-NEXT: .param v128, v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype bitselect_v16i8 (v128, v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare <16 x i8> @llvm.wasm.bitselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
 define <16 x i8> @bitselect_v16i8(<16 x i8> %c, <16 x i8> %v1, <16 x i8> %v2) {
   %a = call <16 x i8> @llvm.wasm.bitselect.v16i8(
     <16 x i8> %c, <16 x i8> %v1, <16 x i8> %v2
   )
   ret <16 x i8> %a
 }
 
 ; ==============================================================================
 ; 8 x i16
 ; ==============================================================================
 ; CHECK-LABEL: add_sat_s_v8i16:
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype add_sat_s_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.add_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>)
 define <8 x i16> @add_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) {
   %a = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y)
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: add_sat_u_v8i16:
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype add_sat_u_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.add_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16>, <8 x i16>)
 define <8 x i16> @add_sat_u_v8i16(<8 x i16> %x, <8 x i16> %y) {
   %a = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y)
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: sub_sat_s_v8i16:
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype sub_sat_s_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.sub_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.wasm.sub.saturate.signed.v8i16(<8 x i16>, <8 x i16>)
 define <8 x i16> @sub_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) {
   %a = call <8 x i16> @llvm.wasm.sub.saturate.signed.v8i16(
     <8 x i16> %x, <8 x i16> %y
   )
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: sub_sat_u_v8i16:
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype sub_sat_u_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.sub_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.wasm.sub.saturate.unsigned.v8i16(<8 x i16>, <8 x i16>)
 define <8 x i16> @sub_sat_u_v8i16(<8 x i16> %x, <8 x i16> %y) {
   %a = call <8 x i16> @llvm.wasm.sub.saturate.unsigned.v8i16(
     <8 x i16> %x, <8 x i16> %y
   )
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: any_v8i16:
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: .functype any_v8i16 (v128) -> (i32){{$}}
 ; SIMD128-NEXT: i16x8.any_true $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.anytrue.v8i16(<8 x i16>)
 define i32 @any_v8i16(<8 x i16> %x) {
   %a = call i32 @llvm.wasm.anytrue.v8i16(<8 x i16> %x)
   ret i32 %a
 }
 
 ; CHECK-LABEL: all_v8i16:
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: .functype all_v8i16 (v128) -> (i32){{$}}
 ; SIMD128-NEXT: i16x8.all_true $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.alltrue.v8i16(<8 x i16>)
 define i32 @all_v8i16(<8 x i16> %x) {
   %a = call i32 @llvm.wasm.alltrue.v8i16(<8 x i16> %x)
   ret i32 %a
 }
 
 ; CHECK-LABEL: bitselect_v8i16:
-; SIMD128-NEXT: .param v128, v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype bitselect_v8i16 (v128, v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.wasm.bitselect.v8i16(<8 x i16>, <8 x i16>, <8 x i16>)
 define <8 x i16> @bitselect_v8i16(<8 x i16> %c, <8 x i16> %v1, <8 x i16> %v2) {
   %a = call <8 x i16> @llvm.wasm.bitselect.v8i16(
     <8 x i16> %c, <8 x i16> %v1, <8 x i16> %v2
   )
   ret <8 x i16> %a
 }
 
 ; ==============================================================================
 ; 4 x i32
 ; ==============================================================================
 ; CHECK-LABEL: any_v4i32:
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: .functype any_v4i32 (v128) -> (i32){{$}}
 ; SIMD128-NEXT: i32x4.any_true $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.anytrue.v4i32(<4 x i32>)
 define i32 @any_v4i32(<4 x i32> %x) {
   %a = call i32 @llvm.wasm.anytrue.v4i32(<4 x i32> %x)
   ret i32 %a
 }
 
 ; CHECK-LABEL: all_v4i32:
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: .functype all_v4i32 (v128) -> (i32){{$}}
 ; SIMD128-NEXT: i32x4.all_true $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.alltrue.v4i32(<4 x i32>)
 define i32 @all_v4i32(<4 x i32> %x) {
   %a = call i32 @llvm.wasm.alltrue.v4i32(<4 x i32> %x)
   ret i32 %a
 }
 
 ; CHECK-LABEL: bitselect_v4i32:
-; SIMD128-NEXT: .param v128, v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype bitselect_v4i32 (v128, v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare <4 x i32> @llvm.wasm.bitselect.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
 define <4 x i32> @bitselect_v4i32(<4 x i32> %c, <4 x i32> %v1, <4 x i32> %v2) {
   %a = call <4 x i32> @llvm.wasm.bitselect.v4i32(
     <4 x i32> %c, <4 x i32> %v1, <4 x i32> %v2
   )
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: trunc_sat_s_v4i32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype trunc_sat_s_v4i32 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.trunc_sat_s/f32x4 $push[[R:[0-9]+]]=, $0
 ; SIMD128-NEXT: return $pop[[R]]
 declare <4 x i32> @llvm.wasm.trunc.saturate.signed.v4i32.v4f32(<4 x float>)
 define <4 x i32> @trunc_sat_s_v4i32(<4 x float> %x) {
   %a = call <4 x i32> @llvm.wasm.trunc.saturate.signed.v4i32.v4f32(<4 x float> %x)
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: trunc_sat_u_v4i32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype trunc_sat_u_v4i32 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.trunc_sat_u/f32x4 $push[[R:[0-9]+]]=, $0
 ; SIMD128-NEXT: return $pop[[R]]
 declare <4 x i32> @llvm.wasm.trunc.saturate.unsigned.v4i32.v4f32(<4 x float>)
 define <4 x i32> @trunc_sat_u_v4i32(<4 x float> %x) {
   %a = call <4 x i32> @llvm.wasm.trunc.saturate.unsigned.v4i32.v4f32(<4 x float> %x)
   ret <4 x i32> %a
 }
 
 ; ==============================================================================
 ; 2 x i64
 ; ==============================================================================
 ; CHECK-LABEL: any_v2i64:
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: .functype any_v2i64 (v128) -> (i32){{$}}
 ; SIMD128-NEXT: i64x2.any_true $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.anytrue.v2i64(<2 x i64>)
 define i32 @any_v2i64(<2 x i64> %x) {
   %a = call i32 @llvm.wasm.anytrue.v2i64(<2 x i64> %x)
   ret i32 %a
 }
 
 ; CHECK-LABEL: all_v2i64:
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: .functype all_v2i64 (v128) -> (i32){{$}}
 ; SIMD128-NEXT: i64x2.all_true $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.alltrue.v2i64(<2 x i64>)
 define i32 @all_v2i64(<2 x i64> %x) {
   %a = call i32 @llvm.wasm.alltrue.v2i64(<2 x i64> %x)
   ret i32 %a
 }
 
 ; CHECK-LABEL: bitselect_v2i64:
-; SIMD128-NEXT: .param v128, v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype bitselect_v2i64 (v128, v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare <2 x i64> @llvm.wasm.bitselect.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)
 define <2 x i64> @bitselect_v2i64(<2 x i64> %c, <2 x i64> %v1, <2 x i64> %v2) {
   %a = call <2 x i64> @llvm.wasm.bitselect.v2i64(
     <2 x i64> %c, <2 x i64> %v1, <2 x i64> %v2
   )
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: trunc_sat_s_v2i64:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype trunc_sat_s_v2i64 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.trunc_sat_s/f64x2 $push[[R:[0-9]+]]=, $0
 ; SIMD128-NEXT: return $pop[[R]]
 declare <2 x i64> @llvm.wasm.trunc.saturate.signed.v2i64.v2f64(<2 x double>)
 define <2 x i64> @trunc_sat_s_v2i64(<2 x double> %x) {
   %a = call <2 x i64> @llvm.wasm.trunc.saturate.signed.v2i64.v2f64(<2 x double> %x)
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: trunc_sat_u_v2i64:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype trunc_sat_u_v2i64 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.trunc_sat_u/f64x2 $push[[R:[0-9]+]]=, $0
 ; SIMD128-NEXT: return $pop[[R]]
 declare <2 x i64> @llvm.wasm.trunc.saturate.unsigned.v2i64.v2f64(<2 x double>)
 define <2 x i64> @trunc_sat_u_v2i64(<2 x double> %x) {
   %a = call <2 x i64> @llvm.wasm.trunc.saturate.unsigned.v2i64.v2f64(<2 x double> %x)
   ret <2 x i64> %a
 }
 
 ; ==============================================================================
 ; 4 x f32
 ; ==============================================================================
 ; CHECK-LABEL: bitselect_v4f32:
-; SIMD128-NEXT: .param v128, v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype bitselect_v4f32 (v128, v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare <4 x float> @llvm.wasm.bitselect.v4f32(<4 x float>, <4 x float>, <4 x float>)
 define <4 x float> @bitselect_v4f32(<4 x float> %c, <4 x float> %v1, <4 x float> %v2) {
   %a = call <4 x float> @llvm.wasm.bitselect.v4f32(
     <4 x float> %c, <4 x float> %v1, <4 x float> %v2
   )
   ret <4 x float> %a
 }
 
 ; ==============================================================================
 ; 2 x f64
 ; ==============================================================================
 ; CHECK-LABEL: bitselect_v2f64:
-; SIMD128-NEXT: .param v128, v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype bitselect_v2f64 (v128, v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare <2 x double> @llvm.wasm.bitselect.v2f64(<2 x double>, <2 x double>, <2 x double>)
 define <2 x double> @bitselect_v2f64(<2 x double> %c, <2 x double> %v1, <2 x double> %v2) {
   %a = call <2 x double> @llvm.wasm.bitselect.v2f64(
     <2 x double> %c, <2 x double> %v1, <2 x double> %v2
   )
   ret <2 x double> %a
 }

test/CodeGen/WebAssembly/simd-load-store-alignment.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128 | FileCheck %s
 
 ; Test loads and stores with custom alignment values.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; ==============================================================================
 ; 16 x i8
 ; ==============================================================================
 
 ; CHECK-LABEL: load_v16i8_a1:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype load_v16i8_a1 (i32) -> (v128){{$}}
 ; CHECK-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0):p2align=0{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @load_v16i8_a1(<16 x i8> *%p) {
   %v = load <16 x i8>, <16 x i8>* %p, align 1
   ret <16 x i8> %v
 }
 
 ; CHECK-LABEL: load_v16i8_a4:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype load_v16i8_a4 (i32) -> (v128){{$}}
 ; CHECK-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0):p2align=2{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @load_v16i8_a4(<16 x i8> *%p) {
   %v = load <16 x i8>, <16 x i8>* %p, align 4
   ret <16 x i8> %v
 }
 
 ; 16 is the default alignment for v128 so no attribute is needed.
 
 ; CHECK-LABEL: load_v16i8_a16:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype load_v16i8_a16 (i32) -> (v128){{$}}
 ; CHECK-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @load_v16i8_a16(<16 x i8> *%p) {
   %v = load <16 x i8>, <16 x i8>* %p, align 16
   ret <16 x i8> %v
 }
 
 ; 32 is greater than the default alignment so it is ignored.
 
 ; CHECK-LABEL: load_v16i8_a32:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype load_v16i8_a32 (i32) -> (v128){{$}}
 ; CHECK-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @load_v16i8_a32(<16 x i8> *%p) {
   %v = load <16 x i8>, <16 x i8>* %p, align 32
   ret <16 x i8> %v
 }
 
 ; CHECK-LABEL: store_v16i8_a1:
-; CHECK-NEXT: .param i32, v128{{$}}
+; CHECK-NEXT: .functype store_v16i8_a1 (i32, v128) -> (){{$}}
 ; CHECK-NEXT: v128.store 0($0):p2align=0, $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_v16i8_a1(<16 x i8> *%p, <16 x i8> %v) {
   store <16 x i8> %v, <16 x i8>* %p, align 1
   ret void
 }
 
 ; CHECK-LABEL: store_v16i8_a4:
-; CHECK-NEXT: .param i32, v128{{$}}
+; CHECK-NEXT: .functype store_v16i8_a4 (i32, v128) -> (){{$}}
 ; CHECK-NEXT: v128.store 0($0):p2align=2, $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_v16i8_a4(<16 x i8> *%p, <16 x i8> %v) {
   store <16 x i8> %v, <16 x i8>* %p, align 4
   ret void
 }
 
 ; 16 is the default alignment for v128 so no attribute is needed.
 
 ; CHECK-LABEL: store_v16i8_a16:
-; CHECK-NEXT: .param i32, v128{{$}}
+; CHECK-NEXT: .functype store_v16i8_a16 (i32, v128) -> (){{$}}
 ; CHECK-NEXT: v128.store 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_v16i8_a16(<16 x i8> *%p, <16 x i8> %v) {
   store <16 x i8> %v, <16 x i8>* %p, align 16
   ret void
 }
 
 ; 32 is greater than the default alignment so it is ignored.
 
 ; CHECK-LABEL: store_v16i8_a32:
-; CHECK-NEXT: .param i32, v128{{$}}
+; CHECK-NEXT: .functype store_v16i8_a32 (i32, v128) -> (){{$}}
 ; CHECK-NEXT: v128.store 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_v16i8_a32(<16 x i8> *%p, <16 x i8> %v) {
   store <16 x i8> %v, <16 x i8>* %p, align 32
   ret void
 }
 
 ; ==============================================================================
 ; 8 x i16
 ; ==============================================================================
 
 ; CHECK-LABEL: load_v8i16_a1:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype load_v8i16_a1 (i32) -> (v128){{$}}
 ; CHECK-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0):p2align=0{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @load_v8i16_a1(<8 x i16> *%p) {
   %v = load <8 x i16>, <8 x i16>* %p, align 1
   ret <8 x i16> %v
 }
 
 ; CHECK-LABEL: load_v8i16_a4:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype load_v8i16_a4 (i32) -> (v128){{$}}
 ; CHECK-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0):p2align=2{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @load_v8i16_a4(<8 x i16> *%p) {
   %v = load <8 x i16>, <8 x i16>* %p, align 4
   ret <8 x i16> %v
 }
 
 ; 8 is the default alignment for v128 so no attribute is needed.
 
 ; CHECK-LABEL: load_v8i16_a16:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype load_v8i16_a16 (i32) -> (v128){{$}}
 ; CHECK-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @load_v8i16_a16(<8 x i16> *%p) {
   %v = load <8 x i16>, <8 x i16>* %p, align 16
   ret <8 x i16> %v
 }
 
 ; 32 is greater than the default alignment so it is ignored.
 
 ; CHECK-LABEL: load_v8i16_a32:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype load_v8i16_a32 (i32) -> (v128){{$}}
 ; CHECK-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @load_v8i16_a32(<8 x i16> *%p) {
   %v = load <8 x i16>, <8 x i16>* %p, align 32
   ret <8 x i16> %v
 }
 
 ; CHECK-LABEL: store_v8i16_a1:
-; CHECK-NEXT: .param i32, v128{{$}}
+; CHECK-NEXT: .functype store_v8i16_a1 (i32, v128) -> (){{$}}
 ; CHECK-NEXT: v128.store 0($0):p2align=0, $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_v8i16_a1(<8 x i16> *%p, <8 x i16> %v) {
   store <8 x i16> %v, <8 x i16>* %p, align 1
   ret void
 }
 
 ; CHECK-LABEL: store_v8i16_a4:
-; CHECK-NEXT: .param i32, v128{{$}}
+; CHECK-NEXT: .functype store_v8i16_a4 (i32, v128) -> (){{$}}
 ; CHECK-NEXT: v128.store 0($0):p2align=2, $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_v8i16_a4(<8 x i16> *%p, <8 x i16> %v) {
   store <8 x i16> %v, <8 x i16>* %p, align 4
   ret void
 }
 
 ; 16 is the default alignment for v128 so no attribute is needed.
 
 ; CHECK-LABEL: store_v8i16_a16:
-; CHECK-NEXT: .param i32, v128{{$}}
+; CHECK-NEXT: .functype store_v8i16_a16 (i32, v128) -> (){{$}}
 ; CHECK-NEXT: v128.store 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_v8i16_a16(<8 x i16> *%p, <8 x i16> %v) {
   store <8 x i16> %v, <8 x i16>* %p, align 16
   ret void
 }
 
 ; 32 is greater than the default alignment so it is ignored.
 
 ; CHECK-LABEL: store_v8i16_a32:
-; CHECK-NEXT: .param i32, v128{{$}}
+; CHECK-NEXT: .functype store_v8i16_a32 (i32, v128) -> (){{$}}
 ; CHECK-NEXT: v128.store 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_v8i16_a32(<8 x i16> *%p, <8 x i16> %v) {
   store <8 x i16> %v, <8 x i16>* %p, align 32
   ret void
 }
 
 ; ==============================================================================
 ; 4 x i32
 ; ==============================================================================
 
 ; CHECK-LABEL: load_v4i32_a1:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype load_v4i32_a1 (i32) -> (v128){{$}}
 ; CHECK-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0):p2align=0{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @load_v4i32_a1(<4 x i32> *%p) {
   %v = load <4 x i32>, <4 x i32>* %p, align 1
   ret <4 x i32> %v
 }
 
 ; CHECK-LABEL: load_v4i32_a4:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype load_v4i32_a4 (i32) -> (v128){{$}}
 ; CHECK-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0):p2align=2{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @load_v4i32_a4(<4 x i32> *%p) {
   %v = load <4 x i32>, <4 x i32>* %p, align 4
   ret <4 x i32> %v
 }
 
 ; 4 is the default alignment for v128 so no attribute is needed.
 
 ; CHECK-LABEL: load_v4i32_a16:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype load_v4i32_a16 (i32) -> (v128){{$}}
 ; CHECK-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @load_v4i32_a16(<4 x i32> *%p) {
   %v = load <4 x i32>, <4 x i32>* %p, align 16
   ret <4 x i32> %v
 }
 
 ; 32 is greater than the default alignment so it is ignored.
 
 ; CHECK-LABEL: load_v4i32_a32:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype load_v4i32_a32 (i32) -> (v128){{$}}
 ; CHECK-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @load_v4i32_a32(<4 x i32> *%p) {
   %v = load <4 x i32>, <4 x i32>* %p, align 32
   ret <4 x i32> %v
 }
 
 ; CHECK-LABEL: store_v4i32_a1:
-; CHECK-NEXT: .param i32, v128{{$}}
+; CHECK-NEXT: .functype store_v4i32_a1 (i32, v128) -> (){{$}}
 ; CHECK-NEXT: v128.store 0($0):p2align=0, $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_v4i32_a1(<4 x i32> *%p, <4 x i32> %v) {
   store <4 x i32> %v, <4 x i32>* %p, align 1
   ret void
 }
 
 ; CHECK-LABEL: store_v4i32_a4:
-; CHECK-NEXT: .param i32, v128{{$}}
+; CHECK-NEXT: .functype store_v4i32_a4 (i32, v128) -> (){{$}}
 ; CHECK-NEXT: v128.store 0($0):p2align=2, $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_v4i32_a4(<4 x i32> *%p, <4 x i32> %v) {
   store <4 x i32> %v, <4 x i32>* %p, align 4
   ret void
 }
 
 ; 16 is the default alignment for v128 so no attribute is needed.
 
 ; CHECK-LABEL: store_v4i32_a16:
-; CHECK-NEXT: .param i32, v128{{$}}
+; CHECK-NEXT: .functype store_v4i32_a16 (i32, v128) -> (){{$}}
 ; CHECK-NEXT: v128.store 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_v4i32_a16(<4 x i32> *%p, <4 x i32> %v) {
   store <4 x i32> %v, <4 x i32>* %p, align 16
   ret void
 }
 
 ; 32 is greater than the default alignment so it is ignored.
 
 ; CHECK-LABEL: store_v4i32_a32:
-; CHECK-NEXT: .param i32, v128{{$}}
+; CHECK-NEXT: .functype store_v4i32_a32 (i32, v128) -> (){{$}}
 ; CHECK-NEXT: v128.store 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_v4i32_a32(<4 x i32> *%p, <4 x i32> %v) {
   store <4 x i32> %v, <4 x i32>* %p, align 32
   ret void
 }
 
 ; ==============================================================================
 ; 2 x i64
 ; ==============================================================================
 
 ; CHECK-LABEL: load_v2i64_a1:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype load_v2i64_a1 (i32) -> (v128){{$}}
 ; CHECK-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0):p2align=0{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_v2i64_a1(<2 x i64> *%p) {
   %v = load <2 x i64>, <2 x i64>* %p, align 1
   ret <2 x i64> %v
 }
 
 ; CHECK-LABEL: load_v2i64_a4:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype load_v2i64_a4 (i32) -> (v128){{$}}
 ; CHECK-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0):p2align=2{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_v2i64_a4(<2 x i64> *%p) {
   %v = load <2 x i64>, <2 x i64>* %p, align 4
   ret <2 x i64> %v
 }
 
 ; 2 is the default alignment for v128 so no attribute is needed.
 
 ; CHECK-LABEL: load_v2i64_a16:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype load_v2i64_a16 (i32) -> (v128){{$}}
 ; CHECK-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_v2i64_a16(<2 x i64> *%p) {
   %v = load <2 x i64>, <2 x i64>* %p, align 16
   ret <2 x i64> %v
 }
 
 ; 32 is greater than the default alignment so it is ignored.
 
 ; CHECK-LABEL: load_v2i64_a32:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype load_v2i64_a32 (i32) -> (v128){{$}}
 ; CHECK-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_v2i64_a32(<2 x i64> *%p) {
   %v = load <2 x i64>, <2 x i64>* %p, align 32
   ret <2 x i64> %v
 }
 
 ; CHECK-LABEL: store_v2i64_a1:
-; CHECK-NEXT: .param i32, v128{{$}}
+; CHECK-NEXT: .functype store_v2i64_a1 (i32, v128) -> (){{$}}
 ; CHECK-NEXT: v128.store 0($0):p2align=0, $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_v2i64_a1(<2 x i64> *%p, <2 x i64> %v) {
   store <2 x i64> %v, <2 x i64>* %p, align 1
   ret void
 }
 
 ; CHECK-LABEL: store_v2i64_a4:
-; CHECK-NEXT: .param i32, v128{{$}}
+; CHECK-NEXT: .functype store_v2i64_a4 (i32, v128) -> (){{$}}
 ; CHECK-NEXT: v128.store 0($0):p2align=2, $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_v2i64_a4(<2 x i64> *%p, <2 x i64> %v) {
   store <2 x i64> %v, <2 x i64>* %p, align 4
   ret void
 }
 
 ; 16 is the default alignment for v128 so no attribute is needed.
 
 ; CHECK-LABEL: store_v2i64_a16:
-; CHECK-NEXT: .param i32, v128{{$}}
+; CHECK-NEXT: .functype store_v2i64_a16 (i32, v128) -> (){{$}}
 ; CHECK-NEXT: v128.store 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_v2i64_a16(<2 x i64> *%p, <2 x i64> %v) {
   store <2 x i64> %v, <2 x i64>* %p, align 16
   ret void
 }
 
 ; 32 is greater than the default alignment so it is ignored.
 
 ; CHECK-LABEL: store_v2i64_a32:
-; CHECK-NEXT: .param i32, v128{{$}}
+; CHECK-NEXT: .functype store_v2i64_a32 (i32, v128) -> (){{$}}
 ; CHECK-NEXT: v128.store 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_v2i64_a32(<2 x i64> *%p, <2 x i64> %v) {
   store <2 x i64> %v, <2 x i64>* %p, align 32
   ret void
 }
 
 ; ==============================================================================
 ; 4 x float
 ; ==============================================================================
 
 ; CHECK-LABEL: load_v4f32_a1:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype load_v4f32_a1 (i32) -> (v128){{$}}
 ; CHECK-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0):p2align=0{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @load_v4f32_a1(<4 x float> *%p) {
   %v = load <4 x float>, <4 x float>* %p, align 1
   ret <4 x float> %v
 }
 
 ; CHECK-LABEL: load_v4f32_a4:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype load_v4f32_a4 (i32) -> (v128){{$}}
 ; CHECK-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0):p2align=2{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @load_v4f32_a4(<4 x float> *%p) {
   %v = load <4 x float>, <4 x float>* %p, align 4
   ret <4 x float> %v
 }
 
 ; 4 is the default alignment for v128 so no attribute is needed.
 
 ; CHECK-LABEL: load_v4f32_a16:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype load_v4f32_a16 (i32) -> (v128){{$}}
 ; CHECK-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @load_v4f32_a16(<4 x float> *%p) {
   %v = load <4 x float>, <4 x float>* %p, align 16
   ret <4 x float> %v
 }
 
 ; 32 is greater than the default alignment so it is ignored.
 
 ; CHECK-LABEL: load_v4f32_a32:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype load_v4f32_a32 (i32) -> (v128){{$}}
 ; CHECK-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @load_v4f32_a32(<4 x float> *%p) {
   %v = load <4 x float>, <4 x float>* %p, align 32
   ret <4 x float> %v
 }
 
 ; CHECK-LABEL: store_v4f32_a1:
-; CHECK-NEXT: .param i32, v128{{$}}
+; CHECK-NEXT: .functype store_v4f32_a1 (i32, v128) -> (){{$}}
 ; CHECK-NEXT: v128.store 0($0):p2align=0, $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_v4f32_a1(<4 x float> *%p, <4 x float> %v) {
   store <4 x float> %v, <4 x float>* %p, align 1
   ret void
 }
 
 ; CHECK-LABEL: store_v4f32_a4:
-; CHECK-NEXT: .param i32, v128{{$}}
+; CHECK-NEXT: .functype store_v4f32_a4 (i32, v128) -> (){{$}}
 ; CHECK-NEXT: v128.store 0($0):p2align=2, $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_v4f32_a4(<4 x float> *%p, <4 x float> %v) {
   store <4 x float> %v, <4 x float>* %p, align 4
   ret void
 }
 
 ; 16 is the default alignment for v128 so no attribute is needed.
 
 ; CHECK-LABEL: store_v4f32_a16:
-; CHECK-NEXT: .param i32, v128{{$}}
+; CHECK-NEXT: .functype store_v4f32_a16 (i32, v128) -> (){{$}}
 ; CHECK-NEXT: v128.store 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_v4f32_a16(<4 x float> *%p, <4 x float> %v) {
   store <4 x float> %v, <4 x float>* %p, align 16
   ret void
 }
 
 ; 32 is greater than the default alignment so it is ignored.
 
 ; CHECK-LABEL: store_v4f32_a32:
-; CHECK-NEXT: .param i32, v128{{$}}
+; CHECK-NEXT: .functype store_v4f32_a32 (i32, v128) -> (){{$}}
 ; CHECK-NEXT: v128.store 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_v4f32_a32(<4 x float> *%p, <4 x float> %v) {
   store <4 x float> %v, <4 x float>* %p, align 32
   ret void
 }
 
 ; ==============================================================================
 ; 2 x double
 ; ==============================================================================
 
 ; CHECK-LABEL: load_v2f64_a1:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype load_v2f64_a1 (i32) -> (v128){{$}}
 ; CHECK-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0):p2align=0{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @load_v2f64_a1(<2 x double> *%p) {
   %v = load <2 x double>, <2 x double>* %p, align 1
   ret <2 x double> %v
 }
 
 ; CHECK-LABEL: load_v2f64_a4:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype load_v2f64_a4 (i32) -> (v128){{$}}
 ; CHECK-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0):p2align=2{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @load_v2f64_a4(<2 x double> *%p) {
   %v = load <2 x double>, <2 x double>* %p, align 4
   ret <2 x double> %v
 }
 
 ; 2 is the default alignment for v128 so no attribute is needed.
 
 ; CHECK-LABEL: load_v2f64_a16:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype load_v2f64_a16 (i32) -> (v128){{$}}
 ; CHECK-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @load_v2f64_a16(<2 x double> *%p) {
   %v = load <2 x double>, <2 x double>* %p, align 16
   ret <2 x double> %v
 }
 
 ; 32 is greater than the default alignment so it is ignored.
 
 ; CHECK-LABEL: load_v2f64_a32:
-; CHECK-NEXT: .param i32{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype load_v2f64_a32 (i32) -> (v128){{$}}
 ; CHECK-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @load_v2f64_a32(<2 x double> *%p) {
   %v = load <2 x double>, <2 x double>* %p, align 32
   ret <2 x double> %v
 }
 
 ; CHECK-LABEL: store_v2f64_a1:
-; CHECK-NEXT: .param i32, v128{{$}}
+; CHECK-NEXT: .functype store_v2f64_a1 (i32, v128) -> (){{$}}
 ; CHECK-NEXT: v128.store 0($0):p2align=0, $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_v2f64_a1(<2 x double> *%p, <2 x double> %v) {
   store <2 x double> %v, <2 x double>* %p, align 1
   ret void
 }
 
 ; CHECK-LABEL: store_v2f64_a4:
-; CHECK-NEXT: .param i32, v128{{$}}
+; CHECK-NEXT: .functype store_v2f64_a4 (i32, v128) -> (){{$}}
 ; CHECK-NEXT: v128.store 0($0):p2align=2, $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_v2f64_a4(<2 x double> *%p, <2 x double> %v) {
   store <2 x double> %v, <2 x double>* %p, align 4
   ret void
 }
 
 ; 16 is the default alignment for v128 so no attribute is needed.
 
 ; CHECK-LABEL: store_v2f64_a16:
-; CHECK-NEXT: .param i32, v128{{$}}
+; CHECK-NEXT: .functype store_v2f64_a16 (i32, v128) -> (){{$}}
 ; CHECK-NEXT: v128.store 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_v2f64_a16(<2 x double> *%p, <2 x double> %v) {
   store <2 x double> %v, <2 x double>* %p, align 16
   ret void
 }
 
 ; 32 is greater than the default alignment so it is ignored.
 
 ; CHECK-LABEL: store_v2f64_a32:
-; CHECK-NEXT: .param i32, v128{{$}}
+; CHECK-NEXT: .functype store_v2f64_a32 (i32, v128) -> (){{$}}
 ; CHECK-NEXT: v128.store 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @store_v2f64_a32(<2 x double> *%p, <2 x double> %v) {
   store <2 x double> %v, <2 x double>* %p, align 32
   ret void
 }

test/CodeGen/WebAssembly/simd-offset.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128
 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128-VM
 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=-simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,NO-SIMD128
 
 ; Test SIMD loads and stores
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; ==============================================================================
 ; 16 x i8
 ; ==============================================================================
 ; CHECK-LABEL: load_v16i8:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v16i8 (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @load_v16i8(<16 x i8>* %p) {
   %v = load <16 x i8>, <16 x i8>* %p
   ret <16 x i8> %v
 }
 
 ; CHECK-LABEL: load_v16i8_with_folded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v16i8_with_folded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @load_v16i8_with_folded_offset(<16 x i8>* %p) {
   %q = ptrtoint <16 x i8>* %p to i32
   %r = add nuw i32 %q, 16
   %s = inttoptr i32 %r to <16 x i8>*
   %v = load <16 x i8>, <16 x i8>* %s
   ret <16 x i8> %v
 }
 
 ; CHECK-LABEL: load_v16i8_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v16i8_with_folded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @load_v16i8_with_folded_gep_offset(<16 x i8>* %p) {
   %s = getelementptr inbounds <16 x i8>, <16 x i8>* %p, i32 1
   %v = load <16 x i8>, <16 x i8>* %s
   ret <16 x i8> %v
 }
 
 ; CHECK-LABEL: load_v16i8_with_unfolded_gep_negative_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v16i8_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @load_v16i8_with_unfolded_gep_negative_offset(<16 x i8>* %p) {
   %s = getelementptr inbounds <16 x i8>, <16 x i8>* %p, i32 -1
   %v = load <16 x i8>, <16 x i8>* %s
   ret <16 x i8> %v
 }
 
 ; CHECK-LABEL: load_v16i8_with_unfolded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v16i8_with_unfolded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @load_v16i8_with_unfolded_offset(<16 x i8>* %p) {
   %q = ptrtoint <16 x i8>* %p to i32
   %r = add nsw i32 %q, 16
   %s = inttoptr i32 %r to <16 x i8>*
   %v = load <16 x i8>, <16 x i8>* %s
   ret <16 x i8> %v
 }
 
 ; CHECK-LABEL: load_v16i8_with_unfolded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v16i8_with_unfolded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @load_v16i8_with_unfolded_gep_offset(<16 x i8>* %p) {
   %s = getelementptr <16 x i8>, <16 x i8>* %p, i32 1
   %v = load <16 x i8>, <16 x i8>* %s
   ret <16 x i8> %v
 }
 
 ; CHECK-LABEL: load_v16i8_from_numeric_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v16i8_from_numeric_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @load_v16i8_from_numeric_address() {
   %s = inttoptr i32 32 to <16 x i8>*
   %v = load <16 x i8>, <16 x i8>* %s
   ret <16 x i8> %v
 }
 
 ; CHECK-LABEL: load_v16i8_from_global_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v16i8_from_global_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, gv_v16i8($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 @gv_v16i8 = global <16 x i8> <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>
 define <16 x i8> @load_v16i8_from_global_address() {
   %v = load <16 x i8>, <16 x i8>* @gv_v16i8
   ret <16 x i8> %v
 }
 
 ; CHECK-LABEL: store_v16i8:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v16i8 (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 0($1), $0{{$}}
 define void @store_v16i8(<16 x i8> %v, <16 x i8>* %p) {
   store <16 x i8> %v , <16 x i8>* %p
   ret void
 }
 
 ; CHECK-LABEL: store_v16i8_with_folded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v16i8_with_folded_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 16($1), $0{{$}}
 define void @store_v16i8_with_folded_offset(<16 x i8> %v, <16 x i8>* %p) {
   %q = ptrtoint <16 x i8>* %p to i32
   %r = add nuw i32 %q, 16
   %s = inttoptr i32 %r to <16 x i8>*
   store <16 x i8> %v , <16 x i8>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v16i8_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v16i8_with_folded_gep_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 16($1), $0{{$}}
 define void @store_v16i8_with_folded_gep_offset(<16 x i8> %v, <16 x i8>* %p) {
   %s = getelementptr inbounds <16 x i8>, <16 x i8>* %p, i32 1
   store <16 x i8> %v , <16 x i8>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v16i8_with_unfolded_gep_negative_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v16i8_with_unfolded_gep_negative_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[R:[0-9]+]]=, $1, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[R]]), $0{{$}}
 define void @store_v16i8_with_unfolded_gep_negative_offset(<16 x i8> %v, <16 x i8>* %p) {
   %s = getelementptr inbounds <16 x i8>, <16 x i8>* %p, i32 -1
   store <16 x i8> %v , <16 x i8>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v16i8_with_unfolded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v16i8_with_unfolded_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[R:[0-9]+]]=, $1, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[R]]), $0{{$}}
 define void @store_v16i8_with_unfolded_offset(<16 x i8> %v, <16 x i8>* %p) {
   %s = getelementptr inbounds <16 x i8>, <16 x i8>* %p, i32 -1
   store <16 x i8> %v , <16 x i8>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v16i8_with_unfolded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v16i8_with_unfolded_gep_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[R:[0-9]+]]=, $1, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[R]]), $0{{$}}
 define void @store_v16i8_with_unfolded_gep_offset(<16 x i8> %v, <16 x i8>* %p) {
   %s = getelementptr <16 x i8>, <16 x i8>* %p, i32 1
   store <16 x i8> %v , <16 x i8>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v16i8_to_numeric_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .functype store_v16i8_to_numeric_address (v128) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[R:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.store 32($pop[[R]]), $0{{$}}
 define void @store_v16i8_to_numeric_address(<16 x i8> %v) {
   %s = inttoptr i32 32 to <16 x i8>*
   store <16 x i8> %v , <16 x i8>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v16i8_to_global_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .functype store_v16i8_to_global_address (v128) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[R:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.store gv_v16i8($pop[[R]]), $0{{$}}
 define void @store_v16i8_to_global_address(<16 x i8> %v) {
   store <16 x i8> %v , <16 x i8>* @gv_v16i8
   ret void
 }
 
 ; ==============================================================================
 ; 8 x i16
 ; ==============================================================================
 ; CHECK-LABEL: load_v8i16:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v8i16 (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @load_v8i16(<8 x i16>* %p) {
   %v = load <8 x i16>, <8 x i16>* %p
   ret <8 x i16> %v
 }
 
 ; CHECK-LABEL: load_v8i16_with_folded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v8i16_with_folded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @load_v8i16_with_folded_offset(<8 x i16>* %p) {
   %q = ptrtoint <8 x i16>* %p to i32
   %r = add nuw i32 %q, 16
   %s = inttoptr i32 %r to <8 x i16>*
   %v = load <8 x i16>, <8 x i16>* %s
   ret <8 x i16> %v
 }
 
 ; CHECK-LABEL: load_v8i16_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v8i16_with_folded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @load_v8i16_with_folded_gep_offset(<8 x i16>* %p) {
   %s = getelementptr inbounds <8 x i16>, <8 x i16>* %p, i32 1
   %v = load <8 x i16>, <8 x i16>* %s
   ret <8 x i16> %v
 }
 
 ; CHECK-LABEL: load_v8i16_with_unfolded_gep_negative_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v8i16_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @load_v8i16_with_unfolded_gep_negative_offset(<8 x i16>* %p) {
   %s = getelementptr inbounds <8 x i16>, <8 x i16>* %p, i32 -1
   %v = load <8 x i16>, <8 x i16>* %s
   ret <8 x i16> %v
 }
 
 ; CHECK-LABEL: load_v8i16_with_unfolded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v8i16_with_unfolded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[L0:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[L0]]{{$}}
 define <8 x i16> @load_v8i16_with_unfolded_offset(<8 x i16>* %p) {
   %q = ptrtoint <8 x i16>* %p to i32
   %r = add nsw i32 %q, 16
   %s = inttoptr i32 %r to <8 x i16>*
   %v = load <8 x i16>, <8 x i16>* %s
   ret <8 x i16> %v
 }
 
 ; CHECK-LABEL: load_v8i16_with_unfolded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v8i16_with_unfolded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @load_v8i16_with_unfolded_gep_offset(<8 x i16>* %p) {
   %s = getelementptr <8 x i16>, <8 x i16>* %p, i32 1
   %v = load <8 x i16>, <8 x i16>* %s
   ret <8 x i16> %v
 }
 
 ; CHECK-LABEL: load_v8i16_from_numeric_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v8i16_from_numeric_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @load_v8i16_from_numeric_address() {
   %s = inttoptr i32 32 to <8 x i16>*
   %v = load <8 x i16>, <8 x i16>* %s
   ret <8 x i16> %v
 }
 
 ; CHECK-LABEL: load_v8i16_from_global_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v8i16_from_global_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, gv_v8i16($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 @gv_v8i16 = global <8 x i16> <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>
 define <8 x i16> @load_v8i16_from_global_address() {
   %v = load <8 x i16>, <8 x i16>* @gv_v8i16
   ret <8 x i16> %v
 }
 
 ; CHECK-LABEL: store_v8i16:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v8i16 (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 0($1), $0{{$}}
 define void @store_v8i16(<8 x i16> %v, <8 x i16>* %p) {
   store <8 x i16> %v , <8 x i16>* %p
   ret void
 }
 
 ; CHECK-LABEL: store_v8i16_with_folded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v8i16_with_folded_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 16($1), $0{{$}}
 define void @store_v8i16_with_folded_offset(<8 x i16> %v, <8 x i16>* %p) {
   %q = ptrtoint <8 x i16>* %p to i32
   %r = add nuw i32 %q, 16
   %s = inttoptr i32 %r to <8 x i16>*
   store <8 x i16> %v , <8 x i16>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v8i16_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v8i16_with_folded_gep_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 16($1), $0{{$}}
 define void @store_v8i16_with_folded_gep_offset(<8 x i16> %v, <8 x i16>* %p) {
   %s = getelementptr inbounds <8 x i16>, <8 x i16>* %p, i32 1
   store <8 x i16> %v , <8 x i16>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v8i16_with_unfolded_gep_negative_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v8i16_with_unfolded_gep_negative_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[R:[0-9]+]]=, $1, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[R]]), $0{{$}}
 define void @store_v8i16_with_unfolded_gep_negative_offset(<8 x i16> %v, <8 x i16>* %p) {
   %s = getelementptr inbounds <8 x i16>, <8 x i16>* %p, i32 -1
   store <8 x i16> %v , <8 x i16>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v8i16_with_unfolded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v8i16_with_unfolded_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[R:[0-9]+]]=, $1, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[R]]), $0{{$}}
 define void @store_v8i16_with_unfolded_offset(<8 x i16> %v, <8 x i16>* %p) {
   %s = getelementptr inbounds <8 x i16>, <8 x i16>* %p, i32 -1
   store <8 x i16> %v , <8 x i16>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v8i16_with_unfolded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v8i16_with_unfolded_gep_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[R:[0-9]+]]=, $1, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[R]]), $0{{$}}
 define void @store_v8i16_with_unfolded_gep_offset(<8 x i16> %v, <8 x i16>* %p) {
   %s = getelementptr <8 x i16>, <8 x i16>* %p, i32 1
   store <8 x i16> %v , <8 x i16>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v8i16_to_numeric_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .functype store_v8i16_to_numeric_address (v128) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.store 32($pop[[L0]]), $0{{$}}
 define void @store_v8i16_to_numeric_address(<8 x i16> %v) {
   %s = inttoptr i32 32 to <8 x i16>*
   store <8 x i16> %v , <8 x i16>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v8i16_to_global_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .functype store_v8i16_to_global_address (v128) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[R:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.store gv_v8i16($pop[[R]]), $0{{$}}
 define void @store_v8i16_to_global_address(<8 x i16> %v) {
   store <8 x i16> %v , <8 x i16>* @gv_v8i16
   ret void
 }
 
 ; ==============================================================================
 ; 4 x i32
 ; ==============================================================================
 ; CHECK-LABEL: load_v4i32:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v4i32 (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @load_v4i32(<4 x i32>* %p) {
   %v = load <4 x i32>, <4 x i32>* %p
   ret <4 x i32> %v
 }
 
 ; CHECK-LABEL: load_v4i32_with_folded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v4i32_with_folded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @load_v4i32_with_folded_offset(<4 x i32>* %p) {
   %q = ptrtoint <4 x i32>* %p to i32
   %r = add nuw i32 %q, 16
   %s = inttoptr i32 %r to <4 x i32>*
   %v = load <4 x i32>, <4 x i32>* %s
   ret <4 x i32> %v
 }
 
 ; CHECK-LABEL: load_v4i32_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v4i32_with_folded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @load_v4i32_with_folded_gep_offset(<4 x i32>* %p) {
   %s = getelementptr inbounds <4 x i32>, <4 x i32>* %p, i32 1
   %v = load <4 x i32>, <4 x i32>* %s
   ret <4 x i32> %v
 }
 
 ; CHECK-LABEL: load_v4i32_with_unfolded_gep_negative_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v4i32_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @load_v4i32_with_unfolded_gep_negative_offset(<4 x i32>* %p) {
   %s = getelementptr inbounds <4 x i32>, <4 x i32>* %p, i32 -1
   %v = load <4 x i32>, <4 x i32>* %s
   ret <4 x i32> %v
 }
 
 ; CHECK-LABEL: load_v4i32_with_unfolded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v4i32_with_unfolded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @load_v4i32_with_unfolded_offset(<4 x i32>* %p) {
   %q = ptrtoint <4 x i32>* %p to i32
   %r = add nsw i32 %q, 16
   %s = inttoptr i32 %r to <4 x i32>*
   %v = load <4 x i32>, <4 x i32>* %s
   ret <4 x i32> %v
 }
 
 ; CHECK-LABEL: load_v4i32_with_unfolded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v4i32_with_unfolded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @load_v4i32_with_unfolded_gep_offset(<4 x i32>* %p) {
   %s = getelementptr <4 x i32>, <4 x i32>* %p, i32 1
   %v = load <4 x i32>, <4 x i32>* %s
   ret <4 x i32> %v
 }
 
 ; CHECK-LABEL: load_v4i32_from_numeric_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v4i32_from_numeric_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @load_v4i32_from_numeric_address() {
   %s = inttoptr i32 32 to <4 x i32>*
   %v = load <4 x i32>, <4 x i32>* %s
   ret <4 x i32> %v
 }
 
 ; CHECK-LABEL: load_v4i32_from_global_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v4i32_from_global_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, gv_v4i32($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 @gv_v4i32 = global <4 x i32> <i32 42, i32 42, i32 42, i32 42>
 define <4 x i32> @load_v4i32_from_global_address() {
   %v = load <4 x i32>, <4 x i32>* @gv_v4i32
   ret <4 x i32> %v
 }
 
 ; CHECK-LABEL: store_v4i32:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v4i32 (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 0($1), $0{{$}}
 define void @store_v4i32(<4 x i32> %v, <4 x i32>* %p) {
   store <4 x i32> %v , <4 x i32>* %p
   ret void
 }
 
 ; CHECK-LABEL: store_v4i32_with_folded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v4i32_with_folded_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 16($1), $0{{$}}
 define void @store_v4i32_with_folded_offset(<4 x i32> %v, <4 x i32>* %p) {
   %q = ptrtoint <4 x i32>* %p to i32
   %r = add nuw i32 %q, 16
   %s = inttoptr i32 %r to <4 x i32>*
   store <4 x i32> %v , <4 x i32>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v4i32_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v4i32_with_folded_gep_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 16($1), $0{{$}}
 define void @store_v4i32_with_folded_gep_offset(<4 x i32> %v, <4 x i32>* %p) {
   %s = getelementptr inbounds <4 x i32>, <4 x i32>* %p, i32 1
   store <4 x i32> %v , <4 x i32>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v4i32_with_unfolded_gep_negative_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v4i32_with_unfolded_gep_negative_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[R:[0-9]+]]=, $1, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[R]]), $0{{$}}
 define void @store_v4i32_with_unfolded_gep_negative_offset(<4 x i32> %v, <4 x i32>* %p) {
   %s = getelementptr inbounds <4 x i32>, <4 x i32>* %p, i32 -1
   store <4 x i32> %v , <4 x i32>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v4i32_with_unfolded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v4i32_with_unfolded_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[R:[0-9]+]]=, $1, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[R]]), $0{{$}}
 define void @store_v4i32_with_unfolded_offset(<4 x i32> %v, <4 x i32>* %p) {
   %s = getelementptr inbounds <4 x i32>, <4 x i32>* %p, i32 -1
   store <4 x i32> %v , <4 x i32>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v4i32_with_unfolded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v4i32_with_unfolded_gep_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[R:[0-9]+]]=, $1, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[R]]), $0{{$}}
 define void @store_v4i32_with_unfolded_gep_offset(<4 x i32> %v, <4 x i32>* %p) {
   %s = getelementptr <4 x i32>, <4 x i32>* %p, i32 1
   store <4 x i32> %v , <4 x i32>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v4i32_to_numeric_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .functype store_v4i32_to_numeric_address (v128) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.store 32($pop[[L0]]), $0{{$}}
 define void @store_v4i32_to_numeric_address(<4 x i32> %v) {
   %s = inttoptr i32 32 to <4 x i32>*
   store <4 x i32> %v , <4 x i32>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v4i32_to_global_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .functype store_v4i32_to_global_address (v128) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[R:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.store gv_v4i32($pop[[R]]), $0{{$}}
 define void @store_v4i32_to_global_address(<4 x i32> %v) {
   store <4 x i32> %v , <4 x i32>* @gv_v4i32
   ret void
 }
 
 ; ==============================================================================
 ; 2 x i64
 ; ==============================================================================
 ; CHECK-LABEL: load_v2i64:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v2i64 (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_v2i64(<2 x i64>* %p) {
   %v = load <2 x i64>, <2 x i64>* %p
   ret <2 x i64> %v
 }
 
 ; CHECK-LABEL: load_v2i64_with_folded_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v2i64_with_folded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_v2i64_with_folded_offset(<2 x i64>* %p) {
   %q = ptrtoint <2 x i64>* %p to i32
   %r = add nuw i32 %q, 16
   %s = inttoptr i32 %r to <2 x i64>*
   %v = load <2 x i64>, <2 x i64>* %s
   ret <2 x i64> %v
 }
 
 ; CHECK-LABEL: load_v2i64_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v2i64_with_folded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_v2i64_with_folded_gep_offset(<2 x i64>* %p) {
   %s = getelementptr inbounds <2 x i64>, <2 x i64>* %p, i32 1
   %v = load <2 x i64>, <2 x i64>* %s
   ret <2 x i64> %v
 }
 
 ; CHECK-LABEL: load_v2i64_with_unfolded_gep_negative_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v2i64_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_v2i64_with_unfolded_gep_negative_offset(<2 x i64>* %p) {
   %s = getelementptr inbounds <2 x i64>, <2 x i64>* %p, i32 -1
   %v = load <2 x i64>, <2 x i64>* %s
   ret <2 x i64> %v
 }
 
 ; CHECK-LABEL: load_v2i64_with_unfolded_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v2i64_with_unfolded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_v2i64_with_unfolded_offset(<2 x i64>* %p) {
   %q = ptrtoint <2 x i64>* %p to i32
   %r = add nsw i32 %q, 16
   %s = inttoptr i32 %r to <2 x i64>*
   %v = load <2 x i64>, <2 x i64>* %s
   ret <2 x i64> %v
 }
 
 ; CHECK-LABEL: load_v2i64_with_unfolded_gep_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v2i64_with_unfolded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_v2i64_with_unfolded_gep_offset(<2 x i64>* %p) {
   %s = getelementptr <2 x i64>, <2 x i64>* %p, i32 1
   %v = load <2 x i64>, <2 x i64>* %s
   ret <2 x i64> %v
 }
 
 ; CHECK-LABEL: load_v2i64_from_numeric_address:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v2i64_from_numeric_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_v2i64_from_numeric_address() {
   %s = inttoptr i32 32 to <2 x i64>*
   %v = load <2 x i64>, <2 x i64>* %s
   ret <2 x i64> %v
 }
 
 ; CHECK-LABEL: load_v2i64_from_global_address:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v2i64_from_global_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, gv_v2i64($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 @gv_v2i64 = global <2 x i64> <i64 42, i64 42>
 define <2 x i64> @load_v2i64_from_global_address() {
   %v = load <2 x i64>, <2 x i64>* @gv_v2i64
   ret <2 x i64> %v
 }
 
 ; CHECK-LABEL: store_v2i64:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v2i64 (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 0($1), $0{{$}}
 define void @store_v2i64(<2 x i64> %v, <2 x i64>* %p) {
   store <2 x i64> %v , <2 x i64>* %p
   ret void
 }
 
 ; CHECK-LABEL: store_v2i64_with_folded_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v2i64_with_folded_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 16($1), $0{{$}}
 define void @store_v2i64_with_folded_offset(<2 x i64> %v, <2 x i64>* %p) {
   %q = ptrtoint <2 x i64>* %p to i32
   %r = add nuw i32 %q, 16
   %s = inttoptr i32 %r to <2 x i64>*
   store <2 x i64> %v , <2 x i64>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v2i64_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v2i64_with_folded_gep_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 16($1), $0{{$}}
 define void @store_v2i64_with_folded_gep_offset(<2 x i64> %v, <2 x i64>* %p) {
   %s = getelementptr inbounds <2 x i64>, <2 x i64>* %p, i32 1
   store <2 x i64> %v , <2 x i64>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v2i64_with_unfolded_gep_negative_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v2i64_with_unfolded_gep_negative_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[R:[0-9]+]]=, $1, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[R]]), $0{{$}}
 define void @store_v2i64_with_unfolded_gep_negative_offset(<2 x i64> %v, <2 x i64>* %p) {
   %s = getelementptr inbounds <2 x i64>, <2 x i64>* %p, i32 -1
   store <2 x i64> %v , <2 x i64>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v2i64_with_unfolded_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v2i64_with_unfolded_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[R:[0-9]+]]=, $1, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[R]]), $0{{$}}
 define void @store_v2i64_with_unfolded_offset(<2 x i64> %v, <2 x i64>* %p) {
   %s = getelementptr inbounds <2 x i64>, <2 x i64>* %p, i32 -1
   store <2 x i64> %v , <2 x i64>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v2i64_with_unfolded_gep_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v2i64_with_unfolded_gep_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[R:[0-9]+]]=, $1, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[R]]), $0{{$}}
 define void @store_v2i64_with_unfolded_gep_offset(<2 x i64> %v, <2 x i64>* %p) {
   %s = getelementptr <2 x i64>, <2 x i64>* %p, i32 1
   store <2 x i64> %v , <2 x i64>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v2i64_to_numeric_address:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .functype store_v2i64_to_numeric_address (v128) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.store 32($pop[[L0]]), $0{{$}}
 define void @store_v2i64_to_numeric_address(<2 x i64> %v) {
   %s = inttoptr i32 32 to <2 x i64>*
   store <2 x i64> %v , <2 x i64>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v2i64_to_global_address:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .functype store_v2i64_to_global_address (v128) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[R:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.store gv_v2i64($pop[[R]]), $0{{$}}
 define void @store_v2i64_to_global_address(<2 x i64> %v) {
   store <2 x i64> %v , <2 x i64>* @gv_v2i64
   ret void
 }
 
 ; ==============================================================================
 ; 4 x float
 ; ==============================================================================
 ; CHECK-LABEL: load_v4f32:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v4f32 (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @load_v4f32(<4 x float>* %p) {
   %v = load <4 x float>, <4 x float>* %p
   ret <4 x float> %v
 }
 
 ; CHECK-LABEL: load_v4f32_with_folded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v4f32_with_folded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @load_v4f32_with_folded_offset(<4 x float>* %p) {
   %q = ptrtoint <4 x float>* %p to i32
   %r = add nuw i32 %q, 16
   %s = inttoptr i32 %r to <4 x float>*
   %v = load <4 x float>, <4 x float>* %s
   ret <4 x float> %v
 }
 
 ; CHECK-LABEL: load_v4f32_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v4f32_with_folded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @load_v4f32_with_folded_gep_offset(<4 x float>* %p) {
   %s = getelementptr inbounds <4 x float>, <4 x float>* %p, i32 1
   %v = load <4 x float>, <4 x float>* %s
   ret <4 x float> %v
 }
 
 ; CHECK-LABEL: load_v4f32_with_unfolded_gep_negative_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v4f32_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @load_v4f32_with_unfolded_gep_negative_offset(<4 x float>* %p) {
   %s = getelementptr inbounds <4 x float>, <4 x float>* %p, i32 -1
   %v = load <4 x float>, <4 x float>* %s
   ret <4 x float> %v
 }
 
 ; CHECK-LABEL: load_v4f32_with_unfolded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v4f32_with_unfolded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @load_v4f32_with_unfolded_offset(<4 x float>* %p) {
   %q = ptrtoint <4 x float>* %p to i32
   %r = add nsw i32 %q, 16
   %s = inttoptr i32 %r to <4 x float>*
   %v = load <4 x float>, <4 x float>* %s
   ret <4 x float> %v
 }
 
 ; CHECK-LABEL: load_v4f32_with_unfolded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v4f32_with_unfolded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @load_v4f32_with_unfolded_gep_offset(<4 x float>* %p) {
   %s = getelementptr <4 x float>, <4 x float>* %p, i32 1
   %v = load <4 x float>, <4 x float>* %s
   ret <4 x float> %v
 }
 
 ; CHECK-LABEL: load_v4f32_from_numeric_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v4f32_from_numeric_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @load_v4f32_from_numeric_address() {
   %s = inttoptr i32 32 to <4 x float>*
   %v = load <4 x float>, <4 x float>* %s
   ret <4 x float> %v
 }
 
 ; CHECK-LABEL: load_v4f32_from_global_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v4f32_from_global_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, gv_v4f32($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 @gv_v4f32 = global <4 x float> <float 42., float 42., float 42., float 42.>
 define <4 x float> @load_v4f32_from_global_address() {
   %v = load <4 x float>, <4 x float>* @gv_v4f32
   ret <4 x float> %v
 }
 
 ; CHECK-LABEL: store_v4f32:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v4f32 (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 0($1), $0{{$}}
 define void @store_v4f32(<4 x float> %v, <4 x float>* %p) {
   store <4 x float> %v , <4 x float>* %p
   ret void
 }
 
 ; CHECK-LABEL: store_v4f32_with_folded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v4f32_with_folded_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 16($1), $0{{$}}
 define void @store_v4f32_with_folded_offset(<4 x float> %v, <4 x float>* %p) {
   %q = ptrtoint <4 x float>* %p to i32
   %r = add nuw i32 %q, 16
   %s = inttoptr i32 %r to <4 x float>*
   store <4 x float> %v , <4 x float>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v4f32_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v4f32_with_folded_gep_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 16($1), $0{{$}}
 define void @store_v4f32_with_folded_gep_offset(<4 x float> %v, <4 x float>* %p) {
   %s = getelementptr inbounds <4 x float>, <4 x float>* %p, i32 1
   store <4 x float> %v , <4 x float>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v4f32_with_unfolded_gep_negative_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v4f32_with_unfolded_gep_negative_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[R:[0-9]+]]=, $1, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[R]]), $0{{$}}
 define void @store_v4f32_with_unfolded_gep_negative_offset(<4 x float> %v, <4 x float>* %p) {
   %s = getelementptr inbounds <4 x float>, <4 x float>* %p, i32 -1
   store <4 x float> %v , <4 x float>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v4f32_with_unfolded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v4f32_with_unfolded_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[R:[0-9]+]]=, $1, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[R]]), $0{{$}}
 define void @store_v4f32_with_unfolded_offset(<4 x float> %v, <4 x float>* %p) {
   %s = getelementptr inbounds <4 x float>, <4 x float>* %p, i32 -1
   store <4 x float> %v , <4 x float>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v4f32_with_unfolded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v4f32_with_unfolded_gep_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[R:[0-9]+]]=, $1, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[R]]), $0{{$}}
 define void @store_v4f32_with_unfolded_gep_offset(<4 x float> %v, <4 x float>* %p) {
   %s = getelementptr <4 x float>, <4 x float>* %p, i32 1
   store <4 x float> %v , <4 x float>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v4f32_to_numeric_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .functype store_v4f32_to_numeric_address (v128) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.store 32($pop[[L0]]), $0{{$}}
 define void @store_v4f32_to_numeric_address(<4 x float> %v) {
   %s = inttoptr i32 32 to <4 x float>*
   store <4 x float> %v , <4 x float>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v4f32_to_global_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .functype store_v4f32_to_global_address (v128) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[R:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.store gv_v4f32($pop[[R]]), $0{{$}}
 define void @store_v4f32_to_global_address(<4 x float> %v) {
   store <4 x float> %v , <4 x float>* @gv_v4f32
   ret void
 }
 
 ; ==============================================================================
 ; 2 x double
 ; ==============================================================================
 ; CHECK-LABEL: load_v2f64:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v2f64 (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @load_v2f64(<2 x double>* %p) {
   %v = load <2 x double>, <2 x double>* %p
   ret <2 x double> %v
 }
 
 ; CHECK-LABEL: load_v2f64_with_folded_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v2f64_with_folded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @load_v2f64_with_folded_offset(<2 x double>* %p) {
   %q = ptrtoint <2 x double>* %p to i32
   %r = add nuw i32 %q, 16
   %s = inttoptr i32 %r to <2 x double>*
   %v = load <2 x double>, <2 x double>* %s
   ret <2 x double> %v
 }
 
 ; CHECK-LABEL: load_v2f64_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v2f64_with_folded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @load_v2f64_with_folded_gep_offset(<2 x double>* %p) {
   %s = getelementptr inbounds <2 x double>, <2 x double>* %p, i32 1
   %v = load <2 x double>, <2 x double>* %s
   ret <2 x double> %v
 }
 
 ; CHECK-LABEL: load_v2f64_with_unfolded_gep_negative_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v2f64_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @load_v2f64_with_unfolded_gep_negative_offset(<2 x double>* %p) {
   %s = getelementptr inbounds <2 x double>, <2 x double>* %p, i32 -1
   %v = load <2 x double>, <2 x double>* %s
   ret <2 x double> %v
 }
 
 ; CHECK-LABEL: load_v2f64_with_unfolded_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v2f64_with_unfolded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @load_v2f64_with_unfolded_offset(<2 x double>* %p) {
   %q = ptrtoint <2 x double>* %p to i32
   %r = add nsw i32 %q, 16
   %s = inttoptr i32 %r to <2 x double>*
   %v = load <2 x double>, <2 x double>* %s
   ret <2 x double> %v
 }
 
 ; CHECK-LABEL: load_v2f64_with_unfolded_gep_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v2f64_with_unfolded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @load_v2f64_with_unfolded_gep_offset(<2 x double>* %p) {
   %s = getelementptr <2 x double>, <2 x double>* %p, i32 1
   %v = load <2 x double>, <2 x double>* %s
   ret <2 x double> %v
 }
 
 ; CHECK-LABEL: load_v2f64_from_numeric_address:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v2f64_from_numeric_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @load_v2f64_from_numeric_address() {
   %s = inttoptr i32 32 to <2 x double>*
   %v = load <2 x double>, <2 x double>* %s
   ret <2 x double> %v
 }
 
 ; CHECK-LABEL: load_v2f64_from_global_address:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype load_v2f64_from_global_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, gv_v2f64($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 @gv_v2f64 = global <2 x double> <double 42., double 42.>
 define <2 x double> @load_v2f64_from_global_address() {
   %v = load <2 x double>, <2 x double>* @gv_v2f64
   ret <2 x double> %v
 }
 
 ; CHECK-LABEL: store_v2f64:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v2f64 (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 0($1), $0{{$}}
 define void @store_v2f64(<2 x double> %v, <2 x double>* %p) {
   store <2 x double> %v , <2 x double>* %p
   ret void
 }
 
 ; CHECK-LABEL: store_v2f64_with_folded_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v2f64_with_folded_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 16($1), $0{{$}}
 define void @store_v2f64_with_folded_offset(<2 x double> %v, <2 x double>* %p) {
   %q = ptrtoint <2 x double>* %p to i32
   %r = add nuw i32 %q, 16
   %s = inttoptr i32 %r to <2 x double>*
   store <2 x double> %v , <2 x double>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v2f64_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v2f64_with_folded_gep_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 16($1), $0{{$}}
 define void @store_v2f64_with_folded_gep_offset(<2 x double> %v, <2 x double>* %p) {
   %s = getelementptr inbounds <2 x double>, <2 x double>* %p, i32 1
   store <2 x double> %v , <2 x double>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v2f64_with_unfolded_gep_negative_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v2f64_with_unfolded_gep_negative_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[R:[0-9]+]]=, $1, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[R]]), $0{{$}}
 define void @store_v2f64_with_unfolded_gep_negative_offset(<2 x double> %v, <2 x double>* %p) {
   %s = getelementptr inbounds <2 x double>, <2 x double>* %p, i32 -1
   store <2 x double> %v , <2 x double>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v2f64_with_unfolded_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v2f64_with_unfolded_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[R:[0-9]+]]=, $1, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[R]]), $0{{$}}
 define void @store_v2f64_with_unfolded_offset(<2 x double> %v, <2 x double>* %p) {
   %s = getelementptr inbounds <2 x double>, <2 x double>* %p, i32 -1
   store <2 x double> %v , <2 x double>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v2f64_with_unfolded_gep_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .param v128, i32{{$}}
+; SIMD128-NEXT: .functype store_v2f64_with_unfolded_gep_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[R:[0-9]+]]=, $1, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[R]]), $0{{$}}
 define void @store_v2f64_with_unfolded_gep_offset(<2 x double> %v, <2 x double>* %p) {
   %s = getelementptr <2 x double>, <2 x double>* %p, i32 1
   store <2 x double> %v , <2 x double>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v2f64_to_numeric_address:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .functype store_v2f64_to_numeric_address (v128) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.store 32($pop[[L0]]), $0{{$}}
 define void @store_v2f64_to_numeric_address(<2 x double> %v) {
   %s = inttoptr i32 32 to <2 x double>*
   store <2 x double> %v , <2 x double>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v2f64_to_global_address:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
-; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .functype store_v2f64_to_global_address (v128) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[R:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.store gv_v2f64($pop[[R]]), $0{{$}}
 define void @store_v2f64_to_global_address(<2 x double> %v) {
   store <2 x double> %v , <2 x double>* @gv_v2f64
   ret void
 }

test/CodeGen/WebAssembly/simd-select.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext | FileCheck %s
 
 ; Test that vector selects of various varieties lower correctly to bitselects.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; ==============================================================================
 ; 16 x i8
 ; ==============================================================================
 ; CHECK-LABEL: vselect_v16i8:
-; CHECK-NEXT: .param v128, v128, v128{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype vselect_v16i8 (v128, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i32.const $push[[L0:[0-9]+]]=, 7{{$}}
 ; CHECK-NEXT: i8x16.shl $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; CHECK-NEXT: i32.const $push[[L2:[0-9]+]]=, 7{{$}}
 ; CHECK-NEXT: i8x16.shr_s $push[[L3:[0-9]+]]=, $pop[[L1]], $pop[[L2]]{{$}}
 ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @vselect_v16i8(<16 x i1> %c, <16 x i8> %x, <16 x i8> %y) {
   %res = select <16 x i1> %c, <16 x i8> %x, <16 x i8> %y
   ret <16 x i8> %res
 }
 
 ; CHECK-LABEL: select_v16i8:
-; CHECK-NEXT: .param i32, v128, v128{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype select_v16i8 (i32, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i32.const $push[[L0:[0-9]+]]=, -1{{$}}
 ; CHECK-NEXT: i32.const $push[[L1:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i32.select $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]], $0{{$}}
 ; CHECK-NEXT: i8x16.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
 ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @select_v16i8(i1 %c, <16 x i8> %x, <16 x i8> %y) {
   %res = select i1 %c, <16 x i8> %x, <16 x i8> %y
   ret <16 x i8> %res
 }
 
 ; CHECK-LABEL: select_cmp_v16i8:
-; CHECK-NEXT: .param i32, v128, v128{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype select_cmp_v16i8 (i32, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i32.const $push[[L0:[0-9]+]]=, 31
 ; CHECK-NEXT: i32.shr_s $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; CHECK-NEXT: i8x16.splat $push[[L2:[0-9]+]]=, $pop[[L1]]{{$}}
 ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L2]]{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @select_cmp_v16i8(i32 %i, <16 x i8> %x, <16 x i8> %y) {
   %c = icmp slt i32 %i, 0
   %res = select i1 %c, <16 x i8> %x, <16 x i8> %y
   ret <16 x i8> %res
 }
 
 ; CHECK-LABEL: select_ne_v16i8:
-; CHECK-NEXT: .param i32, v128, v128{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype select_ne_v16i8 (i32, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i32.const $push[[L0:[0-9]+]]=, -1{{$}}
 ; CHECK-NEXT: i32.const $push[[L1:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i32.select $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]], $0{{$}}
 ; CHECK-NEXT: i8x16.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
 ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @select_ne_v16i8(i32 %i, <16 x i8> %x, <16 x i8> %y) {
   %c = icmp ne i32 %i, 0
   %res = select i1 %c, <16 x i8> %x, <16 x i8> %y
   ret <16 x i8> %res
 }
 
 ; CHECK-LABEL: select_eq_v16i8:
-; CHECK-NEXT: .param i32, v128, v128{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype select_eq_v16i8 (i32, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i32.const $push[[L1:[0-9]+]]=, -1{{$}}
 ; CHECK-NEXT: i32.select $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]], $0{{$}}
 ; CHECK-NEXT: i8x16.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
 ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @select_eq_v16i8(i32 %i, <16 x i8> %x, <16 x i8> %y) {
   %c = icmp eq i32 %i, 0
   %res = select i1 %c, <16 x i8> %x, <16 x i8> %y
   ret <16 x i8> %res
 }
 
 ; ==============================================================================
 ; 8 x i16
 ; ==============================================================================
 ; CHECK-LABEL: vselect_v8i16:
-; CHECK-NEXT: .param v128, v128, v128{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype vselect_v8i16 (v128, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i32.const $push[[L0:[0-9]+]]=, 15{{$}}
 ; CHECK-NEXT: i16x8.shl $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; CHECK-NEXT: i32.const $push[[L2:[0-9]+]]=, 15{{$}}
 ; CHECK-NEXT: i16x8.shr_s $push[[L3:[0-9]+]]=, $pop[[L1]], $pop[[L2]]{{$}}
 ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @vselect_v8i16(<8 x i1> %c, <8 x i16> %x, <8 x i16> %y) {
   %res = select <8 x i1> %c, <8 x i16> %x, <8 x i16> %y
   ret <8 x i16> %res
 }
 
 ; CHECK-LABEL: select_v8i16:
-; CHECK-NEXT: .param i32, v128, v128{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype select_v8i16 (i32, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i32.const $push[[L0:[0-9]+]]=, -1{{$}}
 ; CHECK-NEXT: i32.const $push[[L1:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i32.select $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]], $0{{$}}
 ; CHECK-NEXT: i16x8.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
 ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @select_v8i16(i1 %c, <8 x i16> %x, <8 x i16> %y) {
   %res = select i1 %c, <8 x i16> %x, <8 x i16> %y
   ret <8 x i16> %res
 }
 
 ; CHECK-LABEL: select_cmp_v8i16:
-; CHECK-NEXT: .param i32, v128, v128{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype select_cmp_v8i16 (i32, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i32.const $push[[L0:[0-9]+]]=, 31{{$}}
 ; CHECK-NEXT: i32.shr_s $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; CHECK-NEXT: i16x8.splat $push[[L2:[0-9]+]]=, $pop[[L1]]{{$}}
 ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L2]]{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @select_cmp_v8i16(i32 %i, <8 x i16> %x, <8 x i16> %y) {
   %c = icmp slt i32 %i, 0
   %res = select i1 %c, <8 x i16> %x, <8 x i16> %y
   ret <8 x i16> %res
 }
 
 ; CHECK-LABEL: select_ne_v8i16:
-; CHECK-NEXT: .param i32, v128, v128{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype select_ne_v8i16 (i32, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i32.const $push[[L0:[0-9]+]]=, -1{{$}}
 ; CHECK-NEXT: i32.const $push[[L1:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i32.select $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]], $0{{$}}
 ; CHECK-NEXT: i16x8.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
 ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @select_ne_v8i16(i32 %i, <8 x i16> %x, <8 x i16> %y) {
   %c = icmp ne i32 %i, 0
   %res = select i1 %c, <8 x i16> %x, <8 x i16> %y
   ret <8 x i16> %res
 }
 
 ; CHECK-LABEL: select_eq_v8i16:
-; CHECK-NEXT: .param i32, v128, v128{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype select_eq_v8i16 (i32, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i32.const $push[[L1:[0-9]+]]=, -1{{$}}
 ; CHECK-NEXT: i32.select $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]], $0{{$}}
 ; CHECK-NEXT: i16x8.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
 ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @select_eq_v8i16(i32 %i, <8 x i16> %x, <8 x i16> %y) {
   %c = icmp eq i32 %i, 0
   %res = select i1 %c, <8 x i16> %x, <8 x i16> %y
   ret <8 x i16> %res
 }
 
 ; ==============================================================================
 ; 4 x i32
 ; ==============================================================================
 ; CHECK-LABEL: vselect_v4i32:
-; CHECK-NEXT: .param v128, v128, v128{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype vselect_v4i32 (v128, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i32.const $push[[L0:[0-9]+]]=, 31{{$}}
 ; CHECK-NEXT: i32x4.shl $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; CHECK-NEXT: i32.const $push[[L2:[0-9]+]]=, 31{{$}}
 ; CHECK-NEXT: i32x4.shr_s $push[[L3:[0-9]+]]=, $pop[[L1]], $pop[[L2]]{{$}}
 ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @vselect_v4i32(<4 x i1> %c, <4 x i32> %x, <4 x i32> %y) {
   %res = select <4 x i1> %c, <4 x i32> %x, <4 x i32> %y
   ret <4 x i32> %res
 }
 
 
 ; CHECK-LABEL: select_v4i32:
-; CHECK-NEXT: .param i32, v128, v128{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype select_v4i32 (i32, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i32.const $push[[L0:[0-9]+]]=, -1{{$}}
 ; CHECK-NEXT: i32.const $push[[L1:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i32.select $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]], $0{{$}}
 ; CHECK-NEXT: i32x4.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
 ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @select_v4i32(i1 %c, <4 x i32> %x, <4 x i32> %y) {
   %res = select i1 %c, <4 x i32> %x, <4 x i32> %y
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: select_cmp_v4i32:
-; CHECK-NEXT: .param i32, v128, v128{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype select_cmp_v4i32 (i32, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i32.const $push[[L0:[0-9]+]]=, 31{{$}}
 ; CHECK-NEXT: i32.shr_s $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; CHECK-NEXT: i32x4.splat $push[[L2:[0-9]+]]=, $pop[[L1]]{{$}}
 ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L2]]{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @select_cmp_v4i32(i32 %i, <4 x i32> %x, <4 x i32> %y) {
   %c = icmp slt i32 %i, 0
   %res = select i1 %c, <4 x i32> %x, <4 x i32> %y
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: select_ne_v4i32:
-; CHECK-NEXT: .param i32, v128, v128{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype select_ne_v4i32 (i32, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i32.const $push[[L0:[0-9]+]]=, -1{{$}}
 ; CHECK-NEXT: i32.const $push[[L1:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i32.select $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]], $0{{$}}
 ; CHECK-NEXT: i32x4.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
 ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @select_ne_v4i32(i32 %i, <4 x i32> %x, <4 x i32> %y) {
   %c = icmp ne i32 %i, 0
   %res = select i1 %c, <4 x i32> %x, <4 x i32> %y
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: select_eq_v4i32:
-; CHECK-NEXT: .param i32, v128, v128{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype select_eq_v4i32 (i32, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i32.const $push[[L1:[0-9]+]]=, -1{{$}}
 ; CHECK-NEXT: i32.select $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]], $0{{$}}
 ; CHECK-NEXT: i32x4.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
 ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @select_eq_v4i32(i32 %i, <4 x i32> %x, <4 x i32> %y) {
   %c = icmp eq i32 %i, 0
   %res = select i1 %c, <4 x i32> %x, <4 x i32> %y
   ret <4 x i32> %res
 }
 
 ; ==============================================================================
 ; 2 x i64
 ; ==============================================================================
 ; CHECK-LABEL: vselect_v2i64:
-; CHECK-NEXT: .param v128, v128, v128{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype vselect_v2i64 (v128, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i32.const $push[[L0:[0-9]+]]=, 63{{$}}
 ; CHECK-NEXT: i64x2.shl $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; CHECK-NEXT: i32.const $push[[L2:[0-9]+]]=, 63{{$}}
 ; CHECK-NEXT: i64x2.shr_s $push[[L3:[0-9]+]]=, $pop[[L1]], $pop[[L2]]{{$}}
 ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @vselect_v2i64(<2 x i1> %c, <2 x i64> %x, <2 x i64> %y) {
   %res = select <2 x i1> %c, <2 x i64> %x, <2 x i64> %y
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: select_v2i64:
-; CHECK-NEXT: .param i32, v128, v128{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype select_v2i64 (i32, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i64.const $push[[L0:[0-9]+]]=, -1{{$}}
 ; CHECK-NEXT: i64.const $push[[L1:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i64.select $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]], $0{{$}}
 ; CHECK-NEXT: i64x2.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
 ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @select_v2i64(i1 %c, <2 x i64> %x, <2 x i64> %y) {
   %res = select i1 %c, <2 x i64> %x, <2 x i64> %y
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: select_cmp_v2i64:
-; CHECK-NEXT: .param i32, v128, v128{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype select_cmp_v2i64 (i32, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i64.const $push[[L0:[0-9]+]]=, -1{{$}}
 ; CHECK-NEXT: i64.const $push[[L1:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i32.const $push[[L2:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i32.lt_s $push[[L3:[0-9]+]]=, $0, $pop[[L2]]{{$}}
 ; CHECK-NEXT: i64.select $push[[L4:[0-9]+]]=, $pop[[L0]], $pop[[L1]], $pop[[L3]]{{$}}
 ; CHECK-NEXT: i64x2.splat $push[[L5:[0-9]+]]=, $pop[[L4]]{{$}}
 ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L5]]{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @select_cmp_v2i64(i32 %i, <2 x i64> %x, <2 x i64> %y) {
   %c = icmp slt i32 %i, 0
   %res = select i1 %c, <2 x i64> %x, <2 x i64> %y
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: select_ne_v2i64:
-; CHECK-NEXT: .param i32, v128, v128{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype select_ne_v2i64 (i32, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i64.const $push[[L0:[0-9]+]]=, -1{{$}}
 ; CHECK-NEXT: i64.const $push[[L1:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i64.select $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]], $0{{$}}
 ; CHECK-NEXT: i64x2.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
 ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @select_ne_v2i64(i32 %i, <2 x i64> %x, <2 x i64> %y) {
   %c = icmp ne i32 %i, 0
   %res = select i1 %c, <2 x i64> %x, <2 x i64> %y
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: select_eq_v2i64:
-; CHECK-NEXT: .param i32, v128, v128{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype select_eq_v2i64 (i32, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i64.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i64.const $push[[L1:[0-9]+]]=, -1{{$}}
 ; CHECK-NEXT: i64.select $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]], $0{{$}}
 ; CHECK-NEXT: i64x2.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
 ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @select_eq_v2i64(i32 %i, <2 x i64> %x, <2 x i64> %y) {
   %c = icmp eq i32 %i, 0
   %res = select i1 %c, <2 x i64> %x, <2 x i64> %y
   ret <2 x i64> %res
 }
 
 ; ==============================================================================
 ; 4 x float
 ; ==============================================================================
 ; CHECK-LABEL: vselect_v4f32:
-; CHECK-NEXT: .param v128, v128, v128{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype vselect_v4f32 (v128, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i32.const $push[[L0:[0-9]+]]=, 31{{$}}
 ; CHECK-NEXT: i32x4.shl $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; CHECK-NEXT: i32.const $push[[L2:[0-9]+]]=, 31{{$}}
 ; CHECK-NEXT: i32x4.shr_s $push[[L3:[0-9]+]]=, $pop[[L1]], $pop[[L2]]{{$}}
 ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @vselect_v4f32(<4 x i1> %c, <4 x float> %x, <4 x float> %y) {
   %res = select <4 x i1> %c, <4 x float> %x, <4 x float> %y
   ret <4 x float> %res
 }
 
 ; CHECK-LABEL: select_v4f32:
-; CHECK-NEXT: .param i32, v128, v128{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype select_v4f32 (i32, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i32.const $push[[L0:[0-9]+]]=, -1{{$}}
 ; CHECK-NEXT: i32.const $push[[L1:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i32.select $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]], $0{{$}}
 ; CHECK-NEXT: i32x4.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
 ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @select_v4f32(i1 %c, <4 x float> %x, <4 x float> %y) {
   %res = select i1 %c, <4 x float> %x, <4 x float> %y
   ret <4 x float> %res
 }
 
 ; CHECK-LABEL: select_cmp_v4f32:
-; CHECK-NEXT: .param i32, v128, v128{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype select_cmp_v4f32 (i32, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i32.const $push[[L0:[0-9]+]]=, 31{{$}}
 ; CHECK-NEXT: i32.shr_s $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; CHECK-NEXT: i32x4.splat $push[[L2:[0-9]+]]=, $pop[[L1]]{{$}}
 ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L2]]{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @select_cmp_v4f32(i32 %i, <4 x float> %x, <4 x float> %y) {
   %c = icmp slt i32 %i, 0
   %res = select i1 %c, <4 x float> %x, <4 x float> %y
   ret <4 x float> %res
 }
 
 ; CHECK-LABEL: select_ne_v4f32:
-; CHECK-NEXT: .param i32, v128, v128{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype select_ne_v4f32 (i32, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i32.const $push[[L0:[0-9]+]]=, -1{{$}}
 ; CHECK-NEXT: i32.const $push[[L1:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i32.select $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]], $0{{$}}
 ; CHECK-NEXT: i32x4.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
 ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @select_ne_v4f32(i32 %i, <4 x float> %x, <4 x float> %y) {
   %c = icmp ne i32 %i, 0
   %res = select i1 %c, <4 x float> %x, <4 x float> %y
   ret <4 x float> %res
 }
 
 ; CHECK-LABEL: select_eq_v4f32:
-; CHECK-NEXT: .param i32, v128, v128{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype select_eq_v4f32 (i32, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i32.const $push[[L1:[0-9]+]]=, -1{{$}}
 ; CHECK-NEXT: i32.select $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]], $0{{$}}
 ; CHECK-NEXT: i32x4.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
 ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @select_eq_v4f32(i32 %i, <4 x float> %x, <4 x float> %y) {
   %c = icmp eq i32 %i, 0
   %res = select i1 %c, <4 x float> %x, <4 x float> %y
   ret <4 x float> %res
 }
 
 ; ==============================================================================
 ; 2 x double
 ; ==============================================================================
 ; CHECK-LABEL: vselect_v2f64:
-; CHECK-NEXT: .param v128, v128, v128{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype vselect_v2f64 (v128, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i32.const $push[[L0:[0-9]+]]=, 63{{$}}
 ; CHECK-NEXT: i64x2.shl $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; CHECK-NEXT: i32.const $push[[L2:[0-9]+]]=, 63{{$}}
 ; CHECK-NEXT: i64x2.shr_s $push[[L3:[0-9]+]]=, $pop[[L1]], $pop[[L2]]{{$}}
 ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @vselect_v2f64(<2 x i1> %c, <2 x double> %x, <2 x double> %y) {
   %res = select <2 x i1> %c, <2 x double> %x, <2 x double> %y
   ret <2 x double> %res
 }
 
 ; CHECK-LABEL: select_v2f64:
-; CHECK-NEXT: .param i32, v128, v128{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype select_v2f64 (i32, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i64.const $push[[L0:[0-9]+]]=, -1{{$}}
 ; CHECK-NEXT: i64.const $push[[L1:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i64.select $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]], $0{{$}}
 ; CHECK-NEXT: i64x2.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
 ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @select_v2f64(i1 %c, <2 x double> %x, <2 x double> %y) {
   %res = select i1 %c, <2 x double> %x, <2 x double> %y
   ret <2 x double> %res
 }
 
 ; CHECK-LABEL: select_cmp_v2f64:
-; CHECK-NEXT: .param i32, v128, v128{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype select_cmp_v2f64 (i32, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i64.const $push[[L0:[0-9]+]]=, -1{{$}}
 ; CHECK-NEXT: i64.const $push[[L1:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i32.const $push[[L2:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i32.lt_s $push[[L3:[0-9]+]]=, $0, $pop[[L2]]{{$}}
 ; CHECK-NEXT: i64.select $push[[L4:[0-9]+]]=, $pop[[L0]], $pop[[L1]], $pop[[L3]]{{$}}
 ; CHECK-NEXT: i64x2.splat $push[[L5:[0-9]+]]=, $pop[[L4]]{{$}}
 ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L5]]{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @select_cmp_v2f64(i32 %i, <2 x double> %x, <2 x double> %y) {
   %c = icmp slt i32 %i, 0
   %res = select i1 %c, <2 x double> %x, <2 x double> %y
   ret <2 x double> %res
 }
 
 ; CHECK-LABEL: select_ne_v2f64:
-; CHECK-NEXT: .param i32, v128, v128{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype select_ne_v2f64 (i32, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i64.const $push[[L0:[0-9]+]]=, -1{{$}}
 ; CHECK-NEXT: i64.const $push[[L1:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i64.select $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]], $0{{$}}
 ; CHECK-NEXT: i64x2.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
 ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @select_ne_v2f64(i32 %i, <2 x double> %x, <2 x double> %y) {
   %c = icmp ne i32 %i, 0
   %res = select i1 %c, <2 x double> %x, <2 x double> %y
   ret <2 x double> %res
 }
 
 ; CHECK-LABEL: select_eq_v2f64:
-; CHECK-NEXT: .param i32, v128, v128{{$}}
-; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: .functype select_eq_v2f64 (i32, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i64.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i64.const $push[[L1:[0-9]+]]=, -1{{$}}
 ; CHECK-NEXT: i64.select $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]], $0{{$}}
 ; CHECK-NEXT: i64x2.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
 ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @select_eq_v2f64(i32 %i, <2 x double> %x, <2 x double> %y) {
   %c = icmp eq i32 %i, 0
   %res = select i1 %c, <2 x double> %x, <2 x double> %y
   ret <2 x double> %res
 }

test/CodeGen/WebAssembly/simd-sext-inreg.ll

 ; RUN: llc < %s -asm-verbose=false -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128
 ; RUN: llc < %s -asm-verbose=false -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128-VM
 ; RUN: llc < %s -asm-verbose=false -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=-simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,NO-SIMD128
 
 ; Test that vector sign extensions lower to shifts
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: sext_inreg_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype sext_inreg_v16i8 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[T0:[0-9]+]]=, 7{{$}}
 ; SIMD128-NEXT: i8x16.shl $push[[T1:[0-9]+]]=, $0, $pop[[T0]]{{$}}
 ; SIMD128-NEXT: i32.const $push[[T2:[0-9]+]]=, 7{{$}}
 ; SIMD128-NEXT: i8x16.shr_s $push[[R:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @sext_inreg_v16i8(<16 x i1> %x) {
   %res = sext <16 x i1> %x to <16 x i8>
   ret <16 x i8> %res
 }
 
 ; CHECK-LABEL: sext_inreg_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype sext_inreg_v8i16 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[T0:[0-9]+]]=, 15{{$}}
 ; SIMD128-NEXT: i16x8.shl $push[[T1:[0-9]+]]=, $0, $pop[[T0]]{{$}}
 ; SIMD128-NEXT: i32.const $push[[T2:[0-9]+]]=, 15{{$}}
 ; SIMD128-NEXT: i16x8.shr_s $push[[R:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @sext_inreg_v8i16(<8 x i1> %x) {
   %res = sext <8 x i1> %x to <8 x i16>
   ret <8 x i16> %res
 }
 
 ; CHECK-LABEL: sext_inreg_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype sext_inreg_v4i32 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[T0:[0-9]+]]=, 31{{$}}
 ; SIMD128-NEXT: i32x4.shl $push[[T1:[0-9]+]]=, $0, $pop[[T0]]{{$}}
 ; SIMD128-NEXT: i32.const $push[[T2:[0-9]+]]=, 31{{$}}
 ; SIMD128-NEXT: i32x4.shr_s $push[[R:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @sext_inreg_v4i32(<4 x i1> %x) {
   %res = sext <4 x i1> %x to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: sext_inreg_v2i64:
 ; NO-SIMD128-NOT: i64x2
 ; SDIM128-VM-NOT: i64x2
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype sext_inreg_v2i64 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[T0:[0-9]+]]=, 63{{$}}
 ; SIMD128-NEXT: i64x2.shl $push[[T1:[0-9]+]]=, $0, $pop[[T0]]{{$}}
 ; SIMD128-NEXT: i32.const $push[[T2:[0-9]+]]=, 63{{$}}
 ; SIMD128-NEXT: i64x2.shr_s $push[[R:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @sext_inreg_v2i64(<2 x i1> %x) {
   %res = sext <2 x i1> %x to <2 x i64>
   ret <2 x i64> %res
 }

test/CodeGen/WebAssembly/simd.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128
 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128-VM
 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=-simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,NO-SIMD128
 
 ; Test that basic SIMD128 vector manipulation operations assemble as expected.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; ==============================================================================
 ; 16 x i8
 ; ==============================================================================
 ; CHECK-LABEL: const_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype const_v16i8 () -> (v128){{$}}
 ; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=,
 ; SIMD128-SAME: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @const_v16i8() {
   ret <16 x i8> <i8 00, i8 01, i8 02, i8 03, i8 04, i8 05, i8 06, i8 07,
                  i8 08, i8 09, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>
 }
 
 ; CHECK-LABEL: splat_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype splat_v16i8 (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.splat $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @splat_v16i8(i8 %x) {
   %v = insertelement <16 x i8> undef, i8 %x, i32 0
   %res = shufflevector <16 x i8> %v, <16 x i8> undef,
     <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0,
                 i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   ret <16 x i8> %res
 }
 
 ; CHECK-LABEL: const_splat_v16i8:
 ; SIMD128: i8x16.splat
 define <16 x i8> @const_splat_v16i8() {
   ret <16 x i8> <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42,
                  i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>
 }
 
 ; CHECK-LABEL: extract_v16i8_s:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: .functype extract_v16i8_s (v128) -> (i32){{$}}
 ; SIMD128-NEXT: i8x16.extract_lane_s $push[[R:[0-9]+]]=, $0, 13{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define i32 @extract_v16i8_s(<16 x i8> %v) {
   %elem = extractelement <16 x i8> %v, i8 13
   %a = sext i8 %elem to i32
   ret i32 %a
 }
 
 ; CHECK-LABEL: extract_var_v16i8_s:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, i32{{$}}
-; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: .functype extract_var_v16i8_s (v128, i32) -> (i32){{$}}
 ; SIMD128-NEXT: get_global $push[[L0:[0-9]+]]=, __stack_pointer@GLOBAL
 ; SIMD128-NEXT: i32.const $push[[L1:[0-9]+]]=, 16
 ; SIMD128-NEXT: i32.sub $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]
 ; SIMD128-NEXT: tee_local $push[[L3:[0-9]+]]=, $2=, $pop[[L2]]
 ; SIMD128-NEXT: v128.store 0($pop[[L3]]), $0
 ; SIMD128-NEXT: i32.const $push[[L4:[0-9]+]]=, 15
 ; SIMD128-NEXT: i32.and $push[[L5:[0-9]+]]=, $1, $pop[[L4]]
 ; SIMD128-NEXT: i32.or $push[[L6:[0-9]+]]=, $2, $pop[[L5]]
 ; SIMD128-NEXT: i32.load8_s $push[[R:[0-9]+]]=, 0($pop[[L6]])
 ; SIMD128-NEXT: return $pop[[R]]
 define i32 @extract_var_v16i8_s(<16 x i8> %v, i32 %i) {
   %elem = extractelement <16 x i8> %v, i32 %i
   %a = sext i8 %elem to i32
   ret i32 %a
 }
 
 ; CHECK-LABEL: extract_undef_v16i8_s:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: .functype extract_undef_v16i8_s (v128) -> (i32){{$}}
 ; SIMD128-NEXT: i8x16.extract_lane_s $push[[R:[0-9]+]]=, $0, 0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define i32 @extract_undef_v16i8_s(<16 x i8> %v) {
   %elem = extractelement <16 x i8> %v, i8 undef
   %a = sext i8 %elem to i32
   ret i32 %a
 }
 
 ; CHECK-LABEL: extract_v16i8_u:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: .functype extract_v16i8_u (v128) -> (i32){{$}}
 ; SIMD128-NEXT: i8x16.extract_lane_u $push[[R:[0-9]+]]=, $0, 13{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define i32 @extract_v16i8_u(<16 x i8> %v) {
   %elem = extractelement <16 x i8> %v, i8 13
   %a = zext i8 %elem to i32
   ret i32 %a
 }
 
 ; CHECK-LABEL: extract_var_v16i8_u:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, i32{{$}}
-; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: .functype extract_var_v16i8_u (v128, i32) -> (i32){{$}}
 ; SIMD128-NEXT: get_global $push[[L0:[0-9]+]]=, __stack_pointer@GLOBAL{{$}}
 ; SIMD128-NEXT: i32.const $push[[L1:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.sub $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; SIMD128-NEXT: tee_local $push[[L3:[0-9]+]]=, $2=, $pop[[L2]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[L3]]), $0{{$}}
 ; SIMD128-NEXT: i32.const $push[[L4:[0-9]+]]=, 15{{$}}
 ; SIMD128-NEXT: i32.and $push[[L5:[0-9]+]]=, $1, $pop[[L4]]{{$}}
 ; SIMD128-NEXT: i32.or $push[[L6:[0-9]+]]=, $2, $pop[[L5]]{{$}}
 ; SIMD128-NEXT: i32.load8_u $push[[R:[0-9]+]]=, 0($pop[[L6]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define i32 @extract_var_v16i8_u(<16 x i8> %v, i32 %i) {
   %elem = extractelement <16 x i8> %v, i32 %i
   %a = zext i8 %elem to i32
   ret i32 %a
 }
 
 ; CHECK-LABEL: extract_undef_v16i8_u:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: .functype extract_undef_v16i8_u (v128) -> (i32){{$}}
 ; SIMD128-NEXT: i8x16.extract_lane_u $push[[R:[0-9]+]]=, $0, 0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define i32 @extract_undef_v16i8_u(<16 x i8> %v) {
   %elem = extractelement <16 x i8> %v, i8 undef
   %a = zext i8 %elem to i32
   ret i32 %a
 }
 
 ; CHECK-LABEL: extract_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: .functype extract_v16i8 (v128) -> (i32){{$}}
 ; SIMD128-NEXT: i8x16.extract_lane_u $push[[R:[0-9]+]]=, $0, 13{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define i8 @extract_v16i8(<16 x i8> %v) {
   %elem = extractelement <16 x i8> %v, i8 13
   ret i8 %elem
 }
 
 ; CHECK-LABEL: extract_var_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, i32{{$}}
-; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: .functype extract_var_v16i8 (v128, i32) -> (i32){{$}}
 ; SIMD128-NEXT: get_global $push[[L0:[0-9]+]]=, __stack_pointer@GLOBAL{{$}}
 ; SIMD128-NEXT: i32.const $push[[L1:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.sub $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; SIMD128-NEXT: tee_local $push[[L3:[0-9]+]]=, $2=, $pop[[L2]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[L3]]), $0{{$}}
 ; SIMD128-NEXT: i32.const $push[[L4:[0-9]+]]=, 15{{$}}
 ; SIMD128-NEXT: i32.and $push[[L5:[0-9]+]]=, $1, $pop[[L4]]{{$}}
 ; SIMD128-NEXT: i32.or $push[[L6:[0-9]+]]=, $2, $pop[[L5]]{{$}}
 ; SIMD128-NEXT: i32.load8_u $push[[R:[0-9]+]]=, 0($pop[[L6]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define i8 @extract_var_v16i8(<16 x i8> %v, i32 %i) {
   %elem = extractelement <16 x i8> %v, i32 %i
   ret i8 %elem
 }
 
 ; CHECK-LABEL: extract_undef_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: .functype extract_undef_v16i8 (v128) -> (i32){{$}}
 ; SIMD128-NEXT: i8x16.extract_lane_u $push[[R:[0-9]+]]=, $0, 0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define i8 @extract_undef_v16i8(<16 x i8> %v) {
   %elem = extractelement <16 x i8> %v, i8 undef
   ret i8 %elem
 }
 
 ; CHECK-LABEL: replace_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype replace_v16i8 (v128, i32) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.replace_lane $push[[R:[0-9]+]]=, $0, 11, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @replace_v16i8(<16 x i8> %v, i8 %x) {
   %res = insertelement <16 x i8> %v, i8 %x, i32 11
   ret <16 x i8> %res
 }
 
 ; CHECK-LABEL: replace_var_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, i32, i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype replace_var_v16i8 (v128, i32, i32) -> (v128){{$}}
 ; SIMD128-NEXT: get_global $push[[L0:[0-9]+]]=, __stack_pointer@GLOBAL{{$}}
 ; SIMD128-NEXT: i32.const $push[[L1:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.sub $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; SIMD128-NEXT: tee_local $push[[L3:[0-9]+]]=, $3=, $pop[[L2]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[L3]]), $0{{$}}
 ; SIMD128-NEXT: i32.const $push[[L4:[0-9]+]]=, 15{{$}}
 ; SIMD128-NEXT: i32.and $push[[L5:[0-9]+]]=, $1, $pop[[L4]]{{$}}
 ; SIMD128-NEXT: i32.or $push[[L6:[0-9]+]]=, $3, $pop[[L5]]{{$}}
 ; SIMD128-NEXT: i32.store8 0($pop[[L6]]), $2{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($3){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @replace_var_v16i8(<16 x i8> %v, i32 %i, i8 %x) {
   %res = insertelement <16 x i8> %v, i8 %x, i32 %i
   ret <16 x i8> %res
 }
 
 ; CHECK-LABEL: replace_undef_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param v128, i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype replace_undef_v16i8 (v128, i32) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.replace_lane $push[[R:[0-9]+]]=, $0, 0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @replace_undef_v16i8(<16 x i8> %v, i8 %x) {
   %res = insertelement <16 x i8> %v, i8 %x, i32 undef
   ret <16 x i8> %res
 }
 
 ; CHECK-LABEL: shuffle_v16i8:
 ; NO-SIMD128-NOT: v8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shuffle_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
 ; SIMD128-SAME: 0, 17, 2, 19, 4, 21, 6, 23, 8, 25, 10, 27, 12, 29, 14, 31{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @shuffle_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %res = shufflevector <16 x i8> %x, <16 x i8> %y,
     <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23,
                 i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
   ret <16 x i8> %res
 }
 
 ; CHECK-LABEL: shuffle_undef_v16i8:
 ; NO-SIMD128-NOT: v8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shuffle_undef_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
 ; SIMD128-SAME: 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @shuffle_undef_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %res = shufflevector <16 x i8> %x, <16 x i8> %y,
     <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef,
                 i32 undef, i32 undef, i32 undef, i32 undef,
                 i32 undef, i32 undef, i32 undef, i32 undef,
                 i32 undef, i32 undef, i32 undef, i32 undef>
   ret <16 x i8> %res
 }
 
 ; CHECK-LABEL: build_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .param i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype build_v16i8 (i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.splat $push[[L0:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: i8x16.replace_lane $push[[L1:[0-9]+]]=, $pop[[L0]], 1, $1{{$}}
 ; SIMD128-NEXT: i8x16.replace_lane $push[[L2:[0-9]+]]=, $pop[[L1]], 2, $2{{$}}
 ; SIMD128-NEXT: i8x16.replace_lane $push[[L3:[0-9]+]]=, $pop[[L2]], 3, $3{{$}}
 ; SIMD128-NEXT: i8x16.replace_lane $push[[L4:[0-9]+]]=, $pop[[L3]], 4, $4{{$}}
 ; SIMD128-NEXT: i8x16.replace_lane $push[[L5:[0-9]+]]=, $pop[[L4]], 5, $5{{$}}
 ; SIMD128-NEXT: i8x16.replace_lane $push[[L6:[0-9]+]]=, $pop[[L5]], 6, $6{{$}}
 ; SIMD128-NEXT: i8x16.replace_lane $push[[L7:[0-9]+]]=, $pop[[L6]], 7, $7{{$}}
define <16 x i8> @build_v16i8(i8 %x0, i8 %x1, i8 %x2, i8 %x3,
   ret <16 x i8> %res
 }
 
 ; ==============================================================================
 ; 8 x i16
 ; ==============================================================================
 ; CHECK-LABEL: const_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype const_v8i16 () -> (v128){{$}}
 ; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=, 256, 770, 1284, 1798, 2312, 2826, 3340, 3854{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @const_v8i16() {
   ret <8 x i16> <i16 256, i16 770, i16 1284, i16 1798,
                  i16 2312, i16 2826, i16 3340, i16 3854>
 }
 
 ; CHECK-LABEL: splat_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype splat_v8i16 (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.splat $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @splat_v8i16(i16 %x) {
   %v = insertelement <8 x i16> undef, i16 %x, i32 0
   %res = shufflevector <8 x i16> %v, <8 x i16> undef,
     <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   ret <8 x i16> %res
 }
 
 ; CHECK-LABEL: const_splat_v8i16:
 ; SIMD128: i16x8.splat
 define <8 x i16> @const_splat_v8i16() {
   ret <8 x i16> <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>
 }
 
 ; CHECK-LABEL: extract_v8i16_s:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: .functype extract_v8i16_s (v128) -> (i32){{$}}
 ; SIMD128-NEXT: i16x8.extract_lane_s $push[[R:[0-9]+]]=, $0, 5{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define i32 @extract_v8i16_s(<8 x i16> %v) {
   %elem = extractelement <8 x i16> %v, i16 5
   %a = sext i16 %elem to i32
   ret i32 %a
 }
 
 ; CHECK-LABEL: extract_var_v8i16_s:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, i32{{$}}
-; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: .functype extract_var_v8i16_s (v128, i32) -> (i32){{$}}
 ; SIMD128-NEXT: get_global $push[[L0:[0-9]+]]=, __stack_pointer@GLOBAL{{$}}
 ; SIMD128-NEXT: i32.const $push[[L1:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.sub $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; SIMD128-NEXT: tee_local $push[[L3:[0-9]+]]=, $2=, $pop[[L2]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[L3]]), $0{{$}}
 ; SIMD128-NEXT: i32.const $push[[L4:[0-9]+]]=, 7{{$}}
 ; SIMD128-NEXT: i32.and $push[[L5:[0-9]+]]=, $1, $pop[[L4]]{{$}}
 ; SIMD128-NEXT: i32.const $push[[L6:[0-9]+]]=, 1{{$}}
 ; SIMD128-NEXT: i32.shl $push[[L7:[0-9]+]]=, $pop[[L5]], $pop[[L6]]{{$}}
 ; SIMD128-NEXT: i32.or $push[[L8:[0-9]+]]=, $2, $pop[[L7]]{{$}}
 ; SIMD128-NEXT: i32.load16_s $push[[R:[0-9]+]]=, 0($pop[[L8]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define i32 @extract_var_v8i16_s(<8 x i16> %v, i32 %i) {
   %elem = extractelement <8 x i16> %v, i32 %i
   %a = sext i16 %elem to i32
   ret i32 %a
 }
 
 ; CHECK-LABEL: extract_undef_v8i16_s:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: .functype extract_undef_v8i16_s (v128) -> (i32){{$}}
 ; SIMD128-NEXT: i16x8.extract_lane_s $push[[R:[0-9]+]]=, $0, 0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define i32 @extract_undef_v8i16_s(<8 x i16> %v) {
   %elem = extractelement <8 x i16> %v, i16 undef
   %a = sext i16 %elem to i32
   ret i32 %a
 }
 
 ; CHECK-LABEL: extract_v8i16_u:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: .functype extract_v8i16_u (v128) -> (i32){{$}}
 ; SIMD128-NEXT: i16x8.extract_lane_u $push[[R:[0-9]+]]=, $0, 5{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define i32 @extract_v8i16_u(<8 x i16> %v) {
   %elem = extractelement <8 x i16> %v, i16 5
   %a = zext i16 %elem to i32
   ret i32 %a
 }
 
 ; CHECK-LABEL: extract_var_v8i16_u:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, i32{{$}}
-; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: .functype extract_var_v8i16_u (v128, i32) -> (i32){{$}}
 ; SIMD128-NEXT: get_global $push[[L0:[0-9]+]]=, __stack_pointer@GLOBAL{{$}}
 ; SIMD128-NEXT: i32.const $push[[L1:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.sub $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; SIMD128-NEXT: tee_local $push[[L3:[0-9]+]]=, $2=, $pop[[L2]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[L3]]), $0{{$}}
 ; SIMD128-NEXT: i32.const $push[[L4:[0-9]+]]=, 7{{$}}
 ; SIMD128-NEXT: i32.and $push[[L5:[0-9]+]]=, $1, $pop[[L4]]{{$}}
 ; SIMD128-NEXT: i32.const $push[[L6:[0-9]+]]=, 1{{$}}
 ; SIMD128-NEXT: i32.shl $push[[L7:[0-9]+]]=, $pop[[L5]], $pop[[L6]]{{$}}
 ; SIMD128-NEXT: i32.or $push[[L8:[0-9]+]]=, $2, $pop[[L7]]{{$}}
 ; SIMD128-NEXT: i32.load16_u $push[[R:[0-9]+]]=, 0($pop[[L8]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define i32 @extract_var_v8i16_u(<8 x i16> %v, i32 %i) {
   %elem = extractelement <8 x i16> %v, i32 %i
   %a = zext i16 %elem to i32
   ret i32 %a
 }
 
 ; CHECK-LABEL: extract_undef_v8i16_u:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: .functype extract_undef_v8i16_u (v128) -> (i32){{$}}
 ; SIMD128-NEXT: i16x8.extract_lane_u $push[[R:[0-9]+]]=, $0, 0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define i32 @extract_undef_v8i16_u(<8 x i16> %v) {
   %elem = extractelement <8 x i16> %v, i16 undef
   %a = zext i16 %elem to i32
   ret i32 %a
 }
 
 ; CHECK-LABEL: extract_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: .functype extract_v8i16 (v128) -> (i32){{$}}
 ; SIMD128-NEXT: i16x8.extract_lane_u $push[[R:[0-9]+]]=, $0, 5{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define i16 @extract_v8i16(<8 x i16> %v) {
   %elem = extractelement <8 x i16> %v, i16 5
   ret i16 %elem
 }
 
 ; CHECK-LABEL: extract_var_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, i32{{$}}
-; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: .functype extract_var_v8i16 (v128, i32) -> (i32){{$}}
 ; SIMD128-NEXT: get_global $push[[L0:[0-9]+]]=, __stack_pointer@GLOBAL{{$}}
 ; SIMD128-NEXT: i32.const $push[[L1:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.sub $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; SIMD128-NEXT: tee_local $push[[L3:[0-9]+]]=, $2=, $pop[[L2]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[L3]]), $0{{$}}
 ; SIMD128-NEXT: i32.const $push[[L4:[0-9]+]]=, 7{{$}}
 ; SIMD128-NEXT: i32.and $push[[L5:[0-9]+]]=, $1, $pop[[L4]]{{$}}
 ; SIMD128-NEXT: i32.const $push[[L6:[0-9]+]]=, 1{{$}}
 ; SIMD128-NEXT: i32.shl $push[[L7:[0-9]+]]=, $pop[[L5]], $pop[[L6]]{{$}}
 ; SIMD128-NEXT: i32.or $push[[L8:[0-9]+]]=, $2, $pop[[L7]]{{$}}
 ; SIMD128-NEXT: i32.load16_u $push[[R:[0-9]+]]=, 0($pop[[L8]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define i16 @extract_var_v8i16(<8 x i16> %v, i32 %i) {
   %elem = extractelement <8 x i16> %v, i32 %i
   ret i16 %elem
 }
 
 ; CHECK-LABEL: extract_undef_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: .functype extract_undef_v8i16 (v128) -> (i32){{$}}
 ; SIMD128-NEXT: i16x8.extract_lane_u $push[[R:[0-9]+]]=, $0, 0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define i16 @extract_undef_v8i16(<8 x i16> %v) {
   %elem = extractelement <8 x i16> %v, i16 undef
   ret i16 %elem
 }
 
 ; CHECK-LABEL: replace_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype replace_v8i16 (v128, i32) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.replace_lane $push[[R:[0-9]+]]=, $0, 7, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @replace_v8i16(<8 x i16> %v, i16 %x) {
   %res = insertelement <8 x i16> %v, i16 %x, i32 7
   ret <8 x i16> %res
 }
 
 ; CHECK-LABEL: replace_var_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, i32, i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype replace_var_v8i16 (v128, i32, i32) -> (v128){{$}}
 ; SIMD128-NEXT: get_global $push[[L0:[0-9]+]]=, __stack_pointer@GLOBAL{{$}}
 ; SIMD128-NEXT: i32.const $push[[L1:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.sub $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; SIMD128-NEXT: tee_local $push[[L3:[0-9]+]]=, $3=, $pop[[L2]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[L3]]), $0{{$}}
 ; SIMD128-NEXT: i32.const $push[[L4:[0-9]+]]=, 7{{$}}
 ; SIMD128-NEXT: i32.and $push[[L5:[0-9]+]]=, $1, $pop[[L4]]{{$}}
 ; SIMD128-NEXT: i32.const $push[[L6:[0-9]+]]=, 1{{$}}
 ; SIMD128-NEXT: i32.shl $push[[L7:[0-9]+]]=, $pop[[L5]], $pop[[L6]]{{$}}
 ; SIMD128-NEXT: i32.or $push[[L8:[0-9]+]]=, $3, $pop[[L7]]{{$}}
 ; SIMD128-NEXT: i32.store16 0($pop[[L8]]), $2{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($3){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @replace_var_v8i16(<8 x i16> %v, i32 %i, i16 %x) {
   %res = insertelement <8 x i16> %v, i16 %x, i32 %i
   ret <8 x i16> %res
 }
 
 ; CHECK-LABEL: replace_undef_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param v128, i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype replace_undef_v8i16 (v128, i32) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.replace_lane $push[[R:[0-9]+]]=, $0, 0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @replace_undef_v8i16(<8 x i16> %v, i16 %x) {
   %res = insertelement <8 x i16> %v, i16 %x, i32 undef
   ret <8 x i16> %res
 }
 
 ; CHECK-LABEL: shuffle_v8i16:
 ; NO-SIMD128-NOT: v8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shuffle_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
 ; SIMD128-SAME: 0, 1, 18, 19, 4, 5, 22, 23, 8, 9, 26, 27, 12, 13, 30, 31{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @shuffle_v8i16(<8 x i16> %x, <8 x i16> %y) {
   %res = shufflevector <8 x i16> %x, <8 x i16> %y,
     <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
   ret <8 x i16> %res
 }
 
 ; CHECK-LABEL: shuffle_undef_v8i16:
 ; NO-SIMD128-NOT: v8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shuffle_undef_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
 ; SIMD128-SAME: 2, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @shuffle_undef_v8i16(<8 x i16> %x, <8 x i16> %y) {
   %res = shufflevector <8 x i16> %x, <8 x i16> %y,
     <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef,
                i32 undef, i32 undef, i32 undef, i32 undef>
   ret <8 x i16> %res
 }
 
 ; CHECK-LABEL: build_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-NEXT: .param i32, i32, i32, i32, i32, i32, i32, i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype build_v8i16 (i32, i32, i32, i32, i32, i32, i32, i32) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.splat $push[[L0:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: i16x8.replace_lane $push[[L1:[0-9]+]]=, $pop[[L0]], 1, $1{{$}}
 ; SIMD128-NEXT: i16x8.replace_lane $push[[L2:[0-9]+]]=, $pop[[L1]], 2, $2{{$}}
 ; SIMD128-NEXT: i16x8.replace_lane $push[[L3:[0-9]+]]=, $pop[[L2]], 3, $3{{$}}
 ; SIMD128-NEXT: i16x8.replace_lane $push[[L4:[0-9]+]]=, $pop[[L3]], 4, $4{{$}}
 ; SIMD128-NEXT: i16x8.replace_lane $push[[L5:[0-9]+]]=, $pop[[L4]], 5, $5{{$}}
 ; SIMD128-NEXT: i16x8.replace_lane $push[[L6:[0-9]+]]=, $pop[[L5]], 6, $6{{$}}
 ; SIMD128-NEXT: i16x8.replace_lane $push[[R:[0-9]+]]=, $pop[[L6]], 7, $7{{$}}
define <8 x i16> @build_v8i16(i16 %x0, i16 %x1, i16 %x2, i16 %x3,
   ret <8 x i16> %res
 }
 
 ; ==============================================================================
 ; 4 x i32
 ; ==============================================================================
 ; CHECK-LABEL: const_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype const_v4i32 () -> (v128){{$}}
 ; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=, 50462976, 117835012, 185207048, 252579084{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @const_v4i32() {
   ret <4 x i32> <i32 50462976, i32 117835012, i32 185207048, i32 252579084>
 }
 
 ; CHECK-LABEL: splat_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype splat_v4i32 (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.splat $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @splat_v4i32(i32 %x) {
   %v = insertelement <4 x i32> undef, i32 %x, i32 0
   %res = shufflevector <4 x i32> %v, <4 x i32> undef,
     <4 x i32> <i32 0, i32 0, i32 0, i32 0>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: const_splat_v4i32:
 ; SIMD128: i32x4.splat
 define <4 x i32> @const_splat_v4i32() {
   ret <4 x i32> <i32 42, i32 42, i32 42, i32 42>
 }
 
 ; CHECK-LABEL: extract_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: .functype extract_v4i32 (v128) -> (i32){{$}}
 ; SIMD128-NEXT: i32x4.extract_lane $push[[R:[0-9]+]]=, $0, 3{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define i32 @extract_v4i32(<4 x i32> %v) {
   %elem = extractelement <4 x i32> %v, i32 3
   ret i32 %elem
 }
 
 ; CHECK-LABEL: extract_var_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128, i32{{$}}
-; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: .functype extract_var_v4i32 (v128, i32) -> (i32){{$}}
 ; SIMD128-NEXT: get_global $push[[L0:[0-9]+]]=, __stack_pointer@GLOBAL{{$}}
 ; SIMD128-NEXT: i32.const $push[[L1:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.sub $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; SIMD128-NEXT: tee_local $push[[L3:[0-9]+]]=, $2=, $pop[[L2]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[L3]]), $0{{$}}
 ; SIMD128-NEXT: i32.const $push[[L4:[0-9]+]]=, 3{{$}}
 ; SIMD128-NEXT: i32.and $push[[L5:[0-9]+]]=, $1, $pop[[L4]]{{$}}
 ; SIMD128-NEXT: i32.const $push[[L6:[0-9]+]]=, 2{{$}}
 ; SIMD128-NEXT: i32.shl $push[[L7:[0-9]+]]=, $pop[[L5]], $pop[[L6]]{{$}}
 ; SIMD128-NEXT: i32.or $push[[L4:[0-9]+]]=, $2, $pop[[L7]]{{$}}
 ; SIMD128-NEXT: i32.load $push[[R:[0-9]+]]=, 0($pop[[L4]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define i32 @extract_var_v4i32(<4 x i32> %v, i32 %i) {
   %elem = extractelement <4 x i32> %v, i32 %i
   ret i32 %elem
 }
 
 ; CHECK-LABEL: extract_undef_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: .functype extract_undef_v4i32 (v128) -> (i32){{$}}
 ; SIMD128-NEXT: i32x4.extract_lane $push[[R:[0-9]+]]=, $0, 0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define i32 @extract_undef_v4i32(<4 x i32> %v) {
   %elem = extractelement <4 x i32> %v, i32 undef
   ret i32 %elem
 }
 
 ; CHECK-LABEL: replace_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128, i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype replace_v4i32 (v128, i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.replace_lane $push[[R:[0-9]+]]=, $0, 2, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @replace_v4i32(<4 x i32> %v, i32 %x) {
   %res = insertelement <4 x i32> %v, i32 %x, i32 2
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: replace_var_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128, i32, i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype replace_var_v4i32 (v128, i32, i32) -> (v128){{$}}
 ; SIMD128-NEXT: get_global $push[[L0:[0-9]+]]=, __stack_pointer@GLOBAL{{$}}
 ; SIMD128-NEXT: i32.const $push[[L1:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.sub $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; SIMD128-NEXT: tee_local $push[[L3:[0-9]+]]=, $3=, $pop[[L2]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[L3]]), $0{{$}}
 ; SIMD128-NEXT: i32.const $push[[L4:[0-9]+]]=, 3{{$}}
 ; SIMD128-NEXT: i32.and $push[[L5:[0-9]+]]=, $1, $pop[[L4]]{{$}}
 ; SIMD128-NEXT: i32.const $push[[L6:[0-9]+]]=, 2{{$}}
 ; SIMD128-NEXT: i32.shl $push[[L7:[0-9]+]]=, $pop[[L5]], $pop[[L6]]{{$}}
 ; SIMD128-NEXT: i32.or $push[[L4:[0-9]+]]=, $3, $pop[[L7]]{{$}}
 ; SIMD128-NEXT: i32.store 0($pop[[L4]]), $2{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($3){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @replace_var_v4i32(<4 x i32> %v, i32 %i, i32 %x) {
   %res = insertelement <4 x i32> %v, i32 %x, i32 %i
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: replace_undef_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param v128, i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype replace_undef_v4i32 (v128, i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.replace_lane $push[[R:[0-9]+]]=, $0, 0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @replace_undef_v4i32(<4 x i32> %v, i32 %x) {
   %res = insertelement <4 x i32> %v, i32 %x, i32 undef
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: shuffle_v4i32:
 ; NO-SIMD128-NOT: v8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shuffle_v4i32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
 ; SIMD128-SAME: 0, 1, 2, 3, 20, 21, 22, 23, 8, 9, 10, 11, 28, 29, 30, 31{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @shuffle_v4i32(<4 x i32> %x, <4 x i32> %y) {
   %res = shufflevector <4 x i32> %x, <4 x i32> %y,
     <4 x i32> <i32 0, i32 5, i32 2, i32 7>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: shuffle_undef_v4i32:
 ; NO-SIMD128-NOT: v8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shuffle_undef_v4i32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
 ; SIMD128-SAME: 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @shuffle_undef_v4i32(<4 x i32> %x, <4 x i32> %y) {
   %res = shufflevector <4 x i32> %x, <4 x i32> %y,
     <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: build_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-NEXT: .param i32, i32, i32, i32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype build_v4i32 (i32, i32, i32, i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.splat $push[[L0:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: i32x4.replace_lane $push[[L1:[0-9]+]]=, $pop[[L0]], 1, $1{{$}}
 ; SIMD128-NEXT: i32x4.replace_lane $push[[L2:[0-9]+]]=, $pop[[L1]], 2, $2{{$}}
 ; SIMD128-NEXT: i32x4.replace_lane $push[[R:[0-9]+]]=, $pop[[L2]], 3, $3{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @build_v4i32(i32 %x0, i32 %x1, i32 %x2, i32 %x3) {
   %t0 = insertelement <4 x i32> undef, i32 %x0, i32 0
   %t1 = insertelement <4 x i32> %t0, i32 %x1, i32 1
   %t2 = insertelement <4 x i32> %t1, i32 %x2, i32 2
   %res = insertelement <4 x i32> %t2, i32 %x3, i32 3
   ret <4 x i32> %res
 }
 
 ; ==============================================================================
 ; 2 x i64
 ; ==============================================================================
 ; CHECK-LABEL: const_v2i64:
 ; NO-SIMD128-NOT: i64x2
 ; SIMD128-VM-NOT: i64x2
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype const_v2i64 () -> (v128){{$}}
 ; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=, 506097522914230528, 1084818905618843912{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @const_v2i64() {
   ret <2 x i64> <i64 506097522914230528, i64 1084818905618843912>
 }
 
 ; CHECK-LABEL: splat_v2i64:
 ; NO-SIMD128-NOT: i64x2
 ; SIMD128-VM-NOT: i64x2
-; SIMD128-NEXT: .param i64{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype splat_v2i64 (i64) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.splat $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @splat_v2i64(i64 %x) {
   %t1 = insertelement <2 x i64> zeroinitializer, i64 %x, i32 0
   %res = insertelement <2 x i64> %t1, i64 %x, i32 1
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: const_splat_v2i64:
 ; SIMD128: i64x2.splat
 define <2 x i64> @const_splat_v2i64() {
   ret <2 x i64> <i64 42, i64 42>
 }
 
 ; CHECK-LABEL: extract_v2i64:
 ; NO-SIMD128-NOT: i64x2
 ; SIMD128-VM-NOT: i64x2
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result i64{{$}}
+; SIMD128-NEXT: .functype extract_v2i64 (v128) -> (i64){{$}}
 ; SIMD128-NEXT: i64x2.extract_lane $push[[R:[0-9]+]]=, $0, 1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define i64 @extract_v2i64(<2 x i64> %v) {
   %elem = extractelement <2 x i64> %v, i64 1
   ret i64 %elem
 }
 
 ; CHECK-LABEL: extract_var_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-NEXT: .param v128, i32{{$}}
-; SIMD128-NEXT: .result i64{{$}}
+; SIMD128-NEXT: .functype extract_var_v2i64 (v128, i32) -> (i64){{$}}
 ; SIMD128-NEXT: get_global $push[[L0:[0-9]+]]=, __stack_pointer@GLOBAL{{$}}
 ; SIMD128-NEXT: i32.const $push[[L1:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.sub $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; SIMD128-NEXT: tee_local $push[[L3:[0-9]+]]=, $2=, $pop[[L2]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[L3]]), $0{{$}}
 ; SIMD128-NEXT: i32.const $push[[L2:[0-9]+]]=, 1{{$}}
 ; SIMD128-NEXT: i32.and $push[[L5:[0-9]+]]=, $1, $pop[[L2]]{{$}}
 ; SIMD128-NEXT: i32.const $push[[L6:[0-9]+]]=, 3{{$}}
 ; SIMD128-NEXT: i32.shl $push[[L7:[0-9]+]]=, $pop[[L5]], $pop[[L6]]{{$}}
 ; SIMD128-NEXT: i32.or $push[[L2:[0-9]+]]=, $2, $pop[[L7]]{{$}}
 ; SIMD128-NEXT: i64.load $push[[R:[0-9]+]]=, 0($pop[[L2]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define i64 @extract_var_v2i64(<2 x i64> %v, i32 %i) {
   %elem = extractelement <2 x i64> %v, i32 %i
   ret i64 %elem
 }
 
 ; CHECK-LABEL: extract_undef_v2i64:
 ; NO-SIMD128-NOT: i64x2
 ; SIMD128-VM-NOT: i64x2
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result i64{{$}}
+; SIMD128-NEXT: .functype extract_undef_v2i64 (v128) -> (i64){{$}}
 ; SIMD128-NEXT: i64x2.extract_lane $push[[R:[0-9]+]]=, $0, 0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define i64 @extract_undef_v2i64(<2 x i64> %v) {
   %elem = extractelement <2 x i64> %v, i64 undef
   ret i64 %elem
 }
 
 ; CHECK-LABEL: replace_v2i64:
 ; NO-SIMD128-NOT: i64x2
 ; SIMD128-VM-NOT: i64x2
-; SIMD128-NEXT: .param v128, i64{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype replace_v2i64 (v128, i64) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $0, 0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @replace_v2i64(<2 x i64> %v, i64 %x) {
   %res = insertelement <2 x i64> %v, i64 %x, i32 0
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: replace_var_v2i64:
 ; NO-SIMD128-NOT: i64x2
 ; SIMD128-VM-NOT: i64x2
-; SIMD128-NEXT: .param v128, i32, i64{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype replace_var_v2i64 (v128, i32, i64) -> (v128){{$}}
 ; SIMD128-NEXT: get_global $push[[L0:[0-9]+]]=, __stack_pointer@GLOBAL{{$}}
 ; SIMD128-NEXT: i32.const $push[[L1:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.sub $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; SIMD128-NEXT: tee_local $push[[L3:[0-9]+]]=, $3=, $pop[[L2]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[L3]]), $0{{$}}
 ; SIMD128-NEXT: i32.const $push[[L2:[0-9]+]]=, 1{{$}}
 ; SIMD128-NEXT: i32.and $push[[L5:[0-9]+]]=, $1, $pop[[L2]]{{$}}
 ; SIMD128-NEXT: i32.const $push[[L6:[0-9]+]]=, 3{{$}}
 ; SIMD128-NEXT: i32.shl $push[[L7:[0-9]+]]=, $pop[[L5]], $pop[[L6]]{{$}}
 ; SIMD128-NEXT: i32.or $push[[L2:[0-9]+]]=, $3, $pop[[L7]]{{$}}
 ; SIMD128-NEXT: i64.store 0($pop[[L2]]), $2{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($3){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @replace_var_v2i64(<2 x i64> %v, i32 %i, i64 %x) {
   %res = insertelement <2 x i64> %v, i64 %x, i32 %i
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: replace_undef_v2i64:
 ; NO-SIMD128-NOT: i64x2
 ; SIMD128-VM-NOT: i64x2
-; SIMD128-NEXT: .param v128, i64{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype replace_undef_v2i64 (v128, i64) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $0, 0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @replace_undef_v2i64(<2 x i64> %v, i64 %x) {
   %res = insertelement <2 x i64> %v, i64 %x, i32 undef
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: shuffle_v2i64:
 ; NO-SIMD128-NOT: v8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shuffle_v2i64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
 ; SIMD128-SAME: 0, 1, 2, 3, 4, 5, 6, 7, 24, 25, 26, 27, 28, 29, 30, 31{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @shuffle_v2i64(<2 x i64> %x, <2 x i64> %y) {
   %res = shufflevector <2 x i64> %x, <2 x i64> %y, <2 x i32> <i32 0, i32 3>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: shuffle_undef_v2i64:
 ; NO-SIMD128-NOT: v8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shuffle_undef_v2i64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
 ; SIMD128-SAME: 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 0, 0, 0, 0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @shuffle_undef_v2i64(<2 x i64> %x, <2 x i64> %y) {
   %res = shufflevector <2 x i64> %x, <2 x i64> %y,
     <2 x i32> <i32 1, i32 undef>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: build_v2i64:
 ; NO-SIMD128-NOT: i64x2
 ; SIMD128-VM-NOT: i64x2
-; SIMD128-NEXT: .param i64, i64{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype build_v2i64 (i64, i64) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.splat $push[[L0:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L0]], 1, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @build_v2i64(i64 %x0, i64 %x1) {
   %t0 = insertelement <2 x i64> undef, i64 %x0, i32 0
   %res = insertelement <2 x i64> %t0, i64 %x1, i32 1
   ret <2 x i64> %res
 }
 
 ; ==============================================================================
 ; 4 x f32
 ; ==============================================================================
 ; CHECK-LABEL: const_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype const_v4f32 () -> (v128){{$}}
 ; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=,
 ; SIMD128-SAME: 0x1.0402p-121, 0x1.0c0a08p-113, 0x1.14121p-105, 0x1.1c1a18p-97{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @const_v4f32() {
   ret <4 x float> <float 0x3860402000000000, float 0x38e0c0a080000000,
                    float 0x3961412100000000, float 0x39e1c1a180000000>
 }
 
 ; CHECK-LABEL: splat_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param f32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype splat_v4f32 (f32) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.splat $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @splat_v4f32(float %x) {
   %v = insertelement <4 x float> undef, float %x, i32 0
   %res = shufflevector <4 x float> %v, <4 x float> undef,
     <4 x i32> <i32 0, i32 0, i32 0, i32 0>
   ret <4 x float> %res
 }
 
 ; CHECK-LABEL: const_splat_v4f32
 ; SIMD128: f32x4.splat
 define <4 x float> @const_splat_v4f32() {
   ret <4 x float> <float 42., float 42., float 42., float 42.>
 }
 
 ; CHECK-LABEL: extract_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result f32{{$}}
+; SIMD128-NEXT: .functype extract_v4f32 (v128) -> (f32){{$}}
 ; SIMD128-NEXT: f32x4.extract_lane $push[[R:[0-9]+]]=, $0, 3{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define float @extract_v4f32(<4 x float> %v) {
   %elem = extractelement <4 x float> %v, i32 3
   ret float %elem
 }
 
 ; CHECK-LABEL: extract_var_v4f32:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-NEXT: .param v128, i32{{$}}
-; SIMD128-NEXT: .result f32{{$}}
+; SIMD128-NEXT: .functype extract_var_v4f32 (v128, i32) -> (f32){{$}}
 ; SIMD128-NEXT: get_global $push[[L0:[0-9]+]]=, __stack_pointer@GLOBAL{{$}}
 ; SIMD128-NEXT: i32.const $push[[L1:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.sub $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; SIMD128-NEXT: tee_local $push[[L3:[0-9]+]]=, $2=, $pop[[L2]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[L3]]), $0{{$}}
 ; SIMD128-NEXT: i32.const $push[[L2:[0-9]+]]=, 3{{$}}
 ; SIMD128-NEXT: i32.and $push[[L5:[0-9]+]]=, $1, $pop[[L2]]{{$}}
 ; SIMD128-NEXT: i32.const $push[[L6:[0-9]+]]=, 2{{$}}
 ; SIMD128-NEXT: i32.shl $push[[L7:[0-9]+]]=, $pop[[L5]], $pop[[L6]]{{$}}
 ; SIMD128-NEXT: i32.or $push[[L2:[0-9]+]]=, $2, $pop[[L7]]{{$}}
 ; SIMD128-NEXT: f32.load $push[[R:[0-9]+]]=, 0($pop[[L2]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define float @extract_var_v4f32(<4 x float> %v, i32 %i) {
   %elem = extractelement <4 x float> %v, i32 %i
   ret float %elem
 }
 
 ; CHECK-LABEL: extract_undef_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result f32{{$}}
+; SIMD128-NEXT: .functype extract_undef_v4f32 (v128) -> (f32){{$}}
 ; SIMD128-NEXT: f32x4.extract_lane $push[[R:[0-9]+]]=, $0, 0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define float @extract_undef_v4f32(<4 x float> %v) {
   %elem = extractelement <4 x float> %v, i32 undef
   ret float %elem
 }
 
 ; CHECK-LABEL: replace_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, f32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype replace_v4f32 (v128, f32) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.replace_lane $push[[R:[0-9]+]]=, $0, 2, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @replace_v4f32(<4 x float> %v, float %x) {
   %res = insertelement <4 x float> %v, float %x, i32 2
   ret <4 x float> %res
 }
 
 ; CHECK-LABEL: replace_var_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, i32, f32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype replace_var_v4f32 (v128, i32, f32) -> (v128){{$}}
 ; SIMD128-NEXT: get_global $push[[L0:[0-9]+]]=, __stack_pointer@GLOBAL{{$}}
 ; SIMD128-NEXT: i32.const $push[[L1:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.sub $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; SIMD128-NEXT: tee_local $push[[L3:[0-9]+]]=, $3=, $pop[[L2]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[L3]]), $0{{$}}
 ; SIMD128-NEXT: i32.const $push[[L2:[0-9]+]]=, 3{{$}}
 ; SIMD128-NEXT: i32.and $push[[L5:[0-9]+]]=, $1, $pop[[L2]]{{$}}
 ; SIMD128-NEXT: i32.const $push[[L6:[0-9]+]]=, 2{{$}}
 ; SIMD128-NEXT: i32.shl $push[[L7:[0-9]+]]=, $pop[[L5]], $pop[[L6]]{{$}}
 ; SIMD128-NEXT: i32.or $push[[L2:[0-9]+]]=, $3, $pop[[L7]]{{$}}
 ; SIMD128-NEXT: f32.store 0($pop[[L2]]), $2{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($3){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @replace_var_v4f32(<4 x float> %v, i32 %i, float %x) {
   %res = insertelement <4 x float> %v, float %x, i32 %i
   ret <4 x float> %res
 }
 
 ; CHECK-LABEL: replace_undef_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param v128, f32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype replace_undef_v4f32 (v128, f32) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.replace_lane $push[[R:[0-9]+]]=, $0, 0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @replace_undef_v4f32(<4 x float> %v, float %x) {
   %res = insertelement <4 x float> %v, float %x, i32 undef
   ret <4 x float> %res
 }
 
 ; CHECK-LABEL: shuffle_v4f32:
 ; NO-SIMD128-NOT: v8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shuffle_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
 ; SIMD128-SAME: 0, 1, 2, 3, 20, 21, 22, 23, 8, 9, 10, 11, 28, 29, 30, 31{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @shuffle_v4f32(<4 x float> %x, <4 x float> %y) {
   %res = shufflevector <4 x float> %x, <4 x float> %y,
     <4 x i32> <i32 0, i32 5, i32 2, i32 7>
   ret <4 x float> %res
 }
 
 ; CHECK-LABEL: shuffle_undef_v4f32:
 ; NO-SIMD128-NOT: v8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shuffle_undef_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
 ; SIMD128-SAME: 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @shuffle_undef_v4f32(<4 x float> %x, <4 x float> %y) {
   %res = shufflevector <4 x float> %x, <4 x float> %y,
     <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
   ret <4 x float> %res
 }
 
 ; CHECK-LABEL: build_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .param f32, f32, f32, f32{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype build_v4f32 (f32, f32, f32, f32) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.splat $push[[L0:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: f32x4.replace_lane $push[[L1:[0-9]+]]=, $pop[[L0]], 1, $1{{$}}
 ; SIMD128-NEXT: f32x4.replace_lane $push[[L2:[0-9]+]]=, $pop[[L1]], 2, $2{{$}}
 ; SIMD128-NEXT: f32x4.replace_lane $push[[R:[0-9]+]]=, $pop[[L2]], 3, $3{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @build_v4f32(float %x0, float %x1, float %x2, float %x3) {
   %t0 = insertelement <4 x float> undef, float %x0, i32 0
   %t1 = insertelement <4 x float> %t0, float %x1, i32 1
   %t2 = insertelement <4 x float> %t1, float %x2, i32 2
   %res = insertelement <4 x float> %t2, float %x3, i32 3
   ret <4 x float> %res
 }
 
 ; ==============================================================================
 ; 2 x f64
 ; ==============================================================================
 ; CHECK-LABEL: const_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype const_v2f64 () -> (v128){{$}}
 ; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=, 0x1.60504030201p-911, 0x1.e0d0c0b0a0908p-783{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @const_v2f64() {
   ret <2 x double> <double 0x0706050403020100, double 0x0F0E0D0C0B0A0908>
 }
 
 ; CHECK-LABEL: splat_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param f64{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype splat_v2f64 (f64) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.splat $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @splat_v2f64(double %x) {
   %t1 = insertelement <2 x double> zeroinitializer, double %x, i3 0
   %res = insertelement <2 x double> %t1, double %x, i32 1
   ret <2 x double> %res
 }
 
 ; CHECK-LABEL: const_splat_v2f64:
 ; SIMD128: f64x2.splat
 define <2 x double> @const_splat_v2f64() {
   ret <2 x double> <double 42., double 42.>
 }
 
 ; CHECK-LABEL: extract_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result f64{{$}}
+; SIMD128-NEXT: .functype extract_v2f64 (v128) -> (f64){{$}}
 ; SIMD128-NEXT: f64x2.extract_lane $push[[R:[0-9]+]]=, $0, 1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define double @extract_v2f64(<2 x double> %v) {
   %elem = extractelement <2 x double> %v, i32 1
   ret double %elem
 }
 
 ; CHECK-LABEL: extract_var_v2f64:
 ; NO-SIMD128-NOT: i62x2
-; SIMD128-NEXT: .param v128, i32{{$}}
-; SIMD128-NEXT: .result f64{{$}}
+; SIMD128-NEXT: .functype extract_var_v2f64 (v128, i32) -> (f64){{$}}
 ; SIMD128-NEXT: get_global $push[[L0:[0-9]+]]=, __stack_pointer@GLOBAL{{$}}
 ; SIMD128-NEXT: i32.const $push[[L1:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.sub $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; SIMD128-NEXT: tee_local $push[[L3:[0-9]+]]=, $2=, $pop[[L2]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[L3]]), $0{{$}}
 ; SIMD128-NEXT: i32.const $push[[L2:[0-9]+]]=, 1{{$}}
 ; SIMD128-NEXT: i32.and $push[[L5:[0-9]+]]=, $1, $pop[[L2]]{{$}}
 ; SIMD128-NEXT: i32.const $push[[L6:[0-9]+]]=, 3{{$}}
 ; SIMD128-NEXT: i32.shl $push[[L7:[0-9]+]]=, $pop[[L5]], $pop[[L6]]{{$}}
 ; SIMD128-NEXT: i32.or $push[[L2:[0-9]+]]=, $2, $pop[[L7]]{{$}}
 ; SIMD128-NEXT: f64.load $push[[R:[0-9]+]]=, 0($pop[[L2]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define double @extract_var_v2f64(<2 x double> %v, i32 %i) {
   %elem = extractelement <2 x double> %v, i32 %i
   ret double %elem
 }
 
 ; CHECK-LABEL: extract_undef_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param v128{{$}}
-; SIMD128-NEXT: .result f64{{$}}
+; SIMD128-NEXT: .functype extract_undef_v2f64 (v128) -> (f64){{$}}
 ; SIMD128-NEXT: f64x2.extract_lane $push[[R:[0-9]+]]=, $0, 0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define double @extract_undef_v2f64(<2 x double> %v) {
   %elem = extractelement <2 x double> %v, i32 undef
   ret double %elem
 }
 
 ; CHECK-LABEL: replace_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param v128, f64{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype replace_v2f64 (v128, f64) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.replace_lane $push[[R:[0-9]+]]=, $0, 0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @replace_v2f64(<2 x double> %v, double %x) {
   %res = insertelement <2 x double> %v, double %x, i32 0
   ret <2 x double> %res
 }
 
 ; CHECK-LABEL: replace_var_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param v128, i32, f64{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype replace_var_v2f64 (v128, i32, f64) -> (v128){{$}}
 ; SIMD128-NEXT: get_global $push[[L0:[0-9]+]]=, __stack_pointer@GLOBAL{{$}}
 ; SIMD128-NEXT: i32.const $push[[L1:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.sub $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; SIMD128-NEXT: tee_local $push[[L3:[0-9]+]]=, $3=, $pop[[L2]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[L3]]), $0{{$}}
 ; SIMD128-NEXT: i32.const $push[[L2:[0-9]+]]=, 1{{$}}
 ; SIMD128-NEXT: i32.and $push[[L5:[0-9]+]]=, $1, $pop[[L2]]{{$}}
 ; SIMD128-NEXT: i32.const $push[[L6:[0-9]+]]=, 3{{$}}
 ; SIMD128-NEXT: i32.shl $push[[L7:[0-9]+]]=, $pop[[L5]], $pop[[L6]]{{$}}
 ; SIMD128-NEXT: i32.or $push[[L2:[0-9]+]]=, $3, $pop[[L7]]{{$}}
 ; SIMD128-NEXT: f64.store 0($pop[[L2]]), $2{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($3){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @replace_var_v2f64(<2 x double> %v, i32 %i, double %x) {
   %res = insertelement <2 x double> %v, double %x, i32 %i
   ret <2 x double> %res
 }
 
 ; CHECK-LABEL: replace_undef_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param v128, f64{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype replace_undef_v2f64 (v128, f64) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.replace_lane $push[[R:[0-9]+]]=, $0, 0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @replace_undef_v2f64(<2 x double> %v, double %x) {
   %res = insertelement <2 x double> %v, double %x, i32 undef
   ret <2 x double> %res
 }
 
 ; CHECK-LABEL: shuffle_v2f64:
 ; NO-SIMD128-NOT: v8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shuffle_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
 ; SIMD128-SAME: 0, 1, 2, 3, 4, 5, 6, 7, 24, 25, 26, 27, 28, 29, 30, 31{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @shuffle_v2f64(<2 x double> %x, <2 x double> %y) {
   %res = shufflevector <2 x double> %x, <2 x double> %y,
     <2 x i32> <i32 0, i32 3>
   ret <2 x double> %res
 }
 
 ; CHECK-LABEL: shuffle_undef_v2f64:
 ; NO-SIMD128-NOT: v8x16
-; SIMD128-NEXT: .param v128, v128{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype shuffle_undef_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
 ; SIMD128-SAME: 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 0, 0, 0, 0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @shuffle_undef_v2f64(<2 x double> %x, <2 x double> %y) {
   %res = shufflevector <2 x double> %x, <2 x double> %y,
     <2 x i32> <i32 1, i32 undef>
   ret <2 x double> %res
 }
 
 ; CHECK-LABEL: build_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
-; SIMD128-NEXT: .param f64, f64{{$}}
-; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: .functype build_v2f64 (f64, f64) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.splat $push[[L0:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: f64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L0]], 1, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @build_v2f64(double %x0, double %x1) {
   %t0 = insertelement <2 x double> undef, double %x0, i32 0
   %res = insertelement <2 x double> %t0, double %x1, i32 1
   ret <2 x double> %res
 }

test/CodeGen/WebAssembly/store.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -fast-isel -fast-isel-abort=1 | FileCheck %s
 
 ; Test that basic stores are assembled properly.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: sti32:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype sti32 (i32, i32) -> (){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i32.store 0($pop[[L0]]), $pop[[L1]]{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti32(i32 *%p, i32 %v) {
   store i32 %v, i32* %p
   ret void
 }
 
 ; CHECK-LABEL: sti64:
-; CHECK-NEXT: .param i32, i64{{$}}
+; CHECK-NEXT: .functype sti64 (i32, i64) -> (){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i64.store 0($pop[[L0]]), $pop[[L1]]{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti64(i64 *%p, i64 %v) {
   store i64 %v, i64* %p
   ret void
 }
 
 ; CHECK-LABEL: stf32:
-; CHECK-NEXT: .param i32, f32{{$}}
+; CHECK-NEXT: .functype stf32 (i32, f32) -> (){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: f32.store 0($pop[[L0]]), $pop[[L1]]{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @stf32(float *%p, float %v) {
   store float %v, float* %p
   ret void
 }
 
 ; CHECK-LABEL: stf64:
-; CHECK-NEXT: .param i32, f64{{$}}
+; CHECK-NEXT: .functype stf64 (i32, f64) -> (){{$}}
 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: get_local $push[[L1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: f64.store 0($pop[[L0]]), $pop[[L1]]{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @stf64(double *%p, double %v) {
   store double %v, double* %p
   ret void
 }

test/CodeGen/WebAssembly/unsupported-function-bitcasts.ll

 ; RUN: llc < %s -asm-verbose=false -wasm-keep-registers | FileCheck %s
 
 ; Test that function pointer casts that require conversions of arguments or
 ; return types are converted to unreachable.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 declare i32 @has_i64_arg(i64)
 declare i32 @has_ptr_arg(i8*)
 
 ; CHECK-LABEL: test_invalid_rtn:
-; CHECK-NEXT: i32.const   $push[[L0:[0-9]+]]=, 0{{$}}
+; CHECK:      i32.const   $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i32.call $push[[L1:[0-9]+]]=, .Lhas_i64_arg_bitcast_invalid.2@FUNCTION, $pop[[L0]]{{$}}
 ; CHECK-NEXT: drop $pop[[L1]]{{$}}
 ; CHECK-NEXT: i64.const   $push[[L0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: i64.call $push[[L1:[0-9]+]]=, .Lhas_i64_arg_bitcast_invalid@FUNCTION, $pop[[L0]]{{$}}
 ; CHECK-NEXT: drop $pop[[L1]]{{$}}
 ; CHECK-NEXT: end_function
 define void @test_invalid_rtn() {
 entry:
   call i32 bitcast (i32 (i64)* @has_i64_arg to i32 (i32)*)(i32 0)
   call [1 x i64] bitcast (i32 (i64)* @has_i64_arg to [1 x i64] (i64)*)(i64 0)
   ret void
 }
 
 ; CHECK-LABEL: test_struct_rtn:
 ; CHECK:  call      has_i64_arg@FUNCTION, $pop6, $pop0
 define void @test_struct_rtn() {
   call {i32, i32} bitcast (i32 (i64)* @has_i64_arg to {i32, i32} (i64)*)(i64 0)
   ret void
 }
 
 ; CHECK-LABEL: test_invalid_arg:
-; CHECK-NEXT:   i32.const $push[[L0:[0-9]+]]=, 2{{$}}
+; CHECK:        i32.const $push[[L0:[0-9]+]]=, 2{{$}}
 ; CHECK-NEXT:   i32.call  $push[[L1:[0-9]+]]=, .Lhas_ptr_arg_bitcast_invalid.4@FUNCTION, $pop[[L0]]{{$}}
 ; CHECK-NEXT:   drop  $pop[[L1]]{{$}}
 ; CHECK-NEXT:   i32.const $push[[L0:[0-9]+]]=, 2{{$}}
 ; CHECK-NEXT:   i32.call  $push[[L1:[0-9]+]]=, has_ptr_arg@FUNCTION, $pop[[L0]]{{$}}
 ; CHECK-NEXT:   drop  $pop[[L1]]{{$}}
 ; CHECK-NEXT:   i64.const $push[[L0:[0-9]+]]=, 3{{$}}
 ; CHECK-NEXT:   i32.call  $push[[L1:[0-9]+]]=, .Lhas_ptr_arg_bitcast_invalid@FUNCTION, $pop[[L0]]{{$}}
 ; CHECK-NEXT:   drop  $pop[[L1]]{{$}}
 ; CHECK-NEXT:   end_function
 define void @test_invalid_arg() {
 entry:
   call i32 bitcast (i32 (i8*)* @has_ptr_arg to i32 (i8)*)(i8 2)
   call i32 bitcast (i32 (i8*)* @has_ptr_arg to i32 (i32)*)(i32 2)
   call i32 bitcast (i32 (i8*)* @has_ptr_arg to i32 (i64)*)(i64 3)
   ret void
 }
 
 ; CHECK-LABEL: .Lhas_i64_arg_bitcast_invalid:
-; CHECK-NEXT:  .param   i64
-; CHECK-NEXT:  .result  i64
+; CHECK-NEXT:  .functype .Lhas_i64_arg_bitcast_invalid (i64) -> (i64)
 ; CHECK-NEXT:  unreachable
 ; CHECK-NEXT:  end_function
 
 ; CHECK-LABEL: .Lhas_i64_arg_bitcast_invalid.2:
-; CHECK-NEXT:  .param   i32
-; CHECK-NEXT:  .result  i32
+; CHECK-NEXT:  .functype .Lhas_i64_arg_bitcast_invalid.2 (i32) -> (i32)
 ; CHECK-NEXT:  unreachable
 ; CHECK-NEXT:  end_function
 
 ; CHECK-LABEL: .Lhas_ptr_arg_bitcast_invalid:
-; CHECK-NEXT:   .param    i64
-; CHECK-NEXT:   .result   i32
+; CHECK-NEXT:   .functype .Lhas_ptr_arg_bitcast_invalid (i64) -> (i32)
 ; CHECK-NEXT:   unreachable
 ; CHECK-NEXT:   end_function
 
 ; CHECK-LABEL: .Lhas_ptr_arg_bitcast_invalid.4:
-; CHECK-NEXT:   .param    i32
-; CHECK-NEXT:   .result   i32
+; CHECK-NEXT:   .functype .Lhas_ptr_arg_bitcast_invalid.4 (i32) -> (i32)
 ; CHECK-NEXT:   unreachable
 ; CHECK-NEXT:   end_function

test/CodeGen/WebAssembly/unused-argument.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
 
 ; Make sure that argument offsets are correct even if some arguments are unused.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: unused_first:
-; CHECK-NEXT: .param i32, i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype unused_first (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: return $1{{$}}
 define i32 @unused_first(i32 %x, i32 %y) {
   ret i32 %y
 }
 
 ; CHECK-LABEL: unused_second:
-; CHECK-NEXT: .param i32, i32{{$}}
-; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .functype unused_second (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: return $0{{$}}
 define i32 @unused_second(i32 %x, i32 %y) {
   ret i32 %x
 }
 
 ; CHECK-LABEL: call_something:
-; CHECK-NEXT: {{^}} i32.call $drop=, return_something@FUNCTION{{$}}
+; CHECK:      {{^}} i32.call $drop=, return_something@FUNCTION{{$}}
 ; CHECK-NEXT: return{{$}}
 declare i32 @return_something()
 define void @call_something() {
   call i32 @return_something()
   ret void
 }

test/CodeGen/WebAssembly/userstack.ll

define void @frameaddress_0() {
   %t = call i8* @llvm.frameaddress(i32 0)
   call void @use_i8_star(i8* %t)
   ret void
 }
 
 ; Test __builtin_frame_address(1).
 
 ; CHECK-LABEL: frameaddress_1:
-; CHECK-NEXT: i32.const $push0=, 0{{$}}
+; CHECK:      i32.const $push0=, 0{{$}}
 ; CHECK-NEXT: call use_i8_star@FUNCTION, $pop0{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @frameaddress_1() {
   %t = call i8* @llvm.frameaddress(i32 1)
   call void @use_i8_star(i8* %t)
   ret void
 }
 

test/CodeGen/WebAssembly/varargs.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -verify-machineinstrs | FileCheck %s
 
 ; Test varargs constructs.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; Test va_start.
 
 ; TODO: Test va_start.
 ; CHECK-LABEL: start:
-; CHECK-NEXT: .param i32, i32
+; CHECK-NEXT: .functype start (i32, i32) -> ()
 ; CHECK-NOT: __stack_pointer
 define void @start(i8** %ap, ...) {
 entry:
   %0 = bitcast i8** %ap to i8*
 ; Store the second argument (the hidden vararg buffer pointer) into ap
 ; CHECK: i32.store 0($0), $1
   call void @llvm.va_start(i8* %0)
   ret void
 }
 
 ; Test va_end.
 
 ; CHECK-LABEL: end:
-; CHECK-NEXT: .param i32{{$}}
+; CHECK-NEXT: .functype end (i32) -> (){{$}}
 ; CHECK-NEXT: return{{$}}
 define void @end(i8** %ap) {
 entry:
   %0 = bitcast i8** %ap to i8*
   call void @llvm.va_end(i8* %0)
   ret void
 }
 
 ; Test va_copy.
 
 ; CHECK-LABEL: copy:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype copy (i32, i32) -> (){{$}}
 ; CHECK-NEXT: i32.load  $push0=, 0($1){{$}}
 ; CHECK-NEXT: i32.store 0($0), $pop0{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @copy(i8** %ap, i8** %bp) {
 entry:
   %0 = bitcast i8** %ap to i8*
   %1 = bitcast i8** %bp to i8*
   call void @llvm.va_copy(i8* %0, i8* %1)
   ret void
 }
 
 ; Test va_arg with an i8 argument.
 
 ; CHECK-LABEL: arg_i8:
-; CHECK-NEXT: .param     i32{{$}}
-; CHECK-NEXT: .result    i32{{$}}
+; CHECK-NEXT: .functype arg_i8 (i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.load   $push[[NUM0:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: tee_local  $push[[NUM1:[0-9]+]]=, $1=, $pop[[NUM0]]{{$}}
 ; CHECK-NEXT: i32.const  $push[[NUM2:[0-9]+]]=, 4{{$}}
 ; CHECK-NEXT: i32.add    $push[[NUM3:[0-9]+]]=, $pop[[NUM1]], $pop[[NUM2]]{{$}}
 ; CHECK-NEXT: i32.store  0($0), $pop[[NUM3]]{{$}}
 ; CHECK-NEXT: i32.load   $push[[NUM4:[0-9]+]]=, 0($1){{$}}
 ; CHECK-NEXT: return     $pop[[NUM4]]{{$}}
 define i8 @arg_i8(i8** %ap) {
 entry:
   %t = va_arg i8** %ap, i8
   ret i8 %t
 }
 
 ; Test va_arg with an i32 argument.
 
 ; CHECK-LABEL: arg_i32:
-; CHECK-NEXT: .param     i32{{$}}
-; CHECK-NEXT: .result    i32{{$}}
+; CHECK-NEXT: .functype arg_i32 (i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.load   $push[[NUM0:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: i32.const  $push[[NUM1:[0-9]+]]=, 3{{$}}
 ; CHECK-NEXT: i32.add    $push[[NUM2:[0-9]+]]=, $pop[[NUM0]], $pop[[NUM1]]{{$}}
 ; CHECK-NEXT: i32.const  $push[[NUM3:[0-9]+]]=, -4{{$}}
 ; CHECK-NEXT: i32.and    $push[[NUM4:[0-9]+]]=, $pop[[NUM2]], $pop[[NUM3]]{{$}}
 ; CHECK-NEXT: tee_local  $push[[NUM5:[0-9]+]]=, $1=, $pop[[NUM4]]{{$}}
 ; CHECK-NEXT: i32.const  $push[[NUM6:[0-9]+]]=, 4{{$}}
 ; CHECK-NEXT: i32.add    $push[[NUM7:[0-9]+]]=, $pop[[NUM5]], $pop[[NUM6]]{{$}}
 ; CHECK-NEXT: i32.store  0($0), $pop[[NUM7]]{{$}}
 ; CHECK-NEXT: i32.load   $push[[NUM8:[0-9]+]]=, 0($1){{$}}
 ; CHECK-NEXT: return     $pop[[NUM8]]{{$}}
 define i32 @arg_i32(i8** %ap) {
 entry:
   %t = va_arg i8** %ap, i32
   ret i32 %t
 }
 
 ; Test va_arg with an i128 argument.
 
 ; CHECK-LABEL: arg_i128:
-; CHECK-NEXT: .param i32, i32{{$}}
+; CHECK-NEXT: .functype arg_i128 (i32, i32) -> (){{$}}
 ; CHECK: i32.and
 ; CHECK: i64.load
 ; CHECK: i64.load
 ; CHECK: return{{$}}
 define i128 @arg_i128(i8** %ap) {
 entry:
   %t = va_arg i8** %ap, i128
   ret i128 %t
 }
 
 ; Test a varargs call with no actual arguments.
 
 declare void @callee(...)
 
 ; CHECK-LABEL: caller_none:
-; CHECK-NEXT: i32.const $push0=, 0
+; CHECK:      i32.const $push0=, 0
 ; CHECK-NEXT: call callee@FUNCTION, $pop0
 ; CHECK-NEXT: return{{$}}
 define void @caller_none() {
   call void (...) @callee()
   ret void
 }
 
 ; Test a varargs call with some actual arguments.
 ; Note that the store of 2.0 is converted to an i64 store; this optimization
 ; is not needed on WebAssembly, but there isn't currently a convenient hook for
 ; disabling it.
 
 ; CHECK-LABEL: caller_some
 ; CHECK-DAG: i32.store
 ; CHECK-DAG: i64.store
 define void @caller_some() {
   call void (...) @callee(i32 0, double 2.0)
   ret void
 }
 
 ; Test a va_start call in a non-entry block
 ; CHECK-LABEL: startbb:
-; CHECK: .param i32, i32, i32
+; CHECK: .functype startbb (i32, i32, i32) -> ()
 define void @startbb(i1 %cond, i8** %ap, ...) {
 entry:
   br i1 %cond, label %bb0, label %bb1
 bb0:
   ret void
 bb1:
   %0 = bitcast i8** %ap to i8*
 ; Store the second argument (the hidden vararg buffer pointer) into ap

 define void @call_nonlegal_fixed() nounwind {
   call void (fp128, ...) @callee_with_nonlegal_fixed(fp128 0xL00000000000000000000000000000000)
   ret void
 }
 
 ; Test a definition a varargs function with a non-legal fixed argument.
 
 ; CHECK-LABEL: nonlegal_fixed:
-; CHECK-NEXT: .param          i64, i64, i32{{$}}
+; CHECK-NEXT: .functype nonlegal_fixed (i64, i64, i32) -> (){{$}}
 define void @nonlegal_fixed(fp128 %x, ...) nounwind {
   ret void
 }
 
 declare void @llvm.va_start(i8*)
 declare void @llvm.va_end(i8*)
 declare void @llvm.va_copy(i8*, i8*)

test/MC/WebAssembly/basic-assembly.s

 # RUN: llvm-mc -triple=wasm32-unknown-unknown -mattr=+simd128,+nontrapping-fptoint,+exception-handling < %s | FileCheck %s
 # this one is just here to see if it converts to .o without errors, but doesn't check any output:
 # RUN: llvm-mc -triple=wasm32-unknown-unknown -filetype=obj -mattr=+simd128,+nontrapping-fptoint,+exception-handling < %s
 
     .text
     .section .text.main,"",@
     .type    test0,@function
 test0:
     # Test all types:
-    .param      i32, i64
-    .result     i32
+    .functype   test0 (i32, i64) -> (i32)
     .local      f32, f64, v128, v128
     # Explicit getlocal/setlocal:
     get_local   2
     set_local   2
     # Immediates:
     i32.const   -1
     f64.const   0x1.999999999999ap1
     v128.const  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
.LBB0_5:
     get_global  __stack_pointer@GLOBAL
     end_function
 .Lfunc_end0:
   .size test0, .Lfunc_end0-test0
     .globaltype __stack_pointer, i32
 
 # CHECK:           .text
 # CHECK-LABEL: test0:
-# CHECK-NEXT:      .param      i32, i64
-# CHECK-NEXT:      .result     i32
+# CHECK-NEXT:      .functype test0 (i32, i64) -> (i32)
 # CHECK-NEXT:      .local      f32, f64
 # CHECK-NEXT:      get_local   2
 # CHECK-NEXT:      set_local   2
 # CHECK-NEXT:      i32.const   -1
 # CHECK-NEXT:      f64.const   0x1.999999999999ap1
 # CHECK-NEXT:      v128.const  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
 # CHECK-NEXT:      v128.const  0, 1, 2, 3, 4, 5, 6, 7
 # CHECK-NEXT:      get_local   0