[NFC][AArch64] Split out backend features

[dnsampaio]

Summary

This patch splits backend features currently hidden behind architecture versions.
For example, currently the only way to activate complex numbers extension is targeting an v8.3 architecture, where after the patch this extension can be added separately.
This refactoring is required by the new command lines proposal:
http://lists.llvm.org/pipermail/llvm-dev/2018-September/126346.html

[DavidSpickett]

lib/Target/AArch64/AArch64InstrInfo.td

46

Can you clarify what RASv8_4 adds? Is it a 'crypto' situation where the v8_4 meaning of crypto includes the previous meaning of crypto?

I'm wondering if these instructions are better described as requiring v8.4 and RAS, but I'd need to check the spec to get a better idea. If what it adds is completely separate then a new feature is probably fine.

2680–2682

Nitpick: add a blank line here.

test/MC/AArch64/armv8.2a-persistent-memory.s

7

(just picked a random test line, it's not important which one)

What's our usual policy where an instruction could be enabled by a feature or an arch? Do we currently say:
instr requires: one of armv8.x, feature
Or, as this line does:
instr requires feature

I'm not bothered about adding that information if we don't already do it, but we should follow previous precedent.

test/MC/AArch64/armv8.3a-signed-pointer.s

142

I think these lines are out of order, it may be ignoring this first line. (and it's the only '^' in this file so it sticks out)

[DavidSpickett]

Also, is this really NFC? It should be no change to existing usage, but it adds new options so that's a change at least to llvm-mc.

[dnsampaio]

lib/Target/AArch64/AArch64InstrInfo.td

46

RAS v8.4 imposes less constraints of use of the barrier (ESB) use, from RAS (v8.2). It also add new features. So it is sort of a 'crypto' thing.

However, I would prefer to split the feature into rasv8_4, and declare that it implies the older RAS. Keeping a distinct feature makes it easier to backported it to ARM v8.3, if ever required.

test/MC/AArch64/armv8.2a-persistent-memory.s

7

That comes directly from tablegen, and it goes with the name of the feature that it requires. Unfortunately, tablegen won't allow to say it requires ccpp OR armv8.x.

I relied on the test of dotprod, where it says only requires dotprod.

test/MC/AArch64/armv8.3a-signed-pointer.s

142

Not really. I'm ensuring that in the file with the missing requirements, there is no other line between
msr apgakeyhi_el1, x0
and
pacia x0, x1

using CHECK-REQ-NEXT:

CHECK-REQ: error: expected writable system register or pstate
CHECK-REQ-NEXT: msr apgakeyhi_el1, x0
CHECK-REQ-NEXT: ^
CHECK-REQ-NEXT: error: instruction requires: pa
// CHECK-REQ-NEXT: pacia x0, x1

[dnsampaio]

Added FeatureRASv8_4 implies RAS.
NIT fix.

[bryanpkc]

lib/Target/AArch64/AArch64.td

88

Shouldn't this feature imply FeatureID_ISAR6_EL1 instead of FeatureID_AA64MMFR2_EL1?

220

Shouldn't this feature imply FeatureID_ISAR6_EL1 instead of FeatureID_AA64MMFR2_EL1?

229

Shouldn't this feature imply FeatureID_ISAR6_EL1 instead of FeatureID_AA64MMFR2_EL1?

IMO, the description should say Javascript or JavaScript to make it easier to grep.

273

The architecture reference manual states that the ARMv8.4-TLBI feature is identified by ID_AA64ISAR0_EL1.TLB, not ID_AA64MMFR2_EL1. Is this discrepancy intentional?

[olista01]

Have you discussed these feature names with the GCC devs? I know we can change the user-facing names used by clang in in TargetParser, but it's easier for us if they match.

For the feature registers (ISAR6 and MMFR2), maybe we should just make these registers always available? These registers are all defined to read as all-zeroes in older architectures, which means no features described by that register are implemented. If we continue like this then we will have to add an extra feature to pretty much every new architectural feature for the ID register.

lib/Target/AArch64/AArch64.td

36

Why is this up here, and not with the other v8.2A features?

[dnsampaio]

Hi @olista01 and @bryanpkc. Thanks for the reviews.

In D54633#1306653, @olista01 wrote:

Have you discussed these feature names with the GCC devs? I know we can change the user-facing names used by clang in in TargetParser, but it's easier for us if they match.

Indeed I did not. As you said, they are not visible to the user. I'll check with the gcc devs how they have these features split and named though.

For the feature registers (ISAR6 and MMFR2), maybe we should just make these registers always available? These registers are all defined to read as all-zeroes in older architectures, which means no features described by that register are implemented. If we continue like this then we will have to add an extra feature to pretty much every new architectural feature for the ID register.

Indeed it seems the case for the ID_ISAR6_EL1 exist, so I'll just remove the constraints over it.
However, the ID_AA64MMFR2_EL1 register was added in v8.2. So I believe we should check as to warn the user if he might get undefined behavior by accessing it when not present.

lib/Target/AArch64/AArch64.td

36

I have not seen any pstates and registers Features before, so I created a region apart. No technical problem with it. I'll move UAO to the other features.

88

Indeed, ID_ISAR6_EL1 is used in arm32, not arm64. In arm64 it is identified using ID_AA64ISAR0_EL1, that has no constraints. So I can just remove this implication.

220

Yes, and same as the above, the implication is not required.

229

You are right with the naming. The space in Java Script was not intentional.
Nice catch again about the registers. Indeed for arm64 it is ID_AA64ISAR0_EL1.FHM using bits [51:48]. So I can just remove this implication.

273

Indeed the TLB instructions features are identified by ID_AA64ISAR0_EL1[59:56].
However, the use for TTL field in address operations is identified by ID_AA64MMFR2_EL1[51:48] field TTL. So this feature holds true. Even if the processor does not support it, it requires the register to tell it does not support it.

[dnsampaio]

Fixed:
the features implications/dependencies.
the name of the JavaScript conversion feature.
some test files.

@olista01: Most GCC devs I asked about internal feature names emphatically said that sync of internal names of features is not required. And most of the features are not even visible internally, as they are also associated with architecture reviews. So not much to do about that.

So I tried to make their description as close as possible to the reference manual, as to make it easy to grep for them. Further changes for defining arguments should be straightforward.

[bryanpkc]

lib/Target/AArch64/AArch64.td

283

Should FeatureWRC imply FeatureRCPC?

[olista01]

However, the ID_AA64MMFR2_EL1 register was added in v8.2. So I believe we should check as to warn the user if he might get undefined behavior by accessing it when not present.

The encoding of ID_AA64MMFR2_EL1 was defined to read as zero before Armv8.2A, so using it on earlier targets isn't a problem.

lib/Target/AArch64/AArch64.td

61

RAS doesn't use ID_AA64MMFR2_EL1.

93

None of the existing features have the with "has" in the name (first parameter), so I think we should stick with that convention.

231

This feature is in AA64MMFR2_EL1.

238

This should also depend on FeatureFullFP16.

252

Capitalisation: "PArtitioning"

259

I think this name is too generic, trace has always been a part of the 64-bit architecture, this feature just enables some extensions to it.

264

This should be "Activity", not "Active".

271

This name is too generic, maybe "tlbi-range"?

282

This is an extension over FeatureRCPC which adds immediate-offset versions of the instructions, so maybe FeatureRCPC/"rcpc-offset" would be better?

316

These are v8.2-A features, so they should be further up with the other v8.2A features.

lib/Target/AArch64/AArch64InstrInfo.td

2967

This is the "Limited ordering regions" (ARMv8.1-LOR in the ArmARM) extension, not "Virtualization host extensions" (ARMv8.1-VHE). This will need a separate subtarget feature.

lib/Target/AArch64/AArch64SystemOperands.td

67

Why does this depend on FeatureID_AA64MMFR2_EL1? This feature is identified by AA64MMFR1_EL1, not AA64MMFR2_EL1.

340

FeaturePsUAO already depends on FeatureID_AA64MMFR2_EL1, so I don't think we need to mention FeatureID_AA64MMFR2_EL1 here.

1291

This one should be FeaturePA, FeaturePAN is "Privileged Access Never".

[dnsampaio]

lib/Target/AArch64/AArch64.td

61

True.

93

Ok.

238

They FP16 instructions are dependent of FullFP16. In AArch64InstrFormats.td, you will see that such instructions depend on ComplNum, NEON and FullFP16.

259

Ok, will set to TRACEv8_4.

271

tlb-rmi TLB Range and Management Instructions?

283

Yes it should. Indeed the naming is not the best. Will set it to RCPC_IMMO, as for "RCPC with Immediate Offset".

lib/Target/AArch64/AArch64InstrInfo.td

2967

Indeed the feature is there, just got it wrong here. Thanks.

[dnsampaio]

Removed the register (system operand) constraint, and associated test case.
Fixed PAN, RCPC dependencies and instructions that depend on PA, not PAN.
Changed some names to be more meaningful.
Removed the prefix "has" from the features flags.
Fixed tests

[dnsampaio]

Fix the tlb-rmi feature argument and test file.

[dnsampaio]

NIT in the v8.4a trace tests.

[dnsampaio]

Fixed one comment.

[olista01]

A few nits, but otherwise LGTM, no need to re-review after fixing them.

lib/Target/AArch64/AArch64.td

98

Feature name (first parameter) still contains "has".

231

Not done yet?

[olista01]

lib/Target/AArch64/AArch64.td

231

Ah, we decided to remove the subtarget feature for AA64MMFR2_EL1, ignore this.

[dnsampaio]

Trying to fix a windows bot failing test, dividing the test into multiple files and using full line matching.

lib/Target/AArch64/AArch64.td

 
 def FeatureSM4 : SubtargetFeature<
     "sm4", "HasSM4", "true",
     "Enable SM3 and SM4 support", [FeatureNEON]>;
 
 def FeatureSHA2 : SubtargetFeature<
     "sha2", "HasSHA2", "true",
     "Enable SHA1 and SHA256 support", [FeatureNEON]>;
 
 def FeatureSHA3 : SubtargetFeature<
     "sha3", "HasSHA3", "true",
     "Enable SHA512 and SHA3 support", [FeatureNEON, FeatureSHA2]>;
 
 def FeatureAES : SubtargetFeature<
     "aes", "HasAES", "true",
     "Enable AES support", [FeatureNEON]>;
 
 // Crypto has been split up and any combination is now valid (see the
 // crypto defintions above). Also, crypto is now context sensitive:
 // it has a different meaning for e.g. Armv8.4 than it has for Armv8.2.
 // Therefore, we rely on Clang, the user interacing tool, to pass on the
 // appropriate crypto options. But here in the backend, crypto has very little
 // meaning anymore. We kept the Crypto defintion here for backward
 // compatibility, and now imply features SHA2 and AES, which was the
 // "traditional" meaning of Crypto.
 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
   "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>;
 
 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
   "Enable ARMv8 CRC-32 checksum instructions">;
 
 def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
   "Enable ARMv8 Reliability, Availability and Serviceability Extensions">;
 
 def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true",
   "Enable ARMv8.1 Large System Extension (LSE) atomic instructions">;
 
 def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true",
   "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions">;
 
+def FeaturePAN : SubtargetFeature<
+    "pan", "HasPAN", "true",
+    "Enables ARM v8.1 Privileged Access-Never extension">;
+
+def FeatureLOR : SubtargetFeature<
+    "lor", "HasLOR", "true",
+    "Enables ARM v8.1 Limited Ordering Regions extension">;
+
+def FeatureVH : SubtargetFeature<
+    "vh", "HasVH", "true",
+    "Enables ARM v8.1 Virtual Host extension">;
+
 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
   "Enable ARMv8 PMUv3 Performance Monitors extension">;
 
 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
   "Full FP16", [FeatureFPARMv8]>;
 
 def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true",
   "Enable FP16 FML instructions", [FeatureFullFP16]>;
 
 def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
   "Enable Statistical Profiling extension">;
 
+def FeaturePAN_RWV : SubtargetFeature<
+    "pan-rwv", "HasPAN_RWV", "true",
+    "Enable v8.2 PAN s1e1R and s1e1W Variants",
+    [FeaturePAN]>;
+
+// UAO PState
+def FeaturePsUAO : SubtargetFeature< "hasPsUAO", "HasPsUAO", "true",
+    "Enable v8.2 UAO PState">;
+
+def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP",
+    "true", "Enable v8.2 data Cache Clean to Point of Persistence" >;
+
 def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true",
   "Enable Scalable Vector Extension (SVE) instructions">;
 
 def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
                                         "Has zero-cycle register moves">;
 def FeatureZCZeroingGP : SubtargetFeature<"zcz-gp", "HasZeroCycleZeroingGP", "true",
                                         "Has zero-cycle zeroing instructions for generic registers">;
 
def FeatureRCPC : SubtargetFeature<"rcpc", "HasRCPC", "true",
                                    "Enable support for RCPC extension">;
 
 def FeatureUseRSqrt : SubtargetFeature<
     "use-reciprocal-square-root", "UseRSqrt", "true",
     "Use the reciprocal square root approximation">;
 
 def FeatureDotProd : SubtargetFeature<
     "dotprod", "HasDotProd", "true",
     "Enable dot product support">;
 
+def FeaturePA : SubtargetFeature<
+    "pa", "HasPA", "true",
+    "Enable v8.3-A Pointer Authentication enchancement">;
+
+def FeatureJS : SubtargetFeature<
+    "jsconv", "HasJS", "true",
+    "Enable v8.3-A JavaScript FP conversion enchancement",
+    [FeatureFPARMv8]>;
+
+def FeatureCCIDX : SubtargetFeature<
+    "ccidx", "HasCCIDX", "true",
+    "Enable v8.3-A Extend of the CCSIDR number of sets">;
+
+def FeatureComplxNum : SubtargetFeature<
+    "complxnum", "HasComplxNum", "true",
+    "Enable v8.3-A Floating-point complex number support",
+    [FeatureNEON]>;
+
+def FeatureNV : SubtargetFeature<
+    "nv", "HasNV", "true",
+    "Enable v8.4-A Nested Virtualization Enchancement">;
+
+def FeatureRASv8_4 : SubtargetFeature<
+    "rasv8_4", "HasRASv8_4", "true",
+    "Enable v8.4-A Reliability, Availability and Serviceability extension",
+    [FeatureRAS]>;
+
+def FeatureMPAM : SubtargetFeature<
+    "mpam", "HasMPAM", "true",
+    "Enable v8.4-A Memory system Partitioning and Monitoring extension">;
+
+def FeatureDIT : SubtargetFeature<
+    "dit", "HasDIT", "true",
+    "Enable v8.4-A Data Independent Timing instructions">;
+
+def FeatureTRACEV8_4 : SubtargetFeature<
+    "tracev8.4", "HasTRACEV8_4", "true",
+    "Enable v8.4-A Trace extension">;
+
+def FeatureAM : SubtargetFeature<
+    "am", "HasAM", "true",
+    "Enable v8.4-A Activity Monitors extension">;
+
+def FeatureSEL2 : SubtargetFeature<
+    "sel2", "HasSEL2", "true",
+    "Enable v8.4-A Secure Exception Level 2 extension">;
+
+def FeatureTLB_RMI : SubtargetFeature<
+    "tlb-rmi", "HasTLB_RMI", "true",
+    "Enable v8.4-A TLB Range and Maintenance Instructions">;
+
+def FeatureFMI : SubtargetFeature<
+    "fmi", "HasFMI", "true",
+    "Enable v8.4-A Flag Manipulation Instructions">;
+
+// 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset
+def FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true",
+    "Enable v8.4-A RCPC instructions with Immediate Offsets",
+    [FeatureRCPC]>;
+
 def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",
                                         "NegativeImmediates", "false",
                                         "Convert immediates and instructions "
                                         "to their negated or complemented "
                                         "equivalent when the immediate does "
                                         "not fit in the encoding.">;
 
 def FeatureLSLFast : SubtargetFeature<
     "lsl-fast", "HasLSLFast", "true",
     "CPU has a fastpath logical shift of up to 3 places">;

 
 def FeatureSpecCtrl : SubtargetFeature<"specctrl", "HasSpecCtrl", "true",
   "Enable speculation control barrier" >;
 
 def FeaturePredCtrl : SubtargetFeature<"predctrl", "HasPredCtrl", "true",
   "Enable execution and data prediction invalidation instructions" >;
 
 def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP",
-    "true", "Enable Cache Clean to Point of Deep Persistence" >;
+    "true", "Enable v8.5 Cache Clean to Point of Deep Persistence" >;
 
 def FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI",
     "true", "Enable Branch Target Identification" >;
 
 def FeatureRandGen : SubtargetFeature<"rand", "HasRandGen",
     "true", "Enable Random Number generation instructions" >;
 
 def FeatureMTE : SubtargetFeature<"mte", "HasMTE",
     "true", "Enable Memory Tagging Extension" >;
 
 //===----------------------------------------------------------------------===//
 // Architectures.
 //
 
 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
-  "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM]>;
+  "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM,
+  FeaturePAN, FeatureLOR, FeatureVH]>;
 
 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
-  "Support ARM v8.2a instructions", [HasV8_1aOps, FeatureRAS]>;
+  "Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO, 
+  FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>;
 
 def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
-  "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC]>;
+  "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePA,
+  FeatureJS, FeatureCCIDX, FeatureComplxNum]>;
 
 def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
-  "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd]>;
+  "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd,
+  FeatureNV, FeatureRASv8_4, FeatureMPAM, FeatureDIT,
+  FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeatureTLB_RMI,
+  FeatureFMI, FeatureRCPC_IMMO]>;
 
 def HasV8_5aOps : SubtargetFeature<
   "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
   [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict,
    FeatureSpecCtrl, FeaturePredCtrl, FeatureCacheDeepPersist,
    FeatureBranchTargetId]
 >;
 

lib/Target/AArch64/AArch64InstrFormats.td

class BaseSIMDThreeSameVectorComplex<bit Q, bit U, bits<2> size, bits<3> opcode,
   // Non-tied version (FCADD) only has one rotation bit
   let Inst{12}    = rot;
   let Inst{11}    = 0;
   let Inst{10}    = 1;
   let Inst{9-5}   = Rn;
   let Inst{4-0}   = Rd;
 }
 
+//8.3 CompNum - Floating-point complex number support
 multiclass SIMDThreeSameVectorComplexHSD<bit U, bits<3> opcode, Operand rottype,
                                           string asm, SDPatternOperator OpNode>{
-  let Predicates = [HasV8_3a, HasNEON, HasFullFP16] in {
+  let Predicates = [HasComplxNum, HasNEON, HasFullFP16] in {
   def v4f16 : BaseSIMDThreeSameVectorComplex<0, U, 0b01, opcode, V64, rottype,
               asm, ".4h",
               [(set (v4f16 V64:$dst), (OpNode (v4f16 V64:$Rd),
                                               (v4f16 V64:$Rn),
                                               (v4f16 V64:$Rm),
                                               (rottype i32:$rot)))]>;
 
   def v8f16 : BaseSIMDThreeSameVectorComplex<1, U, 0b01, opcode, V128, rottype,
               asm, ".8h",
               [(set (v8f16 V128:$dst), (OpNode (v8f16 V128:$Rd),
                                                (v8f16 V128:$Rn),
                                                (v8f16 V128:$Rm),
                                                (rottype i32:$rot)))]>;
   }
 
-  let Predicates = [HasV8_3a, HasNEON] in {
+  let Predicates = [HasComplxNum, HasNEON] in {
   def v2f32 : BaseSIMDThreeSameVectorComplex<0, U, 0b10, opcode, V64, rottype,
               asm, ".2s",
               [(set (v2f32 V64:$dst), (OpNode (v2f32 V64:$Rd),
                                               (v2f32 V64:$Rn),
                                               (v2f32 V64:$Rm),
                                               (rottype i32:$rot)))]>;
 
   def v4f32 : BaseSIMDThreeSameVectorComplex<1, U, 0b10, opcode, V128, rottype,
class BaseSIMDThreeSameVectorTiedComplex<bit Q, bit U, bits<2> size,
   let Inst{10}    = 1;
   let Inst{9-5}   = Rn;
   let Inst{4-0}   = Rd;
 }
 
 multiclass SIMDThreeSameVectorTiedComplexHSD<bit U, bits<3> opcode,
                                              Operand rottype, string asm,
                                              SDPatternOperator OpNode> {
-  let Predicates = [HasV8_3a, HasNEON, HasFullFP16] in {
+  let Predicates = [HasComplxNum, HasNEON, HasFullFP16] in {
   def v4f16 : BaseSIMDThreeSameVectorTiedComplex<0, U, 0b01, opcode, V64,
               rottype, asm, ".4h",
               [(set (v4f16 V64:$dst), (OpNode (v4f16 V64:$Rd),
                                               (v4f16 V64:$Rn),
                                               (v4f16 V64:$Rm),
                                               (rottype i32:$rot)))]>;
 
   def v8f16 : BaseSIMDThreeSameVectorTiedComplex<1, U, 0b01, opcode, V128,
               rottype, asm, ".8h",
               [(set (v8f16 V128:$dst), (OpNode (v8f16 V128:$Rd),
                                                (v8f16 V128:$Rn),
                                                (v8f16 V128:$Rm),
                                                (rottype i32:$rot)))]>;
   }
 
-  let Predicates = [HasV8_3a, HasNEON] in {
+  let Predicates = [HasComplxNum, HasNEON] in {
   def v2f32 : BaseSIMDThreeSameVectorTiedComplex<0, U, 0b10, opcode, V64,
               rottype, asm, ".2s",
               [(set (v2f32 V64:$dst), (OpNode (v2f32 V64:$Rd),
                                               (v2f32 V64:$Rn),
                                               (v2f32 V64:$Rm),
                                               (rottype i32:$rot)))]>;
 
   def v4f32 : BaseSIMDThreeSameVectorTiedComplex<1, U, 0b10, opcode, V128,
class BaseSIMDIndexedTiedComplex<bit Q, bit U, bit Scalar, bits<2> size,
   let Inst{4-0}   = Rd;
 }
 
 // The complex instructions index by pairs of elements, so the VectorIndexes
 // don't match the lane types, and the index bits are different to the other
 // classes.
 multiclass SIMDIndexedTiedComplexHSD<bit U, bit opc1, bit opc2, Operand rottype,
                                      string asm, SDPatternOperator OpNode> {
-  let Predicates = [HasV8_3a,HasNEON,HasFullFP16] in {
+  let Predicates = [HasComplxNum, HasNEON, HasFullFP16] in {
   def v4f16_indexed : BaseSIMDIndexedTiedComplex<0, 1, 0, 0b01, opc1, opc2, V64,
                       V64, V128, VectorIndexD, rottype, asm, ".4h", ".4h",
                       ".4h", ".h", []> {
     bits<1> idx;
     let Inst{11} = 0;
     let Inst{21} = idx{0};
   }
 
   def v8f16_indexed : BaseSIMDIndexedTiedComplex<1, 1, 0, 0b01, opc1, opc2,
                       V128, V128, V128, VectorIndexS, rottype, asm, ".8h",
                       ".8h", ".8h", ".h", []> {
     bits<2> idx;
     let Inst{11} = idx{1};
     let Inst{21} = idx{0};
   }
-  } // Predicates = [HasV8_3a,HasNEON,HasFullFP16]
+  } // Predicates = HasComplxNum, HasNEON, HasFullFP16]
 
-  let Predicates = [HasV8_3a,HasNEON] in {
+  let Predicates = [HasComplxNum, HasNEON] in {
   def v4f32_indexed : BaseSIMDIndexedTiedComplex<1, 1, 0, 0b10, opc1, opc2,
                       V128, V128, V128, VectorIndexD, rottype, asm, ".4s",
                       ".4s", ".4s", ".s", []> {
     bits<1> idx;
     let Inst{11} = idx{0};
     let Inst{21} = 0;
   }
-  } // Predicates = [HasV8_3a,HasNEON]
+  } // Predicates = [HasComplxNum, HasNEON]
 }
 
 //----------------------------------------------------------------------------
 // Crypto extensions
 //----------------------------------------------------------------------------
 
 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
 class AESBase<bits<4> opc, string asm, dag outs, dag ins, string cstr,

lib/Target/AArch64/AArch64InstrInfo.td

 def HasV8_2a         : Predicate<"Subtarget->hasV8_2aOps()">,
                                  AssemblerPredicate<"HasV8_2aOps", "armv8.2a">;
 def HasV8_3a         : Predicate<"Subtarget->hasV8_3aOps()">,
                                  AssemblerPredicate<"HasV8_3aOps", "armv8.3a">;
 def HasV8_4a         : Predicate<"Subtarget->hasV8_4aOps()">,
                                  AssemblerPredicate<"HasV8_4aOps", "armv8.4a">;
 def HasV8_5a         : Predicate<"Subtarget->hasV8_5aOps()">,
                                  AssemblerPredicate<"HasV8_5aOps", "armv8.5a">;
+def HasVH            : Predicate<"Subtarget->hasVH()">,
+                       AssemblerPredicate<"FeatureVH", "vh">;
+
+def HasLOR           : Predicate<"Subtarget->hasLOR()">,
+                       AssemblerPredicate<"FeatureLOR", "lor">;
+
+def HasPA            : Predicate<"Subtarget->hasPA()">,
+                       AssemblerPredicate<"FeaturePA", "pa">;
+
+def HasJS            : Predicate<"Subtarget->hasJS()">,
+                       AssemblerPredicate<"FeatureJS", "jsconv">;
+
+def HasCCIDX         : Predicate<"Subtarget->hasCCIDX()">,
+                       AssemblerPredicate<"FeatureCCIDX", "ccidx">;
+
+def HasComplxNum      : Predicate<"Subtarget->hasComplxNum()">,
+                       AssemblerPredicate<"FeatureComplxNum", "complxnum">;
+
+def HasNV            : Predicate<"Subtarget->hasNV()">,
+                       AssemblerPredicate<"FeatureNV", "nv">;
+
+def HasRASv8_4       : Predicate<"Subtarget->hasRASv8_4()">,
+                       AssemblerPredicate<"FeatureRASv8_4", "rasv8_4">;
+
+def HasMPAM          : Predicate<"Subtarget->hasMPAM()">,
+                       AssemblerPredicate<"FeatureMPAM", "mpam">;
+
+def HasDIT           : Predicate<"Subtarget->hasDIT()">,
+                       AssemblerPredicate<"FeatureDIT", "dit">;
+
+def HasTRACEV8_4         : Predicate<"Subtarget->hasTRACEV8_4()">,
+                       AssemblerPredicate<"FeatureTRACEV8_4", "tracev8.4">;
+
+def HasAM            : Predicate<"Subtarget->hasAM()">,
+                       AssemblerPredicate<"FeatureAM", "am">;
+
+def HasSEL2          : Predicate<"Subtarget->hasSEL2()">,
+                       AssemblerPredicate<"FeatureSEL2", "sel2">;
+
+def HasTLB_RMI          : Predicate<"Subtarget->hasTLB_RMI()">,
+                       AssemblerPredicate<"FeatureTLB_RMI", "tlb-rmi">;
+
+def HasFMI           : Predicate<"Subtarget->hasFMI()">,
+                       AssemblerPredicate<"FeatureFMI", "fmi">;
+
+def HasRCPC_IMMO      : Predicate<"Subtarget->hasRCPCImm()">,
+                       AssemblerPredicate<"FeatureRCPC_IMMO", "rcpc-immo">;
+
 def HasFPARMv8       : Predicate<"Subtarget->hasFPARMv8()">,
                                AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
 def HasNEON          : Predicate<"Subtarget->hasNEON()">,
                                  AssemblerPredicate<"FeatureNEON", "neon">;
 def HasCrypto        : Predicate<"Subtarget->hasCrypto()">,
                                  AssemblerPredicate<"FeatureCrypto", "crypto">;
 def HasSM4           : Predicate<"Subtarget->hasSM4()">,
                                  AssemblerPredicate<"FeatureSM4", "sm4">;
def DSB   : CRmSystemI<barrier_op, 0b100, "dsb",
                        [(int_aarch64_dsb (i32 imm32_0_15:$CRm))]>;
 
 def ISB   : CRmSystemI<barrier_op, 0b110, "isb",
                        [(int_aarch64_isb (i32 imm32_0_15:$CRm))]>;
 
 def TSB   : CRmSystemI<barrier_op, 0b010, "tsb", []> {
   let CRm        = 0b0010;
   let Inst{12}   = 0;
-  let Predicates = [HasV8_4a];
+  let Predicates = [HasTRACEV8_4];
 }
 }
 
 // ARMv8.2-A Dot Product
 let Predicates = [HasDotProd] in {
 defm SDOT : SIMDThreeSameVectorDot<0, "sdot", int_aarch64_neon_sdot>;
 defm UDOT : SIMDThreeSameVectorDot<1, "udot", int_aarch64_neon_udot>;
 defm SDOTlane : SIMDThreeSameVectorDotIndex<0, "sdot", int_aarch64_neon_sdot>;
let Uses = [X16, X17], Defs = [X17], CRm = 0b0001 in {
   def AUTIB1716  : SystemNoOperands<0b110, "autib1716">;
 }
 
 let Uses = [LR], Defs = [LR], CRm = 0b0000 in {
   def XPACLRI   : SystemNoOperands<0b111, "xpaclri">;
 }
 
 // These pointer authentication isntructions require armv8.3a
-let Predicates = [HasV8_3a] in {
+let Predicates = [HasPA] in {
   multiclass SignAuth<bits<3> prefix, bits<3> prefix_z, string asm> {
     def IA   : SignAuthOneData<prefix, 0b00, !strconcat(asm, "ia")>;
     def IB   : SignAuthOneData<prefix, 0b01, !strconcat(asm, "ib")>;
     def DA   : SignAuthOneData<prefix, 0b10, !strconcat(asm, "da")>;
     def DB   : SignAuthOneData<prefix, 0b11, !strconcat(asm, "db")>;
     def IZA  : SignAuthZero<prefix_z, 0b00, !strconcat(asm, "iza")>;
     def DZA  : SignAuthZero<prefix_z, 0b10, !strconcat(asm, "dza")>;
     def IZB  : SignAuthZero<prefix_z, 0b01, !strconcat(asm, "izb")>;
let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
     def RETAB   : AuthReturn<0b010, 1, "retab">;
     def ERETAA  : AuthReturn<0b100, 0, "eretaa">;
     def ERETAB  : AuthReturn<0b100, 1, "eretab">;
   }
 
   defm LDRAA  : AuthLoad<0, "ldraa", simm10Scaled>;
   defm LDRAB  : AuthLoad<1, "ldrab", simm10Scaled>;
 
-  // v8.3a floating point conversion for javascript
-  let Predicates = [HasV8_3a, HasFPARMv8] in
-  def FJCVTZS  : BaseFPToIntegerUnscaled<0b01, 0b11, 0b110, FPR64, GPR32,
-                                        "fjcvtzs", []> {
-    let Inst{31} = 0;
-  }
-
-} // HasV8_3a
+}
+
+let Predicates = [HasJS, HasFPARMv8] in
+} // HasJS, HasFPARMv8
 
 // v8.4 Flag manipulation instructions
-let Predicates = [HasV8_4a] in {
+let Predicates = [HasFMI] in {
 def CFINV : SimpleSystemI<0, (ins), "cfinv", "">, Sched<[WriteSys]> {
   let Inst{20-5} = 0b0000001000000000;
 }
 def SETF8  : BaseFlagManipulation<0, 0, (ins GPR32:$Rn), "setf8", "{\t$Rn}">;
 def SETF16 : BaseFlagManipulation<0, 1, (ins GPR32:$Rn), "setf16", "{\t$Rn}">;
 def RMIF   : FlagRotate<(ins GPR64:$Rn, uimm6:$imm, imm0_15:$mask), "rmif",
                         "{\t$Rn, $imm, $mask}">;
-} // HasV8_4a
+} // HasFMI
 
 // v8.5 flag manipulation instructions
 let Predicates = [HasAltNZCV], Uses = [NZCV], Defs = [NZCV] in {
 
 def XAFLAG : PstateWriteSimple<(ins), "xaflag", "">, Sched<[WriteSys]> {
   let Inst{18-16} = 0b000;
   let Inst{11-8} = 0b0000;
   let Unpredictable{11-8} = 0b1111;
defm STURQ : StoreUnscaled<0b00, 1, 0b10, FPR128Op, "stur",
                                  (am_unscaled128 GPR64sp:$Rn, simm9:$offset))]>;
 defm STURHH : StoreUnscaled<0b01, 0, 0b00, GPR32z, "sturh",
                          [(truncstorei16 GPR32z:$Rt,
                                  (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
 defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32z, "sturb",
                          [(truncstorei8 GPR32z:$Rt,
                                   (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
 
-// Armv8.4 LDAPR & STLR with Immediate Offset instruction
-let Predicates = [HasV8_4a] in {
+// Armv8.4 Weaker Release Consistency enhancements
+//         LDAPR & STLR with Immediate Offset instructions
+let Predicates = [HasRCPC_IMMO] in {
 defm STLURB     : BaseStoreUnscaleV84<"stlurb",  0b00, 0b00, GPR32>;
 defm STLURH     : BaseStoreUnscaleV84<"stlurh",  0b01, 0b00, GPR32>;
 defm STLURW     : BaseStoreUnscaleV84<"stlur",   0b10, 0b00, GPR32>;
 defm STLURX     : BaseStoreUnscaleV84<"stlur",   0b11, 0b00, GPR64>;
 defm LDAPURB    : BaseLoadUnscaleV84<"ldapurb",  0b00, 0b01, GPR32>;
 defm LDAPURSBW  : BaseLoadUnscaleV84<"ldapursb", 0b00, 0b11, GPR32>;
 defm LDAPURSBX  : BaseLoadUnscaleV84<"ldapursb", 0b00, 0b10, GPR64>;
 defm LDAPURH    : BaseLoadUnscaleV84<"ldapurh",  0b01, 0b01, GPR32>;

 def LDXPX  : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">;
 
 def STLXPW : StoreExclusivePair<0b10, 0, 0, 1, 1, GPR32, "stlxp">;
 def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">;
 
 def STXPW  : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;
 def STXPX  : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
 
-let Predicates = [HasV8_1a] in {
+let Predicates = [HasLOR] in {
   // v8.1a "Limited Order Region" extension load-acquire instructions
   def LDLARW  : LoadAcquire   <0b10, 1, 1, 0, 0, GPR32, "ldlar">;
   def LDLARX  : LoadAcquire   <0b11, 1, 1, 0, 0, GPR64, "ldlar">;
   def LDLARB  : LoadAcquire   <0b00, 1, 1, 0, 0, GPR32, "ldlarb">;
   def LDLARH  : LoadAcquire   <0b01, 1, 1, 0, 0, GPR32, "ldlarh">;
 
   // v8.1a "Limited Order Region" extension store-release instructions
   def STLLRW  : StoreRelease   <0b10, 1, 0, 0, 0, GPR32, "stllr">;

lib/Target/AArch64/AArch64Subtarget.h

protected:
   bool HasLSE = false;
   bool HasRAS = false;
   bool HasRDM = false;
   bool HasPerfMon = false;
   bool HasFullFP16 = false;
   bool HasFP16FML = false;
   bool HasSPE = false;
 
+  // ARMv8.1 extensions
+  bool HasVH = false;
+  bool HasPAN = false;
+  bool HasLOR = false;
+
+  // ARMv8.2 extensions
+  bool HasPsUAO = false;
+  bool HasPAN_RWV = false;
+  bool HasCCPP = false;
+
+  // ARMv8.3 extensions
+  bool HasPA = false;
+  bool HasJS = false;
+  bool HasCCIDX = false;
+  bool HasComplxNum = false;
+
+  // ARMv8.4 extensions
+  bool HasNV = false;
+  bool HasRASv8_4 = false;
+  bool HasMPAM = false;
+  bool HasDIT = false;
+  bool HasTRACEV8_4 = false;
+  bool HasAM = false;
+  bool HasSEL2 = false;
+  bool HasTLB_RMI = false;
+  bool HasFMI = false;
+  bool HasRCPC_IMMO = false;
   // ARMv8.4 Crypto extensions
   bool HasSM4 = true;
   bool HasSHA3 = true;
 
   bool HasSHA2 = true;
   bool HasAES = true;
 
   bool HasLSLFast = false;
public:
   bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
 
   bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
 
   bool useAA() const override { return UseAA; }
 
+  bool hasVH() const { return HasVH; }
+  bool hasPAN() const { return HasPAN; }
+  bool hasLOR() const { return HasLOR; }
+
+  bool hasPsUAO() const { return HasPsUAO; }
+  bool hasPAN_RWV() const { return HasPAN_RWV; }
+  bool hasCCPP() const { return HasCCPP; }
+
+  bool hasPA() const { return HasPA; }
+  bool hasJS() const { return HasJS; }
+  bool hasCCIDX() const { return HasCCIDX; }
+  bool hasComplxNum() const { return HasComplxNum; }
+
+  bool hasNV() const { return HasNV; }
+  bool hasRASv8_4() const { return HasRASv8_4; }
+  bool hasMPAM() const { return HasMPAM; }
+  bool hasDIT() const { return HasDIT; }
+  bool hasTRACEV8_4() const { return HasTRACEV8_4; }
+  bool hasAM() const { return HasAM; }
+  bool hasSEL2() const { return HasSEL2; }
+  bool hasTLB_RMI() const { return HasTLB_RMI; }
+  bool hasFMI() const { return HasFMI; }
+  bool hasRCPC_IMMO() const { return HasRCPC_IMMO; }
+
   bool useSmallAddressing() const {
     switch (TLInfo.getTargetMachine().getCodeModel()) {
       case CodeModel::Kernel:
         // Kernel is currently allowed only for Fuchsia targets,
         // where it is the same as Small for almost all purposes.
       case CodeModel::Small:
         return true;
       default:

lib/Target/AArch64/AArch64SystemOperands.td

 // This file defines the symbolic operands permitted for various kinds of
 // AArch64 system instruction.
 //
 //===----------------------------------------------------------------------===//
 
 include "llvm/TableGen/SearchableTable.td"
 
 //===----------------------------------------------------------------------===//
+// Features that, for the compiler, only enable system operands and PStates
+//===----------------------------------------------------------------------===//
+
+def HasCCPP    : Predicate<"Subtarget->hasCCPP()">,
+                 AssemblerPredicate<"FeatureCCPP", "ccpp">;
+
+def HasPAN     : Predicate<"Subtarget->hasPAN()">,
+                 AssemblerPredicate<"FeaturePAN",
+                 "ARM v8.1  Privileged Access-Never extension">;
+
+def HasPsUAO   : Predicate<"Subtarget->hasPsUAO()">,
+                 AssemblerPredicate<"FeaturePsUAO",
+                 "ARM v8.2 UAO PState extension">;
+
+def HasPAN_RWV : Predicate<"Subtarget->hasPAN_RWV()">,
+                 AssemblerPredicate<"FeaturePAN_RWV",
+                 "ARM v8.2 PAN AT S1E1R and AT S1E1W Variation">;
+
+//===----------------------------------------------------------------------===//
 // AT (address translate) instruction options.
 //===----------------------------------------------------------------------===//
 
 class AT<string name, bits<3> op1, bits<4> crn, bits<4> crm,
          bits<3> op2> : SearchableTable {
   let SearchableFields = ["Name", "Encoding"];
   let EnumValueField = "Encoding";
 

 def : AT<"S1E3W",  0b110, 0b0111, 0b1000, 0b001>;
 def : AT<"S1E0R",  0b000, 0b0111, 0b1000, 0b010>;
 def : AT<"S1E0W",  0b000, 0b0111, 0b1000, 0b011>;
 def : AT<"S12E1R", 0b100, 0b0111, 0b1000, 0b100>;
 def : AT<"S12E1W", 0b100, 0b0111, 0b1000, 0b101>;
 def : AT<"S12E0R", 0b100, 0b0111, 0b1000, 0b110>;
 def : AT<"S12E0W", 0b100, 0b0111, 0b1000, 0b111>;
 
-let Requires = [{ {AArch64::HasV8_2aOps} }] in {
+let Requires = [{ {AArch64::FeaturePAN_RWV} }] in {
 def : AT<"S1E1RP", 0b000, 0b0111, 0b1001, 0b000>;
 def : AT<"S1E1WP", 0b000, 0b0111, 0b1001, 0b001>;
 }
 
 //===----------------------------------------------------------------------===//
 // DMB/DSB (data barrier) instruction options.
 //===----------------------------------------------------------------------===//
 

 def : DC<"IVAC",  0b000, 0b0111, 0b0110, 0b001>;
 def : DC<"ISW",   0b000, 0b0111, 0b0110, 0b010>;
 def : DC<"CVAC",  0b011, 0b0111, 0b1010, 0b001>;
 def : DC<"CSW",   0b000, 0b0111, 0b1010, 0b010>;
 def : DC<"CVAU",  0b011, 0b0111, 0b1011, 0b001>;
 def : DC<"CIVAC", 0b011, 0b0111, 0b1110, 0b001>;
 def : DC<"CISW",  0b000, 0b0111, 0b1110, 0b010>;
 
-let Requires = [{ {AArch64::HasV8_2aOps} }] in
+let Requires = [{ {AArch64::FeatureCCPP} }] in
 def : DC<"CVAP",  0b011, 0b0111, 0b1100, 0b001>;
 
 let Requires = [{ {AArch64::FeatureCacheDeepPersist} }] in
 def : DC<"CVADP",  0b011, 0b0111, 0b1101, 0b001>;
 
 let Requires = [{ {AArch64::FeatureMTE} }] in {
 def : DC<"IGVAC",   0b000, 0b0111, 0b0110, 0b011>;
 def : DC<"IGSW",    0b000, 0b0111, 0b0110, 0b100>;

 class TSB<string name, bits<4> encoding> : SearchableTable{
   let SearchableFields = ["Name", "Encoding"];
   let EnumValueField = "Encoding";
 
   string Name = name;
   bits<4> Encoding;
   let Encoding = encoding;
 
-  code Requires = [{ {AArch64::HasV8_4aOps} }];
+  code Requires = [{ {AArch64::FeatureTRACEV8_4} }];
 }
 
 def : TSB<"csync", 0>;
 
 //===----------------------------------------------------------------------===//
 // PRFM (prefetch) instruction options.
 //===----------------------------------------------------------------------===//
 
class PState<string name, bits<5> encoding> : SearchableTable {
   let Encoding = encoding;
   code Requires = [{ {} }];
 }
 
 def : PState<"SPSel",   0b00101>;
 def : PState<"DAIFSet", 0b11110>;
 def : PState<"DAIFClr", 0b11111>;
 // v8.1a "Privileged Access Never" extension-specific PStates
-let Requires = [{ {AArch64::HasV8_1aOps} }] in
+let Requires = [{ {AArch64::FeaturePAN} }] in
 def : PState<"PAN",     0b00100>;
+
 // v8.2a "User Access Override" extension-specific PStates
-let Requires = [{ {AArch64::HasV8_2aOps} }] in
+let Requires = [{ {AArch64::FeaturePsUAO} }] in
 def : PState<"UAO",     0b00011>;
 // v8.4a timining insensitivity of data processing instructions
-let Requires = [{ {AArch64::HasV8_4aOps} }] in
+let Requires = [{ {AArch64::FeatureDIT} }] in
 def : PState<"DIT",     0b11010>;
 // v8.5a Spectre Mitigation
 let Requires = [{ {AArch64::FeatureSpecRestrict} }] in
 def : PState<"SSBS",    0b11001>;
 // v8.5a Memory Tagging Extension
 let Requires = [{ {AArch64::FeatureMTE} }] in
 def : PState<"TCO",     0b11100>;
 

 def : TLBI<"VAAE1",        0b000, 0b1000, 0b0111, 0b011>;
 def : TLBI<"ALLE1",        0b100, 0b1000, 0b0111, 0b100, 0>;
 def : TLBI<"VALE1",        0b000, 0b1000, 0b0111, 0b101>;
 def : TLBI<"VALE2",        0b100, 0b1000, 0b0111, 0b101>;
 def : TLBI<"VALE3",        0b110, 0b1000, 0b0111, 0b101>;
 def : TLBI<"VMALLS12E1",   0b100, 0b1000, 0b0111, 0b110, 0>;
 def : TLBI<"VAALE1",       0b000, 0b1000, 0b0111, 0b111>;
 
+// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI)
+let Requires = [{ {AArch64::FeatureTLB_RMI} }] in {
 // Armv8.4-A Outer Sharable TLB Maintenance instructions:
-let Requires = [{ {AArch64::HasV8_4aOps} }] in {
 //                         op1    CRn     CRm     op2
 def : TLBI<"VMALLE1OS",    0b000, 0b1000, 0b0001, 0b000, 0>;
 def : TLBI<"VAE1OS",       0b000, 0b1000, 0b0001, 0b001>;
 def : TLBI<"ASIDE1OS",     0b000, 0b1000, 0b0001, 0b010>;
 def : TLBI<"VAAE1OS",      0b000, 0b1000, 0b0001, 0b011>;
 def : TLBI<"VALE1OS",      0b000, 0b1000, 0b0001, 0b101>;
 def : TLBI<"VAALE1OS",     0b000, 0b1000, 0b0001, 0b111>;
 def : TLBI<"IPAS2E1OS",    0b100, 0b1000, 0b0100, 0b000>;

 def : TLBI<"RVAE2OS",      0b100, 0b1000, 0b0101, 0b001>;
 def : TLBI<"RVALE2OS",     0b100, 0b1000, 0b0101, 0b101>;
 def : TLBI<"RVAE3",        0b110, 0b1000, 0b0110, 0b001>;
 def : TLBI<"RVALE3",       0b110, 0b1000, 0b0110, 0b101>;
 def : TLBI<"RVAE3IS",      0b110, 0b1000, 0b0010, 0b001>;
 def : TLBI<"RVALE3IS",     0b110, 0b1000, 0b0010, 0b101>;
 def : TLBI<"RVAE3OS",      0b110, 0b1000, 0b0101, 0b001>;
 def : TLBI<"RVALE3OS",     0b110, 0b1000, 0b0101, 0b101>;
-}
+} //FeatureTLB_RMI
 
 // Armv8.5-A Prediction Restriction by Context instruction options:
 class PRCTX<string name, bits<4> crm> : SearchableTable {
   let SearchableFields = ["Name", "Encoding"];
   let EnumValueField = "Encoding";
 
   string Name = name;
   bits<11> Encoding;

 def : ROSysReg<"DBGDTRRX_EL0",       0b10, 0b011, 0b0000, 0b0101, 0b000>;
 def : ROSysReg<"MDRAR_EL1",          0b10, 0b000, 0b0001, 0b0000, 0b000>;
 def : ROSysReg<"OSLSR_EL1",          0b10, 0b000, 0b0001, 0b0001, 0b100>;
 def : ROSysReg<"DBGAUTHSTATUS_EL1",  0b10, 0b000, 0b0111, 0b1110, 0b110>;
 def : ROSysReg<"PMCEID0_EL0",        0b11, 0b011, 0b1001, 0b1100, 0b110>;
 def : ROSysReg<"PMCEID1_EL0",        0b11, 0b011, 0b1001, 0b1100, 0b111>;
 def : ROSysReg<"MIDR_EL1",           0b11, 0b000, 0b0000, 0b0000, 0b000>;
 def : ROSysReg<"CCSIDR_EL1",         0b11, 0b001, 0b0000, 0b0000, 0b000>;
+
+//v8.3 CCIDX - extending the CCsIDr number of sets
 def : ROSysReg<"CCSIDR2_EL1",        0b11, 0b001, 0b0000, 0b0000, 0b010> {
-  let Requires = [{ {AArch64::HasV8_3aOps} }];
+  let Requires = [{ {AArch64::FeatureCCIDX} }];
 }
 def : ROSysReg<"CLIDR_EL1",          0b11, 0b001, 0b0000, 0b0000, 0b001>;
 def : ROSysReg<"CTR_EL0",            0b11, 0b011, 0b0000, 0b0000, 0b001>;
 def : ROSysReg<"MPIDR_EL1",          0b11, 0b000, 0b0000, 0b0000, 0b101>;
 def : ROSysReg<"REVIDR_EL1",         0b11, 0b000, 0b0000, 0b0000, 0b110>;
 def : ROSysReg<"AIDR_EL1",           0b11, 0b001, 0b0000, 0b0000, 0b111>;
 def : ROSysReg<"DCZID_EL0",          0b11, 0b011, 0b0000, 0b0000, 0b111>;
 def : ROSysReg<"ID_PFR0_EL1",        0b11, 0b000, 0b0000, 0b0001, 0b000>;

 def : ROSysReg<"ID_AA64DFR0_EL1",     0b11, 0b000, 0b0000, 0b0101, 0b000>;
 def : ROSysReg<"ID_AA64DFR1_EL1",     0b11, 0b000, 0b0000, 0b0101, 0b001>;
 def : ROSysReg<"ID_AA64AFR0_EL1",     0b11, 0b000, 0b0000, 0b0101, 0b100>;
 def : ROSysReg<"ID_AA64AFR1_EL1",     0b11, 0b000, 0b0000, 0b0101, 0b101>;
 def : ROSysReg<"ID_AA64ISAR0_EL1",    0b11, 0b000, 0b0000, 0b0110, 0b000>;
 def : ROSysReg<"ID_AA64ISAR1_EL1",    0b11, 0b000, 0b0000, 0b0110, 0b001>;
 def : ROSysReg<"ID_AA64MMFR0_EL1",    0b11, 0b000, 0b0000, 0b0111, 0b000>;
 def : ROSysReg<"ID_AA64MMFR1_EL1",    0b11, 0b000, 0b0000, 0b0111, 0b001>;
-def : ROSysReg<"ID_AA64MMFR2_EL1",    0b11, 0b000, 0b0000, 0b0111, 0b010> {
-  let Requires = [{ {AArch64::HasV8_2aOps} }];
-}
+def : ROSysReg<"ID_AA64MMFR2_EL1",    0b11, 0b000, 0b0000, 0b0111, 0b010>;
 def : ROSysReg<"MVFR0_EL1",          0b11, 0b000, 0b0000, 0b0011, 0b000>;
 def : ROSysReg<"MVFR1_EL1",          0b11, 0b000, 0b0000, 0b0011, 0b001>;
 def : ROSysReg<"MVFR2_EL1",          0b11, 0b000, 0b0000, 0b0011, 0b010>;
 def : ROSysReg<"RVBAR_EL1",          0b11, 0b000, 0b1100, 0b0000, 0b001>;
 def : ROSysReg<"RVBAR_EL2",          0b11, 0b100, 0b1100, 0b0000, 0b001>;
 def : ROSysReg<"RVBAR_EL3",          0b11, 0b110, 0b1100, 0b0000, 0b001>;
 def : ROSysReg<"ISR_EL1",            0b11, 0b000, 0b1100, 0b0001, 0b000>;
 def : ROSysReg<"CNTPCT_EL0",         0b11, 0b011, 0b1110, 0b0000, 0b001>;

 // SVE control registers
 //                                   Op0   Op1    CRn     CRm     Op2
 let Requires = [{ {AArch64::FeatureSVE} }] in {
 def : ROSysReg<"ID_AA64ZFR0_EL1",    0b11, 0b000, 0b0000, 0b0100, 0b100>;
 }
 
 // v8.1a "Limited Ordering Regions" extension-specific system register
 //                         Op0    Op1     CRn     CRm    Op2
-let Requires = [{ {AArch64::HasV8_1aOps} }] in
+let Requires = [{ {AArch64::FeatureLOR} }] in
 def : ROSysReg<"LORID_EL1",  0b11, 0b000, 0b1010, 0b0100, 0b111>;
 
 // v8.2a "RAS extension" registers
 //                         Op0    Op1     CRn     CRm    Op2
 let Requires = [{ {AArch64::FeatureRAS} }] in {
 def : ROSysReg<"ERRIDR_EL1", 0b11, 0b000, 0b0101, 0b0011, 0b000>;
 def : ROSysReg<"ERXFR_EL1",  0b11, 0b000, 0b0101, 0b0100, 0b000>;
 }

 def : RWSysReg<"ICH_LR10_EL2",       0b11, 0b100, 0b1100, 0b1101, 0b010>;
 def : RWSysReg<"ICH_LR11_EL2",       0b11, 0b100, 0b1100, 0b1101, 0b011>;
 def : RWSysReg<"ICH_LR12_EL2",       0b11, 0b100, 0b1100, 0b1101, 0b100>;
 def : RWSysReg<"ICH_LR13_EL2",       0b11, 0b100, 0b1100, 0b1101, 0b101>;
 def : RWSysReg<"ICH_LR14_EL2",       0b11, 0b100, 0b1100, 0b1101, 0b110>;
 def : RWSysReg<"ICH_LR15_EL2",       0b11, 0b100, 0b1100, 0b1101, 0b111>;
 
 // v8.1a "Privileged Access Never" extension-specific system registers
-let Requires = [{ {AArch64::HasV8_1aOps} }] in
+let Requires = [{ {AArch64::FeaturePAN} }] in
 def : RWSysReg<"PAN", 0b11, 0b000, 0b0100, 0b0010, 0b011>;
 
 // v8.1a "Limited Ordering Regions" extension-specific system registers
 //                         Op0    Op1     CRn     CRm    Op2
-let Requires = [{ {AArch64::HasV8_1aOps} }] in {
+let Requires = [{ {AArch64::FeatureLOR} }] in {
 def : RWSysReg<"LORSA_EL1",  0b11, 0b000, 0b1010, 0b0100, 0b000>;
 def : RWSysReg<"LOREA_EL1",  0b11, 0b000, 0b1010, 0b0100, 0b001>;
 def : RWSysReg<"LORN_EL1",   0b11, 0b000, 0b1010, 0b0100, 0b010>;
 def : RWSysReg<"LORC_EL1",   0b11, 0b000, 0b1010, 0b0100, 0b011>;
 }
 
-// v8.1a "Virtualization hos extensions" system registers
+// v8.1a "Virtualization Host extensions" system registers
 //                              Op0    Op1     CRn     CRm    Op2
-let Requires = [{ {AArch64::HasV8_1aOps} }] in {
+let Requires = [{ {AArch64::FeatureVH} }] in {
 def : RWSysReg<"TTBR1_EL2",       0b11, 0b100, 0b0010, 0b0000, 0b001>;
 def : RWSysReg<"CONTEXTIDR_EL2",  0b11, 0b100, 0b1101, 0b0000, 0b001>;
 def : RWSysReg<"CNTHV_TVAL_EL2",  0b11, 0b100, 0b1110, 0b0011, 0b000>;
 def : RWSysReg<"CNTHV_CVAL_EL2",  0b11, 0b100, 0b1110, 0b0011, 0b010>;
 def : RWSysReg<"CNTHV_CTL_EL2",   0b11, 0b100, 0b1110, 0b0011, 0b001>;
 def : RWSysReg<"SCTLR_EL12",      0b11, 0b101, 0b0001, 0b0000, 0b000>;
 def : RWSysReg<"CPACR_EL12",      0b11, 0b101, 0b0001, 0b0000, 0b010>;
 def : RWSysReg<"TTBR0_EL12",      0b11, 0b101, 0b0010, 0b0000, 0b000>;

 def : RWSysReg<"CNTV_TVAL_EL02",  0b11, 0b101, 0b1110, 0b0011, 0b000>;
 def : RWSysReg<"CNTV_CTL_EL02",   0b11, 0b101, 0b1110, 0b0011, 0b001>;
 def : RWSysReg<"CNTV_CVAL_EL02",  0b11, 0b101, 0b1110, 0b0011, 0b010>;
 def : RWSysReg<"SPSR_EL12",       0b11, 0b101, 0b0100, 0b0000, 0b000>;
 def : RWSysReg<"ELR_EL12",        0b11, 0b101, 0b0100, 0b0000, 0b001>;
 }
 // v8.2a registers
 //                  Op0    Op1     CRn     CRm    Op2
-let Requires = [{ {AArch64::HasV8_2aOps} }] in
+let Requires = [{ {AArch64::FeaturePsUAO} }] in
 def : RWSysReg<"UAO", 0b11, 0b000, 0b0100, 0b0010, 0b100>;
 
 // v8.2a "Statistical Profiling extension" registers
 //                            Op0    Op1     CRn     CRm    Op2
 let Requires = [{ {AArch64::FeatureSPE} }] in {
 def : RWSysReg<"PMBLIMITR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b000>;
 def : RWSysReg<"PMBPTR_EL1",    0b11, 0b000, 0b1001, 0b1010, 0b001>;
 def : RWSysReg<"PMBSR_EL1",     0b11, 0b000, 0b1001, 0b1010, 0b011>;

 def : RWSysReg<"ERXMISC1_EL1",  0b11, 0b000, 0b0101, 0b0101, 0b001>;
 def : RWSysReg<"DISR_EL1",      0b11, 0b000, 0b1100, 0b0001, 0b001>;
 def : RWSysReg<"VDISR_EL2",     0b11, 0b100, 0b1100, 0b0001, 0b001>;
 def : RWSysReg<"VSESR_EL2",     0b11, 0b100, 0b0101, 0b0010, 0b011>;
 }
 
 // v8.3a "Pointer authentication extension" registers
 //                              Op0    Op1     CRn     CRm    Op2
-let Requires = [{ {AArch64::HasV8_3aOps} }] in {
+let Requires = [{ {AArch64::FeaturePA} }] in {
 def : RWSysReg<"APIAKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b000>;
 def : RWSysReg<"APIAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b001>;
 def : RWSysReg<"APIBKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b010>;
 def : RWSysReg<"APIBKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b011>;
 def : RWSysReg<"APDAKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b000>;
 def : RWSysReg<"APDAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b001>;
 def : RWSysReg<"APDBKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b010>;
 def : RWSysReg<"APDBKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b011>;
 def : RWSysReg<"APGAKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0011, 0b000>;
 def : RWSysReg<"APGAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0011, 0b001>;
 }
 
-let Requires = [{ {AArch64::HasV8_4aOps} }] in {
-
+// v8.4 "Secure Exception Level 2 extension"
+let Requires = [{ {AArch64::FeatureSEL2} }] in {
 // v8.4a "Virtualization secure second stage translation" registers
 //                           Op0   Op1    CRn     CRm     Op2
 def : RWSysReg<"VSTCR_EL2" , 0b11, 0b100, 0b0010, 0b0110, 0b010>;
 def : RWSysReg<"VSTTBR_EL2", 0b11, 0b100, 0b0010, 0b0110, 0b000>;
 
 // v8.4a "Virtualization timer" registers
 //                                Op0   Op1    CRn     CRm     Op2
 def : RWSysReg<"CNTHVS_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0100, 0b000>;
 def : RWSysReg<"CNTHVS_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0100, 0b010>;
 def : RWSysReg<"CNTHVS_CTL_EL2",  0b11, 0b100, 0b1110, 0b0100, 0b001>;
 def : RWSysReg<"CNTHPS_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b000>;
 def : RWSysReg<"CNTHPS_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b010>;
 def : RWSysReg<"CNTHPS_CTL_EL2",  0b11, 0b100, 0b1110, 0b0101, 0b001>;
 
 // v8.4a "Virtualization debug state" registers
 //                           Op0   Op1    CRn     CRm     Op2
 def : RWSysReg<"SDER32_EL2", 0b11, 0b100, 0b0001, 0b0011, 0b001>;
+} // FeatureSEL2
 
 // v8.4a RAS registers
-//                              Op0   Op1    CRn     CRm    Op2
+//                              Op0   Op1    CRn     CRm     Op2
+let Requires = [{ {AArch64::FeatureRASv8_4} }] in {
 def : RWSysReg<"ERXPFGCTL_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b101>;
 def : RWSysReg<"ERXPFGCDN_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b110>;
 def : RWSysReg<"ERXTS_EL1",     0b11, 0b000, 0b0101, 0b0101, 0b111>;
 def : RWSysReg<"ERXMISC2_EL1",  0b11, 0b000, 0b0101, 0b0101, 0b010>;
 def : RWSysReg<"ERXMISC3_EL1",  0b11, 0b000, 0b0101, 0b0101, 0b011>;
 def : ROSysReg<"ERXPFGF_EL1",   0b11, 0b000, 0b0101, 0b0100, 0b100>;
+} // FeatureRASv8_4
 
 // v8.4a MPAM registers
 //                             Op0   Op1    CRn     CRm     Op2
+let Requires = [{ {AArch64::FeatureMPAM} }] in {
 def : RWSysReg<"MPAM0_EL1",    0b11, 0b000, 0b1010, 0b0101, 0b001>;
 def : RWSysReg<"MPAM1_EL1",    0b11, 0b000, 0b1010, 0b0101, 0b000>;
 def : RWSysReg<"MPAM2_EL2",    0b11, 0b100, 0b1010, 0b0101, 0b000>;
 def : RWSysReg<"MPAM3_EL3",    0b11, 0b110, 0b1010, 0b0101, 0b000>;
 def : RWSysReg<"MPAM1_EL12",   0b11, 0b101, 0b1010, 0b0101, 0b000>;
 def : RWSysReg<"MPAMHCR_EL2",  0b11, 0b100, 0b1010, 0b0100, 0b000>;
 def : RWSysReg<"MPAMVPMV_EL2", 0b11, 0b100, 0b1010, 0b0100, 0b001>;
 def : RWSysReg<"MPAMVPM0_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b000>;
 def : RWSysReg<"MPAMVPM1_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b001>;
 def : RWSysReg<"MPAMVPM2_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b010>;
 def : RWSysReg<"MPAMVPM3_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b011>;
 def : RWSysReg<"MPAMVPM4_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b100>;
 def : RWSysReg<"MPAMVPM5_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b101>;
 def : RWSysReg<"MPAMVPM6_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b110>;
 def : RWSysReg<"MPAMVPM7_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b111>;
 def : ROSysReg<"MPAMIDR_EL1",  0b11, 0b000, 0b1010, 0b0100, 0b100>;
+} //FeatureMPAM
 
-// v8.4a Activitiy monitor registers
+// v8.4a Activitiy Monitor registers
 //                                 Op0   Op1    CRn     CRm     Op2
+let Requires = [{ {AArch64::FeatureAM} }] in {
 def : RWSysReg<"AMCR_EL0",         0b11, 0b011, 0b1101, 0b0010, 0b000>;
 def : ROSysReg<"AMCFGR_EL0",       0b11, 0b011, 0b1101, 0b0010, 0b001>;
 def : ROSysReg<"AMCGCR_EL0",       0b11, 0b011, 0b1101, 0b0010, 0b010>;
 def : RWSysReg<"AMUSERENR_EL0",    0b11, 0b011, 0b1101, 0b0010, 0b011>;
 def : RWSysReg<"AMCNTENCLR0_EL0",  0b11, 0b011, 0b1101, 0b0010, 0b100>;
 def : RWSysReg<"AMCNTENSET0_EL0",  0b11, 0b011, 0b1101, 0b0010, 0b101>;
 def : RWSysReg<"AMEVCNTR00_EL0",   0b11, 0b011, 0b1101, 0b0100, 0b000>;
 def : RWSysReg<"AMEVCNTR01_EL0",   0b11, 0b011, 0b1101, 0b0100, 0b001>;

 def : RWSysReg<"AMEVTYPER18_EL0",  0b11, 0b011, 0b1101, 0b1111, 0b000>;
 def : RWSysReg<"AMEVTYPER19_EL0",  0b11, 0b011, 0b1101, 0b1111, 0b001>;
 def : RWSysReg<"AMEVTYPER110_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b010>;
 def : RWSysReg<"AMEVTYPER111_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b011>;
 def : RWSysReg<"AMEVTYPER112_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b100>;
 def : RWSysReg<"AMEVTYPER113_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b101>;
 def : RWSysReg<"AMEVTYPER114_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b110>;
 def : RWSysReg<"AMEVTYPER115_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b111>;
+} //FeatureAM
 
-// v8.4a Trace Extension registers
+// v8.4a TracTRACEV8_4ension registers
 //
 // Please note that the 8.4 spec also defines these registers:
 // TRCIDR1, ID_DFR0_EL1, ID_AA64DFR0_EL1, MDSCR_EL1, MDCR_EL2, and MDCR_EL3,
 // but they are already defined above.
 //
 //                                 Op0   Op1    CRn     CRm     Op2
+let Requires = [{ {AArch64::FeatureTRACEV8_4} }] in {
 def : RWSysReg<"TRFCR_EL1",        0b11, 0b000, 0b0001, 0b0010, 0b001>;
 def : RWSysReg<"TRFCR_EL2",        0b11, 0b100, 0b0001, 0b0010, 0b001>;
 def : RWSysReg<"TRFCR_EL12",       0b11, 0b101, 0b0001, 0b0010, 0b001>;
+} //FeatureTRACEV8_4
 
 // v8.4a Timining insensitivity of data processing instructions
+// DIT: Data Independent Timing instructions
 //                                 Op0   Op1    CRn     CRm     Op2
+let Requires = [{ {AArch64::FeatureDIT} }] in {
 def : RWSysReg<"DIT",              0b11, 0b011, 0b0100, 0b0010, 0b101>;
+} //FeatureDIT
 
 // v8.4a Enhanced Support for Nested Virtualization
 //                                 Op0   Op1    CRn     CRm     Op2
+let Requires = [{ {AArch64::FeatureNV} }] in {
 def : RWSysReg<"VNCR_EL2",         0b11, 0b100, 0b0010, 0b0010, 0b000>;
-
-} // HasV8_4aOps
+} //FeatureNV
 
 // SVE control registers
 //                                 Op0   Op1    CRn     CRm     Op2
 let Requires = [{ {AArch64::FeatureSVE} }] in {
 def : RWSysReg<"ZCR_EL1",          0b11, 0b000, 0b0001, 0b0010, 0b000>;
 def : RWSysReg<"ZCR_EL2",          0b11, 0b100, 0b0001, 0b0010, 0b000>;
 def : RWSysReg<"ZCR_EL3",          0b11, 0b110, 0b0001, 0b0010, 0b000>;
 def : RWSysReg<"ZCR_EL12",         0b11, 0b101, 0b0001, 0b0010, 0b000>;

lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

Operands.push_back(AArch64Operand::CreateShiftExtend(
       ShOp, MCE->getValue(), true, S, E, getContext()));
   return MatchOperand_Success;
 }
 
 static const struct Extension {
   const char *Name;
   const FeatureBitset Features;
 } ExtensionMap[] = {
-  { "crc",  {AArch64::FeatureCRC} },
-  { "sm4",  {AArch64::FeatureSM4} },
-  { "sha3", {AArch64::FeatureSHA3} },
-  { "sha2", {AArch64::FeatureSHA2} },
-  { "aes",  {AArch64::FeatureAES} },
-  { "crypto", {AArch64::FeatureCrypto} },
-  { "fp", {AArch64::FeatureFPARMv8} },
-  { "simd", {AArch64::FeatureNEON} },
-  { "ras", {AArch64::FeatureRAS} },
-  { "lse", {AArch64::FeatureLSE} },
-  { "predctrl", {AArch64::FeaturePredCtrl} },
-  { "ccdp", {AArch64::FeatureCacheDeepPersist} },
-  { "mte", {AArch64::FeatureMTE} },
-
+    {"crc", {AArch64::FeatureCRC}},
+    {"sm4", {AArch64::FeatureSM4}},
+    {"sha3", {AArch64::FeatureSHA3}},
+    {"sha2", {AArch64::FeatureSHA2}},
+    {"aes", {AArch64::FeatureAES}},
+    {"crypto", {AArch64::FeatureCrypto}},
+    {"fp", {AArch64::FeatureFPARMv8}},
+    {"simd", {AArch64::FeatureNEON}},
+    {"ras", {AArch64::FeatureRAS}},
+    {"lse", {AArch64::FeatureLSE}},
+    {"predctrl", {AArch64::FeaturePredCtrl}},
+    {"ccdp", {AArch64::FeatureCacheDeepPersist}},
+    {"mte", {AArch64::FeatureMTE}},
+    {"tlbi-rmi", {AArch64::FeatureTLB_RMI}},
+    {"pan-rwv", {AArch64::FeaturePAN_RWV}},
+    {"ccpp", {AArch64::FeatureCCPP}},
     // FIXME: Unsupported extensions
-  { "pan", {} },
-  { "lor", {} },
-  { "rdma", {} },
-  { "profile", {} },
+    {"pan", {}},
+    {"lor", {}},
+    {"rdma", {}},
+    {"profile", {}},
 };
 
-
 static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) {
   if (FBS[AArch64::HasV8_1aOps])
     Str += "ARMv8.1a";
   else if (FBS[AArch64::HasV8_2aOps])
     Str += "ARMv8.2a";
   else if (FBS[AArch64::HasV8_3aOps])
     Str += "ARMv8.3a";
   else if (FBS[AArch64::HasV8_4aOps])

test/MC/AArch64/armv8.2a-at.s

-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a < %s | FileCheck %s
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a < %s 2>&1 | FileCheck %s --check-prefix=ERROR
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a %s -o - | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a,+pan-rwv %s -o - | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a,-pan-rwv %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
 
   at s1e1rp, x1
   at s1e1wp, x2
 // CHECK: at      s1e1rp, x1              // encoding: [0x01,0x79,0x08,0xd5]
 // CHECK: at      s1e1wp, x2              // encoding: [0x22,0x79,0x08,0xd5]
-// ERROR: error: AT S1E1RP requires ARMv8.2a
-// ERROR: error: AT S1E1WP requires ARMv8.2a
+// ERROR: error: AT S1E1RP requires pan-rwv
+// ERROR: error: AT S1E1WP requires pan-rwv

test/MC/AArch64/armv8.2a-mmfr2.s

-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a < %s | FileCheck %s
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a < %s 2>&1 | FileCheck %s --check-prefix=ERROR
-
-  mrs x3, id_aa64mmfr2_el1
-// CHECK: mrs x3, ID_AA64MMFR2_EL1       // encoding: [0x43,0x07,0x38,0xd5]
-// ERROR: error: expected readable system register

test/MC/AArch64/armv8.2a-persistent-memory.s

-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a < %s | FileCheck %s
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a < %s 2>&1 | FileCheck %s --check-prefix=ERROR
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a -o - %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+ccpp -o - %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a -o - %s 2>&1 | FileCheck %s --check-prefix=ERROR
 
   dc cvap, x7
 // CHECK: dc cvap, x7   // encoding: [0x27,0x7c,0x0b,0xd5]
-// ERROR: error: DC CVAP requires ARMv8.2a
+// ERROR: error: DC CVAP requires ccpp

test/MC/AArch64/armv8.3a-complex.s

-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a,-fullfp16 < %s 2>%t | FileCheck %s --check-prefix=CHECK --check-prefix=NO-FP16
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a,-fullfp16 -o - %s 2>%t | \
+// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=NO-FP16
 // RUN: FileCheck --check-prefix=STDERR --check-prefix=STDERR-NO-FP16 %s < %t
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a,+fullfp16 < %s 2>%t | FileCheck %s --check-prefix=CHECK --check-prefix=FP16
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a,+fullfp16 -o - %s 2>%t | \
+// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=FP16
 // RUN: FileCheck --check-prefix=STDERR --check-prefix=STDERR-FP16 %s < %t
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a,-v8.3a,+fullfp16 < %s 2>&1 | FileCheck %s --check-prefix=NO-V83A
-
-
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a,-v8.3a,+fullfp16,+complxnum -o - %s 2>&1 | \
+// RUN: FileCheck %s --check-prefix=FP16
 // ==== FCMLA vector ====
 // Types
   fcmla v0.4h, v1.4h, v2.4h, #0
 // FP16: fcmla   v0.4h, v1.4h, v2.4h, #0 // encoding: [0x20,0xc4,0x42,0x2e]
 // STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16
-// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
+// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: complxnum
   fcmla v0.8h, v1.8h, v2.8h, #0
 // FP16: fcmla   v0.8h, v1.8h, v2.8h, #0 // encoding: [0x20,0xc4,0x42,0x6e]
 // STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16
-// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
+// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: complxnum
   fcmla v0.2s, v1.2s, v2.2s, #0
 // CHECK: fcmla   v0.2s, v1.2s, v2.2s, #0 // encoding: [0x20,0xc4,0x82,0x2e]
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum
   fcmla v0.4s, v1.4s, v2.4s, #0
 // CHECK: fcmla   v0.4s, v1.4s, v2.4s, #0 // encoding: [0x20,0xc4,0x82,0x6e]
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum
   fcmla v0.2d, v1.2d, v2.2d, #0
 // CHECK: fcmla   v0.2d, v1.2d, v2.2d, #0 // encoding: [0x20,0xc4,0xc2,0x6e]
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum
 
 // Rotations
   fcmla v0.2s, v1.2s, v2.2s, #0
 // CHECK: fcmla   v0.2s, v1.2s, v2.2s, #0 // encoding: [0x20,0xc4,0x82,0x2e]
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum
   fcmla v0.2s, v1.2s, v2.2s, #90
 // CHECK: fcmla   v0.2s, v1.2s, v2.2s, #90 // encoding: [0x20,0xcc,0x82,0x2e]
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum
   fcmla v0.2s, v1.2s, v2.2s, #180
 // CHECK: fcmla   v0.2s, v1.2s, v2.2s, #180 // encoding: [0x20,0xd4,0x82,0x2e]
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum
   fcmla v0.2s, v1.2s, v2.2s, #270
 // CHECK: fcmla   v0.2s, v1.2s, v2.2s, #270 // encoding: [0x20,0xdc,0x82,0x2e]
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum
 
 // Invalid rotations
   fcmla v0.2s, v1.2s, v2.2s, #1
 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270.
   fcmla v0.2s, v1.2s, v2.2s, #360
 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270.
   fcmla v0.2s, v1.2s, v2.2s, #-90
 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270.
 
 // ==== FCADD vector ====
 // Types
   fcadd v0.4h, v1.4h, v2.4h, #90
 // FP16: fcadd   v0.4h, v1.4h, v2.4h, #90 // encoding: [0x20,0xe4,0x42,0x2e]
 // STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16
-// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
+// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: complxnum
   fcadd v0.8h, v1.8h, v2.8h, #90
 // FP16: fcadd   v0.8h, v1.8h, v2.8h, #90 // encoding: [0x20,0xe4,0x42,0x6e]
 // STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16
-// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
+// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: complxnum
   fcadd v0.2s, v1.2s, v2.2s, #90
 // CHECK: fcadd   v0.2s, v1.2s, v2.2s, #90 // encoding: [0x20,0xe4,0x82,0x2e]
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum
   fcadd v0.4s, v1.4s, v2.4s, #90
 // CHECK: fcadd   v0.4s, v1.4s, v2.4s, #90 // encoding: [0x20,0xe4,0x82,0x6e]
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum
   fcadd v0.2d, v1.2d, v2.2d, #90
 // CHECK: fcadd   v0.2d, v1.2d, v2.2d, #90 // encoding: [0x20,0xe4,0xc2,0x6e]
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum
 
 // Rotations
   fcadd v0.2s, v1.2s, v2.2s, #90
 // CHECK: fcadd   v0.2s, v1.2s, v2.2s, #90 // encoding: [0x20,0xe4,0x82,0x2e]
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum
   fcadd v0.2s, v1.2s, v2.2s, #270
 // CHECK: fcadd   v0.2s, v1.2s, v2.2s, #270 // encoding: [0x20,0xf4,0x82,0x2e]
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum
 
 // Invalid rotations
   fcadd v0.2s, v1.2s, v2.2s, #1
 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270.
   fcadd v0.2s, v1.2s, v2.2s, #360
 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270.
   fcadd v0.2s, v1.2s, v2.2s, #-90
 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270.
   fcadd v0.2s, v1.2s, v2.2s, #0
 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270.
   fcadd v0.2s, v1.2s, v2.2s, #180
 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270.
 
 // ==== FCMLA indexed ====
 // Types
   fcmla v0.4h, v1.4h, v2.h[0], #0
 // FP16: fcmla   v0.4h, v1.4h, v2.h[0], #0 // encoding: [0x20,0x10,0x42,0x2f]
 // STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16
-// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
+// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: complxnum
   fcmla v0.8h, v1.8h, v2.h[0], #0
 // FP16: fcmla   v0.8h, v1.8h, v2.h[0], #0 // encoding: [0x20,0x10,0x42,0x6f]
 // STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16
-// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
+// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: complxnum
   fcmla v0.2s, v1.2s, v2.s[0], #0
 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: invalid operand for instruction
 // NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: invalid operand for instruction
   fcmla v0.4s, v1.4s, v2.s[0], #0
 // CHECK: fcmla   v0.4s, v1.4s, v2.s[0], #0 // encoding: [0x20,0x10,0x82,0x6f]
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum
   fcmla v0.2d, v1.2d, v2.d[0], #0
 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: invalid operand for instruction
 // NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: invalid operand for instruction
 
 // Rotations
   fcmla v0.4s, v1.4s, v2.s[0], #90
 // CHECK: fcmla   v0.4s, v1.4s, v2.s[0], #90 // encoding: [0x20,0x30,0x82,0x6f]
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum
   fcmla v0.4s, v1.4s, v2.s[0], #180
 // CHECK: fcmla   v0.4s, v1.4s, v2.s[0], #180 // encoding: [0x20,0x50,0x82,0x6f]
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum
   fcmla v0.4s, v1.4s, v2.s[0], #270
 // CHECK: fcmla   v0.4s, v1.4s, v2.s[0], #270 // encoding: [0x20,0x70,0x82,0x6f]
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum
 
 // Valid indices
   fcmla v0.4h, v1.4h, v2.h[1], #0
 // FP16: fcmla   v0.4h, v1.4h, v2.h[1], #0 // encoding: [0x20,0x10,0x62,0x2f]
 // STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16
-// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
+// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: complxnum
   fcmla v0.8h, v1.8h, v2.h[3], #0
 // FP16: fcmla   v0.8h, v1.8h, v2.h[3], #0 // encoding: [0x20,0x18,0x62,0x6f]
 // STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16
-// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
+// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: complxnum
   fcmla v0.4s, v1.4s, v2.s[1], #0
 // CHECK: fcmla   v0.4s, v1.4s, v2.s[1], #0 // encoding: [0x20,0x18,0x82,0x6f]
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum
 
 // Invalid indices
   fcmla v0.4h, v1.4h, v2.h[2], #0
 // STDERR-NO-FP16: :[[@LINE-1]]:{{[0-9]*}}: error: invalid operand for instruction
 // STDERR-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: vector lane must be an integer in range [0, 1].
   fcmla v0.8h, v1.8h, v2.h[4], #0
 // STDERR-NO-FP16: :[[@LINE-1]]:{{[0-9]*}}: error: invalid operand for instruction
 // STDERR-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: vector lane must be an integer in range [0, 3].

test/MC/AArch64/armv8.3a-js.s

-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a < %s 2>&1 | FileCheck %s
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t
-// RUN: FileCheck --check-prefix=CHECK-REQ < %t %s
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a,-fp-armv8 < %s 2> %t
-// RUN: FileCheck --check-prefix=CHECK-NOFP < %t %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a -o - %s 2>&1 | \
+// RUN: FileCheck %s
+
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+jsconv -o - %s 2>&1 | \
+// RUN: FileCheck %s
+
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu %s 2>&1 | \
+// RUN: FileCheck --check-prefix=CHECK-JS %s
+
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+jsconv,-fp-armv8 -o - %s 2>&1 |\
+// RUN: FileCheck --check-prefix=CHECK-REQ %s
 
   fjcvtzs w0, d0
 // CHECK: fjcvtzs w0, d0    // encoding: [0x00,0x00,0x7e,0x1e]
-// CHECK-REQ: error: instruction requires: armv8.3a
-// CHECK-NOFP: error: instruction requires: fp-armv8
+
+// CHECK-JS: error: instruction requires: jsconv
+
+// NOJS: error: instruction requires: jsconv
+
+// CHECK-REQ: error: instruction requires: fp-armv8 jsconv

test/MC/AArch64/armv8.3a-signed-pointer.s

-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a < %s 2> %t | FileCheck %s
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t
-// RUN: FileCheck --check-prefix=CHECK-REQ %s < %t
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a -o - %s 2>&1 | \
+// RUN: FileCheck --check-prefixes=CHECK,ALL %s
 
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu %s -o - > %t.1 2>%t.2
+// RUN: FileCheck --check-prefixes=ALL,NOENC %s < %t.1
+// RUN: FileCheck --check-prefix=CHECK-REQ %s < %t.2
+
+// ALL: .text
   mrs x0, apiakeylo_el1
   mrs x0, apiakeyhi_el1
   mrs x0, apibkeylo_el1
   mrs x0, apibkeyhi_el1
   mrs x0, apdakeylo_el1
   mrs x0, apdakeyhi_el1
   mrs x0, apdbkeylo_el1
   mrs x0, apdbkeyhi_el1
   mrs x0, apgakeylo_el1
   mrs x0, apgakeyhi_el1
-
-// CHECK: mrs x0, APIAKeyLo_EL1     // encoding: [0x00,0x21,0x38,0xd5]
-// CHECK: mrs x0, APIAKeyHi_EL1     // encoding: [0x20,0x21,0x38,0xd5]
-// CHECK: mrs x0, APIBKeyLo_EL1     // encoding: [0x40,0x21,0x38,0xd5]
-// CHECK: mrs x0, APIBKeyHi_EL1     // encoding: [0x60,0x21,0x38,0xd5]
-// CHECK: mrs x0, APDAKeyLo_EL1     // encoding: [0x00,0x22,0x38,0xd5]
-// CHECK: mrs x0, APDAKeyHi_EL1     // encoding: [0x20,0x22,0x38,0xd5]
-// CHECK: mrs x0, APDBKeyLo_EL1     // encoding: [0x40,0x22,0x38,0xd5]
-// CHECK: mrs x0, APDBKeyHi_EL1     // encoding: [0x60,0x22,0x38,0xd5]
-// CHECK: mrs x0, APGAKeyLo_EL1     // encoding: [0x00,0x23,0x38,0xd5]
-// CHECK: mrs x0, APGAKeyHi_EL1     // encoding: [0x20,0x23,0x38,0xd5]
+// ALL-EMPTY:
+// ALL-EMPTY:
+// CHECK-NEXT: mrs x0, APIAKeyLo_EL1     // encoding: [0x00,0x21,0x38,0xd5]
+// CHECK-NEXT: mrs x0, APIAKeyHi_EL1     // encoding: [0x20,0x21,0x38,0xd5]
+// CHECK-NEXT: mrs x0, APIBKeyLo_EL1     // encoding: [0x40,0x21,0x38,0xd5]
+// CHECK-NEXT: mrs x0, APIBKeyHi_EL1     // encoding: [0x60,0x21,0x38,0xd5]
+// CHECK-NEXT: mrs x0, APDAKeyLo_EL1     // encoding: [0x00,0x22,0x38,0xd5]
+// CHECK-NEXT: mrs x0, APDAKeyHi_EL1     // encoding: [0x20,0x22,0x38,0xd5]
+// CHECK-NEXT: mrs x0, APDBKeyLo_EL1     // encoding: [0x40,0x22,0x38,0xd5]
+// CHECK-NEXT: mrs x0, APDBKeyHi_EL1     // encoding: [0x60,0x22,0x38,0xd5]
+// CHECK-NEXT: mrs x0, APGAKeyLo_EL1     // encoding: [0x00,0x23,0x38,0xd5]
+// CHECK-NEXT: mrs x0, APGAKeyHi_EL1     // encoding: [0x20,0x23,0x38,0xd5]
 
 // CHECK-REQ: error: expected readable system register
+// CHECK-REQ-NEXT: mrs x0, apiakeylo_el1
 // CHECK-REQ: error: expected readable system register
+// CHECK-REQ-NEXT: mrs x0, apiakeyhi_el1
 // CHECK-REQ: error: expected readable system register
+// CHECK-REQ-NEXT: mrs x0, apibkeylo_el1
 // CHECK-REQ: error: expected readable system register
+// CHECK-REQ-NEXT: mrs x0, apibkeyhi_el1
 // CHECK-REQ: error: expected readable system register
+// CHECK-REQ-NEXT: mrs x0, apdakeylo_el1
 // CHECK-REQ: error: expected readable system register
+// CHECK-REQ-NEXT: mrs x0, apdakeyhi_el1
 // CHECK-REQ: error: expected readable system register
+// CHECK-REQ-NEXT: mrs x0, apdbkeylo_el1
 // CHECK-REQ: error: expected readable system register
+// CHECK-REQ-NEXT: mrs x0, apdbkeyhi_el1
 // CHECK-REQ: error: expected readable system register
+// CHECK-REQ-NEXT: mrs x0, apgakeylo_el1
 // CHECK-REQ: error: expected readable system register
+// CHECK-REQ-NEXT: mrs x0, apgakeyhi_el1
 
   msr apiakeylo_el1, x0
   msr apiakeyhi_el1, x0
   msr apibkeylo_el1, x0
   msr apibkeyhi_el1, x0
   msr apdakeylo_el1, x0
   msr apdakeyhi_el1, x0
   msr apdbkeylo_el1, x0
   msr apdbkeyhi_el1, x0
   msr apgakeylo_el1, x0
   msr apgakeyhi_el1, x0
-
-// CHECK: msr APIAKeyLo_EL1, x0     // encoding: [0x00,0x21,0x18,0xd5]
-// CHECK: msr APIAKeyHi_EL1, x0     // encoding: [0x20,0x21,0x18,0xd5]
-// CHECK: msr APIBKeyLo_EL1, x0     // encoding: [0x40,0x21,0x18,0xd5]
-// CHECK: msr APIBKeyHi_EL1, x0     // encoding: [0x60,0x21,0x18,0xd5]
-// CHECK: msr APDAKeyLo_EL1, x0     // encoding: [0x00,0x22,0x18,0xd5]
-// CHECK: msr APDAKeyHi_EL1, x0     // encoding: [0x20,0x22,0x18,0xd5]
-// CHECK: msr APDBKeyLo_EL1, x0     // encoding: [0x40,0x22,0x18,0xd5]
-// CHECK: msr APDBKeyHi_EL1, x0     // encoding: [0x60,0x22,0x18,0xd5]
-// CHECK: msr APGAKeyLo_EL1, x0     // encoding: [0x00,0x23,0x18,0xd5]
-// CHECK: msr APGAKeyHi_EL1, x0     // encoding: [0x20,0x23,0x18,0xd5]
+// ALL-EMPTY:
+// ALL-EMPTY:
+// CHECK-NEXT: msr APIAKeyLo_EL1, x0     // encoding: [0x00,0x21,0x18,0xd5]
+// CHECK-NEXT: msr APIAKeyHi_EL1, x0     // encoding: [0x20,0x21,0x18,0xd5]
+// CHECK-NEXT: msr APIBKeyLo_EL1, x0     // encoding: [0x40,0x21,0x18,0xd5]
+// CHECK-NEXT: msr APIBKeyHi_EL1, x0     // encoding: [0x60,0x21,0x18,0xd5]
+// CHECK-NEXT: msr APDAKeyLo_EL1, x0     // encoding: [0x00,0x22,0x18,0xd5]
+// CHECK-NEXT: msr APDAKeyHi_EL1, x0     // encoding: [0x20,0x22,0x18,0xd5]
+// CHECK-NEXT: msr APDBKeyLo_EL1, x0     // encoding: [0x40,0x22,0x18,0xd5]
+// CHECK-NEXT: msr APDBKeyHi_EL1, x0     // encoding: [0x60,0x22,0x18,0xd5]
+// CHECK-NEXT: msr APGAKeyLo_EL1, x0     // encoding: [0x00,0x23,0x18,0xd5]
+// CHECK-NEXT: msr APGAKeyHi_EL1, x0     // encoding: [0x20,0x23,0x18,0xd5]
 
 // CHECK-REQ: error: expected writable system register or pstate
+// CHECK-REQ-NEXT:  msr apiakeylo_el1, x0
 // CHECK-REQ: error: expected writable system register or pstate
+// CHECK-REQ-NEXT:  msr apiakeyhi_el1, x0
 // CHECK-REQ: error: expected writable system register or pstate
+// CHECK-REQ-NEXT:  msr apibkeylo_el1, x0
 // CHECK-REQ: error: expected writable system register or pstate
+// CHECK-REQ-NEXT:  msr apibkeyhi_el1, x0
 // CHECK-REQ: error: expected writable system register or pstate
+// CHECK-REQ-NEXT:  msr apdakeylo_el1, x0
 // CHECK-REQ: error: expected writable system register or pstate
+// CHECK-REQ-NEXT:  msr apdakeyhi_el1, x0
 // CHECK-REQ: error: expected writable system register or pstate
+// CHECK-REQ-NEXT:  msr apdbkeylo_el1, x0
 // CHECK-REQ: error: expected writable system register or pstate
+// CHECK-REQ-NEXT:  msr apdbkeyhi_el1, x0
 // CHECK-REQ: error: expected writable system register or pstate
+// CHECK-REQ-NEXT:  msr apgakeylo_el1, x0
 // CHECK-REQ: error: expected writable system register or pstate
+// CHECK-REQ-NEXT:  msr apgakeyhi_el1, x0
 
+// ALL-EMPTY:
+// ALL-EMPTY:
   paciasp
-// CHECK: paciasp        // encoding: [0x3f,0x23,0x03,0xd5]
-// CHECK-REQ-NOT: error: instruction requires: armv8.3a
+// CHECK-NEXT: paciasp        // encoding: [0x3f,0x23,0x03,0xd5]
+// NOENC-NEXT: paciasp
   autiasp
-// CHECK: autiasp        // encoding: [0xbf,0x23,0x03,0xd5]
-// CHECK-REQ-NOT: error: instruction requires: armv8.3a
+// CHECK-NEXT: autiasp        // encoding: [0xbf,0x23,0x03,0xd5]
+// NOENC-NEXT: autiasp
   paciaz
-// CHECK: paciaz         // encoding: [0x1f,0x23,0x03,0xd5]
-// CHECK-REQ-NOT: error: instruction requires: armv8.3a
+// CHECK-NEXT: paciaz         // encoding: [0x1f,0x23,0x03,0xd5]
+// NOENC-NEXT: paciaz
   autiaz
-// CHECK: autiaz         // encoding: [0x9f,0x23,0x03,0xd5]
-// CHECK-REQ-NOT: error: instruction requires: armv8.3a
+// CHECK-NEXT: autiaz         // encoding: [0x9f,0x23,0x03,0xd5]
+// NOENC-NEXT: autiaz
   pacia1716
-// CHECK: pacia1716      // encoding: [0x1f,0x21,0x03,0xd5]
-// CHECK-REQ-NOT: error: instruction requires: armv8.3a
+// CHECK-NEXT: pacia1716      // encoding: [0x1f,0x21,0x03,0xd5]
+// NOENC-NEXT: pacia1716
   autia1716
-// CHECK: autia1716      // encoding: [0x9f,0x21,0x03,0xd5]
-// CHECK-REQ-NOT: error: instruction requires: armv8.3a
+// CHECK-NEXT: autia1716      // encoding: [0x9f,0x21,0x03,0xd5]
+// NOENC-NEXT: autia1716
   pacibsp
-// CHECK: pacibsp        // encoding: [0x7f,0x23,0x03,0xd5]
-// CHECK-REQ-NOT: error: instruction requires: armv8.3a
+// CHECK-NEXT: pacibsp        // encoding: [0x7f,0x23,0x03,0xd5]
+// NOENC-NEXT: pacibsp
   autibsp
-// CHECK: autibsp        // encoding: [0xff,0x23,0x03,0xd5]
-// CHECK-REQ-NOT: error: instruction requires: armv8.3a
+// CHECK-NEXT: autibsp        // encoding: [0xff,0x23,0x03,0xd5]
+// NOENC-NEXT: autibsp
   pacibz
-// CHECK: pacibz         // encoding: [0x5f,0x23,0x03,0xd5]
-// CHECK-REQ-NOT: error: instruction requires: armv8.3a
+// CHECK-NEXT: pacibz         // encoding: [0x5f,0x23,0x03,0xd5]
+// NOENC-NEXT: pacibz
   autibz
-// CHECK: autibz         // encoding: [0xdf,0x23,0x03,0xd5]
-// CHECK-REQ-NOT: error: instruction requires: armv8.3a
+// CHECK-NEXT: autibz         // encoding: [0xdf,0x23,0x03,0xd5]
+// NOENC-NEXT: autibz
   pacib1716
-// CHECK: pacib1716      // encoding: [0x5f,0x21,0x03,0xd5]
-// CHECK-REQ-NOT: error: instruction requires: armv8.3a
+// CHECK-NEXT: pacib1716      // encoding: [0x5f,0x21,0x03,0xd5]
+// NOENC-NEXT: pacib1716
   autib1716
-// CHECK: autib1716      // encoding: [0xdf,0x21,0x03,0xd5]
-// CHECK-REQ-NOT: error: instruction requires: armv8.3a
+// CHECK-NEXT: autib1716      // encoding: [0xdf,0x21,0x03,0xd5]
+// NOENC-NEXT: autib1716
   xpaclri
-// CHECK: xpaclri           // encoding: [0xff,0x20,0x03,0xd5]
-// CHECK-REQ-NOT: error: instruction requires: armv8.3a
+// CHECK-NEXT: xpaclri           // encoding: [0xff,0x20,0x03,0xd5]
+// NOENC-NEXT: xpaclri
 
+// ALL-EMPTY:
   pacia x0, x1
-// CHECK: pacia x0, x1     // encoding: [0x20,0x00,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: pacia x0, x1     // encoding: [0x20,0x00,0xc1,0xda]
+// CHECK-REQ-NEXT:      ^
+// CHECK-REQ-NEXT: error: instruction requires: pa
+// CHECK-REQ-NEXT: pacia x0, x1
   autia x0, x1
-// CHECK: autia x0, x1     // encoding: [0x20,0x10,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: autia x0, x1     // encoding: [0x20,0x10,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT: autia x0, x1
   pacda x0, x1
-// CHECK: pacda x0, x1     // encoding: [0x20,0x08,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: pacda x0, x1     // encoding: [0x20,0x08,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  pacda x0, x1
   autda x0, x1
-// CHECK: autda x0, x1     // encoding: [0x20,0x18,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: autda x0, x1     // encoding: [0x20,0x18,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  autda x0, x1
   pacib x0, x1
-// CHECK: pacib x0, x1     // encoding: [0x20,0x04,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: pacib x0, x1     // encoding: [0x20,0x04,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  pacib x0, x1
   autib x0, x1
-// CHECK: autib x0, x1     // encoding: [0x20,0x14,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: autib x0, x1     // encoding: [0x20,0x14,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  autib x0, x1
   pacdb x0, x1
-// CHECK: pacdb x0, x1     // encoding: [0x20,0x0c,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: pacdb x0, x1     // encoding: [0x20,0x0c,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  pacdb x0, x1
   autdb x0, x1
-// CHECK: autdb x0, x1     // encoding: [0x20,0x1c,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: autdb x0, x1     // encoding: [0x20,0x1c,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  autdb x0, x1
   pacga x0, x1, x2
-// CHECK: pacga x0, x1, x2  // encoding: [0x20,0x30,0xc2,0x9a]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: pacga x0, x1, x2  // encoding: [0x20,0x30,0xc2,0x9a]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  pacga x0, x1, x2
   paciza x0
-// CHECK: paciza x0         // encoding: [0xe0,0x23,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: paciza x0         // encoding: [0xe0,0x23,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  paciza x0
   autiza x0
-// CHECK: autiza x0         // encoding: [0xe0,0x33,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: autiza x0         // encoding: [0xe0,0x33,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  autiza x0
   pacdza x0
-// CHECK: pacdza x0         // encoding: [0xe0,0x2b,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: pacdza x0         // encoding: [0xe0,0x2b,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  pacdza x0
   autdza x0
-// CHECK: autdza x0         // encoding: [0xe0,0x3b,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: autdza x0         // encoding: [0xe0,0x3b,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  autdza x0
   pacizb x0
-// CHECK: pacizb x0         // encoding: [0xe0,0x27,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: pacizb x0         // encoding: [0xe0,0x27,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  pacizb x0
   autizb x0
-// CHECK: autizb x0         // encoding: [0xe0,0x37,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: autizb x0         // encoding: [0xe0,0x37,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  autizb x0
   pacdzb x0
-// CHECK: pacdzb x0         // encoding: [0xe0,0x2f,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: pacdzb x0         // encoding: [0xe0,0x2f,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  pacdzb x0
   autdzb x0
-// CHECK: autdzb x0         // encoding: [0xe0,0x3f,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: autdzb x0         // encoding: [0xe0,0x3f,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  autdzb x0
   xpaci x0
-// CHECK: xpaci x0          // encoding: [0xe0,0x43,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: xpaci x0          // encoding: [0xe0,0x43,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  xpaci x0
   xpacd x0
-// CHECK: xpacd x0          // encoding: [0xe0,0x47,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: xpacd x0          // encoding: [0xe0,0x47,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  xpacd x0
 
   braa x0, x1
-// CHECK: braa x0, x1       // encoding: [0x01,0x08,0x1f,0xd7]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-EMPTY:
+// CHECK-NEXT: braa x0, x1       // encoding: [0x01,0x08,0x1f,0xd7]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  braa x0, x1
   brab x0, x1
-// CHECK: brab x0, x1       // encoding: [0x01,0x0c,0x1f,0xd7]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: brab x0, x1       // encoding: [0x01,0x0c,0x1f,0xd7]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  brab x0, x1
   blraa x0, x1
-// CHECK: blraa x0, x1      // encoding: [0x01,0x08,0x3f,0xd7]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: blraa x0, x1      // encoding: [0x01,0x08,0x3f,0xd7]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  blraa x0, x1
   blrab x0, x1
-// CHECK: blrab x0, x1      // encoding: [0x01,0x0c,0x3f,0xd7]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: blrab x0, x1      // encoding: [0x01,0x0c,0x3f,0xd7]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  blrab x0, x1
 
   braaz x0
-// CHECK: braaz x0          // encoding: [0x1f,0x08,0x1f,0xd6]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-EMPTY:
+// CHECK-NEXT: braaz x0          // encoding: [0x1f,0x08,0x1f,0xd6]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  braaz x0
   brabz x0
-// CHECK: brabz x0          // encoding: [0x1f,0x0c,0x1f,0xd6]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: brabz x0          // encoding: [0x1f,0x0c,0x1f,0xd6]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  brabz x0
   blraaz x0
-// CHECK: blraaz x0         // encoding: [0x1f,0x08,0x3f,0xd6]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: blraaz x0         // encoding: [0x1f,0x08,0x3f,0xd6]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  blraaz x0
   blrabz x0
-// CHECK: blrabz x0         // encoding: [0x1f,0x0c,0x3f,0xd6]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: blrabz x0         // encoding: [0x1f,0x0c,0x3f,0xd6]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  blrabz x0
   retaa
-// CHECK: retaa             // encoding: [0xff,0x0b,0x5f,0xd6]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: retaa             // encoding: [0xff,0x0b,0x5f,0xd6]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  retaa
   retab
-// CHECK: retab             // encoding: [0xff,0x0f,0x5f,0xd6]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: retab             // encoding: [0xff,0x0f,0x5f,0xd6]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  retab
   eretaa
-// CHECK: eretaa            // encoding: [0xff,0x0b,0x9f,0xd6]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: eretaa            // encoding: [0xff,0x0b,0x9f,0xd6]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  eretaa
   eretab
-// CHECK: eretab            // encoding: [0xff,0x0f,0x9f,0xd6]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: eretab            // encoding: [0xff,0x0f,0x9f,0xd6]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  eretab
   ldraa x0, [x1, 4088]
-// CHECK: ldraa x0, [x1, #4088]  // encoding: [0x20,0xf4,0x3f,0xf8]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: ldraa x0, [x1, #4088]  // encoding: [0x20,0xf4,0x3f,0xf8]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  ldraa x0, [x1, 4088]
   ldraa x0, [x1, -4096]
-// CHECK: ldraa x0, [x1, #-4096] // encoding: [0x20,0x04,0x60,0xf8]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: ldraa x0, [x1, #-4096] // encoding: [0x20,0x04,0x60,0xf8]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  ldraa x0, [x1, -4096]
   ldrab x0, [x1, 4088]
-// CHECK: ldrab x0, [x1, #4088]  // encoding: [0x20,0xf4,0xbf,0xf8]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: ldrab x0, [x1, #4088]  // encoding: [0x20,0xf4,0xbf,0xf8]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  ldrab x0, [x1, 4088]
   ldrab x0, [x1, -4096]
-// CHECK: ldrab x0, [x1, #-4096] // encoding: [0x20,0x04,0xe0,0xf8]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: ldrab x0, [x1, #-4096] // encoding: [0x20,0x04,0xe0,0xf8]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  ldrab x0, [x1, -4096]
   ldraa x0, [x1, 4088]!
-// CHECK: ldraa x0, [x1, #4088]!  // encoding: [0x20,0xfc,0x3f,0xf8]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: ldraa x0, [x1, #4088]!  // encoding: [0x20,0xfc,0x3f,0xf8]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  ldraa x0, [x1, 4088]!
   ldraa x0, [x1, -4096]!
-// CHECK: ldraa x0, [x1, #-4096]! // encoding: [0x20,0x0c,0x60,0xf8]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: ldraa x0, [x1, #-4096]! // encoding: [0x20,0x0c,0x60,0xf8]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  ldraa x0, [x1, -4096]!
   ldrab x0, [x1, 4088]!
-// CHECK: ldrab x0, [x1, #4088]!  // encoding: [0x20,0xfc,0xbf,0xf8]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: ldrab x0, [x1, #4088]!  // encoding: [0x20,0xfc,0xbf,0xf8]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  ldrab x0, [x1, 4088]!
   ldrab x0, [x1, -4096]!
-// CHECK: ldrab x0, [x1, #-4096]! // encoding: [0x20,0x0c,0xe0,0xf8]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: ldrab x0, [x1, #-4096]! // encoding: [0x20,0x0c,0xe0,0xf8]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  ldrab x0, [x1, -4096]!
   ldraa x0, [x1]
-// CHECK: ldraa x0, [x1]  // encoding: [0x20,0x04,0x20,0xf8]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: ldraa x0, [x1]  // encoding: [0x20,0x04,0x20,0xf8]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  ldraa x0, [x1]
   ldrab x0, [x1]
-// CHECK: ldrab x0, [x1]  // encoding: [0x20,0x04,0xa0,0xf8]
-// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NEXT: ldrab x0, [x1]  // encoding: [0x20,0x04,0xa0,0xf8]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  ldrab x0, [x1]

test/MC/AArch64/armv8.4a-flag.s

-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a < %s | FileCheck %s --check-prefix=CHECK
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a %s -o - | \
+// RUN: FileCheck %s
+
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+fmi %s -o - 2>&1 | \
+// RUN: FileCheck %s
+
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a %s -o - 2>&1 | \
+// RUN: FileCheck %s --check-prefix=ERROR
+
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a,-fmi %s -o - 2>&1 | \
+// RUN: FileCheck %s --check-prefix=ERROR
 
 //------------------------------------------------------------------------------
 // Armv8.4-A flag manipulation instructions
 //------------------------------------------------------------------------------
 
   cfinv
   setf8 w1
   setf8 wzr
   setf16 w1
   setf16 wzr
   rmif x1, #63, #15
   rmif xzr, #63, #15
 
 //CHECK:      cfinv                        // encoding: [0x1f,0x40,0x00,0xd5]
 //CHECK-NEXT: setf8 w1                     // encoding: [0x2d,0x08,0x00,0x3a]
 //CHECK-NEXT: setf8 wzr                    // encoding: [0xed,0x0b,0x00,0x3a]
 //CHECK-NEXT: setf16 w1                    // encoding: [0x2d,0x48,0x00,0x3a]
 //CHECK-NEXT: setf16 wzr                   // encoding: [0xed,0x4b,0x00,0x3a]
 //CHECK-NEXT: rmif x1, #63, #15            // encoding: [0x2f,0x84,0x1f,0xba]
 //CHECK-NEXT: rmif xzr, #63, #15           // encoding: [0xef,0x87,0x1f,0xba]
 
-//CHECK-ERROR:      error: instruction requires: armv8.4a
-//CHECK-ERROR-NEXT: cfinv
-//CHECK-ERROR-NEXT: ^
-//CHECK-ERROR-NEXT: error: instruction requires: armv8.4a
-//CHECK-ERROR-NEXT: setf8 w1
-//CHECK-ERROR-NEXT: ^
-//CHECK-ERROR-NEXT: error: instruction requires: armv8.4a
-//CHECK-ERROR-NEXT: setf8 wzr
-//CHECK-ERROR-NEXT: ^
-//CHECK-ERROR-NEXT: error: instruction requires: armv8.4a
-//CHECK-ERROR-NEXT: setf16 w1
-//CHECK-ERROR-NEXT: ^
-//CHECK-ERROR-NEXT: error: instruction requires: armv8.4a
-//CHECK-ERROR-NEXT: setf16 wzr
-//CHECK-ERROR-NEXT: ^
-//CHECK-ERROR-NEXT: error: instruction requires: armv8.4a
-//CHECK-ERROR-NEXT: rmif x1, #63, #15
-//CHECK-ERROR-NEXT: ^
-//CHECK-ERROR-NEXT: error: instruction requires: armv8.4a
-//CHECK-ERROR-NEXT: rmif xzr, #63, #15
-//CHECK-ERROR-NEXT: ^
+//ERROR:      error: instruction requires: fmi
+//ERROR-NEXT: cfinv
+//ERROR-NEXT: ^
+//ERROR-NEXT: error: instruction requires: fmi
+//ERROR-NEXT: setf8 w1
+//ERROR-NEXT: ^
+//ERROR-NEXT: error: instruction requires: fmi
+//ERROR-NEXT: setf8 wzr
+//ERROR-NEXT: ^
+//ERROR-NEXT: error: instruction requires: fmi
+//ERROR-NEXT: setf16 w1
+//ERROR-NEXT: ^
+//ERROR-NEXT: error: instruction requires: fmi
+//ERROR-NEXT: setf16 wzr
+//ERROR-NEXT: ^
+//ERROR-NEXT: error: instruction requires: fmi
+//ERROR-NEXT: rmif x1, #63, #15
+//ERROR-NEXT: ^
+//ERROR-NEXT: error: instruction requires: fmi
+//ERROR-NEXT: rmif xzr, #63, #15
+//ERROR-NEXT: ^

test/MC/AArch64/armv8.4a-ldst.s

-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a < %s | FileCheck %s --check-prefix=CHECK
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a -o - %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a,+rcpc-immo -o - %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a,-rcpc-immo -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84
 
 //------------------------------------------------------------------------------
 // Armv8.4-A LDAPR and STLR instructions with immediate offsets
 //------------------------------------------------------------------------------
 
 STLURB   WZR, [X10]
 STLURB   W1, [X10]
 STLURB   W1, [X10, #-256]

 LDAPUR   X13, [X4, #255]
 ldapur   x14, [sp, #9]
 
 //CHECK:       ldapur    x12, [x3]             // encoding: [0x6c,0x00,0x40,0xd9]
 //CHECK-NEXT:  ldapur  x12, [x3, #-256]        // encoding: [0x6c,0x00,0x50,0xd9]
 //CHECK-NEXT:  ldapur  x13, [x4, #255]         // encoding: [0x8d,0xf0,0x4f,0xd9]
 //CHECK-NEXT:  ldapur  x14, [sp, #9]           // encoding: [0xee,0x93,0x40,0xd9]
 
-//CHECK-NO-V84:      error: instruction requires: armv8.4a
+//CHECK-NO-V84:      error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: STLURB   WZR, [X10]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: STLURB   W1, [X10]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: STLURB   W1, [X10, #-256]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: stlurb   w2, [x11, #255]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: STLURB   W3, [SP, #-3]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: ldapurb  wzr, [x12]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: ldapurb  w4, [x12]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: ldapurb  w4, [x12, #-256]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: LDAPURB  W5, [X13, #255]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: LDAPURB  W6, [SP, #-2]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: LDAPURSB W7, [X14]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: LDAPURSB W7, [X14, #-256]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: ldapursb w8, [x15, #255]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: ldapursb w9, [sp, #-1]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: LDAPURSB X0, [X16]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: LDAPURSB X0, [X16, #-256]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: LDAPURSB X1, [X17, #255]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: ldapursb x2, [sp, #0]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: ldapursb x2, [sp]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: stlurh   w10, [x18]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: stlurh   w10, [x18, #-256]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: STLURH   W11, [X19, #255]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: STLURH   W12, [SP, #1]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: LDAPURH  W13, [X20]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: LDAPURH  W13, [X20, #-256]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: ldapurh  w14, [x21, #255]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: LDAPURH  W15, [SP, #2]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: LDAPURSH W16, [X22]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: LDAPURSH W16, [X22, #-256]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: LDAPURSH W17, [X23, #255]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: ldapursh w18, [sp, #3]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: ldapursh x3, [x24]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: ldapursh x3, [x24, #-256]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: LDAPURSH X4, [X25, #255]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: LDAPURSH X5, [SP, #4]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: STLUR    W19, [X26]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: STLUR    W19, [X26, #-256]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: stlur    w20, [x27, #255]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: STLUR    W21, [SP, #5]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: LDAPUR   W22, [X28]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: LDAPUR   W22, [X28, #-256]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: LDAPUR   W23, [X29, #255]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: ldapur   w24, [sp, #6]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: ldapursw x6, [x30]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: ldapursw x6, [x30, #-256]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: LDAPURSW X7, [X0, #255]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: LDAPURSW X8, [SP, #7]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: STLUR    X9, [X1]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: STLUR    X9, [X1, #-256]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: stlur    x10, [x2, #255]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: STLUR    X11, [SP, #8]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: LDAPUR   X12, [X3]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: LDAPUR   X12, [X3, #-256]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: LDAPUR   X13, [X4, #255]
 //CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
 //CHECK-NO-V84-NEXT: ldapur   x14, [sp, #9]
 //CHECK-NO-V84-NEXT: ^

test/MC/AArch64/armv8.4a-tlb.s

 //CHECK-NEXT:  tlbi  alle3os                 // encoding: [0x1f,0x81,0x0e,0xd5]
 
 tlbi vae1os, sp
 
 //CHECK-ERROR:      error: invalid operand for instruction
 //CHECK-ERROR-NEXT: tlbi vae1os, sp
 //CHECK-ERROR-NEXT:              ^
 
-//CHECK-NO-V84:      error: TLBI VMALLE1OS requires ARMv8.4a
+//CHECK-NO-V84:      error: TLBI VMALLE1OS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi vmalle1os
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI VAE1OS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI VAE1OS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi vae1os, xzr
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI VAE1OS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI VAE1OS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi vae1os, x0
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI ASIDE1OS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI ASIDE1OS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi aside1os, x1
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI VAAE1OS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI VAAE1OS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi vaae1os, x2
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI VALE1OS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI VALE1OS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi vale1os, x3
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI VAALE1OS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI VAALE1OS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi vaale1os, x4
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI IPAS2E1OS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI IPAS2E1OS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi ipas2e1os, x5
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI IPAS2LE1OS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI IPAS2LE1OS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi ipas2le1os, x6
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI VAE2OS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI VAE2OS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi vae2os, x7
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI VALE2OS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI VALE2OS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi vale2os, x8
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI VMALLS12E1OS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI VMALLS12E1OS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi vmalls12e1os
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI VAE3OS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI VAE3OS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi vae3os, x9
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI VALE3OS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI VALE3OS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi vale3os, x10
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI ALLE2OS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI ALLE2OS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi alle2os
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI ALLE1OS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI ALLE1OS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi alle1os
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI ALLE3OS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI ALLE3OS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi alle3os
 //CHECK-NO-V84-NEXT:      ^
 
 // TLB Range maintenance instructions:
 tlbi rvae1, x3
 tlbi rvaae1, x3
 tlbi rvale1, x3
 tlbi rvaale1, x3

 //CHECK-NEXT:  tlbi  rvale3os, xzr           // encoding: [0xbf,0x85,0x0e,0xd5]
 
 tlbi rvae1, sp
 
 //CHECK-ERROR:      error: invalid operand for instruction
 //CHECK-ERROR-NEXT: tlbi rvae1, sp
 //CHECK-ERROR-NEXT:             ^
 
-//CHECK-NO-V84:      error: TLBI RVAE1 requires ARMv8.4a
+//CHECK-NO-V84:      error: TLBI RVAE1 requires tlbi
 //CHECK-NO-V84-NEXT: tlbi rvae1, x3
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI RVAAE1 requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI RVAAE1 requires tlbi
 //CHECK-NO-V84-NEXT: tlbi rvaae1, x3
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI RVALE1 requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI RVALE1 requires tlbi
 //CHECK-NO-V84-NEXT: tlbi rvale1, x3
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI RVAALE1 requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI RVAALE1 requires tlbi
 //CHECK-NO-V84-NEXT: tlbi rvaale1, x3
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT:  error: TLBI RVAE1IS requires ARMv8.4a
+//CHECK-NO-V84-NEXT:  error: TLBI RVAE1IS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi rvae1is, x3
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI RVAAE1IS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI RVAAE1IS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi rvaae1is, x3
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI RVALE1IS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI RVALE1IS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi rvale1is, x3
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI RVAALE1IS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI RVAALE1IS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi rvaale1is, x3
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI RVAE1OS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI RVAE1OS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi rvae1os, x3
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI RVAAE1OS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI RVAAE1OS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi rvaae1os, x3
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI RVALE1OS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI RVALE1OS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi rvale1os, x3
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI RVAALE1OS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI RVAALE1OS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi rvaale1os, x3
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI RIPAS2E1IS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI RIPAS2E1IS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi ripas2e1is, x3
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI RIPAS2LE1IS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI RIPAS2LE1IS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi ripas2le1is, x3
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI RIPAS2E1 requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI RIPAS2E1 requires tlbi
 //CHECK-NO-V84-NEXT: tlbi ripas2e1, X3
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI RIPAS2LE1 requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI RIPAS2LE1 requires tlbi
 //CHECK-NO-V84-NEXT: tlbi ripas2le1, X3
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI RIPAS2E1OS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI RIPAS2E1OS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi ripas2e1os, X3
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI RIPAS2LE1OS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI RIPAS2LE1OS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi ripas2le1os, X3
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI RVAE2 requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI RVAE2 requires tlbi
 //CHECK-NO-V84-NEXT: tlbi rvae2, X3
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI RVALE2 requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI RVALE2 requires tlbi
 //CHECK-NO-V84-NEXT: tlbi rvale2, X3
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI RVAE2IS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI RVAE2IS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi rvae2is, X3
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI RVALE2IS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI RVALE2IS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi rvale2is, X3
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI RVAE2OS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI RVAE2OS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi rvae2os, X3
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI RVALE2OS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI RVALE2OS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi rvale2os, X3
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI RVAE3 requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI RVAE3 requires tlbi
 //CHECK-NO-V84-NEXT: tlbi rvae3, X3
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI RVALE3 requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI RVALE3 requires tlbi
 //CHECK-NO-V84-NEXT: tlbi rvale3, X3
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI RVAE3IS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI RVAE3IS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi rvae3is, X3
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI RVALE3IS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI RVALE3IS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi rvale3is, X3
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI RVAE3OS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI RVAE3OS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi rvae3os, X3
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI RVALE3OS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI RVALE3OS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi rvale3os, X3
 //CHECK-NO-V84-NEXT:      ^
-//CHECK-NO-V84-NEXT: error: TLBI RVALE3OS requires ARMv8.4a
+//CHECK-NO-V84-NEXT: error: TLBI RVALE3OS requires tlbi
 //CHECK-NO-V84-NEXT: tlbi rvale3os, XZR
 //CHECK-NO-V84-NEXT:      ^

test/MC/AArch64/armv8.4a-trace.s

-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a < %s  | FileCheck %s --check-prefix=CHECK
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a -o - 2>&1 %s  | \
+// RUN: FileCheck %s
+
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+tracev8.4 -o - 2>&1 %s  | \
+// RUN: FileCheck %s
+
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a -o - %s 2>&1 | \
+// RUN: FileCheck %s --check-prefix=CHECK-ERROR
+
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a,-tracev8.4 -o - %s 2>&1 | \
+// RUN: FileCheck %s --check-prefixes NOFEATURE,CHECK-ERROR
 
 //------------------------------------------------------------------------------
 // ARMV8.4-A Debug, Trace and PMU Extensions
 //------------------------------------------------------------------------------
 
 msr TRFCR_EL1, x0
 msr TRFCR_EL2, x0
 msr TRFCR_EL12, x0

 //CHECK-ERROR:         ^
 //CHECK-ERROR: error: expected readable system register
 //CHECK-ERROR: mrs x0, TRFCR_EL2
 //CHECK-ERROR:         ^
 //CHECK-ERROR: error: expected readable system register
 //CHECK-ERROR: mrs x0, TRFCR_EL12
 //CHECK-ERROR:         ^
 
-//CHECK-ERROR: error: instruction requires: armv8.4a
+//CHECK-ERROR: error: instruction requires: trace