[llvm-exegesis][NFC] Add a way to declare the default counter binding for unbound CPUs for a target.

[courbet]

Summary

This simplifies the code and moves everything to tablegen for consistency. This
also prepares the ground for adding issue counters.

[gchatelet]

utils/TableGen/ExegesisEmitter.cpp

159

llvm::any_of ?

[courbet]

s/!all(empty)/any(!empty/)

include/llvm/Target/TargetPfmCounters.td

class ProcPfmCounters {
   list<PfmIssueCounter> IssueCounters = [];
 }
 
 // A binding of a set of counters to a CPU.
 class PfmCountersBinding<string cpu_name, ProcPfmCounters counters> {
   string CpuName = cpu_name;
   ProcPfmCounters Counters = counters;
 }
+
+// Declares the default binding for unbound CPUs for the target.
+class PfmCountersDefaultBinding<ProcPfmCounters counters>
+    : PfmCountersBinding<"", counters> {}

lib/Target/AArch64/AArch64.td

 //===----------------------------------------------------------------------===//
 
 def AArch64 : Target {
   let InstructionSet = AArch64InstrInfo;
   let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
   let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
   let AllowRegisterRenaming = 1;
 }
+
+//===----------------------------------------------------------------------===//
+// Pfm Counters
+//===----------------------------------------------------------------------===//
+
+include "AArch64PfmCounters.td"

lib/Target/AArch64/AArch64PfmCounters.td

+//===-- AArch64PfmCounters.td - AArch64 Hardware Counters --*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This describes the available hardware counters for AArch64.
+//
+//===----------------------------------------------------------------------===//
+
+def CpuCyclesPfmCounter : PfmCounter<"CPU_CYCLES">;
+
+def DefaultPfmCounters : ProcPfmCounters {
+  let CycleCounter = CpuCyclesPfmCounter;
+}
+def : PfmCountersDefaultBinding<DefaultPfmCounters>;

lib/Target/AArch64/CMakeLists.txt

 tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel)
 tablegen(LLVM AArch64GenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM AArch64GenMCCodeEmitter.inc -gen-emitter)
 tablegen(LLVM AArch64GenMCPseudoLowering.inc -gen-pseudo-lowering)
 tablegen(LLVM AArch64GenRegisterBank.inc -gen-register-bank)
 tablegen(LLVM AArch64GenRegisterInfo.inc -gen-register-info)
 tablegen(LLVM AArch64GenSubtargetInfo.inc -gen-subtarget)
 tablegen(LLVM AArch64GenSystemOperands.inc -gen-searchable-tables)
+tablegen(LLVM AArch64GenExegesis.inc -gen-exegesis)
 
 add_public_tablegen_target(AArch64CommonTableGen)
 
 add_llvm_target(AArch64CodeGen
   AArch64A57FPLoadBalancing.cpp
   AArch64AdvSIMDScalarPass.cpp
   AArch64AsmPrinter.cpp
   AArch64BranchTargets.cpp

lib/Target/PowerPC/CMakeLists.txt

 set(LLVM_TARGET_DEFINITIONS PPC.td)
 
 tablegen(LLVM PPCGenAsmMatcher.inc -gen-asm-matcher)
 tablegen(LLVM PPCGenAsmWriter.inc -gen-asm-writer)
 tablegen(LLVM PPCGenCallingConv.inc -gen-callingconv)
 tablegen(LLVM PPCGenDAGISel.inc -gen-dag-isel)
 tablegen(LLVM PPCGenDisassemblerTables.inc -gen-disassembler)
 tablegen(LLVM PPCGenFastISel.inc -gen-fast-isel)
 tablegen(LLVM PPCGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM PPCGenMCCodeEmitter.inc -gen-emitter)
 tablegen(LLVM PPCGenRegisterInfo.inc -gen-register-info)
 tablegen(LLVM PPCGenSubtargetInfo.inc -gen-subtarget)
+tablegen(LLVM PPCGenExegesis.inc -gen-exegesis)
 
 add_public_tablegen_target(PowerPCCommonTableGen)
 
 add_llvm_target(PowerPCCodeGen
   PPCBoolRetToInt.cpp
   PPCAsmPrinter.cpp
   PPCBranchSelector.cpp
   PPCBranchCoalescing.cpp

lib/Target/PowerPC/PPC.td

 //===----------------------------------------------------------------------===//
 // PowerPC processors supported.
 //
 
 def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat,
                                            FeatureMFTB]>;
 def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
                                           FeatureFRES, FeatureFRSQRTE,
-                                          FeatureICBT, FeatureBookE, 
+                                          FeatureICBT, FeatureBookE,
                                           FeatureMSYNC, FeatureMFTB]>;
 def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
                                           FeatureFRES, FeatureFRSQRTE,
-                                          FeatureICBT, FeatureBookE, 
+                                          FeatureICBT, FeatureBookE,
                                           FeatureMSYNC, FeatureMFTB]>;
 def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>;
 def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU,
                                        FeatureMFTB]>;
 def : Processor<"603", G3Itineraries, [Directive603,
                                        FeatureFRES, FeatureFRSQRTE,
                                        FeatureMFTB]>;
 def : Processor<"603e", G3Itineraries, [Directive603,
def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
                                         FeatureMFTB]>;
 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
                                       FeatureFRES, FeatureFRSQRTE,
                                       FeatureMFTB]>;
 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
                                             FeatureFRES, FeatureFRSQRTE,
                                             FeatureMFTB]>;
 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
-                                           FeatureFRES, FeatureFRSQRTE, 
+                                           FeatureFRES, FeatureFRSQRTE,
                                            FeatureMFTB]>;
 
 def : ProcessorModel<"970", G5Model,
                   [Directive970, FeatureAltivec,
                    FeatureMFOCRF, FeatureFSqrt,
                    FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
                    Feature64Bit /*, Feature64BitRegs */,
                    FeatureMFTB]>;
 def : ProcessorModel<"g5", G5Model,
                   [Directive970, FeatureAltivec,
                    FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
                    FeatureFRES, FeatureFRSQRTE,
                    Feature64Bit /*, Feature64BitRegs */,
                    FeatureMFTB, DeprecatedDST]>;
 def : ProcessorModel<"e500", PPCE500Model,
                   [DirectiveE500,
                    FeatureICBT, FeatureBookE,
                    FeatureISEL, FeatureMFTB]>;
 def : ProcessorModel<"e500mc", PPCE500mcModel,
                   [DirectiveE500mc,
-                   FeatureSTFIWX, FeatureICBT, FeatureBookE, 
+                   FeatureSTFIWX, FeatureICBT, FeatureBookE,
                    FeatureISEL, FeatureMFTB]>;
 def : ProcessorModel<"e5500", PPCE5500Model,
                   [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
-                   FeatureSTFIWX, FeatureICBT, FeatureBookE, 
+                   FeatureSTFIWX, FeatureICBT, FeatureBookE,
                    FeatureISEL, FeatureMFTB]>;
 def : ProcessorModel<"a2", PPCA2Model,
                   [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
                    FeatureSTFIWX, FeatureLFIWAX,
                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
                    FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX,
def : ProcessorModel<"pwr6x", G5Model,
                   [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
                    FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
                    FeatureFPRND, Feature64Bit,
                    FeatureMFTB, DeprecatedDST]>;
 def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.Power7FeatureList>;
 def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.Power8FeatureList>;
-def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.Power9FeatureList>; 
+def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.Power9FeatureList>;
 def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat,
                                        FeatureMFTB]>;
 def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat,
                                          FeatureMFTB]>;
 def : ProcessorModel<"ppc64", G5Model,
                   [Directive64, FeatureAltivec,
                    FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
                    FeatureFRSQRTE, FeatureSTFIWX,

 def PPC : Target {
   // Information about the instructions.
   let InstructionSet = PPCInstrInfo;
 
   let AssemblyParsers = [PPCAsmParser];
   let AssemblyParserVariants = [PPCAsmParserVariant];
   let AllowRegisterRenaming = 1;
 }
+
+//===----------------------------------------------------------------------===//
+// Pfm Counters
+//===----------------------------------------------------------------------===//
+
+include "PPCPfmCounters.td"

lib/Target/PowerPC/PPCPfmCounters.td

+//===-- PPCPfmCounters.td - PPC Hardware Counters ----------*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This describes the available hardware counters for PPC.
+//
+//===----------------------------------------------------------------------===//
+
+def CpuCyclesPfmCounter : PfmCounter<"CYCLES">;
+
+def DefaultPfmCounters : ProcPfmCounters {
+  let CycleCounter = CpuCyclesPfmCounter;
+}
+def : PfmCountersDefaultBinding<DefaultPfmCounters>;

lib/Target/X86/X86PfmCounters.td

 //===-- X86PfmCounters.td - X86 Hardware Counters ----------*- tablegen -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This describes the available hardware counters for various subtargets.
 //
 //===----------------------------------------------------------------------===//
 
 def UnhaltedCoreCyclesPfmCounter : PfmCounter<"unhalted_core_cycles">;
 def UopsIssuedPfmCounter : PfmCounter<"uops_issued:any">;
 
+// No default counters on X86.
+def DefaultPfmCounters : ProcPfmCounters {}
+def : PfmCountersDefaultBinding<DefaultPfmCounters>;
+
 def SandyBridgePfmCounters : ProcPfmCounters {
   let CycleCounter = UnhaltedCoreCyclesPfmCounter;
   let UopsCounter = UopsIssuedPfmCounter;
   let IssueCounters = [
     PfmIssueCounter<"SBPort0",  "uops_dispatched_port:port_0">,
     PfmIssueCounter<"SBPort1",  "uops_dispatched_port:port_1">,
     PfmIssueCounter<"SBPort23", "uops_dispatched_port:port_2 + uops_dispatched_port:port_3">,
     PfmIssueCounter<"SBPort4",  "uops_dispatched_port:port_4">,

tools/llvm-exegesis/lib/AArch64/Target.cpp

 //===-- Target.cpp ----------------------------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 #include "../Target.h"
 #include "../Latency.h"
 #include "AArch64.h"
 #include "AArch64RegisterInfo.h"
 
 namespace llvm {
 namespace exegesis {
 
-namespace {
-
-class AArch64LatencyBenchmarkRunner : public LatencyBenchmarkRunner {
-public:
-  AArch64LatencyBenchmarkRunner(const LLVMState &State)
-      : LatencyBenchmarkRunner(State) {}
-
-private:
-  const char *getCounterName() const override {
-    // All AArch64 subtargets have CPU_CYCLES as the cycle counter name
-    return "CPU_CYCLES";
-  }
-};
-
-namespace {
-
 static unsigned getLoadImmediateOpcode(unsigned RegBitWidth) {
   switch (RegBitWidth) {
   case 32:
     return llvm::AArch64::MOVi32imm;
   case 64:
     return llvm::AArch64::MOVi64imm;
   }
   llvm_unreachable("Invalid Value Width");
 }
 
 // Generates instruction to load an immediate value into a register.
 static llvm::MCInst loadImmediate(unsigned Reg, unsigned RegBitWidth,
                                   const llvm::APInt &Value) {
   if (Value.getBitWidth() > RegBitWidth)
     llvm_unreachable("Value must fit in the Register");
   return llvm::MCInstBuilder(getLoadImmediateOpcode(RegBitWidth))
       .addReg(Reg)
       .addImm(Value.getZExtValue());
 }
 
-} // namespace
+#include "AArch64GenExegesis.inc"
+
+namespace {
 
 class ExegesisAArch64Target : public ExegesisTarget {
 public:
-  ExegesisAArch64Target() : ExegesisTarget({}) {}
+  ExegesisAArch64Target() : ExegesisTarget(AArch64CpuPfmCounters) {}
 
 private:
   std::vector<llvm::MCInst> setRegTo(const llvm::MCSubtargetInfo &STI,
                                      unsigned Reg,
                                      const llvm::APInt &Value) const override {
     if (llvm::AArch64::GPR32RegClass.contains(Reg))
       return {loadImmediate(Reg, 32, Value)};
     if (llvm::AArch64::GPR64RegClass.contains(Reg))
       return {loadImmediate(Reg, 64, Value)};
     llvm::errs() << "setRegTo is not implemented, results will be unreliable\n";
     return {};
   }
 
   bool matchesArch(llvm::Triple::ArchType Arch) const override {
     return Arch == llvm::Triple::aarch64 || Arch == llvm::Triple::aarch64_be;
   }
 
   void addTargetSpecificPasses(llvm::PassManagerBase &PM) const override {
     // Function return is a pseudo-instruction that needs to be expanded
     PM.add(llvm::createAArch64ExpandPseudoPass());
   }
-
-  std::unique_ptr<BenchmarkRunner>
-  createLatencyBenchmarkRunner(const LLVMState &State) const override {
-    return llvm::make_unique<AArch64LatencyBenchmarkRunner>(State);
-  }
 };
 
 } // namespace
 
 static ExegesisTarget *getTheExegesisAArch64Target() {
   static ExegesisAArch64Target Target;
   return &Target;
 }
 
 void InitializeAArch64ExegesisTarget() {
   ExegesisTarget::registerTarget(getTheExegesisAArch64Target());
 }
 
 } // namespace exegesis
 } // namespace llvm

tools/llvm-exegesis/lib/Latency.h

 public:
   LatencyBenchmarkRunner(const LLVMState &State)
       : BenchmarkRunner(State, InstructionBenchmark::Latency) {}
   ~LatencyBenchmarkRunner() override;
 
 private:
   llvm::Expected<std::vector<BenchmarkMeasure>>
   runMeasurements(const FunctionExecutor &Executor) const override;
-
-  virtual const char *getCounterName() const;
 };
 } // namespace exegesis
 } // namespace llvm
 
 #endif // LLVM_TOOLS_LLVM_EXEGESIS_LATENCY_H

tools/llvm-exegesis/lib/Latency.cpp

if (!Results.empty())
       break;
   }
   if (Results.empty())
     return llvm::make_error<BenchmarkFailure>(
         "No strategy found to make the execution serial");
   return std::move(Results);
 }
 
-const char *LatencyBenchmarkRunner::getCounterName() const {
-  const char *CounterName = State.getPfmCounters().CycleCounter;
-  if (!CounterName)
-    llvm::report_fatal_error("sched model does not define a cycle counter");
-  return CounterName;
-}
-
 LatencyBenchmarkRunner::~LatencyBenchmarkRunner() = default;
 
 llvm::Expected<std::vector<BenchmarkMeasure>>
 LatencyBenchmarkRunner::runMeasurements(
     const FunctionExecutor &Executor) const {
   // Cycle measurements include some overhead from the kernel. Repeat the
   // measure several times and take the minimum value.
   constexpr const int NumMeasurements = 30;
   int64_t MinValue = std::numeric_limits<int64_t>::max();
-  const char *CounterName = getCounterName();
+  const char *CounterName = State.getPfmCounters().CycleCounter;
   if (!CounterName)
-    llvm::report_fatal_error("could not determine cycle counter name");
+    llvm::report_fatal_error("sched model does not define a cycle counter");
   for (size_t I = 0; I < NumMeasurements; ++I) {
     auto ExpectedCounterValue = Executor.runAndMeasure(CounterName);
     if (!ExpectedCounterValue)
       return ExpectedCounterValue.takeError();
     if (*ExpectedCounterValue < MinValue)
       MinValue = *ExpectedCounterValue;
   }
   std::vector<BenchmarkMeasure> Result = {
       BenchmarkMeasure::Create("latency", MinValue)};
   return std::move(Result);
 }
 
 } // namespace exegesis
 } // namespace llvm

tools/llvm-exegesis/lib/PowerPC/Target.cpp

 #include "../Target.h"
 #include "../Latency.h"
 #include "PPC.h"
 #include "PPCRegisterInfo.h"
 
 namespace llvm {
 namespace exegesis {
 
-namespace {
-class PowerPCLatencyBenchmarkRunner : public LatencyBenchmarkRunner {
-public:
-  PowerPCLatencyBenchmarkRunner(const LLVMState &State)
-      : LatencyBenchmarkRunner(State) {}
-
-private:
-  const char *getCounterName() const override {
-    // All PowerPC subtargets have CYCLES as the cycle counter name
-    return "CYCLES";
-  }
-};
-} // end anonymous namespace
+#include "PPCGenExegesis.inc"
 
 namespace {
 class ExegesisPowerPCTarget : public ExegesisTarget {
 public:
-  ExegesisPowerPCTarget() : ExegesisTarget({}) {}
+  ExegesisPowerPCTarget() : ExegesisTarget(PPCCpuPfmCounters) {}
 
 private:
   std::vector<llvm::MCInst> setRegTo(const llvm::MCSubtargetInfo &STI,
                                      unsigned Reg,
                                      const llvm::APInt &Value) const override;
   bool matchesArch(llvm::Triple::ArchType Arch) const override {
     return Arch == llvm::Triple::ppc64le;
   }
-  std::unique_ptr<BenchmarkRunner>
-  createLatencyBenchmarkRunner(const LLVMState &State) const override {
-    return llvm::make_unique<PowerPCLatencyBenchmarkRunner>(State);
-  }
 };
 } // end anonymous namespace
 
 static unsigned getLoadImmediateOpcode(unsigned RegBitWidth) {
   switch (RegBitWidth) {
   case 32:
     return llvm::PPC::LI;
   case 64:

tools/llvm-exegesis/lib/Target.cpp

 
 std::unique_ptr<BenchmarkRunner>
 ExegesisTarget::createUopsBenchmarkRunner(const LLVMState &State) const {
   return llvm::make_unique<UopsBenchmarkRunner>(State);
 }
 
 static_assert(std::is_pod<PfmCountersInfo>::value,
               "We shouldn't have dynamic initialization here");
-const PfmCountersInfo PfmCountersInfo::Default = {nullptr, nullptr, nullptr, 0u};
+const PfmCountersInfo PfmCountersInfo::Default = {nullptr, nullptr, nullptr,
+                                                  0u};
 
 const PfmCountersInfo &
 ExegesisTarget::getPfmCounters(llvm::StringRef CpuName) const {
   assert(std::is_sorted(
              CpuPfmCounters.begin(), CpuPfmCounters.end(),
              [](const CpuAndPfmCounters &LHS, const CpuAndPfmCounters &RHS) {
                return strcmp(LHS.CpuName, RHS.CpuName) < 0;
              }) &&
          "CpuPfmCounters table is not sorted");
 
   // Find entry
   auto Found =
       std::lower_bound(CpuPfmCounters.begin(), CpuPfmCounters.end(), CpuName);
   if (Found == CpuPfmCounters.end() ||
       llvm::StringRef(Found->CpuName) != CpuName) {
-    return PfmCountersInfo::Default;
+    // Use the default.
+    if (CpuPfmCounters.begin() != CpuPfmCounters.end() &&
+        CpuPfmCounters.begin()->CpuName[0] == '\0') {
+      Found = CpuPfmCounters.begin(); // The target specifies a default.
+    } else {
+      return PfmCountersInfo::Default; // No default for the target.
+    }
   }
   assert(Found->PCI && "Missing counters");
   return *Found->PCI;
 }
 
 namespace {
 
 // Default implementation.

unittests/tools/llvm-exegesis/AArch64/TargetTest.cpp

 };
 
 TEST_F(AArch64TargetTest, SetRegToConstant) {
   // The AArch64 target currently doesn't know how to set register values.
   const auto Insts = setRegTo(llvm::AArch64::X0, llvm::APInt());
   EXPECT_THAT(Insts, Not(IsEmpty()));
 }
 
+TEST_F(AArch64TargetTest, DefaultPfmCounters) {
+  EXPECT_EQ(ExegesisTarget_->getPfmCounters("").CycleCounter, "CPU_CYCLES");
+  EXPECT_EQ(ExegesisTarget_->getPfmCounters("unknown_cpu").CycleCounter,
+            "CPU_CYCLES");
+}
+
 } // namespace
 } // namespace exegesis
 } // namespace llvm

unittests/tools/llvm-exegesis/PowerPC/TargetTest.cpp

 TEST_F(PowerPCTargetTest, SetRegToConstant) {
   const std::unique_ptr<llvm::MCSubtargetInfo> STI(
       Target_->createMCSubtargetInfo(kTriple, "generic", ""));
   const auto Insts =
       ExegesisTarget_->setRegTo(*STI, llvm::PPC::X0, llvm::APInt());
   EXPECT_THAT(Insts, Not(IsEmpty()));
 }
 
+TEST_F(PowerPCTargetTest, DefaultPfmCounters) {
+  EXPECT_EQ(ExegesisTarget_->getPfmCounters("").CycleCounter, "CYCLES");
+  EXPECT_EQ(ExegesisTarget_->getPfmCounters("unknown_cpu").CycleCounter,
+            "CYCLES");
+}
+
 } // namespace
 } // namespace exegesis
 } // namespace llvm

utils/TableGen/ExegesisEmitter.cpp

 //===- ExegesisEmitter.cpp - Generate exegesis target data ----------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This tablegen backend emits llvm-exegesis information.
 //
 //===----------------------------------------------------------------------===//
 
+#include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SmallSet.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/Format.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/TableGen/Error.h"
 #include "llvm/TableGen/Record.h"
 #include "llvm/TableGen/TableGenBackend.h"
void ExegesisEmitter::emitPfmCountersInfo(const Record &Def,
                                           raw_ostream &OS) const {
   const auto CycleCounter =
       Def.getValueAsDef("CycleCounter")->getValueAsString("Counter");
   const auto UopsCounter =
       Def.getValueAsDef("UopsCounter")->getValueAsString("Counter");
   const size_t NumIssueCounters =
       Def.getValueAsListOfDefs("IssueCounters").size();
 
-  // This is the default, do not emit.
-  if (CycleCounter.empty() && UopsCounter.empty() && NumIssueCounters == 0)
-    return;
-
   OS << "\nstatic const PfmCountersInfo " << Target << Def.getName()
      << " = {\n";
 
   // Cycle Counter.
   if (CycleCounter.empty())
     OS << "  nullptr,  // No cycle counter.\n";
   else
     OS << "  " << Target << "PfmCounterNames[" << getPfmCounterId(CycleCounter)
void ExegesisEmitter::emitPfmCounters(raw_ostream &OS) const {
   for (const auto &NameAndIndex : PfmCounterNameTable)
     OS << "  \"" << NameAndIndex.first << "\", // " << NameAndIndex.second
        << "\n";
   OS << "};\n\n";
 
   // Emit the IssueCounters table.
   const auto PfmCounterDefs =
       Records.getAllDerivedDefinitions("ProcPfmCounters");
+  // Only emit if non-empty.
+  const bool HasAtLeastOnePfmIssueCounter =
+      llvm::any_of(PfmCounterDefs, [](const Record *Def) {
+        return !Def->getValueAsListOfDefs("IssueCounters").empty();
+      });
+  if (HasAtLeastOnePfmIssueCounter) {
     OS << "static const PfmCountersInfo::IssueCounter " << Target
        << "PfmIssueCounters[] = {\n";
     for (const Record *Def : PfmCounterDefs) {
       for (const Record *ICDef : Def->getValueAsListOfDefs("IssueCounters"))
         OS << "  { " << Target << "PfmCounterNames["
            << getPfmCounterId(ICDef->getValueAsString("Counter")) << "], \""
            << ICDef->getValueAsString("ResourceName") << "\"},\n";
     }
-
     OS << "};\n";
+  }
 
   // Now generate the PfmCountersInfo.
   unsigned IssueCountersTableOffset = 0;
   for (const Record *Def : PfmCounterDefs)
     emitPfmCountersInfo(*Def, IssueCountersTableOffset, OS);
 
   OS << "\n";
-}
+} // namespace
 
 void ExegesisEmitter::emitPfmCountersLookupTable(raw_ostream &OS) const {
   std::vector<Record *> Bindings =
       Records.getAllDerivedDefinitions("PfmCountersBinding");
+  assert(!Bindings.empty() && "there must be at least one binding");
   llvm::sort(Bindings, [](const Record *L, const Record *R) {
     return L->getValueAsString("CpuName") < R->getValueAsString("CpuName");
   });
 
   OS << "// Sorted (by CpuName) array of pfm counters.\n"
      << "static const CpuAndPfmCounters " << Target << "CpuPfmCounters[] = {\n";
   for (Record *Binding : Bindings) {
     // Emit as { "cpu", procinit },