[COFF, ARM64] Add support for MSVC buffer security check

[mstorsjo]

Is there any existing test case for the mingw mode of the stack protector for aarch64? If not, can you add one at the same time, to show that it doesn't change with this patch (i.e. still uses __stack_chk_*).

[mgrang]

In D54248#1291831, @mstorsjo wrote:

Is there any existing test case for the mingw mode of the stack protector for aarch64? If not, can you add one at the same time, to show that it doesn't change with this patch (i.e. still uses __stack_chk_*).

Yes, there is a test case fo ther mingw mode of stack protector: llvm/test/CodeGen/AArch64/ mingw-refptr.ll. I made sure I don't break any existing tests :)

[rnk]

lgtm

llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h

public:
   bool useLoadStackGuardNode() const override;
   TargetLoweringBase::LegalizeTypeAction
   getPreferredVectorAction(MVT VT) const override;
 
   /// If the target has a standard location for the stack protector cookie,
   /// returns the address of that location. Otherwise, returns nullptr.
   Value *getIRStackGuard(IRBuilder<> &IRB) const override;
 
+  void insertSSPDeclarations(Module &M) const override;
+  Value *getSDagStackGuard(const Module &M) const override;
+  Value *getSSPStackGuardCheck(const Module &M) const override;
+
   /// If the target has a standard location for the unsafe stack pointer,
   /// returns the address of that location. Otherwise, returns nullptr.
   Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const override;
 
   /// If a physical register, this returns the register that receives the
   /// exception address on entry to an EH pad.
   unsigned
   getExceptionPointerRegister(const Constant *PersonalityFn) const override {

llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp

Value *AArch64TargetLowering::getIRStackGuard(IRBuilder<> &IRB) const {
   // Fuchsia is similar.
   // <zircon/tls.h> defines ZX_TLS_STACK_GUARD_OFFSET with this value.
   if (Subtarget->isTargetFuchsia())
     return UseTlsOffset(IRB, -0x10);
 
   return TargetLowering::getIRStackGuard(IRB);
 }
 
+void AArch64TargetLowering::insertSSPDeclarations(Module &M) const {
+  // MSVC CRT provides functionalities for stack protection.
+  if (Subtarget->getTargetTriple().isWindowsMSVCEnvironment()) {
+    // MSVC CRT has a global variable holding security cookie.
+    M.getOrInsertGlobal("__security_cookie",
+                        Type::getInt8PtrTy(M.getContext()));
+
+    // MSVC CRT has a function to validate security cookie.
+    auto *SecurityCheckCookie = cast<Function>(
+        M.getOrInsertFunction("__security_check_cookie",
+                              Type::getVoidTy(M.getContext()),
+                              Type::getInt8PtrTy(M.getContext())));
+    SecurityCheckCookie->setCallingConv(CallingConv::Win64);
+    SecurityCheckCookie->addAttribute(1, Attribute::AttrKind::InReg);
+    return;
+  }
+  TargetLowering::insertSSPDeclarations(M);
+}
+
+Value *AArch64TargetLowering::getSDagStackGuard(const Module &M) const {
+  // MSVC CRT has a global variable holding security cookie.
+  if (Subtarget->getTargetTriple().isWindowsMSVCEnvironment())
+    return M.getGlobalVariable("__security_cookie");
+  return TargetLowering::getSDagStackGuard(M);
+}
+
+Value *AArch64TargetLowering::getSSPStackGuardCheck(const Module &M) const {
+  // MSVC CRT has a function to validate security cookie.
+  if (Subtarget->getTargetTriple().isWindowsMSVCEnvironment())
+    return M.getFunction("__security_check_cookie");
+  return TargetLowering::getSSPStackGuardCheck(M);
+}
+
 Value *AArch64TargetLowering::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
   // Android provides a fixed TLS slot for the SafeStack pointer. See the
   // definition of TLS_SLOT_SAFESTACK in
   // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
   if (Subtarget->isTargetAndroid())
     return UseTlsOffset(IRB, 0x48);
 
   // Fuchsia is similar.

llvm/trunk/test/CodeGen/AArch64/stack-protector-target.ll

 ; Test target-specific stack cookie location.
 ; RUN: llc -mtriple=aarch64-linux-android < %s -o - | FileCheck --check-prefix=ANDROID-AARCH64 %s
 ; RUN: llc -mtriple=aarch64-fuchsia < %s -o - | FileCheck --check-prefixes=FUCHSIA-AARCH64-COMMON,FUCHSIA-AARCH64-USER %s
 ; RUN: llc -mtriple=aarch64-fuchsia -code-model=kernel < %s -o - | FileCheck --check-prefixes=FUCHSIA-AARCH64-COMMON,FUCHSIA-AARCH64-KERNEL %s
+; RUN: llc -mtriple=aarch64-windows < %s -o - | FileCheck --check-prefix=WINDOWS-AARCH64 %s
 
 define void @_Z1fv() sspreq {
 entry:
   %x = alloca i32, align 4
   %0 = bitcast i32* %x to i8*
   call void @_Z7CapturePi(i32* nonnull %x)
   ret void
 }

 
 ; FUCHSIA-AARCH64-USER: mrs [[A:.*]], TPIDR_EL0
 ; FUCHSIA-AARCH64-KERNEL: mrs [[A:.*]], TPIDR_EL1
 ; FUCHSIA-AARCH64-COMMON: ldur [[B:.*]], {{\[}}[[A]], #-16]
 ; FUCHSIA-AARCH64-COMMON: str [[B]], [sp,
 ; FUCHSIA-AARCH64-COMMON: ldur [[C:.*]], {{\[}}[[A]], #-16]
 ; FUCHSIA-AARCH64-COMMON: ldr [[D:.*]], [sp,
 ; FUCHSIA-AARCH64-COMMON: cmp [[C]], [[D]]
+
+; WINDOWS-AARCH64: adrp x8, __security_cookie
+; WINDOWS-AARCH64: ldr x8, [x8, __security_cookie]
+; WINDOWS-AARCH64: str x8, [sp, #8]
+; WINDOWS-AARCH64: bl  _Z7CapturePi
+; WINDOWS-AARCH64: ldr x0, [sp, #8]
+; WINDOWS-AARCH64: bl  __security_check_cookie