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Differential D54038

[mips][msa] Fix msa_[st/ld] offset check
ClosedPublic

Authored by abeserminji on Nov 2 2018, 10:10 AM.

Details

Reviewers
atanasyan
petarj
smaksimovic
Commits
rGe59211638cf3: [mips][msa] Fix msa_[st/ld] offset check
rL346302: [mips][msa] Fix msa_[st/ld] offset check
rC346302: [mips][msa] Fix msa_[st/ld] offset check
Summary

When msa_[st/ld]_[b/h/w/d] is called with constexpr as an offset argument,
it can be checked in compile time if it is a valid offset. The offset has to be
a multiple of an element size.
E.g. msa_st_h(p, 5) is not valid, because 5 is not a multiple of 2,
while msa_ld_w(p, 12) is valid, because 12 is a multiple of 4.

Depends on D53984.

Diff Detail

Repository
rC Clang

Event Timeline

abeserminji created this revision.Nov 2 2018, 10:10 AM
Herald added subscribers: jrtc27, arichardson, sdardis. · View Herald TranscriptNov 2 2018, 10:10 AM
atanasyan accepted this revision.Nov 6 2018, 7:59 AM

LGTM

This revision is now accepted and ready to land.Nov 6 2018, 7:59 AM
Closed by commit rC346302: [mips][msa] Fix msa_[st/ld] offset check (authored by abeserminji). · Explain WhyNov 7 2018, 3:40 AM
This revision was automatically updated to reflect the committed changes.
Herald added a subscriber: cfe-commits. · View Herald TranscriptNov 7 2018, 3:40 AM

Revision Contents

PathSize
lib/
Sema/
16 lines
test/
CodeGen/
12 lines
16 lines

Diff 172914

lib/Sema/SemaChecking.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 2,986 Lines • ▼ Show 20 Linesbool Sema::CheckMipsBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
case Mips::BI__builtin_msa_splati_d: i = 1; l = 0; u = 1; break; case Mips::BI__builtin_msa_splati_d: i = 1; l = 0; u = 1; break;
case Mips::BI__builtin_msa_sldi_d: i = 2; l = 0; u = 1; break; case Mips::BI__builtin_msa_sldi_d: i = 2; l = 0; u = 1; break;
// Memory offsets and immediate loads. // Memory offsets and immediate loads.
// These intrinsics take a signed 10 bit immediate. // These intrinsics take a signed 10 bit immediate.
case Mips::BI__builtin_msa_ldi_b: i = 0; l = -128; u = 255; break; case Mips::BI__builtin_msa_ldi_b: i = 0; l = -128; u = 255; break;
case Mips::BI__builtin_msa_ldi_h: case Mips::BI__builtin_msa_ldi_h:
case Mips::BI__builtin_msa_ldi_w: case Mips::BI__builtin_msa_ldi_w:
case Mips::BI__builtin_msa_ldi_d: i = 0; l = -512; u = 511; break; case Mips::BI__builtin_msa_ldi_d: i = 0; l = -512; u = 511; break;
case Mips::BI__builtin_msa_ld_b: i = 1; l = -512; u = 511; m = 16; break; case Mips::BI__builtin_msa_ld_b: i = 1; l = -512; u = 511; m = 1; break;
case Mips::BI__builtin_msa_ld_h: i = 1; l = -1024; u = 1022; m = 16; break; case Mips::BI__builtin_msa_ld_h: i = 1; l = -1024; u = 1022; m = 2; break;
case Mips::BI__builtin_msa_ld_w: i = 1; l = -2048; u = 2044; m = 16; break; case Mips::BI__builtin_msa_ld_w: i = 1; l = -2048; u = 2044; m = 4; break;
case Mips::BI__builtin_msa_ld_d: i = 1; l = -4096; u = 4088; m = 16; break; case Mips::BI__builtin_msa_ld_d: i = 1; l = -4096; u = 4088; m = 8; break;
case Mips::BI__builtin_msa_st_b: i = 2; l = -512; u = 511; m = 16; break; case Mips::BI__builtin_msa_st_b: i = 2; l = -512; u = 511; m = 1; break;
case Mips::BI__builtin_msa_st_h: i = 2; l = -1024; u = 1022; m = 16; break; case Mips::BI__builtin_msa_st_h: i = 2; l = -1024; u = 1022; m = 2; break;
case Mips::BI__builtin_msa_st_w: i = 2; l = -2048; u = 2044; m = 16; break; case Mips::BI__builtin_msa_st_w: i = 2; l = -2048; u = 2044; m = 4; break;
case Mips::BI__builtin_msa_st_d: i = 2; l = -4096; u = 4088; m = 16; break; case Mips::BI__builtin_msa_st_d: i = 2; l = -4096; u = 4088; m = 8; break;
} }
if (!m) if (!m)
return SemaBuiltinConstantArgRange(TheCall, i, l, u); return SemaBuiltinConstantArgRange(TheCall, i, l, u);
return SemaBuiltinConstantArgRange(TheCall, i, l, u) || return SemaBuiltinConstantArgRange(TheCall, i, l, u) ||
SemaBuiltinConstantArgMultiple(TheCall, i, m); SemaBuiltinConstantArgMultiple(TheCall, i, m);
} }
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test/CodeGen/builtins-mips-msa-error.c

Show First 20 Lines • Show All 106 Lines • ▼ Show 20 Linesvoid test(void) {
int_r = __msa_copy_u_w(v4u32_a, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}} int_r = __msa_copy_u_w(v4u32_a, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
ll_r = __msa_copy_u_d(v2i64_a, 2); // expected-error {{argument value 2 is outside the valid range [0, 1]}} ll_r = __msa_copy_u_d(v2i64_a, 2); // expected-error {{argument value 2 is outside the valid range [0, 1]}}
v16i8_r = __msa_insve_b(v16i8_r, 16, v16i8_a); // expected-error {{argument value 16 is outside the valid range [0, 15]}} v16i8_r = __msa_insve_b(v16i8_r, 16, v16i8_a); // expected-error {{argument value 16 is outside the valid range [0, 15]}}
v8i16_r = __msa_insve_h(v8i16_r, 8, v8i16_a); // expected-error {{argument value 8 is outside the valid range [0, 7]}} v8i16_r = __msa_insve_h(v8i16_r, 8, v8i16_a); // expected-error {{argument value 8 is outside the valid range [0, 7]}}
v4i32_r = __msa_insve_w(v4i32_r, 4, v4i32_a); // expected-error {{argument value 4 is outside the valid range [0, 3]}} v4i32_r = __msa_insve_w(v4i32_r, 4, v4i32_a); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
v2i64_r = __msa_insve_d(v2i64_r, 2, v2i64_a); // expected-error {{argument value 2 is outside the valid range [0, 1]}} v2i64_r = __msa_insve_d(v2i64_r, 2, v2i64_a); // expected-error {{argument value 2 is outside the valid range [0, 1]}}
v8i16_r = __msa_ld_h(&v8i16_a, 77); // expected-error {{argument should be a multiple of 16}} v8i16_r = __msa_ld_h(&v8i16_a, 77); // expected-error {{argument should be a multiple of 2}}
v4i32_r = __msa_ld_w(&v4i32_a, 14); // expected-error {{argument should be a multiple of 16}} v4i32_r = __msa_ld_w(&v4i32_a, 14); // expected-error {{argument should be a multiple of 4}}
v2i64_r = __msa_ld_d(&v2i64_a, 23); // expected-error {{argument should be a multiple of 16}} v2i64_r = __msa_ld_d(&v2i64_a, 23); // expected-error {{argument should be a multiple of 8}}
v16i8_r = __msa_ld_b(&v16i8_a, 512); // expected-error {{argument value 512 is outside the valid range [-512, 511]}} v16i8_r = __msa_ld_b(&v16i8_a, 512); // expected-error {{argument value 512 is outside the valid range [-512, 511]}}
v8i16_r = __msa_ld_h(&v8i16_a, 1024); // expected-error {{argument value 1024 is outside the valid range [-1024, 1022]}} v8i16_r = __msa_ld_h(&v8i16_a, 1024); // expected-error {{argument value 1024 is outside the valid range [-1024, 1022]}}
v4i32_r = __msa_ld_w(&v4i32_a, 2048); // expected-error {{argument value 2048 is outside the valid range [-2048, 2044]}} v4i32_r = __msa_ld_w(&v4i32_a, 2048); // expected-error {{argument value 2048 is outside the valid range [-2048, 2044]}}
v2i64_r = __msa_ld_d(&v2i64_a, 4096); // expected-error {{argument value 4096 is outside the valid range [-4096, 4088]}} v2i64_r = __msa_ld_d(&v2i64_a, 4096); // expected-error {{argument value 4096 is outside the valid range [-4096, 4088]}}
v16i8_r = __msa_ldi_b(256); // expected-error {{argument value 256 is outside the valid range [-128, 255]}} v16i8_r = __msa_ldi_b(256); // expected-error {{argument value 256 is outside the valid range [-128, 255]}}
v8i16_r = __msa_ldi_h(512); // expected-error {{argument value 512 is outside the valid range [-512, 511]}} v8i16_r = __msa_ldi_h(512); // expected-error {{argument value 512 is outside the valid range [-512, 511]}}
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Linesvoid test(void) {
v4i32_r = __msa_srli_w(v4i32_a, 32); // expected-error {{argument value 32 is outside the valid range [0, 31]}} v4i32_r = __msa_srli_w(v4i32_a, 32); // expected-error {{argument value 32 is outside the valid range [0, 31]}}
v2i64_r = __msa_srli_d(v2i64_a, 64); // expected-error {{argument value 64 is outside the valid range [0, 63]}} v2i64_r = __msa_srli_d(v2i64_a, 64); // expected-error {{argument value 64 is outside the valid range [0, 63]}}
v16i8_r = __msa_srlri_b(v16i8_a, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}} v16i8_r = __msa_srlri_b(v16i8_a, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}}
v8i16_r = __msa_srlri_h(v8i16_a, 16); // expected-error {{argument value 16 is outside the valid range [0, 15]}} v8i16_r = __msa_srlri_h(v8i16_a, 16); // expected-error {{argument value 16 is outside the valid range [0, 15]}}
v4i32_r = __msa_srlri_w(v4i32_a, 32); // expected-error {{argument value 32 is outside the valid range [0, 31]}} v4i32_r = __msa_srlri_w(v4i32_a, 32); // expected-error {{argument value 32 is outside the valid range [0, 31]}}
v2i64_r = __msa_srlri_d(v2i64_a, 64); // expected-error {{argument value 64 is outside the valid range [0, 63]}} v2i64_r = __msa_srlri_d(v2i64_a, 64); // expected-error {{argument value 64 is outside the valid range [0, 63]}}
__msa_st_h(v8i16_b, &v8i16_a, 51); // expected-error {{argument should be a multiple of 16}} __msa_st_h(v8i16_b, &v8i16_a, 51); // expected-error {{argument should be a multiple of 2}}
__msa_st_w(v4i32_b, &v4i32_a, 51); // expected-error {{argument should be a multiple of 16}} __msa_st_w(v4i32_b, &v4i32_a, 51); // expected-error {{argument should be a multiple of 4}}
__msa_st_d(v2i64_b, &v2i64_a, 12); // expected-error {{argument should be a multiple of 16}} __msa_st_d(v2i64_b, &v2i64_a, 12); // expected-error {{argument should be a multiple of 8}}
__msa_st_b(v16i8_b, &v16i8_a, 512); // expected-error {{argument value 512 is outside the valid range [-512, 511]}} __msa_st_b(v16i8_b, &v16i8_a, 512); // expected-error {{argument value 512 is outside the valid range [-512, 511]}}
__msa_st_h(v8i16_b, &v8i16_a, 1024); // expected-error {{argument value 1024 is outside the valid range [-1024, 1022]}} __msa_st_h(v8i16_b, &v8i16_a, 1024); // expected-error {{argument value 1024 is outside the valid range [-1024, 1022]}}
__msa_st_w(v4i32_b, &v4i32_a, 2048); // expected-error {{argument value 2048 is outside the valid range [-2048, 2044]}} __msa_st_w(v4i32_b, &v4i32_a, 2048); // expected-error {{argument value 2048 is outside the valid range [-2048, 2044]}}
__msa_st_d(v2i64_b, &v2i64_a, 4096); // expected-error {{argument value 4096 is outside the valid range [-4096, 4088]}} __msa_st_d(v2i64_b, &v2i64_a, 4096); // expected-error {{argument value 4096 is outside the valid range [-4096, 4088]}}
v16i8_r = __msa_subvi_b(v16i8_a, 256); // expected-error {{argument value 256 is outside the valid range [0, 31]}} v16i8_r = __msa_subvi_b(v16i8_a, 256); // expected-error {{argument value 256 is outside the valid range [0, 31]}}
v8i16_r = __msa_subvi_h(v8i16_a, 256); // expected-error {{argument value 256 is outside the valid range [0, 31]}} v8i16_r = __msa_subvi_h(v8i16_a, 256); // expected-error {{argument value 256 is outside the valid range [0, 31]}}
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test/CodeGen/builtins-mips-msa.c

Show First 20 Lines • Show All 514 Lines • ▼ Show 20 Linesvoid test(void) {
v4i32_r = __msa_insert_w(v4i32_r, 1, 25); // CHECK: call <4 x i32> @llvm.mips.insert.w( v4i32_r = __msa_insert_w(v4i32_r, 1, 25); // CHECK: call <4 x i32> @llvm.mips.insert.w(
v2i64_r = __msa_insert_d(v2i64_r, 1, 25); // CHECK: call <2 x i64> @llvm.mips.insert.d( v2i64_r = __msa_insert_d(v2i64_r, 1, 25); // CHECK: call <2 x i64> @llvm.mips.insert.d(
v16i8_r = __msa_insve_b(v16i8_r, 1, v16i8_a); // CHECK: call <16 x i8> @llvm.mips.insve.b( v16i8_r = __msa_insve_b(v16i8_r, 1, v16i8_a); // CHECK: call <16 x i8> @llvm.mips.insve.b(
v8i16_r = __msa_insve_h(v8i16_r, 1, v8i16_a); // CHECK: call <8 x i16> @llvm.mips.insve.h( v8i16_r = __msa_insve_h(v8i16_r, 1, v8i16_a); // CHECK: call <8 x i16> @llvm.mips.insve.h(
v4i32_r = __msa_insve_w(v4i32_r, 1, v4i32_a); // CHECK: call <4 x i32> @llvm.mips.insve.w( v4i32_r = __msa_insve_w(v4i32_r, 1, v4i32_a); // CHECK: call <4 x i32> @llvm.mips.insve.w(
v2i64_r = __msa_insve_d(v2i64_r, 1, v2i64_a); // CHECK: call <2 x i64> @llvm.mips.insve.d( v2i64_r = __msa_insve_d(v2i64_r, 1, v2i64_a); // CHECK: call <2 x i64> @llvm.mips.insve.d(
v16i8_r = __msa_ld_b(&v16i8_a, 16); // CHECK: call <16 x i8> @llvm.mips.ld.b( v16i8_r = __msa_ld_b(&v16i8_a, 1); // CHECK: call <16 x i8> @llvm.mips.ld.b(
v8i16_r = __msa_ld_h(&v8i16_a, 32); // CHECK: call <8 x i16> @llvm.mips.ld.h( v8i16_r = __msa_ld_h(&v8i16_a, 2); // CHECK: call <8 x i16> @llvm.mips.ld.h(
v4i32_r = __msa_ld_w(&v4i32_a, 48); // CHECK: call <4 x i32> @llvm.mips.ld.w( v4i32_r = __msa_ld_w(&v4i32_a, 4); // CHECK: call <4 x i32> @llvm.mips.ld.w(
v2i64_r = __msa_ld_d(&v2i64_a, 96); // CHECK: call <2 x i64> @llvm.mips.ld.d( v2i64_r = __msa_ld_d(&v2i64_a, 8); // CHECK: call <2 x i64> @llvm.mips.ld.d(
v16i8_r = __msa_ldi_b(3); // CHECK: call <16 x i8> @llvm.mips.ldi.b( v16i8_r = __msa_ldi_b(3); // CHECK: call <16 x i8> @llvm.mips.ldi.b(
v16i8_r = __msa_ldi_b(-128); // CHECK: call <16 x i8> @llvm.mips.ldi.b( v16i8_r = __msa_ldi_b(-128); // CHECK: call <16 x i8> @llvm.mips.ldi.b(
v16i8_r = __msa_ldi_b(255); // CHECK: call <16 x i8> @llvm.mips.ldi.b( v16i8_r = __msa_ldi_b(255); // CHECK: call <16 x i8> @llvm.mips.ldi.b(
v8i16_r = __msa_ldi_h(3); // CHECK: call <8 x i16> @llvm.mips.ldi.h( v8i16_r = __msa_ldi_h(3); // CHECK: call <8 x i16> @llvm.mips.ldi.h(
v4i32_r = __msa_ldi_w(3); // CHECK: call <4 x i32> @llvm.mips.ldi.w( v4i32_r = __msa_ldi_w(3); // CHECK: call <4 x i32> @llvm.mips.ldi.w(
v2i64_r = __msa_ldi_d(3); // CHECK: call <2 x i64> @llvm.mips.ldi.d( v2i64_r = __msa_ldi_d(3); // CHECK: call <2 x i64> @llvm.mips.ldi.d(
▲ Show 20 Lines • Show All 231 Lines • ▼ Show 20 Linesvoid test(void) {
v4i32_r = __msa_srlr_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.srlr.w( v4i32_r = __msa_srlr_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.srlr.w(
v2i64_r = __msa_srlr_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.srlr.d( v2i64_r = __msa_srlr_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.srlr.d(
v16i8_r = __msa_srlri_b(v16i8_a, 3); // CHECK: call <16 x i8> @llvm.mips.srlri.b( v16i8_r = __msa_srlri_b(v16i8_a, 3); // CHECK: call <16 x i8> @llvm.mips.srlri.b(
v8i16_r = __msa_srlri_h(v8i16_a, 3); // CHECK: call <8 x i16> @llvm.mips.srlri.h( v8i16_r = __msa_srlri_h(v8i16_a, 3); // CHECK: call <8 x i16> @llvm.mips.srlri.h(
v4i32_r = __msa_srlri_w(v4i32_a, 3); // CHECK: call <4 x i32> @llvm.mips.srlri.w( v4i32_r = __msa_srlri_w(v4i32_a, 3); // CHECK: call <4 x i32> @llvm.mips.srlri.w(
v2i64_r = __msa_srlri_d(v2i64_a, 3); // CHECK: call <2 x i64> @llvm.mips.srlri.d( v2i64_r = __msa_srlri_d(v2i64_a, 3); // CHECK: call <2 x i64> @llvm.mips.srlri.d(
__msa_st_b(v16i8_b, &v16i8_a, 16); // CHECK: call void @llvm.mips.st.b( __msa_st_b(v16i8_b, &v16i8_a, 1); // CHECK: call void @llvm.mips.st.b(
__msa_st_h(v8i16_b, &v8i16_a, 32); // CHECK: call void @llvm.mips.st.h( __msa_st_h(v8i16_b, &v8i16_a, 2); // CHECK: call void @llvm.mips.st.h(
__msa_st_w(v4i32_b, &v4i32_a, 48); // CHECK: call void @llvm.mips.st.w( __msa_st_w(v4i32_b, &v4i32_a, 4); // CHECK: call void @llvm.mips.st.w(
__msa_st_d(v2i64_b, &v2i64_a, 96); // CHECK: call void @llvm.mips.st.d( __msa_st_d(v2i64_b, &v2i64_a, 8); // CHECK: call void @llvm.mips.st.d(
v16i8_r = __msa_subs_s_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.subs.s.b( v16i8_r = __msa_subs_s_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.subs.s.b(
v8i16_r = __msa_subs_s_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.subs.s.h( v8i16_r = __msa_subs_s_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.subs.s.h(
v4i32_r = __msa_subs_s_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.subs.s.w( v4i32_r = __msa_subs_s_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.subs.s.w(
v2i64_r = __msa_subs_s_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.subs.s.d( v2i64_r = __msa_subs_s_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.subs.s.d(
v16u8_r = __msa_subs_u_b(v16u8_a, v16u8_b); // CHECK: call <16 x i8> @llvm.mips.subs.u.b( v16u8_r = __msa_subs_u_b(v16u8_a, v16u8_b); // CHECK: call <16 x i8> @llvm.mips.subs.u.b(
v8u16_r = __msa_subs_u_h(v8u16_a, v8u16_b); // CHECK: call <8 x i16> @llvm.mips.subs.u.h( v8u16_r = __msa_subs_u_h(v8u16_a, v8u16_b); // CHECK: call <8 x i16> @llvm.mips.subs.u.h(
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