[WebAssembly] Add V128 to WebAssemblyInstrInfo::copyPhysReg

[aheejin]

Can we have a test case? I think we can have an mir test case with COPY opcode in there. To lower COPY to the relevant COPY_type opcode, we need this function.

[tlively]

• Add MIR test

[tlively]

In D53872#1281488, @aheejin wrote:

Can we have a test case? I think we can have an mir test case with COPY opcode in there. To lower COPY to the relevant COPY_type opcode, we need this function.

Done.

[aheejin]

test/CodeGen/WebAssembly/regcopy.mir

32

I think you can remove these for virtual registers?

36

Do we need frameinfo here?

[tlively]

• Further minimize test case

[tlively]

test/CodeGen/WebAssembly/regcopy.mir

32

Doesn't seem so, but I removed some other things.

36

Nope.

[aheejin]

Otherwise LGTM

test/CodeGen/WebAssembly/regcopy.mir

32

I think you can remove this and add :i32 to the code itself as you did for %0, as in
%0:i32 = COPY %1:i32
The same for other %1 usages in other functions.

lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp

void WebAssemblyInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
   if (RC == &WebAssembly::I32RegClass)
     CopyOpcode = WebAssembly::COPY_I32;
   else if (RC == &WebAssembly::I64RegClass)
     CopyOpcode = WebAssembly::COPY_I64;
   else if (RC == &WebAssembly::F32RegClass)
     CopyOpcode = WebAssembly::COPY_F32;
   else if (RC == &WebAssembly::F64RegClass)
     CopyOpcode = WebAssembly::COPY_F64;
+  else if (RC == &WebAssembly::V128RegClass)
+    CopyOpcode = WebAssembly::COPY_V128;
   else
     llvm_unreachable("Unexpected register class");
 
   BuildMI(MBB, I, DL, get(CopyOpcode), DestReg)
       .addReg(SrcReg, KillSrc ? RegState::Kill : 0);
 }
 
 MachineInstr *WebAssemblyInstrInfo::commuteInstructionImpl(

test/CodeGen/WebAssembly/regcopy.mir

+# RUN: llc %s -o - -run-pass=postrapseudos | FileCheck %s
+--- |
+  target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
+  target triple = "wasm32-unknown-unknown"
+
+  define void @copy_i32() {
+    ret void
+  }
+
+  define void @copy_i64() {
+    ret void
+  }
+
+  define void @copy_f32() {
+    ret void
+  }
+
+  define void @copy_f64() {
+    ret void
+  }
+
+  define void @copy_v128() {
+    ret void
+  }
+...
+---
+name: copy_i32
+# CHECK-LABEL: copy_i32
+registers:
+  - { id: 0, class: i32 }
+  - { id: 1, class: i32 }
+body:             |
+  ; CHECK-LABEL: bb.0:
+  ; CHECK-NEXT: %0:i32 = COPY_I32 %1:i32
+  ; CHECK-NEXT: RETURN_VOID
+  bb.0:
+    %0:i32 = COPY %1
+    RETURN_VOID implicit-def $arguments
+...
+---
+name: copy_i64
+# CHECK-LABEL: copy_i64
+registers:
+  - { id: 0, class: i64 }
+  - { id: 1, class: i64 }
+body:             |
+  ; CHECK-LABEL: bb.0:
+  ; CHECK-NEXT: %0:i64 = COPY_I64 %1:i64
+  ; CHECK-NEXT: RETURN_VOID
+  bb.0:
+    %0:i64 = COPY %1
+    RETURN_VOID implicit-def $arguments
+...
+---
+name: copy_f32
+# CHECK-LABEL: copy_f32
+registers:
+  - { id: 0, class: f32 }
+  - { id: 1, class: f32 }
+body:             |
+  ; CHECK-LABEL: bb.0:
+  ; CHECK-NEXT: %0:f32 = COPY_F32 %1:f32
+  ; CHECK-NEXT: RETURN_VOID
+  bb.0:
+    %0:f32 = COPY %1
+    RETURN_VOID implicit-def $arguments
+...
+---
+name: copy_f64
+# CHECK-LABEL: copy_f64
+registers:
+  - { id: 0, class: f64 }
+  - { id: 1, class: f64 }
+body:             |
+  ; CHECK-LABEL: bb.0:
+  ; CHECK-NEXT: %0:f64 = COPY_F64 %1:f64
+  ; CHECK-NEXT: RETURN_VOID
+  bb.0:
+    %0:f64 = COPY %1
+    RETURN_VOID implicit-def $arguments
+...
+---
+name: copy_v128
+# CHECK-LABEL: copy_v128
+registers:
+  - { id: 0, class: v128 }
+  - { id: 1, class: v128 }
+body:             |
+  ; CHECK-LABEL: bb.0:
+  ; CHECK-NEXT: %0:v128 = COPY_V128 %1:v128
+  ; CHECK-NEXT: RETURN_VOID
+  bb.0:
+    %0:v128 = COPY %1
+    RETURN_VOID implicit-def $arguments
+...