[WebAssembly] Lower away condition truncations for scalar selects

[aheejin]

It seems only 1 can be a possible condition value from a valid LLVM IR, and if that's the case, I think what we need in this case is UndefinedBooleanContent. And I guess that should be the case for all other wasm instructions, but if we comment out this line, a bunch of test fails... Not sure why we need that line and what makes this case exceptional. Could you check?

[tlively]

In D53676#1275284, @aheejin wrote:

It seems only 1 can be a possible condition value from a valid LLVM IR, and if that's the case, I think what we need in this case is UndefinedBooleanContent. And I guess that should be the case for all other wasm instructions, but if we comment out this line, a bunch of test fails... Not sure why we need that line and what makes this case exceptional. Could you check?

I checked it out. The BooleanContents value is used to describe both how bools are produced and how bools are consumed. ZeroOrOneBooleanContent is a correct value for WebAssembly because all of our instructions that produce bools produce either zero or one. Setting the BooleanContents to UndefinedBooleanContent causes LLVM to emit and 1 after every instruction that produces a bool (or at least after instructions that produce bools that are returned from functions). That is why the tests are failing. I'm not sure why LLVM explicitly zeros the high bits instead of leaving them undefined.

I suppose ideally we would be able to separately specify that instructions that produce bools produce either zeros or ones and instructions that consume bools can consume zeros or nonzeros, rather than using a single configuration option for both producers and consumers of bools.

[aheejin]

Thanks!

llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrFloat.td

 def : Pat<(select (i32 (setne I32:$cond, 0)), F64:$lhs, F64:$rhs),
           (SELECT_F64 F64:$lhs, F64:$rhs, I32:$cond)>;
 
 // And again, this time with seteq instead of setne and the arms reversed.
 def : Pat<(select (i32 (seteq I32:$cond, 0)), F32:$lhs, F32:$rhs),
           (SELECT_F32 F32:$rhs, F32:$lhs, I32:$cond)>;
 def : Pat<(select (i32 (seteq I32:$cond, 0)), F64:$lhs, F64:$rhs),
           (SELECT_F64 F64:$rhs, F64:$lhs, I32:$cond)>;
+
+// The legalizer inserts an unnecessary `and 1` to make input conform
+// to getBooleanContents, which we can lower away.
+def : Pat<(select (i32 (and I32:$cond, 1)), F32:$lhs, F32:$rhs),
+          (SELECT_F32 F32:$lhs, F32:$rhs, I32:$cond)>;
+def : Pat<(select (i32 (and I32:$cond, 1)), F64:$lhs, F64:$rhs),
+          (SELECT_F64 F64:$lhs, F64:$rhs, I32:$cond)>;

llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInteger.td

 def : Pat<(select (i32 (setne I32:$cond, 0)), I64:$lhs, I64:$rhs),
           (SELECT_I64 I64:$lhs, I64:$rhs, I32:$cond)>;
 
 // And again, this time with seteq instead of setne and the arms reversed.
 def : Pat<(select (i32 (seteq I32:$cond, 0)), I32:$lhs, I32:$rhs),
           (SELECT_I32 I32:$rhs, I32:$lhs, I32:$cond)>;
 def : Pat<(select (i32 (seteq I32:$cond, 0)), I64:$lhs, I64:$rhs),
           (SELECT_I64 I64:$rhs, I64:$lhs, I32:$cond)>;
+
+// The legalizer inserts an unnecessary `and 1` to make input conform
+// to getBooleanContents, which we can lower away.
+def : Pat<(select (i32 (and I32:$cond, 1)), I32:$lhs, I32:$rhs),
+          (SELECT_I32 I32:$lhs, I32:$rhs, I32:$cond)>;
+def : Pat<(select (i32 (and I32:$cond, 1)), I64:$lhs, I64:$rhs),
+          (SELECT_I64 I64:$lhs, I64:$rhs, I32:$cond)>;

llvm/trunk/test/CodeGen/WebAssembly/select.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s --check-prefixes CHECK,SLOW
 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -fast-isel -fast-isel-abort=1 | FileCheck %s
 
 ; Test that wasm select instruction is selected from LLVM select instruction.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: select_i32_bool:
 ; CHECK-NEXT: .param     i32, i32, i32{{$}}
 ; CHECK-NEXT: .result    i32{{$}}
 ; CHECK-NEXT: i32.select $push0=, $1, $2, $0{{$}}
 ; CHECK-NEXT: return     $pop0{{$}}
 define i32 @select_i32_bool(i1 zeroext %a, i32 %b, i32 %c) {
   %cond = select i1 %a, i32 %b, i32 %c
   ret i32 %cond
 }
 
+; CHECK-LABEL: select_i32_bool_nozext:
+; CHECK-NEXT: .param     i32, i32, i32{{$}}
+; CHECK-NEXT: .result    i32{{$}}
+; SLOW-NEXT: i32.select $push0=, $1, $2, $0{{$}}
+; SLOW-NEXT: return     $pop0{{$}}
+define i32 @select_i32_bool_nozext(i1 %a, i32 %b, i32 %c) {
+  %cond = select i1 %a, i32 %b, i32 %c
+  ret i32 %cond
+}
+
 ; CHECK-LABEL: select_i32_eq:
 ; CHECK-NEXT: .param     i32, i32, i32{{$}}
 ; CHECK-NEXT: .result    i32{{$}}
 ; CHECK-NEXT: i32.select $push0=, $2, $1, $0{{$}}
 ; CHECK-NEXT: return     $pop0{{$}}
 define i32 @select_i32_eq(i32 %a, i32 %b, i32 %c) {
   %cmp = icmp eq i32 %a, 0
   %cond = select i1 %cmp, i32 %b, i32 %c

 ; CHECK-NEXT: .result    i64{{$}}
 ; CHECK-NEXT: i64.select $push0=, $1, $2, $0{{$}}
 ; CHECK-NEXT: return     $pop0{{$}}
 define i64 @select_i64_bool(i1 zeroext %a, i64 %b, i64 %c) {
   %cond = select i1 %a, i64 %b, i64 %c
   ret i64 %cond
 }
 
+; CHECK-LABEL: select_i64_bool_nozext:
+; CHECK-NEXT: .param     i32, i64, i64{{$}}
+; CHECK-NEXT: .result    i64{{$}}
+; SLOW-NEXT: i64.select $push0=, $1, $2, $0{{$}}
+; SLOW-NEXT: return     $pop0{{$}}
+define i64 @select_i64_bool_nozext(i1 %a, i64 %b, i64 %c) {
+  %cond = select i1 %a, i64 %b, i64 %c
+  ret i64 %cond
+}
+
 ; CHECK-LABEL: select_i64_eq:
 ; CHECK-NEXT: .param     i32, i64, i64{{$}}
 ; CHECK-NEXT: .result    i64{{$}}
 ; CHECK-NEXT: i64.select $push0=, $2, $1, $0{{$}}
 ; CHECK-NEXT: return     $pop0{{$}}
 define i64 @select_i64_eq(i32 %a, i64 %b, i64 %c) {
   %cmp = icmp eq i32 %a, 0
   %cond = select i1 %cmp, i64 %b, i64 %c

 ; CHECK-NEXT: .result    f32{{$}}
 ; CHECK-NEXT: f32.select $push0=, $1, $2, $0{{$}}
 ; CHECK-NEXT: return     $pop0{{$}}
 define float @select_f32_bool(i1 zeroext %a, float %b, float %c) {
   %cond = select i1 %a, float %b, float %c
   ret float %cond
 }
 
+; CHECK-LABEL: select_f32_bool_nozext:
+; CHECK-NEXT: .param     i32, f32, f32{{$}}
+; CHECK-NEXT: .result    f32{{$}}
+; SLOW-NEXT: f32.select $push0=, $1, $2, $0{{$}}
+; SLOW-NEXT: return     $pop0{{$}}
+define float @select_f32_bool_nozext(i1 %a, float %b, float %c) {
+  %cond = select i1 %a, float %b, float %c
+  ret float %cond
+}
+
 ; CHECK-LABEL: select_f32_eq:
 ; CHECK-NEXT: .param     i32, f32, f32{{$}}
 ; CHECK-NEXT: .result    f32{{$}}
 ; CHECK-NEXT: f32.select $push0=, $2, $1, $0{{$}}
 ; CHECK-NEXT: return     $pop0{{$}}
 define float @select_f32_eq(i32 %a, float %b, float %c) {
   %cmp = icmp eq i32 %a, 0
   %cond = select i1 %cmp, float %b, float %c

 ; CHECK-NEXT: .result    f64{{$}}
 ; CHECK-NEXT: f64.select $push0=, $1, $2, $0{{$}}
 ; CHECK-NEXT: return     $pop0{{$}}
 define double @select_f64_bool(i1 zeroext %a, double %b, double %c) {
   %cond = select i1 %a, double %b, double %c
   ret double %cond
 }
 
+; CHECK-LABEL: select_f64_bool_nozext:
+; CHECK-NEXT: .param     i32, f64, f64{{$}}
+; CHECK-NEXT: .result    f64{{$}}
+; SLOW-NEXT: f64.select $push0=, $1, $2, $0{{$}}
+; SLOW-NEXT: return     $pop0{{$}}
+define double @select_f64_bool_nozext(i1 %a, double %b, double %c) {
+  %cond = select i1 %a, double %b, double %c
+  ret double %cond
+}
+
 ; CHECK-LABEL: select_f64_eq:
 ; CHECK-NEXT: .param     i32, f64, f64{{$}}
 ; CHECK-NEXT: .result    f64{{$}}
 ; CHECK-NEXT: f64.select $push0=, $2, $1, $0{{$}}
 ; CHECK-NEXT: return     $pop0{{$}}
 define double @select_f64_eq(i32 %a, double %b, double %c) {
   %cmp = icmp eq i32 %a, 0
   %cond = select i1 %cmp, double %b, double %c