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Differential D53580

[AArch64] Refactor definition of EXT patterns to use a multiclass
ClosedPublic

Authored by john.brawn on Oct 23 2018, 8:27 AM.

Details

Reviewers
t.p.northover
olista01
dmgreen
SjoerdMeijer
Commits
rGb8e7887f3329: [AArch64] Refactor definition of EXT patterns to use a multiclass
rL345271: [AArch64] Refactor definition of EXT patterns to use a multiclass
Summary

Using a multiclass reduces duplication, and makes it easier to add new patterns later. This refactoring does add some new patterns, but as far as I can tell there's no IR that will end up triggering them so this is effectively NFC.

Diff Detail

Repository
rL LLVM

Event Timeline

john.brawn created this revision.Oct 23 2018, 8:27 AM
Herald added subscribers: kristof.beyls, javed.absar. · View Herald TranscriptOct 23 2018, 8:27 AM
john.brawn added a child revision: D53582: [AArch64] Add EXT patterns for 64-bit EXT of a subvector of a 128-bit vector.Oct 23 2018, 8:29 AM
dmgreen accepted this revision.Oct 25 2018, 4:19 AM

Nice cleanup. LGTM

This revision is now accepted and ready to land.Oct 25 2018, 4:19 AM
Closed by commit rL345271: [AArch64] Refactor definition of EXT patterns to use a multiclass (authored by john.brawn). · Explain WhyOct 25 2018, 8:03 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AArch64/
56 lines

Diff 171102

llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 4,179 Lines • ▼ Show 20 Linesdef : Pat<(concat_vectors (v2i32 V64:$Rd),
V128:$Rn, V128:$Rm)>; V128:$Rn, V128:$Rm)>;
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
// AdvSIMD bitwise extract from vector instruction. // AdvSIMD bitwise extract from vector instruction.
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
defm EXT : SIMDBitwiseExtract<"ext">; defm EXT : SIMDBitwiseExtract<"ext">;
def : Pat<(v4i16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))), multiclass ExtPat<ValueType VT64, ValueType VT128, int N> {
def : Pat<(VT64 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
(EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>; (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
def : Pat<(v8i16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))), def : Pat<(VT128 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
(EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>; (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
def : Pat<(v2i32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
(EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
def : Pat<(v2f32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
(EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
def : Pat<(v4i32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
(EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
def : Pat<(v4f32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
(EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
def : Pat<(v2i64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
(EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
def : Pat<(v2f64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
(EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
def : Pat<(v4f16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
(EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
def : Pat<(v8f16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
(EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
// We use EXT to handle extract_subvector to copy the upper 64-bits of a // We use EXT to handle extract_subvector to copy the upper 64-bits of a
// 128-bit vector. // 128-bit vector.
def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 8))), def : Pat<(VT64 (extract_subvector V128:$Rn, (i64 N))),
(EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 4))),
(EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 2))),
(EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 1))),
(EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
def : Pat<(v4f16 (extract_subvector V128:$Rn, (i64 4))),
(EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 2))),
(EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 1))),
(EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>; (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
}
defm : ExtPat<v8i8, v16i8, 8>;
defm : ExtPat<v4i16, v8i16, 4>;
defm : ExtPat<v4f16, v8f16, 4>;
defm : ExtPat<v2i32, v4i32, 2>;
defm : ExtPat<v2f32, v4f32, 2>;
defm : ExtPat<v1i64, v2i64, 1>;
defm : ExtPat<v1f64, v2f64, 1>;
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
// AdvSIMD zip vector // AdvSIMD zip vector
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
defm TRN1 : SIMDZipVector<0b010, "trn1", AArch64trn1>; defm TRN1 : SIMDZipVector<0b010, "trn1", AArch64trn1>;
defm TRN2 : SIMDZipVector<0b110, "trn2", AArch64trn2>; defm TRN2 : SIMDZipVector<0b110, "trn2", AArch64trn2>;
defm UZP1 : SIMDZipVector<0b001, "uzp1", AArch64uzp1>; defm UZP1 : SIMDZipVector<0b001, "uzp1", AArch64uzp1>;
▲ Show 20 Lines • Show All 2,458 Lines • Show Last 20 Lines