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[AArch64] Do 64-bit vector move of 0 and -1 by extracting from the 128-bit move
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Authored by john.brawn on Oct 23 2018, 8:22 AM.

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Summary

Currently a vector move of 0 or -1 will use different instructions depending on the size of the vector. Using a single instruction (the 128-bit one) for both gives more opportunity for Machine CSE to eliminate instructions.

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rL LLVM

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john.brawn created this revision.Oct 23 2018, 8:22 AM
dmgreen accepted this revision.Oct 25 2018, 4:19 AM

LGTM.

I was thinking about how this might affect other little cores like the A53/A55, especially around the dual issue on q registers. I don't think it will make much difference though, and the CSE benefits look like a bigger win.

This revision is now accepted and ready to land.Oct 25 2018, 4:19 AM
This revision was automatically updated to reflect the committed changes.