[ARM] Make InstrEmitter mark CPSR defs dead for Thumb1.

[efriedma]

Summary

The "dead" markings allow existing target-independent optimizations, like MachineSink, to trigger more frequently. The CPSR defs would have eventually been marked dead by LiveVariables, so this only affects optimizations before regalloc.

The ARMBaseInstrInfo.cpp is fixing a bug which is only visible with this change: the transform adds a use to an otherwise dead def of CPSR. This is covered by existing regression tests.

Saves roughly 0.1% codesize on a Thumb1 codebase I've been looking at.

Loosely depends on D53452; one regression test related to TBB formation breaks without that change.

[dmgreen]

Interesting. I didn't realise it worked like that. I had presumed that lot of passes would have to be taught about the optional defs, as opposed to them not being marked as dead correctly.

In my testing, the codesize is kind of up and down, looking a little bit up overall. It's roughly a wash, with one big increase in bzip for some reason.

But the performance looks like a big improvement. It fixes the regression we got from rL339472 and shows lots of other I'd previously attributed to D33935. To the extent that D33935 on top of this actually looks it hurts more than it helps. I'm not sure why yet, I would expect them to help each other out more than they hurt each other.

[dmgreen]

Anyway, this looks good to me.

If you want to take a look a bzip's decompress from csibe and figure out why that's increasing, it may help the codesize more, but that shouldn't block this with the other improvements it shows.

Perhaps leave for a day or two in case other people have comments.

llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp

for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {
           unsigned Reg = R->getReg();
           if (TargetRegisterInfo::isPhysicalRegister(Reg))
             UsedRegs.push_back(Reg);
         }
     }
   }
 
   // Finally mark unused registers as dead.
-  if (!UsedRegs.empty() || II.getImplicitDefs())
+  if (!UsedRegs.empty() || II.getImplicitDefs() || II.hasOptionalDef())
     MIB->setPhysRegsDeadExcept(UsedRegs, *TRI);
 
   // Run post-isel target hook to adjust this instruction if needed.
   if (II.hasPostISelHook())
     TLI->AdjustInstrPostInstrSelection(*MIB, Node);
 }
 
 /// EmitSpecialNode - Generate machine code for a target-independent node and

llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp

bool ARMBaseInstrInfo::optimizeCompareInstr(
   CmpInstr.eraseFromParent();
 
   // Modify the condition code of operands in OperandsToUpdate.
   // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
   // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
   for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++)
     OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second);
 
+  MI->clearRegisterDeads(ARM::CPSR);
+
   return true;
 }
 
 bool ARMBaseInstrInfo::shouldSink(const MachineInstr &MI) const {
   // Do not sink MI if it might be used to optimize a redundant compare.
   // We heuristically only look at the instruction immediately following MI to
   // avoid potentially searching the entire basic block.
   if (isPredicated(MI))

llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll

 ; ARM-NEXT:    subne r0, r0, #1
 ; ARM-NEXT:    mov pc, lr
 ;
 ; THUMB-LABEL: test_tst_assessment:
 ; THUMB:       @ %bb.0:
 ; THUMB-NEXT:    movs r2, r0
 ; THUMB-NEXT:    movs r0, #1
 ; THUMB-NEXT:    ands r0, r2
-; THUMB-NEXT:    subs r2, r0, #1
 ; THUMB-NEXT:    lsls r1, r1, #31
 ; THUMB-NEXT:    beq .LBB2_2
 ; THUMB-NEXT:  @ %bb.1:
-; THUMB-NEXT:    movs r0, r2
+; THUMB-NEXT:    subs r0, r0, #1
 ; THUMB-NEXT:  .LBB2_2:
 ; THUMB-NEXT:    bx lr
 ;
 ; T2-LABEL: test_tst_assessment:
 ; T2:       @ %bb.0:
 ; T2-NEXT:    lsls r1, r1, #31
 ; T2-NEXT:    and r0, r0, #1
 ; T2-NEXT:    it ne

llvm/trunk/test/CodeGen/ARM/cmn.ll

 ; T2-NEXT:    cmn.w r0, #78
 ; T2-NEXT:    it gt
 ; T2-NEXT:    movgt r1, #42
 ; T2-NEXT:    mov r0, r1
 ; T2-NEXT:    bx lr
 ;
 ; T1-LABEL: compare_i_gt:
 ; T1:       @ %bb.0: @ %entry
-; T1-NEXT:    mov r1, r0
-; T1-NEXT:    movs r0, #77
-; T1-NEXT:    mvns r3, r0
-; T1-NEXT:    movs r0, #42
-; T1-NEXT:    movs r2, #24
-; T1-NEXT:    cmp r1, r3
+; T1-NEXT:    movs r1, #77
+; T1-NEXT:    mvns r1, r1
+; T1-NEXT:    cmp r0, r1
 ; T1-NEXT:    bgt .LBB0_2
 ; T1-NEXT:  @ %bb.1: @ %entry
-; T1-NEXT:    mov r0, r2
-; T1-NEXT:  .LBB0_2: @ %entry
+; T1-NEXT:    movs r0, #24
+; T1-NEXT:    bx lr
+; T1-NEXT:  .LBB0_2:
+; T1-NEXT:    movs r0, #42
 ; T1-NEXT:    bx lr
 entry:
   %cmp = icmp sgt i32 %a, -78
   %ret = select i1 %cmp, i32 42, i32 24
   ret i32 %ret
 }
 
 define i32 @compare_r_eq(i32 %a, i32 %b) {
 ; T2-LABEL: compare_r_eq:
 ; T2:       @ %bb.0: @ %entry
 ; T2-NEXT:    movs r2, #24
 ; T2-NEXT:    cmn r0, r1
 ; T2-NEXT:    it eq
 ; T2-NEXT:    moveq r2, #42
 ; T2-NEXT:    mov r0, r2
 ; T2-NEXT:    bx lr
 ;
 ; T1-LABEL: compare_r_eq:
 ; T1:       @ %bb.0: @ %entry
-; T1-NEXT:    mov r2, r0
-; T1-NEXT:    movs r0, #42
-; T1-NEXT:    movs r3, #24
-; T1-NEXT:    cmn r2, r1
+; T1-NEXT:    cmn r0, r1
 ; T1-NEXT:    beq .LBB1_2
 ; T1-NEXT:  @ %bb.1: @ %entry
-; T1-NEXT:    mov r0, r3
-; T1-NEXT:  .LBB1_2: @ %entry
+; T1-NEXT:    movs r0, #24
+; T1-NEXT:    bx lr
+; T1-NEXT:  .LBB1_2:
+; T1-NEXT:    movs r0, #42
 ; T1-NEXT:    bx lr
 entry:
   %sub = sub nsw i32 0, %b
   %cmp = icmp eq i32 %a, %sub
   %ret = select i1 %cmp, i32 42, i32 24
   ret i32 %ret
 }

llvm/trunk/test/CodeGen/ARM/intrinsics-overflow.ll

define i32 @sadd_overflow(i32 %a, i32 %b) #0 {
 
   ; CHECK-LABEL: sadd_overflow:
 
   ; ARM: adds r[[R2:[0-9]+]], r[[R0:[0-9]+]], r[[R1:[0-9]+]]
   ; ARM: mov r[[R0]], #1
   ; ARM: movvc r[[R0]], #0
   ; ARM: mov pc, lr
 
-  ; THUMBV6: mov  r[[R2:[0-9]+]], r[[R0:[0-9]+]]
-  ; THUMBV6: adds r[[R3:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
-  ; THUMBV6: movs r[[R0]], #0
-  ; THUMBV6: movs r[[R1]], #1
-  ; THUMBV6: cmp  r[[R3]], r[[R2]]
-  ; THUMBV6: bvc  .L[[LABEL:.*]]
-  ; THUMBV6: mov  r[[R0]], r[[R1]]
-  ; THUMBV6: .L[[LABEL]]:
+  ; THUMBV6: adds    r1, r0, r1
+  ; THUMBV6: cmp     r1, r0
+  ; THUMBV6: bvc     .LBB1_2
 
   ; THUMBV7: adds  r[[R2:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
   ; THUMBV7: mov.w r[[R0:[0-9]+]], #1
   ; THUMBV7: it    vc
   ; THUMBV7: movvc r[[R0]], #0
 }
 
 define i32 @usub_overflow(i32 %a, i32 %b) #0 {
define i32 @ssub_overflow(i32 %a, i32 %b) #0 {
   ret i32 %2
 
   ; CHECK-LABEL: ssub_overflow:
 
   ; ARM: mov r[[R2]], #1
   ; ARM: cmp r[[R0]], r[[R1]]
   ; ARM: movvc r[[R2]], #0
 
-  ; THUMBV6: movs    r[[R0]], #0
-  ; THUMBV6: movs    r[[R3:[0-9]+]], #1
-  ; THUMBV6: cmp     r[[R2]], r[[R1:[0-9]+]]
-  ; THUMBV6: bvc     .L[[LABEL:.*]]
-  ; THUMBV6: mov     r[[R0]], r[[R3]]
-  ; THUMBV6: .L[[LABEL]]:
+  ; THUMBV6: cmp     r0, r1
+  ; THUMBV6: bvc     .LBB3_2
 
   ; THUMBV7: movs  r[[R2:[0-9]+]], #1
   ; THUMBV7: cmp   r[[R0:[0-9]+]], r[[R1:[0-9]+]]
   ; THUMBV7: it    vc
   ; THUMBV7: movvc r[[R2]], #0
   ; THUMBV7: mov   r[[R0]], r[[R2]]
 }
 
 declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32) #1
 declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32) #2
 declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32) #3
 declare { i32, i1 } @llvm.ssub.with.overflow.i32(i32, i32) #4

llvm/trunk/test/CodeGen/ARM/select-imm.ll

 ; ARM: orr [[R1b:r[0-9]+]], [[R1]], #256
 ; ARM: movgt {{r[0-1]}}, #123
 
 ; ARMT2-LABEL: t1:
 ; ARMT2: movw [[R:r[0-1]]], #357
 ; ARMT2: movwgt [[R]], #123
 
 ; THUMB1-LABEL: t1:
-; THUMB1: mov     r1, r0
-; THUMB1: movs    r2, #255
-; THUMB1: adds    r2, #102
-; THUMB1: movs    r0, #123
-; THUMB1: cmp     r1, #1
-; THUMB1: bgt
+; THUMB1: cmp     r0, #1
+; THUMB1: bgt     .LBB0_2
 
 ; THUMB2-LABEL: t1:
 ; THUMB2: movw [[R:r[0-1]]], #357
 ; THUMB2: movgt [[R]], #123
 
   %0 = icmp sgt i32 %c, 1
   %1 = select i1 %0, i32 123, i32 357
   ret i32 %1

 entry:
 ; ARM-LABEL: t6:
 ; ARM-NOT: mov
 ; ARM: cmp r0, #0
 ; ARM: movne r0, #1
 
 ; THUMB1-LABEL: t6:
 ; THUMB1: cmp r{{[0-9]+}}, #0
-; THUMB1: bne
+; THUMB1: beq
 
 ; THUMB2-LABEL: t6:
 ; THUMB2-NOT: mov
 ; THUMB2: cmp r0, #0
 ; THUMB2: it ne
 ; THUMB2: movne r0, #1
   %tobool = icmp ne i32 %a, 0
   %lnot.ext = zext i1 %tobool to i32

llvm/trunk/test/CodeGen/Thumb/branchless-cmp.ll

 ; FIXME: This one hasn't changed actually
 ; but could look like test3b
 define i32 @test4a(i32 %a, i32 %b) {
 entry:
   %cmp = icmp ne i32 %a, %b
   %cond = select i1 %cmp, i32 0, i32 4
   ret i32 %cond
 ; CHECK-LABEL: test4a:
-; CHECK-NOT: b{{(ne)|(eq)}}
-; CHECK:       mov     r2, r0
+; CHECK: bb.0:
+; CHECK-NEXT:  cmp     r0, r1
+; CHECK-NEXT:  bne     .LBB6_2
+; CHECK-NEXT: bb.1:
+; CHECK-NEXT:  movs    r0, #4
+; CHECK-NEXT:  bx      lr
+; CHECK-NEXT: .LBB6_2:
 ; CHECK-NEXT:  movs    r0, #0
-; CHECK-NEXT:  movs    r3, #4
-; CHECK-NEXT:  cmp     r2, r1
-; CHECK-NEXT:  bne     .[[BRANCH:[A-Z0-9_]+]]
-; CHECK:       mov     r0, r3
-; CHECK:       .[[BRANCH]]:
+; CHECK-NEXT:  bx      lr
 }
 
 define i32 @test4b(i32 %a, i32 %b) {
 entry:
   %cmp = icmp ne i32 %a, %b
   %cond = select i1 %cmp, i32 4, i32 0
   ret i32 %cond
 ; CHECK-LABEL: test4b:
 ; CHECK-NOT: b{{(ne)|(eq)}}
 ; CHECK:       subs  r0, r0, r1
 ; CHECK-NEXT:  subs  r1, r0, #1
 ; CHECK-NEXT:  sbcs  r0, r1
 ; CHECK-NEXT:  lsls  r0, r0, #2
 }

llvm/trunk/test/CodeGen/Thumb/consthoist-few-dependents.ll

 ; OPT: store i1 false
 ; OPT: bb3:
 ; OPT: store i1 false
 ; OPT: store i1 false
 ; OPT-NOT: add
 
 ; LLC-LABEL: avalon
 ; LLC-DAG: movs r{{[0-9]+}}, #0
-; LLC-DAG: movs r{{[0-9]+}}, #0
 ; LLC-DAG: movs r{{[0-9]+}}, #1
 ; LLC-NOT: add
 
 @global = local_unnamed_addr global i1 undef, align 1
 @global.0 = local_unnamed_addr global i1 undef, align 1
 
 define void @avalon() #0 {
 bb:

llvm/trunk/test/CodeGen/Thumb/select.ll

 ; CHECK-EABI: bhi
 
 define double @f7(double %a, double %b) {
     %tmp = fcmp olt double %a, 1.234e+00
     %tmp1 = select i1 %tmp, double -1.000e+00, double %b
     ret double %tmp1
 }
 ; CHECK-LABEL: f7:
-; CHECK: blt
+; CHECK: {{blt|bge}}
 ; CHECK: {{blt|bge}}
 ; CHECK: __ltdf2
 ; CHECK-EABI-LABEL: f7:
 ; CHECK-EABI: __aeabi_dcmplt
-; CHECK-EABI: bne
+; CHECK-EABI: {{bne|beq}}
 ; CHECK-EABI: {{bne|beq}}

llvm/trunk/test/CodeGen/Thumb/umulo-128-legalisation-lowering.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=thumb-eabi -mattr=+v6 | FileCheck %s --check-prefixes=THUMBV6
 
 define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
 ; THUMBV6-LABEL: muloti_test:
-; THUMBV6: push    {r4, r5, r6, r7, lr}
-; THUMBV6: sub     sp, #84
-; THUMBV6-NEXT: mov     r6, r3
-; THUMBV6-NEXT: mov     r7, r2
-; THUMBV6-NEXT: mov     r4, r0
-; THUMBV6-NEXT: movs    r5, #0
-; THUMBV6-NEXT: mov     r0, sp
-; THUMBV6-NEXT: str     r5, [r0, #12]
-; THUMBV6-NEXT: str     r5, [r0, #8]
-; THUMBV6-NEXT: ldr     r1, [sp, #116]
-; THUMBV6-NEXT: str     r1, [sp, #68]           @ 4-byte Spill
-; THUMBV6-NEXT: str     r1, [r0, #4]
-; THUMBV6-NEXT: ldr     r1, [sp, #112]
-; THUMBV6-NEXT: str     r1, [sp, #32]           @ 4-byte Spill
-; THUMBV6-NEXT: str     r1, [r0]
-; THUMBV6-NEXT: mov     r0, r2
-; THUMBV6-NEXT: mov     r1, r3
-; THUMBV6-NEXT: mov     r2, r5
-; THUMBV6-NEXT: mov     r3, r5
-; THUMBV6-NEXT: bl      __multi3
-; THUMBV6-NEXT: str     r2, [sp, #40]           @ 4-byte Spill
-; THUMBV6-NEXT: str     r3, [sp, #44]           @ 4-byte Spill
-; THUMBV6-NEXT: str     r4, [sp, #72]           @ 4-byte Spill
-; THUMBV6-NEXT: stm     r4!, {r0, r1}
-; THUMBV6-NEXT: ldr     r4, [sp, #120]
-; THUMBV6-NEXT: str     r6, [sp, #60]           @ 4-byte Spill
-; THUMBV6-NEXT: mov     r0, r6
-; THUMBV6-NEXT: mov     r1, r5
-; THUMBV6-NEXT: mov     r2, r4
-; THUMBV6-NEXT: mov     r3, r5
-; THUMBV6-NEXT: bl      __aeabi_lmul
-; THUMBV6-NEXT: mov     r6, r0
-; THUMBV6-NEXT: str     r1, [sp, #52]           @ 4-byte Spill
-; THUMBV6-NEXT: ldr     r0, [sp, #124]
-; THUMBV6-NEXT: str     r0, [sp, #80]           @ 4-byte Spill
-; THUMBV6-NEXT: mov     r1, r5
-; THUMBV6-NEXT: mov     r2, r7
-; THUMBV6-NEXT: mov     r3, r5
-; THUMBV6-NEXT: bl      __aeabi_lmul
-; THUMBV6-NEXT: str     r1, [sp, #28]           @ 4-byte Spill
-; THUMBV6-NEXT: adds    r6, r0, r6
-; THUMBV6-NEXT: str     r4, [sp, #64]           @ 4-byte Spill
-; THUMBV6-NEXT: mov     r0, r4
-; THUMBV6-NEXT: mov     r1, r5
-; THUMBV6-NEXT: mov     r2, r7
-; THUMBV6-NEXT: mov     r3, r5
-; THUMBV6-NEXT: bl      __aeabi_lmul
-; THUMBV6-NEXT: str     r0, [sp, #24]           @ 4-byte Spill
-; THUMBV6-NEXT: adds    r0, r1, r6
-; THUMBV6-NEXT: str     r0, [sp, #20]           @ 4-byte Spill
-; THUMBV6-NEXT: mov     r0, r5
-; THUMBV6-NEXT: adcs    r0, r5
-; THUMBV6-NEXT: str     r0, [sp, #48]           @ 4-byte Spill
-; THUMBV6-NEXT: ldr     r7, [sp, #104]
-; THUMBV6-NEXT: ldr     r0, [sp, #68]           @ 4-byte Reload
-; THUMBV6-NEXT: mov     r1, r5
-; THUMBV6-NEXT: mov     r2, r7
-; THUMBV6-NEXT: mov     r3, r5
-; THUMBV6-NEXT: bl      __aeabi_lmul
-; THUMBV6-NEXT: mov     r6, r0
-; THUMBV6-NEXT: str     r1, [sp, #56]           @ 4-byte Spill
-; THUMBV6-NEXT: ldr     r0, [sp, #108]
-; THUMBV6-NEXT: str     r0, [sp, #76]           @ 4-byte Spill
-; THUMBV6-NEXT: mov     r1, r5
-; THUMBV6-NEXT: ldr     r4, [sp, #32]           @ 4-byte Reload
-; THUMBV6-NEXT: mov     r2, r4
-; THUMBV6-NEXT: mov     r3, r5
-; THUMBV6-NEXT: bl      __aeabi_lmul
-; THUMBV6-NEXT: str     r1, [sp, #36]           @ 4-byte Spill
-; THUMBV6-NEXT: adds    r6, r0, r6
-; THUMBV6-NEXT: mov     r0, r7
-; THUMBV6-NEXT: mov     r1, r5
-; THUMBV6-NEXT: mov     r2, r4
-; THUMBV6-NEXT: mov     r3, r5
-; THUMBV6-NEXT: bl      __aeabi_lmul
-; THUMBV6-NEXT: adds    r2, r1, r6
-; THUMBV6-NEXT: mov     r1, r5
-; THUMBV6-NEXT: adcs    r1, r5
-; THUMBV6-NEXT: ldr     r3, [sp, #24]           @ 4-byte Reload
-; THUMBV6-NEXT: adds    r0, r0, r3
-; THUMBV6-NEXT: ldr     r3, [sp, #20]           @ 4-byte Reload
-; THUMBV6-NEXT: adcs    r2, r3
-; THUMBV6-NEXT: ldr     r3, [sp, #40]           @ 4-byte Reload
-; THUMBV6-NEXT: adds    r0, r3, r0
-; THUMBV6-NEXT: ldr     r3, [sp, #72]           @ 4-byte Reload
-; THUMBV6-NEXT: str     r0, [r3, #8]
-; THUMBV6-NEXT: ldr     r0, [sp, #44]           @ 4-byte Reload
-; THUMBV6-NEXT: adcs    r2, r0
-; THUMBV6-NEXT: str     r2, [r3, #12]
-; THUMBV6-NEXT: ldr     r2, [sp, #28]           @ 4-byte Reload
-; THUMBV6-NEXT: adcs    r5, r5
-; THUMBV6-NEXT: movs    r0, #1
-; THUMBV6-NEXT: cmp     r2, #0
-; THUMBV6-NEXT: mov     r3, r0
-; THUMBV6-NEXT: bne     .LBB0_2
-; THUMBV6: mov     r3, r2
-; THUMBV6: ldr     r2, [sp, #60]           @ 4-byte Reload
-; THUMBV6-NEXT: cmp     r2, #0
-; THUMBV6-NEXT: mov     r4, r0
-; THUMBV6-NEXT: bne     .LBB0_4
-; THUMBV6: mov     r4, r2
-; THUMBV6: ldr     r2, [sp, #80]           @ 4-byte Reload
-; THUMBV6-NEXT: cmp     r2, #0
-; THUMBV6-NEXT: mov     r2, r0
-; THUMBV6-NEXT: bne     .LBB0_6
-; THUMBV6: ldr     r2, [sp, #80]           @ 4-byte Reload
-; THUMBV6: ands    r2, r4
-; THUMBV6-NEXT: orrs    r2, r3
-; THUMBV6-NEXT: ldr     r4, [sp, #52]           @ 4-byte Reload
-; THUMBV6-NEXT: cmp     r4, #0
-; THUMBV6-NEXT: mov     r3, r0
-; THUMBV6-NEXT: bne     .LBB0_8
-; THUMBV6: mov     r3, r4
-; THUMBV6: orrs    r2, r3
-; THUMBV6-NEXT: ldr     r3, [sp, #48]           @ 4-byte Reload
-; THUMBV6-NEXT: orrs    r2, r3
-; THUMBV6-NEXT: ldr     r3, [sp, #36]           @ 4-byte Reload
-; THUMBV6-NEXT: cmp     r3, #0
-; THUMBV6-NEXT: mov     r4, r0
-; THUMBV6-NEXT: bne     .LBB0_10
-; THUMBV6: mov     r4, r3
-; THUMBV6: ldr     r3, [sp, #68]           @ 4-byte Reload
-; THUMBV6-NEXT: cmp     r3, #0
-; THUMBV6-NEXT: mov     r6, r0
-; THUMBV6-NEXT: bne     .LBB0_12
-; THUMBV6: mov     r6, r3
-; THUMBV6: ldr     r3, [sp, #76]           @ 4-byte Reload
-; THUMBV6-NEXT: cmp     r3, #0
-; THUMBV6-NEXT: mov     r3, r0
-; THUMBV6-NEXT: bne     .LBB0_14
-; THUMBV6: ldr     r3, [sp, #76]           @ 4-byte Reload
-; THUMBV6: ands    r3, r6
-; THUMBV6-NEXT: orrs    r3, r4
-; THUMBV6-NEXT: ldr     r6, [sp, #56]           @ 4-byte Reload
-; THUMBV6-NEXT: cmp     r6, #0
-; THUMBV6-NEXT: mov     r4, r0
-; THUMBV6-NEXT: bne     .LBB0_16
-; THUMBV6: mov     r4, r6
-; THUMBV6: orrs    r3, r4
-; THUMBV6-NEXT: orrs    r3, r1
-; THUMBV6-NEXT: ldr     r4, [sp, #64]           @ 4-byte Reload
-; THUMBV6-NEXT: ldr     r1, [sp, #80]           @ 4-byte Reload
-; THUMBV6-NEXT: orrs    r4, r1
-; THUMBV6-NEXT: cmp     r4, #0
-; THUMBV6-NEXT: mov     r1, r0
-; THUMBV6-NEXT: bne     .LBB0_18
-; THUMBV6: mov     r1, r4
-; THUMBV6: ldr     r4, [sp, #76]           @ 4-byte Reload
-; THUMBV6-NEXT: orrs    r7, r4
-; THUMBV6-NEXT: cmp     r7, #0
-; THUMBV6-NEXT: mov     r4, r0
-; THUMBV6-NEXT: bne     .LBB0_20
-; THUMBV6: mov     r4, r7
-; THUMBV6: ands    r4, r1
-; THUMBV6-NEXT: orrs    r4, r3
-; THUMBV6-NEXT: orrs    r4, r2
-; THUMBV6-NEXT: orrs    r4, r5
-; THUMBV6-NEXT: ands    r4, r0
-; THUMBV6-NEXT: ldr     r0, [sp, #72]           @ 4-byte Reload
-; THUMBV6-NEXT: strb    r4, [r0, #16]
-; THUMBV6-NEXT: add     sp, #84
-; THUMBV6-NEXT: pop     {r4, r5, r6, r7, pc}
+; THUMBV6:       @ %bb.0: @ %start
+; THUMBV6-NEXT:    .save {r4, r5, r6, r7, lr}
+; THUMBV6-NEXT:    push {r4, r5, r6, r7, lr}
+; THUMBV6-NEXT:    .pad #84
+; THUMBV6-NEXT:    sub sp, #84
+; THUMBV6-NEXT:    mov r6, r3
+; THUMBV6-NEXT:    mov r7, r2
+; THUMBV6-NEXT:    mov r4, r0
+; THUMBV6-NEXT:    movs r5, #0
+; THUMBV6-NEXT:    mov r0, sp
+; THUMBV6-NEXT:    str r5, [r0, #12]
+; THUMBV6-NEXT:    str r5, [r0, #8]
+; THUMBV6-NEXT:    ldr r1, [sp, #116]
+; THUMBV6-NEXT:    str r1, [sp, #72] @ 4-byte Spill
+; THUMBV6-NEXT:    str r1, [r0, #4]
+; THUMBV6-NEXT:    ldr r1, [sp, #112]
+; THUMBV6-NEXT:    str r1, [sp, #44] @ 4-byte Spill
+; THUMBV6-NEXT:    str r1, [r0]
+; THUMBV6-NEXT:    mov r0, r2
+; THUMBV6-NEXT:    mov r1, r3
+; THUMBV6-NEXT:    mov r2, r5
+; THUMBV6-NEXT:    mov r3, r5
+; THUMBV6-NEXT:    bl __multi3
+; THUMBV6-NEXT:    str r2, [sp, #36] @ 4-byte Spill
+; THUMBV6-NEXT:    str r3, [sp, #40] @ 4-byte Spill
+; THUMBV6-NEXT:    str r4, [sp, #76] @ 4-byte Spill
+; THUMBV6-NEXT:    stm r4!, {r0, r1}
+; THUMBV6-NEXT:    ldr r4, [sp, #120]
+; THUMBV6-NEXT:    str r6, [sp, #56] @ 4-byte Spill
+; THUMBV6-NEXT:    mov r0, r6
+; THUMBV6-NEXT:    mov r1, r5
+; THUMBV6-NEXT:    mov r2, r4
+; THUMBV6-NEXT:    mov r3, r5
+; THUMBV6-NEXT:    bl __aeabi_lmul
+; THUMBV6-NEXT:    mov r6, r0
+; THUMBV6-NEXT:    str r1, [sp, #48] @ 4-byte Spill
+; THUMBV6-NEXT:    ldr r0, [sp, #124]
+; THUMBV6-NEXT:    str r0, [sp, #80] @ 4-byte Spill
+; THUMBV6-NEXT:    mov r1, r5
+; THUMBV6-NEXT:    mov r2, r7
+; THUMBV6-NEXT:    mov r3, r5
+; THUMBV6-NEXT:    bl __aeabi_lmul
+; THUMBV6-NEXT:    str r1, [sp, #28] @ 4-byte Spill
+; THUMBV6-NEXT:    adds r6, r0, r6
+; THUMBV6-NEXT:    str r4, [sp, #68] @ 4-byte Spill
+; THUMBV6-NEXT:    mov r0, r4
+; THUMBV6-NEXT:    mov r1, r5
+; THUMBV6-NEXT:    mov r2, r7
+; THUMBV6-NEXT:    mov r3, r5
+; THUMBV6-NEXT:    bl __aeabi_lmul
+; THUMBV6-NEXT:    str r0, [sp, #20] @ 4-byte Spill
+; THUMBV6-NEXT:    adds r0, r1, r6
+; THUMBV6-NEXT:    str r0, [sp, #16] @ 4-byte Spill
+; THUMBV6-NEXT:    mov r0, r5
+; THUMBV6-NEXT:    adcs r0, r5
+; THUMBV6-NEXT:    str r0, [sp, #64] @ 4-byte Spill
+; THUMBV6-NEXT:    ldr r7, [sp, #104]
+; THUMBV6-NEXT:    ldr r0, [sp, #72] @ 4-byte Reload
+; THUMBV6-NEXT:    mov r1, r5
+; THUMBV6-NEXT:    mov r2, r7
+; THUMBV6-NEXT:    mov r3, r5
+; THUMBV6-NEXT:    bl __aeabi_lmul
+; THUMBV6-NEXT:    mov r6, r0
+; THUMBV6-NEXT:    str r1, [sp, #52] @ 4-byte Spill
+; THUMBV6-NEXT:    ldr r0, [sp, #108]
+; THUMBV6-NEXT:    str r0, [sp, #60] @ 4-byte Spill
+; THUMBV6-NEXT:    mov r1, r5
+; THUMBV6-NEXT:    ldr r4, [sp, #44] @ 4-byte Reload
+; THUMBV6-NEXT:    mov r2, r4
+; THUMBV6-NEXT:    mov r3, r5
+; THUMBV6-NEXT:    bl __aeabi_lmul
+; THUMBV6-NEXT:    str r1, [sp, #32] @ 4-byte Spill
+; THUMBV6-NEXT:    adds r6, r0, r6
+; THUMBV6-NEXT:    str r7, [sp, #24] @ 4-byte Spill
+; THUMBV6-NEXT:    mov r0, r7
+; THUMBV6-NEXT:    mov r1, r5
+; THUMBV6-NEXT:    mov r2, r4
+; THUMBV6-NEXT:    mov r3, r5
+; THUMBV6-NEXT:    bl __aeabi_lmul
+; THUMBV6-NEXT:    adds r1, r1, r6
+; THUMBV6-NEXT:    mov r2, r5
+; THUMBV6-NEXT:    adcs r2, r5
+; THUMBV6-NEXT:    str r2, [sp, #44] @ 4-byte Spill
+; THUMBV6-NEXT:    ldr r2, [sp, #20] @ 4-byte Reload
+; THUMBV6-NEXT:    adds r0, r0, r2
+; THUMBV6-NEXT:    ldr r2, [sp, #16] @ 4-byte Reload
+; THUMBV6-NEXT:    adcs r1, r2
+; THUMBV6-NEXT:    ldr r2, [sp, #36] @ 4-byte Reload
+; THUMBV6-NEXT:    adds r0, r2, r0
+; THUMBV6-NEXT:    ldr r2, [sp, #76] @ 4-byte Reload
+; THUMBV6-NEXT:    str r0, [r2, #8]
+; THUMBV6-NEXT:    ldr r0, [sp, #40] @ 4-byte Reload
+; THUMBV6-NEXT:    adcs r1, r0
+; THUMBV6-NEXT:    str r1, [r2, #12]
+; THUMBV6-NEXT:    ldr r1, [sp, #28] @ 4-byte Reload
+; THUMBV6-NEXT:    adcs r5, r5
+; THUMBV6-NEXT:    movs r0, #1
+; THUMBV6-NEXT:    cmp r1, #0
+; THUMBV6-NEXT:    mov r2, r0
+; THUMBV6-NEXT:    bne .LBB0_2
+; THUMBV6-NEXT:  @ %bb.1: @ %start
+; THUMBV6-NEXT:    mov r2, r1
+; THUMBV6-NEXT:  .LBB0_2: @ %start
+; THUMBV6-NEXT:    str r2, [sp, #40] @ 4-byte Spill
+; THUMBV6-NEXT:    ldr r1, [sp, #56] @ 4-byte Reload
+; THUMBV6-NEXT:    cmp r1, #0
+; THUMBV6-NEXT:    mov r4, r0
+; THUMBV6-NEXT:    bne .LBB0_4
+; THUMBV6-NEXT:  @ %bb.3: @ %start
+; THUMBV6-NEXT:    mov r4, r1
+; THUMBV6-NEXT:  .LBB0_4: @ %start
+; THUMBV6-NEXT:    ldr r1, [sp, #80] @ 4-byte Reload
+; THUMBV6-NEXT:    cmp r1, #0
+; THUMBV6-NEXT:    mov r2, r0
+; THUMBV6-NEXT:    ldr r3, [sp, #48] @ 4-byte Reload
+; THUMBV6-NEXT:    ldr r6, [sp, #32] @ 4-byte Reload
+; THUMBV6-NEXT:    bne .LBB0_6
+; THUMBV6-NEXT:  @ %bb.5: @ %start
+; THUMBV6-NEXT:    ldr r2, [sp, #80] @ 4-byte Reload
+; THUMBV6-NEXT:  .LBB0_6: @ %start
+; THUMBV6-NEXT:    cmp r3, #0
+; THUMBV6-NEXT:    mov r7, r0
+; THUMBV6-NEXT:    ldr r1, [sp, #72] @ 4-byte Reload
+; THUMBV6-NEXT:    bne .LBB0_8
+; THUMBV6-NEXT:  @ %bb.7: @ %start
+; THUMBV6-NEXT:    mov r7, r3
+; THUMBV6-NEXT:  .LBB0_8: @ %start
+; THUMBV6-NEXT:    cmp r6, #0
+; THUMBV6-NEXT:    mov r3, r0
+; THUMBV6-NEXT:    bne .LBB0_10
+; THUMBV6-NEXT:  @ %bb.9: @ %start
+; THUMBV6-NEXT:    mov r3, r6
+; THUMBV6-NEXT:  .LBB0_10: @ %start
+; THUMBV6-NEXT:    cmp r1, #0
+; THUMBV6-NEXT:    mov r6, r1
+; THUMBV6-NEXT:    mov r1, r0
+; THUMBV6-NEXT:    bne .LBB0_12
+; THUMBV6-NEXT:  @ %bb.11: @ %start
+; THUMBV6-NEXT:    mov r1, r6
+; THUMBV6-NEXT:  .LBB0_12: @ %start
+; THUMBV6-NEXT:    str r7, [sp, #72] @ 4-byte Spill
+; THUMBV6-NEXT:    ands r2, r4
+; THUMBV6-NEXT:    ldr r6, [sp, #60] @ 4-byte Reload
+; THUMBV6-NEXT:    cmp r6, #0
+; THUMBV6-NEXT:    mov r4, r0
+; THUMBV6-NEXT:    bne .LBB0_14
+; THUMBV6-NEXT:  @ %bb.13: @ %start
+; THUMBV6-NEXT:    mov r4, r6
+; THUMBV6-NEXT:  .LBB0_14: @ %start
+; THUMBV6-NEXT:    ldr r7, [sp, #40] @ 4-byte Reload
+; THUMBV6-NEXT:    orrs r2, r7
+; THUMBV6-NEXT:    ands r4, r1
+; THUMBV6-NEXT:    orrs r4, r3
+; THUMBV6-NEXT:    ldr r3, [sp, #52] @ 4-byte Reload
+; THUMBV6-NEXT:    cmp r3, #0
+; THUMBV6-NEXT:    mov r1, r0
+; THUMBV6-NEXT:    bne .LBB0_16
+; THUMBV6-NEXT:  @ %bb.15: @ %start
+; THUMBV6-NEXT:    mov r1, r3
+; THUMBV6-NEXT:  .LBB0_16: @ %start
+; THUMBV6-NEXT:    ldr r3, [sp, #72] @ 4-byte Reload
+; THUMBV6-NEXT:    orrs r2, r3
+; THUMBV6-NEXT:    orrs r4, r1
+; THUMBV6-NEXT:    ldr r1, [sp, #68] @ 4-byte Reload
+; THUMBV6-NEXT:    ldr r3, [sp, #80] @ 4-byte Reload
+; THUMBV6-NEXT:    orrs r1, r3
+; THUMBV6-NEXT:    cmp r1, #0
+; THUMBV6-NEXT:    mov r3, r0
+; THUMBV6-NEXT:    bne .LBB0_18
+; THUMBV6-NEXT:  @ %bb.17: @ %start
+; THUMBV6-NEXT:    mov r3, r1
+; THUMBV6-NEXT:  .LBB0_18: @ %start
+; THUMBV6-NEXT:    ldr r1, [sp, #64] @ 4-byte Reload
+; THUMBV6-NEXT:    orrs r2, r1
+; THUMBV6-NEXT:    ldr r1, [sp, #44] @ 4-byte Reload
+; THUMBV6-NEXT:    orrs r4, r1
+; THUMBV6-NEXT:    ldr r1, [sp, #24] @ 4-byte Reload
+; THUMBV6-NEXT:    orrs r1, r6
+; THUMBV6-NEXT:    mov r6, r1
+; THUMBV6-NEXT:    cmp r1, #0
+; THUMBV6-NEXT:    mov r1, r0
+; THUMBV6-NEXT:    bne .LBB0_20
+; THUMBV6-NEXT:  @ %bb.19: @ %start
+; THUMBV6-NEXT:    mov r1, r6
+; THUMBV6-NEXT:  .LBB0_20: @ %start
+; THUMBV6-NEXT:    ands r1, r3
+; THUMBV6-NEXT:    orrs r1, r4
+; THUMBV6-NEXT:    orrs r1, r2
+; THUMBV6-NEXT:    orrs r1, r5
+; THUMBV6-NEXT:    ands r1, r0
+; THUMBV6-NEXT:    ldr r0, [sp, #76] @ 4-byte Reload
+; THUMBV6-NEXT:    strb r1, [r0, #16]
+; THUMBV6-NEXT:    add sp, #84
+; THUMBV6-NEXT:    pop {r4, r5, r6, r7, pc}
 start:
   %0 = tail call { i128, i1 } @llvm.umul.with.overflow.i128(i128 %l, i128 %r) #2
   %1 = extractvalue { i128, i1 } %0, 0
   %2 = extractvalue { i128, i1 } %0, 1
   %3 = zext i1 %2 to i8
   %4 = insertvalue { i128, i8 } undef, i128 %1, 0
   %5 = insertvalue { i128, i8 } %4, i8 %3, 1
   ret { i128, i8 } %5
 }
 
 ; Function Attrs: nounwind readnone speculatable
 declare { i128, i1 } @llvm.umul.with.overflow.i128(i128, i128) #1
 
 attributes #0 = { nounwind readnone uwtable }
 attributes #1 = { nounwind readnone speculatable }
 attributes #2 = { nounwind }

llvm/trunk/test/CodeGen/Thumb2/thumb2-tbh.ll

 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic | FileCheck %s --check-prefix=CHECK --check-prefix=T2
-; RUN: llc < %s -mtriple=thumbv6m-apple-darwin -relocation-model=pic | FileCheck %s --check-prefix=CHECK --check-prefix=T1
-; RUN: llc < %s -mtriple=thumbv6m-apple-darwin -relocation-model=static | FileCheck %s --check-prefix=CHECK --check-prefix=T1
+; RUN: llc < %s -mtriple=thumbv6m-apple-darwin -relocation-model=pic | FileCheck %s --check-prefix=T1DISABLED
+; FIXME: llc < %s -mtriple=thumbv6m-apple-darwin -relocation-model=pic | FileCheck %s --check-prefix=CHECK --check-prefix=T1
+; FIXME: llc < %s -mtriple=thumbv6m-apple-darwin -relocation-model=static | FileCheck %s --check-prefix=CHECK --check-prefix=T1
+
+; FIXME: Thumb1 tests temporarily disabled; MachineLICM is now hoisting the
+; subs, so the jump table can't be formed.
+; T1DISABLED: .data_region jt32
 
 ; Thumb2 target should reorder the bb's in order to use tbb / tbh.
 
   %struct.R_flstr = type { i32, i32, i8* }
   %struct._T_tstr = type { i32, %struct.R_flstr*, %struct._T_tstr* }
 @_C_nextcmd = external global i32   ; <i32*> [#uses=3]
 @.str31 = external constant [28 x i8], align 1    ; <[28 x i8]*> [#uses=1]
 @_T_gtol = external global %struct._T_tstr*   ; <%struct._T_tstr**> [#uses=2]