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Differential D53383

[PowerPC] Make no-PIC default to match GCC - LLVM
ClosedPublic

Authored by stefanp on Oct 17 2018, 12:36 PM.

Details

Reviewers
nemanjai
kbarton
sfertile
lei
syzaara
hfinkel
joerg
Commits
rG46f840f28678: [PowerPC] Make no-PIC default to match GCC - LLVM
rG046eff502f3b: [PowerPC] Make no-PIC default to match GCC - LLVM
rL348298: [PowerPC] Make no-PIC default to match GCC - LLVM
rL347069: [PowerPC] Make no-PIC default to match GCC - LLVM
Summary

Ran a quick test and determined that for GCC the default option is -fno-PIC for both ELFv1 and ELFv2. We are currently using -fPIC as the default for LLVM.
Would like to revert to what GCC is doing on PowerPC.

NOTE: This patch does not yet include test case updates. Currently working on those updates and will further update this patch at that time. In the meantime I put up this patch to make sure that this is in fact what we want to do.

Diff Detail

Repository
rL LLVM

Event Timeline

stefanp created this revision.Oct 17 2018, 12:36 PM
Herald added a subscriber: jsji. · View Herald TranscriptOct 17 2018, 12:36 PM
stefanp added a child revision: D53384: [PowerPC] Make no-PIC default to match GCC - CLANG.Oct 17 2018, 12:39 PM
stefanp updated this revision to Diff 170401.Oct 22 2018, 6:32 AM

Updated test cases.

stefanp updated this revision to Diff 170927.Oct 24 2018, 10:13 AM

Default on all Power PC platforms is now no-PIC.
If any bugs are exposed by this change we will fix them as they are exposed.

jsji added a comment.EditedOct 24 2018, 11:42 AM

I am seeing two choices in the testcases you updated: one is adding -relocation-model=pic, the other is to update code sequeces.
What is your general rules to choose which one to do?

For those testcase updated with "-relocation-model=pic," do we know what might happen if default is no-PIC?

I am asking because it looks like the choice is kind of random (?).
Some may need more careful thoughts?

eg: maybe we should also check what happens with xray-tail-call-sled.ll for the new default? and how about fast-isel-call.ll, toc-float.ll etc?

stefanp added a comment.Oct 24 2018, 1:24 PM

Generally the way I decided on how to update the test depended on a couple of things:

  1. If the test had this line: ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py it means that we had an auto generate test and if I felt that the test had nothing really to do with PIC or no-PIC I would just regenerate it. For example a number of tests just had addis ld differences.
  2. If the test was not auto generated but it still had nothing to do with PIC / no-PIC I would just add -relocation-model=pic. Changing these tests would not get us very much and it would be a significant amount of work.
  3. For tests that had something to do with PIC / no-PIC I tried to make a judgement call as to what would be more useful to keep (the PIC test or the non-PIC test). If you feel that some of these tests I should have been the other way around let me know. I know you mentioned a couple in your comment and I'll take a look at those.

The reason why it may look a little random is because of all of the testCompare* tests. I don't know why but it seems that some of those tests were auto-generated and some were not but they all have nothing to do with PIC.

joerg added a comment.Oct 24 2018, 1:35 PM

To summarize the discussion on IRC, from my perspective this change is wrong. PPC as architecture is strongly geared towards PIC code. We used to create quite bad position dependent code and I generally don't see the advantage. I can understand wanting to default to PIE (i.e. position independent code with main binary assumption as far as interception is considered). In other words, the middle end generally tended to create better results for position independent codegen. The default behavior of GCC is ephemeral here, IMO.

jedilyn added a subscriber: jedilyn.Oct 25 2018, 12:08 AM
In D53383#1274877, @joerg wrote:

PPC as architecture is strongly geared towards PIC code"

Really some truth, as I know, AIX 64bit mode only supports PIC.

stefanp added a comment.Oct 25 2018, 1:05 PM

@joerg
When you say that we produce quite bad position dependent code do you mean in terms of performance or in terms of correctness? At this point I have not seen any issues with the no-PIC code. If you have an example of this bad code please share the test case.
Also, changing the default option to no-PIC does not mean that everything we do will become no-PIC. For example, the way that the TOC is handled on PPC remains position independent. However, going from PIC to no-PIC does offer a number of opportunities (for example in in-lining).
With respect to PIE I'm not sure what the difference is between PIE and static relocation models in terms of code generation. Is there any reason why you would prefer PIE in this case? Do you have an example that shows it to be better than say no-PIC?

@jedilyn
You are correct that PIC is the only model on AIX. However, the object model (COFF) on AIX is different so the idea of PIC / no-PIC does not mean the same thing it does on Linux anyway. Also AIX is currently not supported for LLVM. If we decide to support it we can look at the options then. However, since AIX only uses one object model and there is no PIC/ no-PIC difference we will probably just end up ignoring the option anyway.

jedilyn added a comment.Oct 25 2018, 8:20 PM
In D53383#1276421, @stefanp wrote:

@jedilyn
You are correct that PIC is the only model on AIX. However, the object model (COFF) on AIX is different so the idea of PIC / no-PIC does not mean the same thing it does on Linux anyway. Also AIX is currently not supported for LLVM. If we decide to support it we can look at the options then. However, since AIX only uses one object model and there is no PIC/ no-PIC difference we will probably just end up ignoring the option anyway.

Thanks for clarification Stefan, it's a good idea just to ignore the PIC option on aix when it gets supported in future.

sfertile accepted this revision.Nov 13 2018, 1:10 PM

I definitely agree we need to fix the PIC by default behavior, PIC implies we need to produce code suitable for a shared object and that has a number of unneeded limitations. I tried to figure out what we are doing differently between pie and static relocation models but don't see much difference.
For the most part we happen to do the same thing, for example the default isOffsetFoldingLegal depends on position-dependence but the PPCTargetLowering overrides it to always return false, we always produce relative jump-tables for ppc64 regardless of the relocation mode, we always use TOC-pointer relative addressing for module local symbols regardles of relocation model . The one difference I did find is TargetLoweringObjectFile::getKindForGlobal although that line looks wrong to me. Static binaries can still link against shared objects. Globals/functions defined in those will not have their addresses resolved at link time, unless maybe this is only a problem on ppc since we don't use copy relocs? (I believe the original PIC by default change was motivated by this but without a clear example I'm not sure why ...). I don't like using the fact there is (or was) bad codegen for the static relocation model as reasoning for picking pie as the default, that bad codegen comes back if the user adds -fno-pie as an option.

I think using static relocation model is the right approach here. I don't think we should deviate from the same default xlc and gcc uses without strong benefit to motivate the difference, and an understanding that the option difference will not impact compatibility.

LGTM

This revision is now accepted and ready to land.Nov 13 2018, 1:10 PM
Closed by commit rL347069: [PowerPC] Make no-PIC default to match GCC - LLVM (authored by stefanp). · Explain WhyNov 16 2018, 10:39 AM
This revision was automatically updated to reflect the committed changes.
stefanp reopened this revision.Nov 16 2018, 12:44 PM
This revision is now accepted and ready to land.Nov 16 2018, 12:44 PM
stefanp updated this revision to Diff 175299.Nov 26 2018, 11:08 AM

Patch is now only for Little Endian.
Big Endian will remain PIC by default as it was before. This is due to a bug found on BE where -fsanitize=leak is not detecting leaks correctly. As Little Endian is a higher priority we will add that code first and then look at the BE issue at a later date.

Closed by commit rL348298: [PowerPC] Make no-PIC default to match GCC - LLVM (authored by stefanp). · Explain WhyDec 4 2018, 12:18 PM
This revision was automatically updated to reflect the committed changes.

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Diff 176688

llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp

Show First 20 Lines • Show All 208 Lines • ▼ Show 20 Linesstatic Reloc::Model getEffectiveRelocModel(const Triple &TT,
Optional<Reloc::Model> RM) { Optional<Reloc::Model> RM) {
if (RM.hasValue()) if (RM.hasValue())
return *RM; return *RM;
// Darwin defaults to dynamic-no-pic. // Darwin defaults to dynamic-no-pic.
if (TT.isOSDarwin()) if (TT.isOSDarwin())
return Reloc::DynamicNoPIC; return Reloc::DynamicNoPIC;
// Non-darwin 64-bit platforms are PIC by default. // Big Endian PPC is PIC by default.
if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) if (TT.getArch() == Triple::ppc64)
return Reloc::PIC_; return Reloc::PIC_;
// 32-bit is static by default. // Rest are static by default.
return Reloc::Static; return Reloc::Static;
} }
static CodeModel::Model getEffectiveCodeModel(const Triple &TT, static CodeModel::Model getEffectiveCodeModel(const Triple &TT,
Optional<CodeModel::Model> CM, Optional<CodeModel::Model> CM,
bool JIT) { bool JIT) {
if (CM) if (CM)
return *CM; return *CM;
▲ Show 20 Lines • Show All 237 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
; The instructions addis,addi, bl are used to calculate the address of TLS ; The instructions addis,addi, bl are used to calculate the address of TLS
; thread local variables. These TLS access code sequences are generated ; thread local variables. These TLS access code sequences are generated
; repeatedly every time the thread local variable is accessed. By communicating ; repeatedly every time the thread local variable is accessed. By communicating
; to Machine CSE that X2 is guaranteed to have the same value within the same ; to Machine CSE that X2 is guaranteed to have the same value within the same
; function call (so called Caller Preserved Physical Register), the redudant ; function call (so called Caller Preserved Physical Register), the redudant
; TLS access code sequences are cleaned up. ; TLS access code sequences are cleaned up.
%"struct.CC::TT" = type { i64, i32 } %"struct.CC::TT" = type { i64, i32 }
▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/PowerPC/addegluecrash.ll

Show All 21 Lines
; CHECK-NEXT: add 4, 5, 4 ; CHECK-NEXT: add 4, 5, 4
; CHECK-NEXT: cmpld 7, 4, 5 ; CHECK-NEXT: cmpld 7, 4, 5
; CHECK-NEXT: mfocrf 10, 1 ; CHECK-NEXT: mfocrf 10, 1
; CHECK-NEXT: rlwinm 10, 10, 29, 31, 31 ; CHECK-NEXT: rlwinm 10, 10, 29, 31, 31
; CHECK-NEXT: # implicit-def: $x4 ; CHECK-NEXT: # implicit-def: $x4
; CHECK-NEXT: mr 4, 10 ; CHECK-NEXT: mr 4, 10
; CHECK-NEXT: clrldi 4, 4, 32 ; CHECK-NEXT: clrldi 4, 4, 32
; CHECK-NEXT: std 4, 0(3) ; CHECK-NEXT: std 4, 0(3)
; CHECK-NEXT: std 6, -8(1) # 8-byte Folded Spill
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%1 = load i64, i64* %a, align 8 %1 = load i64, i64* %a, align 8
%conv = zext i64 %1 to i128 %conv = zext i64 %1 to i128
%2 = load i64, i64* %b, align 8 %2 = load i64, i64* %b, align 8
%conv2 = zext i64 %2 to i128 %conv2 = zext i64 %2 to i128
%mul = mul nuw i128 %conv2, %conv %mul = mul nuw i128 %conv2, %conv
%shr = lshr i128 %mul, 64 %shr = lshr i128 %mul, 64
%agep = getelementptr inbounds i64, i64* %a, i64 1 %agep = getelementptr inbounds i64, i64* %a, i64 1
Show All 21 Lines

llvm/trunk/test/CodeGen/PowerPC/atomics-constant.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s ; RUN: llc < %s | FileCheck %s
target triple = "powerpc64le-unknown-linux-gnu" target triple = "powerpc64le-unknown-linux-gnu"
@a = constant i64 zeroinitializer @a = constant i64 zeroinitializer
define i64 @foo() { define i64 @foo() {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis 3, 2, .LC0@toc@ha ; CHECK-NEXT: addis 3, 2, a@toc@ha
; CHECK-NEXT: li 4, 0 ; CHECK-NEXT: li 4, 0
; CHECK-NEXT: ld 3, .LC0@toc@l(3) ; CHECK-NEXT: addi 3, 3, a@toc@l
; CHECK-NEXT: cmpd 7, 4, 4 ; CHECK-NEXT: cmpd 7, 4, 4
; CHECK-NEXT: ld 3, 0(3) ; CHECK-NEXT: ld 3, 0(3)
; CHECK-NEXT: li 3, 0
; CHECK-NEXT: bne- 7, .+4 ; CHECK-NEXT: bne- 7, .+4
; CHECK-NEXT: isync ; CHECK-NEXT: isync
; CHECK-NEXT: li 3, 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%value = load atomic i64, i64* @a acquire, align 8 %value = load atomic i64, i64* @a acquire, align 8
ret i64 %value ret i64 %value
} }

llvm/trunk/test/CodeGen/PowerPC/f128-aggregates.ll

; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ ; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
; RUN: -enable-ppc-quad-precision -verify-machineinstrs \ ; RUN: -enable-ppc-quad-precision -verify-machineinstrs \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown \ ; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown \
; RUN: -enable-ppc-quad-precision -verify-machineinstrs \ ; RUN: -enable-ppc-quad-precision -verify-machineinstrs \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \ ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
; RUN: | FileCheck -check-prefix=CHECK-BE %s ; RUN: | FileCheck -check-prefix=CHECK-BE %s
; Testing homogeneous aggregates. ; Testing homogeneous aggregates.
%struct.With9fp128params = type { fp128, fp128, fp128, fp128, fp128, fp128, %struct.With9fp128params = type { fp128, fp128, fp128, fp128, fp128, fp128,
fp128, fp128, fp128 } fp128, fp128, fp128 }
▲ Show 20 Lines • Show All 380 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/PowerPC/f128-conv.ll

; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ ; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
; RUN: -enable-ppc-quad-precision -ppc-vsr-nums-as-vr \ ; RUN: -enable-ppc-quad-precision -ppc-vsr-nums-as-vr \
; RUN: -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s ; RUN: -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s
@mem = global [5 x i64] [i64 56, i64 63, i64 3, i64 5, i64 6], align 8 @mem = global [5 x i64] [i64 56, i64 63, i64 3, i64 5, i64 6], align 8
@umem = global [5 x i64] [i64 560, i64 100, i64 34, i64 2, i64 5], align 8 @umem = global [5 x i64] [i64 560, i64 100, i64 34, i64 2, i64 5], align 8
@swMem = global [5 x i32] [i32 5, i32 2, i32 3, i32 4, i32 0], align 4 @swMem = global [5 x i32] [i32 5, i32 2, i32 3, i32 4, i32 0], align 4
@uwMem = global [5 x i32] [i32 5, i32 2, i32 3, i32 4, i32 0], align 4 @uwMem = global [5 x i32] [i32 5, i32 2, i32 3, i32 4, i32 0], align 4
@uhwMem = local_unnamed_addr global [5 x i16] [i16 5, i16 2, i16 3, i16 4, i16 0], align 2 @uhwMem = local_unnamed_addr global [5 x i16] [i16 5, i16 2, i16 3, i16 4, i16 0], align 2
▲ Show 20 Lines • Show All 833 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/PowerPC/f128-truncateNconv.ll

; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ ; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
; RUN: -verify-machineinstrs -enable-ppc-quad-precision \ ; RUN: -verify-machineinstrs -enable-ppc-quad-precision \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
@f128Array = global [4 x fp128] [fp128 0xL00000000000000004004C00000000000, @f128Array = global [4 x fp128] [fp128 0xL00000000000000004004C00000000000,
fp128 0xLF000000000000000400808AB851EB851, fp128 0xLF000000000000000400808AB851EB851,
fp128 0xL5000000000000000400E0C26324C8366, fp128 0xL5000000000000000400E0C26324C8366,
fp128 0xL8000000000000000400A24E2E147AE14], fp128 0xL8000000000000000400A24E2E147AE14],
align 16 align 16
▲ Show 20 Lines • Show All 648 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/PowerPC/f128-vecExtractNconv.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \ ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \
; RUN: -ppc-asm-full-reg-names -verify-machineinstrs \ ; RUN: -relocation-model=pic -ppc-asm-full-reg-names -verify-machineinstrs \
; RUN: -enable-ppc-quad-precision < %s | FileCheck %s ; RUN: -enable-ppc-quad-precision < %s | FileCheck %s
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown -ppc-vsr-nums-as-vr \ ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown -ppc-vsr-nums-as-vr \
; RUN: -ppc-asm-full-reg-names -verify-machineinstrs \ ; RUN: -ppc-asm-full-reg-names -verify-machineinstrs \
; RUN: -enable-ppc-quad-precision < %s | FileCheck %s -check-prefix=CHECK-BE ; RUN: -enable-ppc-quad-precision < %s | FileCheck %s -check-prefix=CHECK-BE
; Vector extract DWord and convert to quad precision. ; Vector extract DWord and convert to quad precision.
@sdwVecMem = global <2 x i64> <i64 88, i64 99>, align 16 @sdwVecMem = global <2 x i64> <i64 88, i64 99>, align 16
▲ Show 20 Lines • Show All 1,436 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/PowerPC/fast-isel-call.ll

; FIXME: FastISel currently returns false if it hits code that uses VSX ; FIXME: FastISel currently returns false if it hits code that uses VSX
; registers and with -fast-isel-abort=1 turned on the test case will then fail. ; registers and with -fast-isel-abort=1 turned on the test case will then fail.
; When fastisel better supports VSX fix up this test case. ; When fastisel better supports VSX fix up this test case.
; ;
; RUN: llc < %s -O0 -verify-machineinstrs -mattr=-vsx -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -ppc-late-peephole=true | FileCheck %s --check-prefix=ELF64 ; RUN: llc < %s -O0 -relocation-model=pic -verify-machineinstrs -mattr=-vsx -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -ppc-late-peephole=true | FileCheck %s --check-prefix=ELF64
define i32 @t1(i8 signext %a) nounwind { define i32 @t1(i8 signext %a) nounwind {
%1 = sext i8 %a to i32 %1 = sext i8 %a to i32
ret i32 %1 ret i32 %1
} }
define i32 @t2(i8 zeroext %a) nounwind { define i32 @t2(i8 zeroext %a) nounwind {
%1 = zext i8 %a to i32 %1 = zext i8 %a to i32
▲ Show 20 Lines • Show All 123 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/PowerPC/mcm-13.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s ; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck %s ; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck %s
; Test correct code generation for medium and large code model ; Test correct code generation for medium and large code model
; for loading and storing a weak variable ; for loading and storing a weak variable
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
@wi = weak global i32 0, align 4 @wi = weak global i32 0, align 4
Show All 17 Lines

llvm/trunk/test/CodeGen/PowerPC/mcm-6.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium < %s | FileCheck %s ; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large < %s | FileCheck %s ; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large < %s | FileCheck %s
; Test correct code generation for medium and large code model ; Test correct code generation for medium and large code model
; for loading and storing a tentatively defined variable. ; for loading and storing a tentatively defined variable.
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
@ti = common global i32 0, align 4 @ti = common global i32 0, align 4
Show All 18 Lines

llvm/trunk/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll

; RUN: llc < %s -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc < %s -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr8 \ ; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr8 -relocation-model=pic \
; RUN: | FileCheck %s ; RUN: | FileCheck %s
; RUN: llc < %s -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc < %s -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr8 \ ; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr8 -relocation-model=pic \
; RUN: | FileCheck %s -check-prefix=CHECK-LE ; RUN: | FileCheck %s -check-prefix=CHECK-LE
; The build[csilf] functions simply test the scalar_to_vector handling with ; The build[csilf] functions simply test the scalar_to_vector handling with
; direct moves. This corresponds to the "insertelement" instruction. Subsequent ; direct moves. This corresponds to the "insertelement" instruction. Subsequent
; to this, there will be a splat corresponding to the shufflevector. ; to this, there will be a splat corresponding to the shufflevector.
@d = common global double 0.000000e+00, align 8 @d = common global double 0.000000e+00, align 8
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llvm/trunk/test/CodeGen/PowerPC/ppc64-blnop.ll

; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s
; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s
; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s
; RUN: llc < %s -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s ; RUN: llc < %s -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s
; RUN: llc < %s -function-sections -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK-FS ; RUN: llc < %s -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s
; RUN: llc < %s -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s
; RUN: llc < %s -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s
; RUN: llc < %s -relocation-model=pic -function-sections -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK-FS
; RUN: llc < %s -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s ; RUN: llc < %s -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s
; RUN: llc < %s -function-sections -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK-FS ; RUN: llc < %s -relocation-model=pic -function-sections -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK-FS
; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc < %s -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -code-model=small -mcpu=pwr8 | FileCheck %s -check-prefix=SCM ; RUN: -code-model=small -mcpu=pwr8 | FileCheck %s -check-prefix=SCM
%class.T = type { [2 x i8] } %class.T = type { [2 x i8] }
define void @e_callee(%class.T* %this, i8* %c) { ret void } define void @e_callee(%class.T* %this, i8* %c) { ret void }
define void @e_caller(%class.T* %this, i8* %c) { define void @e_caller(%class.T* %this, i8* %c) {
call void @e_callee(%class.T* %this, i8* %c) call void @e_callee(%class.T* %this, i8* %c)
ret void ret void
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llvm/trunk/test/CodeGen/PowerPC/ppc64-i128-abi.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 < %s | FileCheck %s -check-prefix=CHECK-LE \ ; RUN: -mcpu=pwr8 < %s | FileCheck %s -check-prefix=CHECK-LE \
; RUN: --implicit-check-not xxswapd ; RUN: --implicit-check-not xxswapd
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr8 < %s | FileCheck %s -check-prefix=CHECK-BE ; RUN: -mcpu=pwr8 < %s | FileCheck %s -check-prefix=CHECK-BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX ; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX \ ; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX \
; RUN: --implicit-check-not xxswapd ; RUN: --implicit-check-not xxswapd
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-BE-NOVSX ; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-BE-NOVSX
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -mattr=-vsx < %s | \ ; RUN: -mcpu=pwr8 -mattr=-vsx < %s | \
; RUN: FileCheck %s -check-prefix=CHECK-LE-NOVSX --implicit-check-not xxswapd ; RUN: FileCheck %s -check-prefix=CHECK-LE-NOVSX --implicit-check-not xxswapd
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s -check-prefix=CHECK-P9 --implicit-check-not xxswapd ; RUN: FileCheck %s -check-prefix=CHECK-P9 --implicit-check-not xxswapd
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX \ ; RUN: -mcpu=pwr9 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX \
; RUN: --implicit-check-not xxswapd ; RUN: --implicit-check-not xxswapd
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -mattr=-power9-vector -mattr=-direct-move < %s | \ ; RUN: -mcpu=pwr9 -mattr=-power9-vector -mattr=-direct-move < %s | \
; RUN: FileCheck %s -check-prefix=CHECK-LE --implicit-check-not xxswapd ; RUN: FileCheck %s -check-prefix=CHECK-LE --implicit-check-not xxswapd
@x = common global <1 x i128> zeroinitializer, align 16 @x = common global <1 x i128> zeroinitializer, align 16
@y = common global <1 x i128> zeroinitializer, align 16 @y = common global <1 x i128> zeroinitializer, align 16
@a = common global i128 zeroinitializer, align 16 @a = common global i128 zeroinitializer, align 16
@b = common global i128 zeroinitializer, align 16 @b = common global i128 zeroinitializer, align 16
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llvm/trunk/test/CodeGen/PowerPC/ppc64le-aggregates.ll

; RUN: llc -verify-machineinstrs < %s -mcpu=pwr8 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs < %s -mcpu=pwr8 \
; RUN: -mattr=+altivec -mattr=-vsx | FileCheck %s ; RUN: -mattr=+altivec -mattr=-vsx | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mattr=+altivec \ ; RUN: llc -relocation-model=pic -verify-machineinstrs < %s -mattr=+altivec \
; RUN: -mattr=-vsx | FileCheck %s ; RUN: -mattr=-vsx | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mcpu=pwr9 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs < %s -mcpu=pwr9 \
; RUN: -mattr=-direct-move -mattr=+altivec | FileCheck %s ; RUN: -mattr=-direct-move -mattr=+altivec | FileCheck %s
; Currently VSX support is disabled for this test because we generate lxsdx ; Currently VSX support is disabled for this test because we generate lxsdx
; instead of lfd, and stxsdx instead of stfd. That is a poor choice when we ; instead of lfd, and stxsdx instead of stfd. That is a poor choice when we
; have reg+imm addressing, and is on the list of things to be fixed. ; have reg+imm addressing, and is on the list of things to be fixed.
; The second run step is to ensure that -march=ppc64le is adequate to select ; The second run step is to ensure that -march=ppc64le is adequate to select
; the same feature set as with -mcpu=pwr8 since that is the baseline for ppc64le. ; the same feature set as with -mcpu=pwr8 since that is the baseline for ppc64le.
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llvm/trunk/test/CodeGen/PowerPC/ppcf128-endian.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec -mattr=-vsx < %s | FileCheck %s ; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec -mattr=-vsx < %s | FileCheck %s
target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu" target triple = "powerpc64le-unknown-linux-gnu"
@g = common global ppc_fp128 0xM00000000000000000000000000000000, align 16 @g = common global ppc_fp128 0xM00000000000000000000000000000000, align 16
define void @callee(ppc_fp128 %x) { define void @callee(ppc_fp128 %x) {
entry: entry:
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llvm/trunk/test/CodeGen/PowerPC/pr32140.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc64le-linux-gnu -mcpu=pwr8 < %s | FileCheck %s ; RUN: llc -mtriple=powerpc64le-linux-gnu -mcpu=pwr8 < %s | FileCheck %s --check-prefix CHECK-LE
; RUN: llc -mtriple=powerpc64-linux-gnu -mcpu=pwr8 < %s | FileCheck %s ; RUN: llc -mtriple=powerpc64-linux-gnu -mcpu=pwr8 < %s | FileCheck %s --check-prefix CHECK-BE
@as = common local_unnamed_addr global i16 0, align 2 @as = common local_unnamed_addr global i16 0, align 2
@bs = common local_unnamed_addr global i16 0, align 2 @bs = common local_unnamed_addr global i16 0, align 2
@ai = common local_unnamed_addr global i32 0, align 4 @ai = common local_unnamed_addr global i32 0, align 4
@bi = common local_unnamed_addr global i32 0, align 4 @bi = common local_unnamed_addr global i32 0, align 4
define void @bswapStorei64Toi32() { define void @bswapStorei64Toi32() {
; CHECK-LABEL: bswapStorei64Toi32: ; CHECK-LABEL: bswapStorei64Toi32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK: lwa 3, 0(3) ; CHECK-NEXT: addis 3, 2, ai@toc@ha
; CHECK-NEXT: addis 4, 2, bi@toc@ha
; CHECK-NEXT: lwa 3, ai@toc@l(3)
; CHECK-NEXT: addi 4, 4, bi@toc@l
; CHECK-NEXT: rldicl 3, 3, 32, 32 ; CHECK-NEXT: rldicl 3, 3, 32, 32
; CHECK-NEXT: stwbrx 3, 0, 4 ; CHECK-NEXT: stwbrx 3, 0, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-LE-LABEL: bswapStorei64Toi32:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addis 3, 2, ai@toc@ha
; CHECK-LE-NEXT: addis 4, 2, bi@toc@ha
; CHECK-LE-NEXT: lwa 3, ai@toc@l(3)
; CHECK-LE-NEXT: addi 4, 4, bi@toc@l
; CHECK-LE-NEXT: rldicl 3, 3, 32, 32
; CHECK-LE-NEXT: stwbrx 3, 0, 4
; CHECK-LE-NEXT: blr
;
; CHECK-BE-LABEL: bswapStorei64Toi32:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis 3, 2, .LC0@toc@ha
; CHECK-BE-NEXT: addis 4, 2, .LC1@toc@ha
; CHECK-BE-NEXT: ld 3, .LC0@toc@l(3)
; CHECK-BE-NEXT: ld 4, .LC1@toc@l(4)
; CHECK-BE-NEXT: lwa 3, 0(3)
; CHECK-BE-NEXT: rldicl 3, 3, 32, 32
; CHECK-BE-NEXT: stwbrx 3, 0, 4
; CHECK-BE-NEXT: blr
entry: entry:
%0 = load i32, i32* @ai, align 4 %0 = load i32, i32* @ai, align 4
%conv.i = sext i32 %0 to i64 %conv.i = sext i32 %0 to i64
%or26.i = tail call i64 @llvm.bswap.i64(i64 %conv.i) %or26.i = tail call i64 @llvm.bswap.i64(i64 %conv.i)
%conv = trunc i64 %or26.i to i32 %conv = trunc i64 %or26.i to i32
store i32 %conv, i32* @bi, align 4 store i32 %conv, i32* @bi, align 4
ret void ret void
} }
define void @bswapStorei32Toi16() { define void @bswapStorei32Toi16() {
; CHECK-LABEL: bswapStorei32Toi16: ; CHECK-LABEL: bswapStorei32Toi16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK: lha 3, 0(3) ; CHECK-NEXT: addis 3, 2, as@toc@ha
; CHECK-NEXT: addis 4, 2, bs@toc@ha
; CHECK-NEXT: lha 3, as@toc@l(3)
; CHECK-NEXT: addi 4, 4, bs@toc@l
; CHECK-NEXT: srwi 3, 3, 16 ; CHECK-NEXT: srwi 3, 3, 16
; CHECK-NEXT: sthbrx 3, 0, 4 ; CHECK-NEXT: sthbrx 3, 0, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-LE-LABEL: bswapStorei32Toi16:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addis 3, 2, as@toc@ha
; CHECK-LE-NEXT: addis 4, 2, bs@toc@ha
; CHECK-LE-NEXT: lha 3, as@toc@l(3)
; CHECK-LE-NEXT: addi 4, 4, bs@toc@l
; CHECK-LE-NEXT: srwi 3, 3, 16
; CHECK-LE-NEXT: sthbrx 3, 0, 4
; CHECK-LE-NEXT: blr
;
; CHECK-BE-LABEL: bswapStorei32Toi16:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis 3, 2, .LC2@toc@ha
; CHECK-BE-NEXT: addis 4, 2, .LC3@toc@ha
; CHECK-BE-NEXT: ld 3, .LC2@toc@l(3)
; CHECK-BE-NEXT: ld 4, .LC3@toc@l(4)
; CHECK-BE-NEXT: lha 3, 0(3)
; CHECK-BE-NEXT: srwi 3, 3, 16
; CHECK-BE-NEXT: sthbrx 3, 0, 4
; CHECK-BE-NEXT: blr
entry: entry:
%0 = load i16, i16* @as, align 2 %0 = load i16, i16* @as, align 2
%conv.i = sext i16 %0 to i32 %conv.i = sext i16 %0 to i32
%or26.i = tail call i32 @llvm.bswap.i32(i32 %conv.i) %or26.i = tail call i32 @llvm.bswap.i32(i32 %conv.i)
%conv = trunc i32 %or26.i to i16 %conv = trunc i32 %or26.i to i16
store i16 %conv, i16* @bs, align 2 store i16 %conv, i16* @bs, align 2
ret void ret void
} }
define void @bswapStorei64Toi16() { define void @bswapStorei64Toi16() {
; CHECK-LABEL: bswapStorei64Toi16: ; CHECK-LABEL: bswapStorei64Toi16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK: lha 3, 0(3) ; CHECK-NEXT: addis 3, 2, as@toc@ha
; CHECK-NEXT: addis 4, 2, bs@toc@ha
; CHECK-NEXT: lha 3, as@toc@l(3)
; CHECK-NEXT: addi 4, 4, bs@toc@l
; CHECK-NEXT: rldicl 3, 3, 16, 48 ; CHECK-NEXT: rldicl 3, 3, 16, 48
; CHECK-NEXT: sthbrx 3, 0, 4 ; CHECK-NEXT: sthbrx 3, 0, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-LE-LABEL: bswapStorei64Toi16:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addis 3, 2, as@toc@ha
; CHECK-LE-NEXT: addis 4, 2, bs@toc@ha
; CHECK-LE-NEXT: lha 3, as@toc@l(3)
; CHECK-LE-NEXT: addi 4, 4, bs@toc@l
; CHECK-LE-NEXT: rldicl 3, 3, 16, 48
; CHECK-LE-NEXT: sthbrx 3, 0, 4
; CHECK-LE-NEXT: blr
;
; CHECK-BE-LABEL: bswapStorei64Toi16:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis 3, 2, .LC2@toc@ha
; CHECK-BE-NEXT: addis 4, 2, .LC3@toc@ha
; CHECK-BE-NEXT: ld 3, .LC2@toc@l(3)
; CHECK-BE-NEXT: ld 4, .LC3@toc@l(4)
; CHECK-BE-NEXT: lha 3, 0(3)
; CHECK-BE-NEXT: rldicl 3, 3, 16, 48
; CHECK-BE-NEXT: sthbrx 3, 0, 4
; CHECK-BE-NEXT: blr
entry: entry:
%0 = load i16, i16* @as, align 2 %0 = load i16, i16* @as, align 2
%conv.i = sext i16 %0 to i64 %conv.i = sext i16 %0 to i64
%or26.i = tail call i64 @llvm.bswap.i64(i64 %conv.i) %or26.i = tail call i64 @llvm.bswap.i64(i64 %conv.i)
%conv = trunc i64 %or26.i to i16 %conv = trunc i64 %or26.i to i16
store i16 %conv, i16* @bs, align 2 store i16 %conv, i16* @bs, align 2
ret void ret void
} }
declare i32 @llvm.bswap.i32(i32) declare i32 @llvm.bswap.i32(i32)
declare i64 @llvm.bswap.i64(i64) declare i64 @llvm.bswap.i64(i64)

llvm/trunk/test/CodeGen/PowerPC/preemption.ll

; RUN: llc -mtriple powerpc64le-unkown-gnu-linux < %s | FileCheck %s ; RUN: llc -mtriple powerpc64le-unkown-gnu-linux -relocation-model=pic \
; RUN: < %s | FileCheck %s
; RUN: llc -mtriple powerpc64le-unkown-gnu-linux -relocation-model=static \ ; RUN: llc -mtriple powerpc64le-unkown-gnu-linux -relocation-model=static \
; RUN: < %s | FileCheck --check-prefix=STATIC %s ; RUN: < %s | FileCheck --check-prefix=STATIC %s
; RUN: llc -mtriple powerpc64le-unkown-gnu-linux -relocation-model=pic \ ; RUN: llc -mtriple powerpc64le-unkown-gnu-linux -relocation-model=pic \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; globals ; globals
@strong_default = global i32 55 @strong_default = global i32 55
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llvm/trunk/test/CodeGen/PowerPC/save-bp.ll

; RUN: llc -mtriple=ppc64-- -ppc-always-use-base-pointer < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC64 ; RUN: llc -mtriple=ppc64-- -ppc-always-use-base-pointer < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC64
; RUN: llc -ppc-always-use-base-pointer < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC32 ; RUN: llc -ppc-always-use-base-pointer -relocation-model=static < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC32
; RUN: llc -ppc-always-use-base-pointer -relocation-model pic < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC32PIC ; RUN: llc -ppc-always-use-base-pointer -relocation-model=pic < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC32PIC
; CHECK-LABEL: fred: ; CHECK-LABEL: fred:
; Check for saving/restoring frame pointer (X31) and base pointer (X30) ; Check for saving/restoring frame pointer (X31) and base pointer (X30)
; on ppc64: ; on ppc64:
; PPC64: std 31, -8(1) ; PPC64: std 31, -8(1)
; PPC64: std 30, -16(1) ; PPC64: std 30, -16(1)
; PPC64: ld 31, -8(1) ; PPC64: ld 31, -8(1)
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llvm/trunk/test/CodeGen/PowerPC/sjlj_no0x.ll

; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -relocation-model=pic -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -relocation-model=pic -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -relocation-model=pic -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -verify-machineinstrs | FileCheck %s
target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu" target triple = "powerpc64le-unknown-linux-gnu"
; Function Attrs: noinline nounwind ; Function Attrs: noinline nounwind
define void @_Z23BuiltinLongJmpFunc1_bufv() #0 { define void @_Z23BuiltinLongJmpFunc1_bufv() #0 {
entry: entry:
call void @llvm.eh.sjlj.longjmp(i8* bitcast (void ()* @_Z23BuiltinLongJmpFunc1_bufv to i8*)) call void @llvm.eh.sjlj.longjmp(i8* bitcast (void ()* @_Z23BuiltinLongJmpFunc1_bufv to i8*))
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llvm/trunk/test/CodeGen/PowerPC/swaps-le-6.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-vsr-nums-as-vr \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr8 -ppc-vsr-nums-as-vr \
; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -O3 < %s | FileCheck %s ; RUN: -O3 < %s | FileCheck %s
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \ ; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \ ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \
; RUN: < %s | FileCheck %s --check-prefix=CHECK-P9 \ ; RUN: < %s | FileCheck %s --check-prefix=CHECK-P9 \
; RUN: --implicit-check-not xxswapd ; RUN: --implicit-check-not xxswapd
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \ ; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \ ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \
; RUN: -mattr=-power9-vector < %s | FileCheck %s ; RUN: -mattr=-power9-vector < %s | FileCheck %s
; These tests verify that VSX swap optimization works when loading a scalar ; These tests verify that VSX swap optimization works when loading a scalar
; into a vector register. ; into a vector register.
@x = global <2 x double> <double 9.970000e+01, double -1.032220e+02>, align 16 @x = global <2 x double> <double 9.970000e+01, double -1.032220e+02>, align 16
▲ Show 20 Lines • Show All 71 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/PowerPC/testComparesi32gtu.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
%struct.tree_common = type { i8, [3 x i8] } %struct.tree_common = type { i8, [3 x i8] }
declare signext i32 @fn2(...) local_unnamed_addr #1 declare signext i32 @fn2(...) local_unnamed_addr #1
; Function Attrs: nounwind ; Function Attrs: nounwind
define i32 @testCompare1(%struct.tree_common* nocapture readonly %arg1) { define i32 @testCompare1(%struct.tree_common* nocapture readonly %arg1) {
Show All 40 Lines

llvm/trunk/test/CodeGen/PowerPC/testComparesi32ltu.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
%struct.tree_common = type { i8, [3 x i8] } %struct.tree_common = type { i8, [3 x i8] }
declare signext i32 @fn2(...) local_unnamed_addr #1 declare signext i32 @fn2(...) local_unnamed_addr #1
; Function Attrs: nounwind ; Function Attrs: nounwind
define i32 @testCompare1(%struct.tree_common* nocapture readonly %arg1) { define i32 @testCompare1(%struct.tree_common* nocapture readonly %arg1) {
Show All 40 Lines

llvm/trunk/test/CodeGen/PowerPC/testComparesieqsc.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; ModuleID = 'ComparisonTestCases/testComparesieqsc.c' ; ModuleID = 'ComparisonTestCases/testComparesieqsc.c'
@glob = common local_unnamed_addr global i8 0, align 1 @glob = common local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqsc(i8 signext %a, i8 signext %b) { define signext i32 @test_ieqsc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ieqsc: ; CHECK-LABEL: test_ieqsc:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsc:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqsc:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i8 %a, %b %cmp = icmp eq i8 %a, %b
%conv2 = zext i1 %cmp to i32 %conv2 = zext i1 %cmp to i32
ret i32 %conv2 ret i32 %conv2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqsc_sext(i8 signext %a, i8 signext %b) { define signext i32 @test_ieqsc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ieqsc_sext: ; CHECK-LABEL: test_ieqsc_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsc_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqsc_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i8 %a, %b %cmp = icmp eq i8 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqsc_z(i8 signext %a) { define signext i32 @test_ieqsc_z(i8 signext %a) {
; CHECK-LABEL: test_ieqsc_z: ; CHECK-LABEL: test_ieqsc_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsc_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqsc_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i8 %a, 0 %cmp = icmp eq i8 %a, 0
%conv1 = zext i1 %cmp to i32 %conv1 = zext i1 %cmp to i32
ret i32 %conv1 ret i32 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqsc_sext_z(i8 signext %a) { define signext i32 @test_ieqsc_sext_z(i8 signext %a) {
; CHECK-LABEL: test_ieqsc_sext_z: ; CHECK-LABEL: test_ieqsc_sext_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsc_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqsc_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i8 %a, 0 %cmp = icmp eq i8 %a, 0
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_ieqsc_store(i8 signext %a, i8 signext %b) { define void @test_ieqsc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ieqsc_store: ; CHECK-LABEL: test_ieqsc_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsc_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqsc_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: stb r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i8 %a, %b %cmp = icmp eq i8 %a, %b
%conv3 = zext i1 %cmp to i8 %conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1 store i8 %conv3, i8* @glob, align 1
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_ieqsc_sext_store(i8 signext %a, i8 signext %b) { define void @test_ieqsc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ieqsc_sext_store: ; CHECK-LABEL: test_ieqsc_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsc_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqsc_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: stb r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i8 %a, %b %cmp = icmp eq i8 %a, %b
%conv3 = sext i1 %cmp to i8 %conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1 store i8 %conv3, i8* @glob, align 1
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_ieqsc_z_store(i8 signext %a) { define void @test_ieqsc_z_store(i8 signext %a) {
; CHECK-LABEL: test_ieqsc_z_store: ; CHECK-LABEL: test_ieqsc_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: stb r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsc_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqsc_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: stb r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i8 %a, 0 %cmp = icmp eq i8 %a, 0
%conv2 = zext i1 %cmp to i8 %conv2 = zext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1 store i8 %conv2, i8* @glob, align 1
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_ieqsc_sext_z_store(i8 signext %a) { define void @test_ieqsc_sext_z_store(i8 signext %a) {
; CHECK-LABEL: test_ieqsc_sext_z_store: ; CHECK-LABEL: test_ieqsc_sext_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: stb r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsc_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqsc_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: stb r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i8 %a, 0 %cmp = icmp eq i8 %a, 0
%conv2 = sext i1 %cmp to i8 %conv2 = sext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1 store i8 %conv2, i8* @glob, align 1
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesieqsi.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; ModuleID = 'ComparisonTestCases/testComparesieqsi.c' ; ModuleID = 'ComparisonTestCases/testComparesieqsi.c'
@glob = common local_unnamed_addr global i32 0, align 4 @glob = common local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqsi(i32 signext %a, i32 signext %b) { define signext i32 @test_ieqsi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ieqsi: ; CHECK-LABEL: test_ieqsi:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsi:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqsi:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i32 %a, %b %cmp = icmp eq i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqsi_sext(i32 signext %a, i32 signext %b) { define signext i32 @test_ieqsi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ieqsi_sext: ; CHECK-LABEL: test_ieqsi_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsi_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqsi_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i32 %a, %b %cmp = icmp eq i32 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqsi_z(i32 signext %a) { define signext i32 @test_ieqsi_z(i32 signext %a) {
; CHECK-LABEL: test_ieqsi_z: ; CHECK-LABEL: test_ieqsi_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsi_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqsi_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i32 %a, 0 %cmp = icmp eq i32 %a, 0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqsi_sext_z(i32 signext %a) { define signext i32 @test_ieqsi_sext_z(i32 signext %a) {
; CHECK-LABEL: test_ieqsi_sext_z: ; CHECK-LABEL: test_ieqsi_sext_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsi_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqsi_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i32 %a, 0 %cmp = icmp eq i32 %a, 0
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_ieqsi_store(i32 signext %a, i32 signext %b) { define void @test_ieqsi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ieqsi_store: ; CHECK-LABEL: test_ieqsi_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsi_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqsi_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i32 %a, %b %cmp = icmp eq i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4 store i32 %conv, i32* @glob, align 4
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_ieqsi_sext_store(i32 signext %a, i32 signext %b) { define void @test_ieqsi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ieqsi_sext_store: ; CHECK-LABEL: test_ieqsi_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsi_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqsi_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i32 %a, %b %cmp = icmp eq i32 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4 store i32 %sub, i32* @glob, align 4
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_ieqsi_z_store(i32 signext %a) { define void @test_ieqsi_z_store(i32 signext %a) {
; CHECK-LABEL: test_ieqsi_z_store: ; CHECK-LABEL: test_ieqsi_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: stw r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsi_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqsi_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: stw r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i32 %a, 0 %cmp = icmp eq i32 %a, 0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4 store i32 %conv, i32* @glob, align 4
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_ieqsi_sext_z_store(i32 signext %a) { define void @test_ieqsi_sext_z_store(i32 signext %a) {
; CHECK-LABEL: test_ieqsi_sext_z_store: ; CHECK-LABEL: test_ieqsi_sext_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: stw r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsi_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqsi_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: stw r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i32 %a, 0 %cmp = icmp eq i32 %a, 0
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4 store i32 %sub, i32* @glob, align 4
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesieqsll.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; ModuleID = 'ComparisonTestCases/testComparesieqsll.c' ; ModuleID = 'ComparisonTestCases/testComparesieqsll.c'
@glob = common local_unnamed_addr global i64 0, align 8 @glob = common local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqsll(i64 %a, i64 %b) { define signext i32 @test_ieqsll(i64 %a, i64 %b) {
; CHECK-LABEL: test_ieqsll: ; CHECK-LABEL: test_ieqsll:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsll:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzd r3, r3
; CHECK-BE-NEXT: rldicl r3, r3, 58, 63
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqsll:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzd r3, r3
; CHECK-LE-NEXT: rldicl r3, r3, 58, 63
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, %b %cmp = icmp eq i64 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqsll_sext(i64 %a, i64 %b) { define signext i32 @test_ieqsll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_ieqsll_sext: ; CHECK-LABEL: test_ieqsll_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsll_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqsll_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, %b %cmp = icmp eq i64 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqsll_z(i64 %a) { define signext i32 @test_ieqsll_z(i64 %a) {
; CHECK-LABEL: test_ieqsll_z: ; CHECK-LABEL: test_ieqsll_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsll_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzd r3, r3
; CHECK-BE-NEXT: rldicl r3, r3, 58, 63
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqsll_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzd r3, r3
; CHECK-LE-NEXT: rldicl r3, r3, 58, 63
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, 0 %cmp = icmp eq i64 %a, 0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqsll_sext_z(i64 %a) { define signext i32 @test_ieqsll_sext_z(i64 %a) {
; CHECK-LABEL: test_ieqsll_sext_z: ; CHECK-LABEL: test_ieqsll_sext_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsll_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqsll_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, 0 %cmp = icmp eq i64 %a, 0
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_ieqsll_store(i64 %a, i64 %b) { define void @test_ieqsll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_ieqsll_store: ; CHECK-LABEL: test_ieqsll_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsll_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: cntlzd r3, r3
; CHECK-BE-NEXT: rldicl r3, r3, 58, 63
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqsll_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzd r3, r3
; CHECK-LE-NEXT: rldicl r3, r3, 58, 63
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, %b %cmp = icmp eq i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_ieqsll_sext_store(i64 %a, i64 %b) { define void @test_ieqsll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_ieqsll_sext_store: ; CHECK-LABEL: test_ieqsll_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsll_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqsll_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, %b %cmp = icmp eq i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_ieqsll_z_store(i64 %a) { define void @test_ieqsll_z_store(i64 %a) {
; CHECK-LABEL: test_ieqsll_z_store: ; CHECK-LABEL: test_ieqsll_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsll_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzd r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: rldicl r3, r3, 58, 63
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqsll_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzd r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 58, 63
; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, 0 %cmp = icmp eq i64 %a, 0
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_ieqsll_sext_z_store(i64 %a) { define void @test_ieqsll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_ieqsll_sext_z_store: ; CHECK-LABEL: test_ieqsll_sext_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsll_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqsll_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, 0 %cmp = icmp eq i64 %a, 0
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesieqss.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; ModuleID = 'ComparisonTestCases/testComparesieqss.c' ; ModuleID = 'ComparisonTestCases/testComparesieqss.c'
@glob = common local_unnamed_addr global i16 0, align 2 @glob = common local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqss(i16 signext %a, i16 signext %b) { define signext i32 @test_ieqss(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_ieqss: ; CHECK-LABEL: test_ieqss:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqss:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqss:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i16 %a, %b %cmp = icmp eq i16 %a, %b
%conv2 = zext i1 %cmp to i32 %conv2 = zext i1 %cmp to i32
ret i32 %conv2 ret i32 %conv2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqss_sext(i16 signext %a, i16 signext %b) { define signext i32 @test_ieqss_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_ieqss_sext: ; CHECK-LABEL: test_ieqss_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqss_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqss_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i16 %a, %b %cmp = icmp eq i16 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqss_z(i16 signext %a) { define signext i32 @test_ieqss_z(i16 signext %a) {
; CHECK-LABEL: test_ieqss_z: ; CHECK-LABEL: test_ieqss_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqss_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqss_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i16 %a, 0 %cmp = icmp eq i16 %a, 0
%conv1 = zext i1 %cmp to i32 %conv1 = zext i1 %cmp to i32
ret i32 %conv1 ret i32 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqss_sext_z(i16 signext %a) { define signext i32 @test_ieqss_sext_z(i16 signext %a) {
; CHECK-LABEL: test_ieqss_sext_z: ; CHECK-LABEL: test_ieqss_sext_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqss_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqss_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i16 %a, 0 %cmp = icmp eq i16 %a, 0
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_ieqss_store(i16 signext %a, i16 signext %b) { define void @test_ieqss_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_ieqss_store: ; CHECK-LABEL: test_ieqss_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqss_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqss_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i16 %a, %b %cmp = icmp eq i16 %a, %b
%conv3 = zext i1 %cmp to i16 %conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2 store i16 %conv3, i16* @glob, align 2
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_ieqss_sext_store(i16 signext %a, i16 signext %b) { define void @test_ieqss_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_ieqss_sext_store: ; CHECK-LABEL: test_ieqss_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqss_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqss_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i16 %a, %b %cmp = icmp eq i16 %a, %b
%conv3 = sext i1 %cmp to i16 %conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2 store i16 %conv3, i16* @glob, align 2
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_ieqss_z_store(i16 signext %a) { define void @test_ieqss_z_store(i16 signext %a) {
; CHECK-LABEL: test_ieqss_z_store: ; CHECK-LABEL: test_ieqss_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: sth r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqss_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqss_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: sth r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i16 %a, 0 %cmp = icmp eq i16 %a, 0
%conv2 = zext i1 %cmp to i16 %conv2 = zext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2 store i16 %conv2, i16* @glob, align 2
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_ieqss_sext_z_store(i16 signext %a) { define void @test_ieqss_sext_z_store(i16 signext %a) {
; CHECK-LABEL: test_ieqss_sext_z_store: ; CHECK-LABEL: test_ieqss_sext_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: sth r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqss_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqss_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: sth r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i16 %a, 0 %cmp = icmp eq i16 %a, 0
%conv2 = sext i1 %cmp to i16 %conv2 = sext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2 store i16 %conv2, i16* @glob, align 2
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesiequc.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; ModuleID = 'ComparisonTestCases/testComparesiequc.c' ; ModuleID = 'ComparisonTestCases/testComparesiequc.c'
@glob = common local_unnamed_addr global i8 0, align 1 @glob = common local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequc(i8 zeroext %a, i8 zeroext %b) { define signext i32 @test_iequc(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_iequc: ; CHECK-LABEL: test_iequc:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequc:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequc:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i8 %a, %b %cmp = icmp eq i8 %a, %b
%conv2 = zext i1 %cmp to i32 %conv2 = zext i1 %cmp to i32
ret i32 %conv2 ret i32 %conv2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequc_sext(i8 zeroext %a, i8 zeroext %b) { define signext i32 @test_iequc_sext(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_iequc_sext: ; CHECK-LABEL: test_iequc_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequc_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequc_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i8 %a, %b %cmp = icmp eq i8 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequc_z(i8 zeroext %a) { define signext i32 @test_iequc_z(i8 zeroext %a) {
; CHECK-LABEL: test_iequc_z: ; CHECK-LABEL: test_iequc_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequc_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequc_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i8 %a, 0 %cmp = icmp eq i8 %a, 0
%conv1 = zext i1 %cmp to i32 %conv1 = zext i1 %cmp to i32
ret i32 %conv1 ret i32 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequc_sext_z(i8 zeroext %a) { define signext i32 @test_iequc_sext_z(i8 zeroext %a) {
; CHECK-LABEL: test_iequc_sext_z: ; CHECK-LABEL: test_iequc_sext_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequc_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequc_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i8 %a, 0 %cmp = icmp eq i8 %a, 0
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_iequc_store(i8 zeroext %a, i8 zeroext %b) { define void @test_iequc_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_iequc_store: ; CHECK-LABEL: test_iequc_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequc_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequc_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: stb r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i8 %a, %b %cmp = icmp eq i8 %a, %b
%conv3 = zext i1 %cmp to i8 %conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1 store i8 %conv3, i8* @glob, align 1
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_iequc_sext_store(i8 zeroext %a, i8 zeroext %b) { define void @test_iequc_sext_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_iequc_sext_store: ; CHECK-LABEL: test_iequc_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequc_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequc_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: stb r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i8 %a, %b %cmp = icmp eq i8 %a, %b
%conv3 = sext i1 %cmp to i8 %conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1 store i8 %conv3, i8* @glob, align 1
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_iequc_z_store(i8 zeroext %a) { define void @test_iequc_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_iequc_z_store: ; CHECK-LABEL: test_iequc_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: stb r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequc_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequc_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: stb r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i8 %a, 0 %cmp = icmp eq i8 %a, 0
%conv2 = zext i1 %cmp to i8 %conv2 = zext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1 store i8 %conv2, i8* @glob, align 1
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_iequc_sext_z_store(i8 zeroext %a) { define void @test_iequc_sext_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_iequc_sext_z_store: ; CHECK-LABEL: test_iequc_sext_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: stb r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequc_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequc_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: stb r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i8 %a, 0 %cmp = icmp eq i8 %a, 0
%conv2 = sext i1 %cmp to i8 %conv2 = sext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1 store i8 %conv2, i8* @glob, align 1
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesiequi.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; ModuleID = 'ComparisonTestCases/testComparesiequi.c' ; ModuleID = 'ComparisonTestCases/testComparesiequi.c'
@glob = common local_unnamed_addr global i32 0, align 4 @glob = common local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequi(i32 zeroext %a, i32 zeroext %b) { define signext i32 @test_iequi(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_iequi: ; CHECK-LABEL: test_iequi:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequi:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequi:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i32 %a, %b %cmp = icmp eq i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequi_sext(i32 zeroext %a, i32 zeroext %b) { define signext i32 @test_iequi_sext(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_iequi_sext: ; CHECK-LABEL: test_iequi_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequi_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequi_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i32 %a, %b %cmp = icmp eq i32 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequi_z(i32 zeroext %a) { define signext i32 @test_iequi_z(i32 zeroext %a) {
; CHECK-LABEL: test_iequi_z: ; CHECK-LABEL: test_iequi_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequi_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequi_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i32 %a, 0 %cmp = icmp eq i32 %a, 0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequi_sext_z(i32 zeroext %a) { define signext i32 @test_iequi_sext_z(i32 zeroext %a) {
; CHECK-LABEL: test_iequi_sext_z: ; CHECK-LABEL: test_iequi_sext_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequi_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequi_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i32 %a, 0 %cmp = icmp eq i32 %a, 0
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_iequi_store(i32 zeroext %a, i32 zeroext %b) { define void @test_iequi_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_iequi_store: ; CHECK-LABEL: test_iequi_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequi_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequi_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i32 %a, %b %cmp = icmp eq i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4 store i32 %conv, i32* @glob, align 4
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_iequi_sext_store(i32 zeroext %a, i32 zeroext %b) { define void @test_iequi_sext_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_iequi_sext_store: ; CHECK-LABEL: test_iequi_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequi_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequi_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i32 %a, %b %cmp = icmp eq i32 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4 store i32 %sub, i32* @glob, align 4
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_iequi_z_store(i32 zeroext %a) { define void @test_iequi_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_iequi_z_store: ; CHECK-LABEL: test_iequi_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: stw r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequi_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequi_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: stw r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i32 %a, 0 %cmp = icmp eq i32 %a, 0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4 store i32 %conv, i32* @glob, align 4
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_iequi_sext_z_store(i32 zeroext %a) { define void @test_iequi_sext_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_iequi_sext_z_store: ; CHECK-LABEL: test_iequi_sext_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: stw r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequi_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequi_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: stw r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i32 %a, 0 %cmp = icmp eq i32 %a, 0
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4 store i32 %sub, i32* @glob, align 4
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesiequll.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; ModuleID = 'ComparisonTestCases/testComparesiequll.c' ; ModuleID = 'ComparisonTestCases/testComparesiequll.c'
@glob = common local_unnamed_addr global i64 0, align 8 @glob = common local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequll(i64 %a, i64 %b) { define signext i32 @test_iequll(i64 %a, i64 %b) {
; CHECK-LABEL: test_iequll: ; CHECK-LABEL: test_iequll:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequll:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzd r3, r3
; CHECK-BE-NEXT: rldicl r3, r3, 58, 63
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequll:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzd r3, r3
; CHECK-LE-NEXT: rldicl r3, r3, 58, 63
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, %b %cmp = icmp eq i64 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequll_sext(i64 %a, i64 %b) { define signext i32 @test_iequll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_iequll_sext: ; CHECK-LABEL: test_iequll_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequll_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequll_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, %b %cmp = icmp eq i64 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequll_z(i64 %a) { define signext i32 @test_iequll_z(i64 %a) {
; CHECK-LABEL: test_iequll_z: ; CHECK-LABEL: test_iequll_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequll_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzd r3, r3
; CHECK-BE-NEXT: rldicl r3, r3, 58, 63
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequll_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzd r3, r3
; CHECK-LE-NEXT: rldicl r3, r3, 58, 63
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, 0 %cmp = icmp eq i64 %a, 0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequll_sext_z(i64 %a) { define signext i32 @test_iequll_sext_z(i64 %a) {
; CHECK-LABEL: test_iequll_sext_z: ; CHECK-LABEL: test_iequll_sext_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequll_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequll_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, 0 %cmp = icmp eq i64 %a, 0
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_iequll_store(i64 %a, i64 %b) { define void @test_iequll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_iequll_store: ; CHECK-LABEL: test_iequll_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequll_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: cntlzd r3, r3
; CHECK-BE-NEXT: rldicl r3, r3, 58, 63
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequll_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzd r3, r3
; CHECK-LE-NEXT: rldicl r3, r3, 58, 63
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, %b %cmp = icmp eq i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_iequll_sext_store(i64 %a, i64 %b) { define void @test_iequll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_iequll_sext_store: ; CHECK-LABEL: test_iequll_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequll_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequll_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, %b %cmp = icmp eq i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_iequll_z_store(i64 %a) { define void @test_iequll_z_store(i64 %a) {
; CHECK-LABEL: test_iequll_z_store: ; CHECK-LABEL: test_iequll_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequll_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzd r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: rldicl r3, r3, 58, 63
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequll_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzd r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 58, 63
; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, 0 %cmp = icmp eq i64 %a, 0
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_iequll_sext_z_store(i64 %a) { define void @test_iequll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_iequll_sext_z_store: ; CHECK-LABEL: test_iequll_sext_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequll_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequll_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, 0 %cmp = icmp eq i64 %a, 0
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesiequs.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; ModuleID = 'ComparisonTestCases/testComparesiequs.c' ; ModuleID = 'ComparisonTestCases/testComparesiequs.c'
@glob = common local_unnamed_addr global i16 0, align 2 @glob = common local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequs(i16 zeroext %a, i16 zeroext %b) { define signext i32 @test_iequs(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_iequs: ; CHECK-LABEL: test_iequs:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequs:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequs:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i16 %a, %b %cmp = icmp eq i16 %a, %b
%conv2 = zext i1 %cmp to i32 %conv2 = zext i1 %cmp to i32
ret i32 %conv2 ret i32 %conv2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequs_sext(i16 zeroext %a, i16 zeroext %b) { define signext i32 @test_iequs_sext(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_iequs_sext: ; CHECK-LABEL: test_iequs_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequs_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequs_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i16 %a, %b %cmp = icmp eq i16 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequs_z(i16 zeroext %a) { define signext i32 @test_iequs_z(i16 zeroext %a) {
; CHECK-LABEL: test_iequs_z: ; CHECK-LABEL: test_iequs_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequs_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequs_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i16 %a, 0 %cmp = icmp eq i16 %a, 0
%conv1 = zext i1 %cmp to i32 %conv1 = zext i1 %cmp to i32
ret i32 %conv1 ret i32 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequs_sext_z(i16 zeroext %a) { define signext i32 @test_iequs_sext_z(i16 zeroext %a) {
; CHECK-LABEL: test_iequs_sext_z: ; CHECK-LABEL: test_iequs_sext_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequs_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequs_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i16 %a, 0 %cmp = icmp eq i16 %a, 0
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_iequs_store(i16 zeroext %a, i16 zeroext %b) { define void @test_iequs_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_iequs_store: ; CHECK-LABEL: test_iequs_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequs_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequs_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i16 %a, %b %cmp = icmp eq i16 %a, %b
%conv3 = zext i1 %cmp to i16 %conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2 store i16 %conv3, i16* @glob, align 2
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_iequs_sext_store(i16 zeroext %a, i16 zeroext %b) { define void @test_iequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_iequs_sext_store: ; CHECK-LABEL: test_iequs_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequs_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequs_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i16 %a, %b %cmp = icmp eq i16 %a, %b
%conv3 = sext i1 %cmp to i16 %conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2 store i16 %conv3, i16* @glob, align 2
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_iequs_z_store(i16 zeroext %a) { define void @test_iequs_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_iequs_z_store: ; CHECK-LABEL: test_iequs_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: sth r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequs_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequs_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: sth r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i16 %a, 0 %cmp = icmp eq i16 %a, 0
%conv2 = zext i1 %cmp to i16 %conv2 = zext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2 store i16 %conv2, i16* @glob, align 2
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_iequs_sext_z_store(i16 zeroext %a) { define void @test_iequs_sext_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_iequs_sext_z_store: ; CHECK-LABEL: test_iequs_sext_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: sth r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequs_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequs_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: sth r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i16 %a, 0 %cmp = icmp eq i16 %a, 0
%conv2 = sext i1 %cmp to i16 %conv2 = sext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2 store i16 %conv2, i16* @glob, align 2
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesigesc.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i8 0, align 1 @glob = common local_unnamed_addr global i8 0, align 1
define signext i32 @test_igesc(i8 signext %a, i8 signext %b) { define signext i32 @test_igesc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igesc: ; CHECK-LABEL: test_igesc:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesc:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesc:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i8 %a, %b %cmp = icmp sge i8 %a, %b
%conv2 = zext i1 %cmp to i32 %conv2 = zext i1 %cmp to i32
ret i32 %conv2 ret i32 %conv2
} }
define signext i32 @test_igesc_sext(i8 signext %a, i8 signext %b) { define signext i32 @test_igesc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igesc_sext: ; CHECK-LABEL: test_igesc_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesc_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesc_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i8 %a, %b %cmp = icmp sge i8 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
define void @test_igesc_store(i8 signext %a, i8 signext %b) { define void @test_igesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igesc_store: ; CHECK-LABEL: test_igesc_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesc_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesc_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: stb r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i8 %a, %b %cmp = icmp sge i8 %a, %b
%conv3 = zext i1 %cmp to i8 %conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1 store i8 %conv3, i8* @glob, align 1
ret void ret void
} }
define void @test_igesc_sext_store(i8 signext %a, i8 signext %b) { define void @test_igesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igesc_sext_store: ; CHECK-LABEL: test_igesc_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesc_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesc_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: stb r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i8 %a, %b %cmp = icmp sge i8 %a, %b
%conv3 = sext i1 %cmp to i8 %conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1 store i8 %conv3, i8* @glob, align 1
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesigesi.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i32 0, align 4 @glob = common local_unnamed_addr global i32 0, align 4
define signext i32 @test_igesi(i32 signext %a, i32 signext %b) { define signext i32 @test_igesi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igesi: ; CHECK-LABEL: test_igesi:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesi:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesi:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i32 %a, %b %cmp = icmp sge i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define signext i32 @test_igesi_sext(i32 signext %a, i32 signext %b) { define signext i32 @test_igesi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igesi_sext: ; CHECK-LABEL: test_igesi_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesi_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesi_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i32 %a, %b %cmp = icmp sge i32 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
define void @test_igesi_store(i32 signext %a, i32 signext %b) { define void @test_igesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igesi_store: ; CHECK-LABEL: test_igesi_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesi_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesi_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i32 %a, %b %cmp = icmp sge i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4 store i32 %conv, i32* @glob, align 4
ret void ret void
} }
define void @test_igesi_sext_store(i32 signext %a, i32 signext %b) { define void @test_igesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igesi_sext_store: ; CHECK-LABEL: test_igesi_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesi_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesi_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i32 %a, %b %cmp = icmp sge i32 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4 store i32 %sub, i32* @glob, align 4
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesigesll.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i64 0, align 8 @glob = common local_unnamed_addr global i64 0, align 8
define signext i32 @test_igesll(i64 %a, i64 %b) { define signext i32 @test_igesll(i64 %a, i64 %b) {
; CHECK-LABEL: test_igesll: ; CHECK-LABEL: test_igesll:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r3, 63 ; CHECK-NEXT: sradi r5, r3, 63
; CHECK-NEXT: rldicl r6, r4, 1, 63 ; CHECK-NEXT: rldicl r6, r4, 1, 63
; CHECK-NEXT: subfc r3, r4, r3 ; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: adde r3, r5, r6 ; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesll:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r3, 63
; CHECK-BE-NEXT: rldicl r6, r4, 1, 63
; CHECK-BE-NEXT: subfc r3, r4, r3
; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesll:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r3, 63
; CHECK-LE-NEXT: rldicl r6, r4, 1, 63
; CHECK-LE-NEXT: subfc r3, r4, r3
; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i64 %a, %b %cmp = icmp sge i64 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define signext i32 @test_igesll_sext(i64 %a, i64 %b) { define signext i32 @test_igesll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_igesll_sext: ; CHECK-LABEL: test_igesll_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r3, 63 ; CHECK-NEXT: sradi r5, r3, 63
; CHECK-NEXT: rldicl r6, r4, 1, 63 ; CHECK-NEXT: rldicl r6, r4, 1, 63
; CHECK-NEXT: subfc r3, r4, r3 ; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: adde r3, r5, r6 ; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesll_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r3, 63
; CHECK-BE-NEXT: rldicl r6, r4, 1, 63
; CHECK-BE-NEXT: subfc r3, r4, r3
; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesll_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r3, 63
; CHECK-LE-NEXT: rldicl r6, r4, 1, 63
; CHECK-LE-NEXT: subfc r3, r4, r3
; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i64 %a, %b %cmp = icmp sge i64 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
define signext i32 @test_igesll_z(i64 %a) { define signext i32 @test_igesll_z(i64 %a) {
; CHECK-LABEL: test_igesll_z: ; CHECK-LABEL: test_igesll_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: not r3, r3 ; CHECK-NEXT: not r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesll_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: not r3, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesll_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: not r3, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sgt i64 %a, -1 %cmp = icmp sgt i64 %a, -1
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define signext i32 @test_igesll_sext_z(i64 %a) { define signext i32 @test_igesll_sext_z(i64 %a) {
; CHECK-LABEL: test_igesll_sext_z: ; CHECK-LABEL: test_igesll_sext_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r3, r3, 63 ; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: not r3, r3 ; CHECK-NEXT: not r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesll_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r3, r3, 63
; CHECK-BE-NEXT: not r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesll_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r3, r3, 63
; CHECK-LE-NEXT: not r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sgt i64 %a, -1 %cmp = icmp sgt i64 %a, -1
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
define void @test_igesll_store(i64 %a, i64 %b) { define void @test_igesll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_igesll_store: ; CHECK-LABEL: test_igesll_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK: sradi r6, r3, 63 ; CHECK-NEXT: sradi r6, r3, 63
; CHECK: subfc r3, r4, r3 ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK: rldicl r3, r4, 1, 63 ; CHECK-NEXT: subfc r3, r4, r3
; CHECK: adde r3, r6, r3 ; CHECK-NEXT: rldicl r3, r4, 1, 63
; CHECK: std r3 ; CHECK-NEXT: adde r3, r6, r3
; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesll_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sradi r6, r3, 63
; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-BE-NEXT: subfc r3, r4, r3
; CHECK-BE-NEXT: rldicl r3, r4, 1, 63
; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: std r3, 0(r5)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesll_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r3, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subfc r3, r4, r3
; CHECK-LE-NEXT: rldicl r3, r4, 1, 63
; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i64 %a, %b %cmp = icmp sge i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
define void @test_igesll_sext_store(i64 %a, i64 %b) { define void @test_igesll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_igesll_sext_store: ; CHECK-LABEL: test_igesll_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r6, r3, 63 ; CHECK-NEXT: sradi r6, r3, 63
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: subfc r3, r4, r3 ; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: rldicl r3, r4, 1, 63 ; CHECK-NEXT: rldicl r3, r4, 1, 63
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: adde r3, r6, r3 ; CHECK-NEXT: adde r3, r6, r3
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesll_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r6, r3, 63
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: subfc r3, r4, r3
; CHECK-BE-NEXT: rldicl r3, r4, 1, 63
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesll_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r3, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subfc r3, r4, r3
; CHECK-LE-NEXT: rldicl r3, r4, 1, 63
; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i64 %a, %b %cmp = icmp sge i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
define void @test_igesll_z_store(i64 %a) { define void @test_igesll_z_store(i64 %a) {
; CHECK-LABEL: test_igesll_z_store: ; CHECK-LABEL: test_igesll_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: not r3, r3 ; CHECK-NEXT: not r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesll_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: not r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesll_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: not r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sgt i64 %a, -1 %cmp = icmp sgt i64 %a, -1
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
define void @test_igesll_sext_z_store(i64 %a) { define void @test_igesll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_igesll_sext_z_store: ; CHECK-LABEL: test_igesll_sext_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: not r3, r3 ; CHECK-NEXT: not r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: sradi r3, r3, 63 ; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: std r3, ; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesll_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: not r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: sradi r3, r3, 63
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesll_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: not r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: sradi r3, r3, 63
; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sgt i64 %a, -1 %cmp = icmp sgt i64 %a, -1
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesigess.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i16 0, align 2 @glob = common local_unnamed_addr global i16 0, align 2
define signext i32 @test_igess(i16 signext %a, i16 signext %b) { define signext i32 @test_igess(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igess: ; CHECK-LABEL: test_igess:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igess:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igess:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i16 %a, %b %cmp = icmp sge i16 %a, %b
%conv2 = zext i1 %cmp to i32 %conv2 = zext i1 %cmp to i32
ret i32 %conv2 ret i32 %conv2
} }
define signext i32 @test_igess_sext(i16 signext %a, i16 signext %b) { define signext i32 @test_igess_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igess_sext: ; CHECK-LABEL: test_igess_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igess_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igess_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i16 %a, %b %cmp = icmp sge i16 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
define void @test_igess_store(i16 signext %a, i16 signext %b) { define void @test_igess_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igess_store: ; CHECK-LABEL: test_igess_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igess_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igess_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i16 %a, %b %cmp = icmp sge i16 %a, %b
%conv3 = zext i1 %cmp to i16 %conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2 store i16 %conv3, i16* @glob, align 2
ret void ret void
} }
define void @test_igess_sext_store(i16 signext %a, i16 signext %b) { define void @test_igess_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igess_sext_store: ; CHECK-LABEL: test_igess_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igess_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igess_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i16 %a, %b %cmp = icmp sge i16 %a, %b
%conv3 = sext i1 %cmp to i16 %conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2 store i16 %conv3, i16* @glob, align 2
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesigtsc.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i8 0, align 1 @glob = common local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtsc(i8 signext %a, i8 signext %b) { define signext i32 @test_igtsc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igtsc: ; CHECK-LABEL: test_igtsc:
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llvm/trunk/test/CodeGen/PowerPC/testComparesigtsi.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i32 0, align 4 @glob = common local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtsi(i32 signext %a, i32 signext %b) { define signext i32 @test_igtsi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igtsi: ; CHECK-LABEL: test_igtsi:
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llvm/trunk/test/CodeGen/PowerPC/testComparesigtsll.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i64 0, align 8 @glob = common local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtsll(i64 %a, i64 %b) { define signext i32 @test_igtsll(i64 %a, i64 %b) {
; CHECK-LABEL: test_igtsll: ; CHECK-LABEL: test_igtsll:
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llvm/trunk/test/CodeGen/PowerPC/testComparesigtss.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i16 0, align 2 @glob = common local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtss(i16 signext %a, i16 signext %b) { define signext i32 @test_igtss(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igtss: ; CHECK-LABEL: test_igtss:
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llvm/trunk/test/CodeGen/PowerPC/testComparesigtuc.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i8 0, align 1 @glob = common local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtuc(i8 zeroext %a, i8 zeroext %b) { define signext i32 @test_igtuc(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_igtuc: ; CHECK-LABEL: test_igtuc:
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llvm/trunk/test/CodeGen/PowerPC/testComparesigtui.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i32 0, align 4 @glob = common local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtui(i32 zeroext %a, i32 zeroext %b) { define signext i32 @test_igtui(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_igtui: ; CHECK-LABEL: test_igtui:
▲ Show 20 Lines • Show All 103 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/PowerPC/testComparesigtus.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i16 0, align 2 @glob = common local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtus(i16 zeroext %a, i16 zeroext %b) { define signext i32 @test_igtus(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_igtus: ; CHECK-LABEL: test_igtus:
▲ Show 20 Lines • Show All 105 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/PowerPC/testComparesilesc.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i8 0, align 1 @glob = common local_unnamed_addr global i8 0, align 1
define signext i32 @test_ilesc(i8 signext %a, i8 signext %b) { define signext i32 @test_ilesc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ilesc: ; CHECK-LABEL: test_ilesc:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesc:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ilesc:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i8 %a, %b %cmp = icmp sle i8 %a, %b
%conv2 = zext i1 %cmp to i32 %conv2 = zext i1 %cmp to i32
ret i32 %conv2 ret i32 %conv2
} }
define signext i32 @test_ilesc_sext(i8 signext %a, i8 signext %b) { define signext i32 @test_ilesc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ilesc_sext: ; CHECK-LABEL: test_ilesc_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesc_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ilesc_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i8 %a, %b %cmp = icmp sle i8 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
define void @test_ilesc_store(i8 signext %a, i8 signext %b) { define void @test_ilesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ilesc_store: ; CHECK-LABEL: test_ilesc_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesc_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ilesc_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: stb r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i8 %a, %b %cmp = icmp sle i8 %a, %b
%conv3 = zext i1 %cmp to i8 %conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1 store i8 %conv3, i8* @glob, align 1
ret void ret void
} }
define void @test_ilesc_sext_store(i8 signext %a, i8 signext %b) { define void @test_ilesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ilesc_sext_store: ; CHECK-LABEL: test_ilesc_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesc_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ilesc_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: stb r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i8 %a, %b %cmp = icmp sle i8 %a, %b
%conv3 = sext i1 %cmp to i8 %conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1 store i8 %conv3, i8* @glob, align 1
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesilesi.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i32 0, align 4 @glob = common local_unnamed_addr global i32 0, align 4
define signext i32 @test_ilesi(i32 signext %a, i32 signext %b) { define signext i32 @test_ilesi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ilesi: ; CHECK-LABEL: test_ilesi:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesi:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ilesi:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i32 %a, %b %cmp = icmp sle i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define signext i32 @test_ilesi_sext(i32 signext %a, i32 signext %b) { define signext i32 @test_ilesi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ilesi_sext: ; CHECK-LABEL: test_ilesi_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesi_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ilesi_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i32 %a, %b %cmp = icmp sle i32 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
define void @test_ilesi_store(i32 signext %a, i32 signext %b) { define void @test_ilesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ilesi_store: ; CHECK-LABEL: test_ilesi_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesi_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ilesi_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i32 %a, %b %cmp = icmp sle i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4 store i32 %conv, i32* @glob, align 4
ret void ret void
} }
define void @test_ilesi_sext_store(i32 signext %a, i32 signext %b) { define void @test_ilesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ilesi_sext_store: ; CHECK-LABEL: test_ilesi_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesi_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ilesi_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i32 %a, %b %cmp = icmp sle i32 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4 store i32 %sub, i32* @glob, align 4
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesilesll.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i64 0, align 8 @glob = common local_unnamed_addr global i64 0, align 8
define signext i32 @test_ilesll(i64 %a, i64 %b) { define signext i32 @test_ilesll(i64 %a, i64 %b) {
; CHECK-LABEL: test_ilesll: ; CHECK-LABEL: test_ilesll:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r4, 63 ; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63 ; CHECK-NEXT: rldicl r6, r3, 1, 63
; CHECK-NEXT: subfc r3, r3, r4 ; CHECK-NEXT: subfc r3, r3, r4
; CHECK-NEXT: adde r3, r5, r6 ; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesll:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r4, 63
; CHECK-BE-NEXT: rldicl r6, r3, 1, 63
; CHECK-BE-NEXT: subfc r3, r3, r4
; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ilesll:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r4, 63
; CHECK-LE-NEXT: rldicl r6, r3, 1, 63
; CHECK-LE-NEXT: subfc r3, r3, r4
; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i64 %a, %b %cmp = icmp sle i64 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define signext i32 @test_ilesll_sext(i64 %a, i64 %b) { define signext i32 @test_ilesll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_ilesll_sext: ; CHECK-LABEL: test_ilesll_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r4, 63 ; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63 ; CHECK-NEXT: rldicl r6, r3, 1, 63
; CHECK-NEXT: subfc r3, r3, r4 ; CHECK-NEXT: subfc r3, r3, r4
; CHECK-NEXT: adde r3, r5, r6 ; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesll_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r4, 63
; CHECK-BE-NEXT: rldicl r6, r3, 1, 63
; CHECK-BE-NEXT: subfc r3, r3, r4
; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ilesll_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r4, 63
; CHECK-LE-NEXT: rldicl r6, r3, 1, 63
; CHECK-LE-NEXT: subfc r3, r3, r4
; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i64 %a, %b %cmp = icmp sle i64 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
define signext i32 @test_ilesll_z(i64 %a) { define signext i32 @test_ilesll_z(i64 %a) {
; CHECK-LABEL: test_ilesll_z: ; CHECK-LABEL: test_ilesll_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi r4, r3, -1 ; CHECK-NEXT: addi r4, r3, -1
; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesll_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addi r4, r3, -1
; CHECK-BE-NEXT: or r3, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ilesll_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addi r4, r3, -1
; CHECK-LE-NEXT: or r3, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp slt i64 %a, 1 %cmp = icmp slt i64 %a, 1
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define signext i32 @test_ilesll_sext_z(i64 %a) { define signext i32 @test_ilesll_sext_z(i64 %a) {
; CHECK-LABEL: test_ilesll_sext_z: ; CHECK-LABEL: test_ilesll_sext_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi r4, r3, -1 ; CHECK-NEXT: addi r4, r3, -1
; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: sradi r3, r3, 63 ; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesll_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addi r4, r3, -1
; CHECK-BE-NEXT: or r3, r4, r3
; CHECK-BE-NEXT: sradi r3, r3, 63
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ilesll_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addi r4, r3, -1
; CHECK-LE-NEXT: or r3, r4, r3
; CHECK-LE-NEXT: sradi r3, r3, 63
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp slt i64 %a, 1 %cmp = icmp slt i64 %a, 1
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
define void @test_ilesll_store(i64 %a, i64 %b) { define void @test_ilesll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_ilesll_store: ; CHECK-LABEL: test_ilesll_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sradi r6, r4, 63 ; CHECK-NEXT: sradi r6, r4, 63
; CHECK-NEXT: ld r5, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: subfc r4, r3, r4 ; CHECK-NEXT: subfc r4, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: adde r3, r6, r3 ; CHECK-NEXT: adde r3, r6, r3
; CHECK-NEXT: std r3, 0(r5) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesll_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sradi r6, r4, 63
; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-BE-NEXT: subfc r4, r3, r4
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: std r3, 0(r5)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ilesll_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r4, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subfc r4, r3, r4
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i64 %a, %b %cmp = icmp sle i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
define void @test_ilesll_sext_store(i64 %a, i64 %b) { define void @test_ilesll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_ilesll_sext_store: ; CHECK-LABEL: test_ilesll_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r6, r4, 63 ; CHECK-NEXT: sradi r6, r4, 63
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: subfc r4, r3, r4 ; CHECK-NEXT: subfc r4, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: adde r3, r6, r3 ; CHECK-NEXT: adde r3, r6, r3
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesll_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r6, r4, 63
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: subfc r4, r3, r4
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ilesll_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r4, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subfc r4, r3, r4
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i64 %a, %b %cmp = icmp sle i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
define void @test_ilesll_z_store(i64 %a) { define void @test_ilesll_z_store(i64 %a) {
; CHECK-LABEL: test_ilesll_z_store: ; CHECK-LABEL: test_ilesll_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addi r5, r3, -1 ; CHECK-NEXT: addi r5, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: or r3, r5, r3 ; CHECK-NEXT: or r3, r5, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesll_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: addi r5, r3, -1
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: or r3, r5, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ilesll_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addi r5, r3, -1
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: or r3, r5, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp slt i64 %a, 1 %cmp = icmp slt i64 %a, 1
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
define void @test_ilesll_sext_z_store(i64 %a) { define void @test_ilesll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_ilesll_sext_z_store: ; CHECK-LABEL: test_ilesll_sext_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addi r5, r3, -1 ; CHECK-NEXT: addi r5, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: or r3, r5, r3 ; CHECK-NEXT: or r3, r5, r3
; CHECK-NEXT: sradi r3, r3, 63 ; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesll_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: addi r5, r3, -1
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: or r3, r5, r3
; CHECK-BE-NEXT: sradi r3, r3, 63
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ilesll_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addi r5, r3, -1
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: or r3, r5, r3
; CHECK-LE-NEXT: sradi r3, r3, 63
; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp slt i64 %a, 1 %cmp = icmp slt i64 %a, 1
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesiless.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i16 0, align 2 @glob = common local_unnamed_addr global i16 0, align 2
define signext i32 @test_iless(i16 signext %a, i16 signext %b) { define signext i32 @test_iless(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iless: ; CHECK-LABEL: test_iless:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iless:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iless:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i16 %a, %b %cmp = icmp sle i16 %a, %b
%conv2 = zext i1 %cmp to i32 %conv2 = zext i1 %cmp to i32
ret i32 %conv2 ret i32 %conv2
} }
define signext i32 @test_iless_sext(i16 signext %a, i16 signext %b) { define signext i32 @test_iless_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iless_sext: ; CHECK-LABEL: test_iless_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iless_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iless_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i16 %a, %b %cmp = icmp sle i16 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
define void @test_iless_store(i16 signext %a, i16 signext %b) { define void @test_iless_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iless_store: ; CHECK-LABEL: test_iless_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iless_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iless_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i16 %a, %b %cmp = icmp sle i16 %a, %b
%conv3 = zext i1 %cmp to i16 %conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2 store i16 %conv3, i16* @glob, align 2
ret void ret void
} }
define void @test_iless_sext_store(i16 signext %a, i16 signext %b) { define void @test_iless_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iless_sext_store: ; CHECK-LABEL: test_iless_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iless_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iless_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i16 %a, %b %cmp = icmp sle i16 %a, %b
%conv3 = sext i1 %cmp to i16 %conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2 store i16 %conv3, i16* @glob, align 2
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesinesc.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i8 0, align 1 @glob = common local_unnamed_addr global i8 0, align 1
define signext i32 @test_inesc(i8 signext %a, i8 signext %b) { define signext i32 @test_inesc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_inesc: ; CHECK-LABEL: test_inesc:
; CHECK: xor r3, r3, r4 ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_inesc:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_inesc:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i8 %a, %b %cmp = icmp ne i8 %a, %b
%conv2 = zext i1 %cmp to i32 %conv2 = zext i1 %cmp to i32
ret i32 %conv2 ret i32 %conv2
} }
define signext i32 @test_inesc_sext(i8 signext %a, i8 signext %b) { define signext i32 @test_inesc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_inesc_sext: ; CHECK-LABEL: test_inesc_sext:
; CHECK: xor r3, r3, r4 ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_inesc_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_inesc_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i8 %a, %b %cmp = icmp ne i8 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
define signext i32 @test_inesc_z(i8 signext %a) { define signext i32 @test_inesc_z(i8 signext %a) {
; CHECK-LABEL: test_inesc_z: ; CHECK-LABEL: test_inesc_z:
; CHECK: cntlzw r3, r3 ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_inesc_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_inesc_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i8 %a, 0 %cmp = icmp ne i8 %a, 0
%conv1 = zext i1 %cmp to i32 %conv1 = zext i1 %cmp to i32
ret i32 %conv1 ret i32 %conv1
} }
define signext i32 @test_inesc_sext_z(i8 signext %a) { define signext i32 @test_inesc_sext_z(i8 signext %a) {
; CHECK-LABEL: test_inesc_sext_z: ; CHECK-LABEL: test_inesc_sext_z:
; CHECK: cntlzw r3, r3 ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_inesc_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_inesc_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i8 %a, 0 %cmp = icmp ne i8 %a, 0
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
define void @test_inesc_store(i8 signext %a, i8 signext %b) { define void @test_inesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_inesc_store: ; CHECK-LABEL: test_inesc_store:
; CHECK: xor r3, r3, r4 ; CHECK: # %bb.0: # %entry
; CHECK: cntlzw r3, r3 ; CHECK-NEXT: xor r3, r3, r4
; CHECK: srwi r3, r3, 5 ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK: xori r3, r3, 1 ; CHECK-NEXT: cntlzw r3, r3
; CHECK: stb r3, 0(r4) ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_inesc_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_inesc_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: stb r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i8 %a, %b %cmp = icmp ne i8 %a, %b
%conv3 = zext i1 %cmp to i8 %conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1 store i8 %conv3, i8* @glob, align 1
ret void ret void
} }
define void @test_inesc_sext_store(i8 signext %a, i8 signext %b) { define void @test_inesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_inesc_sext_store: ; CHECK-LABEL: test_inesc_sext_store:
; CHECK: xor r3, r3, r4 ; CHECK: # %bb.0: # %entry
; CHECK: cntlzw r3, r3 ; CHECK-NEXT: xor r3, r3, r4
; CHECK: srwi r3, r3, 5 ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK: xori r3, r3, 1 ; CHECK-NEXT: cntlzw r3, r3
; CHECK: neg r3, r3 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK: stb r3, 0(r4) ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_inesc_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_inesc_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: stb r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i8 %a, %b %cmp = icmp ne i8 %a, %b
%conv3 = sext i1 %cmp to i8 %conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1 store i8 %conv3, i8* @glob, align 1
ret void ret void
} }
define void @test_inesc_z_store(i8 signext %a) { define void @test_inesc_z_store(i8 signext %a) {
; CHECK-LABEL: test_inesc_z_store: ; CHECK-LABEL: test_inesc_z_store:
; CHECK: cntlzw r3, r3 ; CHECK: # %bb.0: # %entry
; CHECK: srwi r3, r3, 5 ; CHECK-NEXT: cntlzw r3, r3
; CHECK: xori r3, r3, 1 ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK: stb r3, 0(r4) ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_inesc_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_inesc_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: stb r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i8 %a, 0 %cmp = icmp ne i8 %a, 0
%conv2 = zext i1 %cmp to i8 %conv2 = zext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1 store i8 %conv2, i8* @glob, align 1
ret void ret void
} }
define void @test_inesc_sext_z_store(i8 signext %a) { define void @test_inesc_sext_z_store(i8 signext %a) {
; CHECK-LABEL: test_inesc_sext_z_store: ; CHECK-LABEL: test_inesc_sext_z_store:
; CHECK: cntlzw r3, r3 ; CHECK: # %bb.0: # %entry
; CHECK: srwi r3, r3, 5 ; CHECK-NEXT: cntlzw r3, r3
; CHECK: xori r3, r3, 1 ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK: neg r3, r3 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK: stb r3, 0(r4) ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stb r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_inesc_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_inesc_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: stb r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i8 %a, 0 %cmp = icmp ne i8 %a, 0
%conv2 = sext i1 %cmp to i8 %conv2 = sext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1 store i8 %conv2, i8* @glob, align 1
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesinesi.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i32 0, align 4 @glob = common local_unnamed_addr global i32 0, align 4
define signext i32 @test_inesi(i32 signext %a, i32 signext %b) { define signext i32 @test_inesi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_inesi: ; CHECK-LABEL: test_inesi:
; CHECK: xor r3, r3, r4 ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_inesi:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_inesi:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i32 %a, %b %cmp = icmp ne i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define signext i32 @test_inesi_sext(i32 signext %a, i32 signext %b) { define signext i32 @test_inesi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_inesi_sext: ; CHECK-LABEL: test_inesi_sext:
; CHECK: xor r3, r3, r4 ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_inesi_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_inesi_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i32 %a, %b %cmp = icmp ne i32 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
define signext i32 @test_inesi_z(i32 signext %a) { define signext i32 @test_inesi_z(i32 signext %a) {
; CHECK-LABEL: test_inesi_z: ; CHECK-LABEL: test_inesi_z:
; CHECK: cntlzw r3, r3 ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_inesi_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_inesi_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i32 %a, 0 %cmp = icmp ne i32 %a, 0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define signext i32 @test_inesi_sext_z(i32 signext %a) { define signext i32 @test_inesi_sext_z(i32 signext %a) {
; CHECK-LABEL: test_inesi_sext_z: ; CHECK-LABEL: test_inesi_sext_z:
; CHECK: cntlzw r3, r3 ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_inesi_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_inesi_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i32 %a, 0 %cmp = icmp ne i32 %a, 0
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
define void @test_inesi_store(i32 signext %a, i32 signext %b) { define void @test_inesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_inesi_store: ; CHECK-LABEL: test_inesi_store:
; CHECK: xor r3, r3, r4 ; CHECK: # %bb.0: # %entry
; CHECK: cntlzw r3, r3 ; CHECK-NEXT: xor r3, r3, r4
; CHECK: srwi r3, r3, 5 ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK: xori r3, r3, 1 ; CHECK-NEXT: cntlzw r3, r3
; CHECK: stw r3, 0(r4) ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_inesi_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_inesi_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i32 %a, %b %cmp = icmp ne i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4 store i32 %conv, i32* @glob, align 4
ret void ret void
} }
define void @test_inesi_sext_store(i32 signext %a, i32 signext %b) { define void @test_inesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_inesi_sext_store: ; CHECK-LABEL: test_inesi_sext_store:
; CHECK: xor r3, r3, r4 ; CHECK: # %bb.0: # %entry
; CHECK: cntlzw r3, r3 ; CHECK-NEXT: xor r3, r3, r4
; CHECK: srwi r3, r3, 5 ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK: xori r3, r3, 1 ; CHECK-NEXT: cntlzw r3, r3
; CHECK: neg r3, r3 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK: stw r3, 0(r4) ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_inesi_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_inesi_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i32 %a, %b %cmp = icmp ne i32 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4 store i32 %sub, i32* @glob, align 4
ret void ret void
} }
define void @test_inesi_z_store(i32 signext %a) { define void @test_inesi_z_store(i32 signext %a) {
; CHECK-LABEL: test_inesi_z_store: ; CHECK-LABEL: test_inesi_z_store:
; CHECK: cntlzw r3, r3 ; CHECK: # %bb.0: # %entry
; CHECK: srwi r3, r3, 5 ; CHECK-NEXT: cntlzw r3, r3
; CHECK: xori r3, r3, 1 ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK: stw r3, 0(r4) ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_inesi_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_inesi_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: stw r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i32 %a, 0 %cmp = icmp ne i32 %a, 0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4 store i32 %conv, i32* @glob, align 4
ret void ret void
} }
define void @test_inesi_sext_z_store(i32 signext %a) { define void @test_inesi_sext_z_store(i32 signext %a) {
; CHECK-LABEL: test_inesi_sext_z_store: ; CHECK-LABEL: test_inesi_sext_z_store:
; CHECK: cntlzw r3, r3 ; CHECK: # %bb.0: # %entry
; CHECK: srwi r3, r3, 5 ; CHECK-NEXT: cntlzw r3, r3
; CHECK: xori r3, r3, 1 ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK: neg r3, r3 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK: stw r3, 0(r4) ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_inesi_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_inesi_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: stw r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i32 %a, 0 %cmp = icmp ne i32 %a, 0
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4 store i32 %sub, i32* @glob, align 4
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesinesll.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i64 0, align 8 @glob = common local_unnamed_addr global i64 0, align 8
define signext i32 @test_inesll(i64 %a, i64 %b) { define signext i32 @test_inesll(i64 %a, i64 %b) {
; CHECK-LABEL: test_inesll: ; CHECK-LABEL: test_inesll:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addic r4, r3, -1 ; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3 ; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_inesll:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: addic r4, r3, -1
; CHECK-BE-NEXT: subfe r3, r4, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_inesll:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addic r4, r3, -1
; CHECK-LE-NEXT: subfe r3, r4, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i64 %a, %b %cmp = icmp ne i64 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define signext i32 @test_inesll_sext(i64 %a, i64 %b) { define signext i32 @test_inesll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_inesll_sext: ; CHECK-LABEL: test_inesll_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_inesll_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: subfic r3, r3, 0
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_inesll_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: subfic r3, r3, 0
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i64 %a, %b %cmp = icmp ne i64 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
define signext i32 @test_inesll_z(i64 %a) { define signext i32 @test_inesll_z(i64 %a) {
; CHECK-LABEL: test_inesll_z: ; CHECK-LABEL: test_inesll_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addic r4, r3, -1 ; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3 ; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_inesll_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addic r4, r3, -1
; CHECK-BE-NEXT: subfe r3, r4, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_inesll_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addic r4, r3, -1
; CHECK-LE-NEXT: subfe r3, r4, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i64 %a, 0 %cmp = icmp ne i64 %a, 0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define signext i32 @test_inesll_sext_z(i64 %a) { define signext i32 @test_inesll_sext_z(i64 %a) {
; CHECK-LABEL: test_inesll_sext_z: ; CHECK-LABEL: test_inesll_sext_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_inesll_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: subfic r3, r3, 0
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_inesll_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: subfic r3, r3, 0
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i64 %a, 0 %cmp = icmp ne i64 %a, 0
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
define void @test_inesll_store(i64 %a, i64 %b) { define void @test_inesll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_inesll_store: ; CHECK-LABEL: test_inesll_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: addic r5, r3, -1 ; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r5, r3 ; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_inesll_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: addic r5, r3, -1
; CHECK-BE-NEXT: subfe r3, r5, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_inesll_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: addic r4, r3, -1
; CHECK-LE-NEXT: subfe r3, r4, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i64 %a, %b %cmp = icmp ne i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
define void @test_inesll_sext_store(i64 %a, i64 %b) { define void @test_inesll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_inesll_sext_store: ; CHECK-LABEL: test_inesll_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_inesll_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: subfic r3, r3, 0
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_inesll_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subfic r3, r3, 0
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i64 %a, %b %cmp = icmp ne i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
define void @test_inesll_z_store(i64 %a) { define void @test_inesll_z_store(i64 %a) {
; CHECK-LABEL: test_inesll_z_store: ; CHECK-LABEL: test_inesll_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addic r5, r3, -1 ; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: subfe r3, r5, r3 ; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_inesll_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: addic r5, r3, -1
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: subfe r3, r5, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_inesll_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addic r5, r3, -1
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: subfe r3, r5, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i64 %a, 0 %cmp = icmp ne i64 %a, 0
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
define void @test_inesll_sext_z_store(i64 %a) { define void @test_inesll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_inesll_sext_z_store: ; CHECK-LABEL: test_inesll_sext_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_inesll_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: subfic r3, r3, 0
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_inesll_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: subfic r3, r3, 0
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i64 %a, 0 %cmp = icmp ne i64 %a, 0
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesiness.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i16 0, align 2 @glob = common local_unnamed_addr global i16 0, align 2
define signext i32 @test_iness(i16 signext %a, i16 signext %b) { define signext i32 @test_iness(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iness: ; CHECK-LABEL: test_iness:
; CHECK: xor r3, r3, r4 ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iness:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iness:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i16 %a, %b %cmp = icmp ne i16 %a, %b
%conv2 = zext i1 %cmp to i32 %conv2 = zext i1 %cmp to i32
ret i32 %conv2 ret i32 %conv2
} }
define signext i32 @test_iness_sext(i16 signext %a, i16 signext %b) { define signext i32 @test_iness_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iness_sext: ; CHECK-LABEL: test_iness_sext:
; CHECK: xor r3, r3, r4 ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iness_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iness_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i16 %a, %b %cmp = icmp ne i16 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
define signext i32 @test_iness_z(i16 signext %a) { define signext i32 @test_iness_z(i16 signext %a) {
; CHECK-LABEL: test_iness_z: ; CHECK-LABEL: test_iness_z:
; CHECK: cntlzw r3, r3 ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iness_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iness_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i16 %a, 0 %cmp = icmp ne i16 %a, 0
%conv1 = zext i1 %cmp to i32 %conv1 = zext i1 %cmp to i32
ret i32 %conv1 ret i32 %conv1
} }
define signext i32 @test_iness_sext_z(i16 signext %a) { define signext i32 @test_iness_sext_z(i16 signext %a) {
; CHECK-LABEL: test_iness_sext_z: ; CHECK-LABEL: test_iness_sext_z:
; CHECK: cntlzw r3, r3 ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iness_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iness_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i16 %a, 0 %cmp = icmp ne i16 %a, 0
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
define void @test_iness_store(i16 signext %a, i16 signext %b) { define void @test_iness_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iness_store: ; CHECK-LABEL: test_iness_store:
; CHECK: xor r3, r3, r4 ; CHECK: # %bb.0: # %entry
; CHECK: cntlzw r3, r3 ; CHECK-NEXT: xor r3, r3, r4
; CHECK: srwi r3, r3, 5 ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK: xori r3, r3, 1 ; CHECK-NEXT: cntlzw r3, r3
; CHECK: sth r3, 0(r4) ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iness_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iness_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i16 %a, %b %cmp = icmp ne i16 %a, %b
%conv3 = zext i1 %cmp to i16 %conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2 store i16 %conv3, i16* @glob, align 2
ret void ret void
} }
define void @test_iness_sext_store(i16 signext %a, i16 signext %b) { define void @test_iness_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iness_sext_store: ; CHECK-LABEL: test_iness_sext_store:
; CHECK: xor r3, r3, r4 ; CHECK: # %bb.0: # %entry
; CHECK: cntlzw r3, r3 ; CHECK-NEXT: xor r3, r3, r4
; CHECK: srwi r3, r3, 5 ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK: xori r3, r3, 1 ; CHECK-NEXT: cntlzw r3, r3
; CHECK: neg r3, r3 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK: sth r3, 0(r4) ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iness_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iness_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i16 %a, %b %cmp = icmp ne i16 %a, %b
%conv3 = sext i1 %cmp to i16 %conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2 store i16 %conv3, i16* @glob, align 2
ret void ret void
} }
define void @test_iness_z_store(i16 signext %a) { define void @test_iness_z_store(i16 signext %a) {
; CHECK-LABEL: test_iness_z_store: ; CHECK-LABEL: test_iness_z_store:
; CHECK: cntlzw r3, r3 ; CHECK: # %bb.0: # %entry
; CHECK: srwi r3, r3, 5 ; CHECK-NEXT: cntlzw r3, r3
; CHECK: xori r3, r3, 1 ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK: sth r3, 0(r4) ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iness_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iness_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: sth r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i16 %a, 0 %cmp = icmp ne i16 %a, 0
%conv2 = zext i1 %cmp to i16 %conv2 = zext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2 store i16 %conv2, i16* @glob, align 2
ret void ret void
} }
define void @test_iness_sext_z_store(i16 signext %a) { define void @test_iness_sext_z_store(i16 signext %a) {
; CHECK-LABEL: test_iness_sext_z_store: ; CHECK-LABEL: test_iness_sext_z_store:
; CHECK: cntlzw r3, r3 ; CHECK: # %bb.0: # %entry
; CHECK: srwi r3, r3, 5 ; CHECK-NEXT: cntlzw r3, r3
; CHECK: xori r3, r3, 1 ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK: neg r3, r3 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK: sth r3, 0(r4) ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sth r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iness_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iness_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: sth r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i16 %a, 0 %cmp = icmp ne i16 %a, 0
%conv2 = sext i1 %cmp to i16 %conv2 = sext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2 store i16 %conv2, i16* @glob, align 2
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesineuc.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i8 0, align 1 @glob = common local_unnamed_addr global i8 0, align 1
define signext i32 @test_ineuc(i8 zeroext %a, i8 zeroext %b) { define signext i32 @test_ineuc(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_ineuc: ; CHECK-LABEL: test_ineuc:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ineuc:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ineuc:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i8 %a, %b %cmp = icmp ne i8 %a, %b
%conv2 = zext i1 %cmp to i32 %conv2 = zext i1 %cmp to i32
ret i32 %conv2 ret i32 %conv2
} }
define signext i32 @test_ineuc_sext(i8 zeroext %a, i8 zeroext %b) { define signext i32 @test_ineuc_sext(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_ineuc_sext: ; CHECK-LABEL: test_ineuc_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ineuc_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ineuc_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i8 %a, %b %cmp = icmp ne i8 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
define signext i32 @test_ineuc_z(i8 zeroext %a) { define signext i32 @test_ineuc_z(i8 zeroext %a) {
; CHECK-LABEL: test_ineuc_z: ; CHECK-LABEL: test_ineuc_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ineuc_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ineuc_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i8 %a, 0 %cmp = icmp ne i8 %a, 0
%conv1 = zext i1 %cmp to i32 %conv1 = zext i1 %cmp to i32
ret i32 %conv1 ret i32 %conv1
} }
define signext i32 @test_ineuc_sext_z(i8 zeroext %a) { define signext i32 @test_ineuc_sext_z(i8 zeroext %a) {
; CHECK-LABEL: test_ineuc_sext_z: ; CHECK-LABEL: test_ineuc_sext_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ineuc_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ineuc_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i8 %a, 0 %cmp = icmp ne i8 %a, 0
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
define void @test_ineuc_store(i8 zeroext %a, i8 zeroext %b) { define void @test_ineuc_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_ineuc_store: ; CHECK-LABEL: test_ineuc_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ineuc_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ineuc_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: stb r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i8 %a, %b %cmp = icmp ne i8 %a, %b
%conv3 = zext i1 %cmp to i8 %conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1 store i8 %conv3, i8* @glob, align 1
ret void ret void
} }
define void @test_ineuc_sext_store(i8 zeroext %a, i8 zeroext %b) { define void @test_ineuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_ineuc_sext_store: ; CHECK-LABEL: test_ineuc_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ineuc_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ineuc_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: stb r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i8 %a, %b %cmp = icmp ne i8 %a, %b
%conv3 = sext i1 %cmp to i8 %conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1 store i8 %conv3, i8* @glob, align 1
ret void ret void
} }
define void @test_ineuc_z_store(i8 zeroext %a) { define void @test_ineuc_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_ineuc_z_store: ; CHECK-LABEL: test_ineuc_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: stb r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ineuc_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ineuc_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: stb r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i8 %a, 0 %cmp = icmp ne i8 %a, 0
%conv2 = zext i1 %cmp to i8 %conv2 = zext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1 store i8 %conv2, i8* @glob, align 1
ret void ret void
} }
define void @test_ineuc_sext_z_store(i8 zeroext %a) { define void @test_ineuc_sext_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_ineuc_sext_z_store: ; CHECK-LABEL: test_ineuc_sext_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: stb r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ineuc_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ineuc_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: stb r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i8 %a, 0 %cmp = icmp ne i8 %a, 0
%conv2 = sext i1 %cmp to i8 %conv2 = sext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1 store i8 %conv2, i8* @glob, align 1
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesineui.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i32 0, align 4 @glob = common local_unnamed_addr global i32 0, align 4
define signext i32 @test_ineui(i32 zeroext %a, i32 zeroext %b) { define signext i32 @test_ineui(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_ineui: ; CHECK-LABEL: test_ineui:
; CHECK: xor r3, r3, r4 ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ineui:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ineui:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i32 %a, %b %cmp = icmp ne i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define signext i32 @test_ineui_sext(i32 zeroext %a, i32 zeroext %b) { define signext i32 @test_ineui_sext(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_ineui_sext: ; CHECK-LABEL: test_ineui_sext:
; CHECK: xor r3, r3, r4 ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ineui_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ineui_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i32 %a, %b %cmp = icmp ne i32 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
define signext i32 @test_ineui_z(i32 zeroext %a) { define signext i32 @test_ineui_z(i32 zeroext %a) {
; CHECK-LABEL: test_ineui_z: ; CHECK-LABEL: test_ineui_z:
; CHECK: cntlzw r3, r3 ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ineui_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ineui_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i32 %a, 0 %cmp = icmp ne i32 %a, 0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define signext i32 @test_ineui_sext_z(i32 zeroext %a) { define signext i32 @test_ineui_sext_z(i32 zeroext %a) {
; CHECK-LABEL: test_ineui_sext_z: ; CHECK-LABEL: test_ineui_sext_z:
; CHECK: cntlzw r3, r3 ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ineui_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ineui_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i32 %a, 0 %cmp = icmp ne i32 %a, 0
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
define void @test_ineui_store(i32 zeroext %a, i32 zeroext %b) { define void @test_ineui_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_ineui_store: ; CHECK-LABEL: test_ineui_store:
; CHECK: xor r3, r3, r4 ; CHECK: # %bb.0: # %entry
; CHECK: cntlzw r3, r3 ; CHECK-NEXT: xor r3, r3, r4
; CHECK: srwi r3, r3, 5 ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK: xori r3, r3, 1 ; CHECK-NEXT: cntlzw r3, r3
; CHECK: stw r3, 0(r4) ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ineui_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ineui_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i32 %a, %b %cmp = icmp ne i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4 store i32 %conv, i32* @glob, align 4
ret void ret void
} }
define void @test_ineui_sext_store(i32 zeroext %a, i32 zeroext %b) { define void @test_ineui_sext_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_ineui_sext_store: ; CHECK-LABEL: test_ineui_sext_store:
; CHECK: xor r3, r3, r4 ; CHECK: # %bb.0: # %entry
; CHECK: cntlzw r3, r3 ; CHECK-NEXT: xor r3, r3, r4
; CHECK: srwi r3, r3, 5 ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK: xori r3, r3, 1 ; CHECK-NEXT: cntlzw r3, r3
; CHECK: neg r3, r3 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK: stw r3, 0(r4) ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ineui_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ineui_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i32 %a, %b %cmp = icmp ne i32 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4 store i32 %sub, i32* @glob, align 4
ret void ret void
} }
define void @test_ineui_z_store(i32 zeroext %a) { define void @test_ineui_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_ineui_z_store: ; CHECK-LABEL: test_ineui_z_store:
; CHECK: cntlzw r3, r3 ; CHECK: # %bb.0: # %entry
; CHECK: srwi r3, r3, 5 ; CHECK-NEXT: cntlzw r3, r3
; CHECK: xori r3, r3, 1 ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK: stw r3, 0(r4) ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ineui_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ineui_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: stw r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i32 %a, 0 %cmp = icmp ne i32 %a, 0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4 store i32 %conv, i32* @glob, align 4
ret void ret void
} }
define void @test_ineui_sext_z_store(i32 zeroext %a) { define void @test_ineui_sext_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_ineui_sext_z_store: ; CHECK-LABEL: test_ineui_sext_z_store:
; CHECK: cntlzw r3, r3 ; CHECK: # %bb.0: # %entry
; CHECK: srwi r3, r3, 5 ; CHECK-NEXT: cntlzw r3, r3
; CHECK: xori r3, r3, 1 ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK: neg r3, r3 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK: stw r3, 0(r4) ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ineui_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ineui_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: stw r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i32 %a, 0 %cmp = icmp ne i32 %a, 0
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4 store i32 %sub, i32* @glob, align 4
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesineull.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i64 0, align 8 @glob = common local_unnamed_addr global i64 0, align 8
define signext i32 @test_ineull(i64 %a, i64 %b) { define signext i32 @test_ineull(i64 %a, i64 %b) {
; CHECK-LABEL: test_ineull: ; CHECK-LABEL: test_ineull:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addic r4, r3, -1 ; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3 ; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ineull:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: addic r4, r3, -1
; CHECK-BE-NEXT: subfe r3, r4, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ineull:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addic r4, r3, -1
; CHECK-LE-NEXT: subfe r3, r4, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i64 %a, %b %cmp = icmp ne i64 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define signext i32 @test_ineull_sext(i64 %a, i64 %b) { define signext i32 @test_ineull_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_ineull_sext: ; CHECK-LABEL: test_ineull_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ineull_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: subfic r3, r3, 0
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ineull_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: subfic r3, r3, 0
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i64 %a, %b %cmp = icmp ne i64 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
define signext i32 @test_ineull_z(i64 %a) { define signext i32 @test_ineull_z(i64 %a) {
; CHECK-LABEL: test_ineull_z: ; CHECK-LABEL: test_ineull_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addic r4, r3, -1 ; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3 ; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ineull_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addic r4, r3, -1
; CHECK-BE-NEXT: subfe r3, r4, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ineull_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addic r4, r3, -1
; CHECK-LE-NEXT: subfe r3, r4, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i64 %a, 0 %cmp = icmp ne i64 %a, 0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define signext i32 @test_ineull_sext_z(i64 %a) { define signext i32 @test_ineull_sext_z(i64 %a) {
; CHECK-LABEL: test_ineull_sext_z: ; CHECK-LABEL: test_ineull_sext_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ineull_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: subfic r3, r3, 0
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ineull_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: subfic r3, r3, 0
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i64 %a, 0 %cmp = icmp ne i64 %a, 0
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
define void @test_ineull_store(i64 %a, i64 %b) { define void @test_ineull_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_ineull_store: ; CHECK-LABEL: test_ineull_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: addic r5, r3, -1 ; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r5, r3 ; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ineull_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: addic r5, r3, -1
; CHECK-BE-NEXT: subfe r3, r5, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ineull_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: addic r4, r3, -1
; CHECK-LE-NEXT: subfe r3, r4, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i64 %a, %b %cmp = icmp ne i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
define void @test_ineull_sext_store(i64 %a, i64 %b) { define void @test_ineull_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_ineull_sext_store: ; CHECK-LABEL: test_ineull_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ineull_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: subfic r3, r3, 0
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ineull_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subfic r3, r3, 0
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i64 %a, %b %cmp = icmp ne i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
define void @test_ineull_z_store(i64 %a) { define void @test_ineull_z_store(i64 %a) {
; CHECK-LABEL: test_ineull_z_store: ; CHECK-LABEL: test_ineull_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addic r5, r3, -1 ; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: subfe r3, r5, r3 ; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ineull_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: addic r5, r3, -1
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: subfe r3, r5, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ineull_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addic r5, r3, -1
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: subfe r3, r5, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i64 %a, 0 %cmp = icmp ne i64 %a, 0
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
define void @test_ineull_sext_z_store(i64 %a) { define void @test_ineull_sext_z_store(i64 %a) {
; CHECK-LABEL: test_ineull_sext_z_store: ; CHECK-LABEL: test_ineull_sext_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ineull_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: subfic r3, r3, 0
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ineull_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: subfic r3, r3, 0
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i64 %a, 0 %cmp = icmp ne i64 %a, 0
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesineus.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i16 0, align 2 @glob = common local_unnamed_addr global i16 0, align 2
define signext i32 @test_ineus(i16 zeroext %a, i16 zeroext %b) { define signext i32 @test_ineus(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_ineus: ; CHECK-LABEL: test_ineus:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ineus:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ineus:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i16 %a, %b %cmp = icmp ne i16 %a, %b
%conv2 = zext i1 %cmp to i32 %conv2 = zext i1 %cmp to i32
ret i32 %conv2 ret i32 %conv2
} }
define signext i32 @test_ineus_sext(i16 zeroext %a, i16 zeroext %b) { define signext i32 @test_ineus_sext(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_ineus_sext: ; CHECK-LABEL: test_ineus_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ineus_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ineus_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i16 %a, %b %cmp = icmp ne i16 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
define signext i32 @test_ineus_z(i16 zeroext %a) { define signext i32 @test_ineus_z(i16 zeroext %a) {
; CHECK-LABEL: test_ineus_z: ; CHECK-LABEL: test_ineus_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ineus_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ineus_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i16 %a, 0 %cmp = icmp ne i16 %a, 0
%conv1 = zext i1 %cmp to i32 %conv1 = zext i1 %cmp to i32
ret i32 %conv1 ret i32 %conv1
} }
define signext i32 @test_ineus_sext_z(i16 zeroext %a) { define signext i32 @test_ineus_sext_z(i16 zeroext %a) {
; CHECK-LABEL: test_ineus_sext_z: ; CHECK-LABEL: test_ineus_sext_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ineus_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ineus_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i16 %a, 0 %cmp = icmp ne i16 %a, 0
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
define void @test_ineus_store(i16 zeroext %a, i16 zeroext %b) { define void @test_ineus_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_ineus_store: ; CHECK-LABEL: test_ineus_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ineus_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ineus_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i16 %a, %b %cmp = icmp ne i16 %a, %b
%conv3 = zext i1 %cmp to i16 %conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2 store i16 %conv3, i16* @glob, align 2
ret void ret void
} }
define void @test_ineus_sext_store(i16 zeroext %a, i16 zeroext %b) { define void @test_ineus_sext_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_ineus_sext_store: ; CHECK-LABEL: test_ineus_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ineus_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ineus_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i16 %a, %b %cmp = icmp ne i16 %a, %b
%conv3 = sext i1 %cmp to i16 %conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2 store i16 %conv3, i16* @glob, align 2
ret void ret void
} }
define void @test_ineus_z_store(i16 zeroext %a) { define void @test_ineus_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_ineus_z_store: ; CHECK-LABEL: test_ineus_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: sth r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ineus_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ineus_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: sth r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i16 %a, 0 %cmp = icmp ne i16 %a, 0
%conv2 = zext i1 %cmp to i16 %conv2 = zext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2 store i16 %conv2, i16* @glob, align 2
ret void ret void
} }
define void @test_ineus_sext_z_store(i16 zeroext %a) { define void @test_ineus_sext_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_ineus_sext_z_store: ; CHECK-LABEL: test_ineus_sext_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: sth r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ineus_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ineus_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: sth r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i16 %a, 0 %cmp = icmp ne i16 %a, 0
%conv2 = sext i1 %cmp to i16 %conv2 = sext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2 store i16 %conv2, i16* @glob, align 2
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testCompareslleqsc.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; ModuleID = 'ComparisonTestCases/testCompareslleqsc.c' ; ModuleID = 'ComparisonTestCases/testCompareslleqsc.c'
@glob = common local_unnamed_addr global i8 0, align 1 @glob = common local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqsc(i8 signext %a, i8 signext %b) { define i64 @test_lleqsc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lleqsc: ; CHECK-LABEL: test_lleqsc:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsc:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqsc:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i8 %a, %b %cmp = icmp eq i8 %a, %b
%conv3 = zext i1 %cmp to i64 %conv3 = zext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqsc_sext(i8 signext %a, i8 signext %b) { define i64 @test_lleqsc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lleqsc_sext: ; CHECK-LABEL: test_lleqsc_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsc_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqsc_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i8 %a, %b %cmp = icmp eq i8 %a, %b
%conv3 = sext i1 %cmp to i64 %conv3 = sext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqsc_z(i8 signext %a) { define i64 @test_lleqsc_z(i8 signext %a) {
; CHECK-LABEL: test_lleqsc_z: ; CHECK-LABEL: test_lleqsc_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsc_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqsc_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i8 %a, 0 %cmp = icmp eq i8 %a, 0
%conv2 = zext i1 %cmp to i64 %conv2 = zext i1 %cmp to i64
ret i64 %conv2 ret i64 %conv2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqsc_sext_z(i8 signext %a) { define i64 @test_lleqsc_sext_z(i8 signext %a) {
; CHECK-LABEL: test_lleqsc_sext_z: ; CHECK-LABEL: test_lleqsc_sext_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsc_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqsc_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i8 %a, 0 %cmp = icmp eq i8 %a, 0
%conv2 = sext i1 %cmp to i64 %conv2 = sext i1 %cmp to i64
ret i64 %conv2 ret i64 %conv2
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_lleqsc_store(i8 signext %a, i8 signext %b) { define void @test_lleqsc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lleqsc_store: ; CHECK-LABEL: test_lleqsc_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsc_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqsc_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: stb r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i8 %a, %b %cmp = icmp eq i8 %a, %b
%conv3 = zext i1 %cmp to i8 %conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1 store i8 %conv3, i8* @glob, align 1
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_lleqsc_sext_store(i8 signext %a, i8 signext %b) { define void @test_lleqsc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lleqsc_sext_store: ; CHECK-LABEL: test_lleqsc_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsc_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqsc_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: stb r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i8 %a, %b %cmp = icmp eq i8 %a, %b
%conv3 = sext i1 %cmp to i8 %conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1 store i8 %conv3, i8* @glob, align 1
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_lleqsc_z_store(i8 signext %a) { define void @test_lleqsc_z_store(i8 signext %a) {
; CHECK-LABEL: test_lleqsc_z_store: ; CHECK-LABEL: test_lleqsc_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: stb r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsc_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqsc_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: stb r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i8 %a, 0 %cmp = icmp eq i8 %a, 0
%conv2 = zext i1 %cmp to i8 %conv2 = zext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1 store i8 %conv2, i8* @glob, align 1
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_lleqsc_sext_z_store(i8 signext %a) { define void @test_lleqsc_sext_z_store(i8 signext %a) {
; CHECK-LABEL: test_lleqsc_sext_z_store: ; CHECK-LABEL: test_lleqsc_sext_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: stb r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsc_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqsc_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: stb r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i8 %a, 0 %cmp = icmp eq i8 %a, 0
%conv2 = sext i1 %cmp to i8 %conv2 = sext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1 store i8 %conv2, i8* @glob, align 1
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testCompareslleqsi.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i32 0, align 4 @glob = common local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqsi(i32 signext %a, i32 signext %b) { define i64 @test_lleqsi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lleqsi: ; CHECK-LABEL: test_lleqsi:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsi:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqsi:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i32 %a, %b %cmp = icmp eq i32 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqsi_sext(i32 signext %a, i32 signext %b) { define i64 @test_lleqsi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lleqsi_sext: ; CHECK-LABEL: test_lleqsi_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsi_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqsi_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i32 %a, %b %cmp = icmp eq i32 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqsi_z(i32 signext %a) { define i64 @test_lleqsi_z(i32 signext %a) {
; CHECK-LABEL: test_lleqsi_z: ; CHECK-LABEL: test_lleqsi_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsi_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqsi_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i32 %a, 0 %cmp = icmp eq i32 %a, 0
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqsi_sext_z(i32 signext %a) { define i64 @test_lleqsi_sext_z(i32 signext %a) {
; CHECK-LABEL: test_lleqsi_sext_z: ; CHECK-LABEL: test_lleqsi_sext_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsi_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqsi_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i32 %a, 0 %cmp = icmp eq i32 %a, 0
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_lleqsi_store(i32 signext %a, i32 signext %b) { define void @test_lleqsi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lleqsi_store: ; CHECK-LABEL: test_lleqsi_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsi_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqsi_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i32 %a, %b %cmp = icmp eq i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4 store i32 %conv, i32* @glob, align 4
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_lleqsi_sext_store(i32 signext %a, i32 signext %b) { define void @test_lleqsi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lleqsi_sext_store: ; CHECK-LABEL: test_lleqsi_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsi_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqsi_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i32 %a, %b %cmp = icmp eq i32 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4 store i32 %sub, i32* @glob, align 4
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_lleqsi_z_store(i32 signext %a) { define void @test_lleqsi_z_store(i32 signext %a) {
; CHECK-LABEL: test_lleqsi_z_store: ; CHECK-LABEL: test_lleqsi_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: stw r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECKNEXT: blr ; CHECKNEXT: blr
; CHECK-BE-LABEL: test_lleqsi_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqsi_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: stw r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i32 %a, 0 %cmp = icmp eq i32 %a, 0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4 store i32 %conv, i32* @glob, align 4
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_lleqsi_sext_z_store(i32 signext %a) { define void @test_lleqsi_sext_z_store(i32 signext %a) {
; CHECK-LABEL: test_lleqsi_sext_z_store: ; CHECK-LABEL: test_lleqsi_sext_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: stw r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsi_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqsi_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: stw r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i32 %a, 0 %cmp = icmp eq i32 %a, 0
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4 store i32 %sub, i32* @glob, align 4
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testCompareslleqsll.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i64 0, align 8 @glob = common local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqsll(i64 %a, i64 %b) { define i64 @test_lleqsll(i64 %a, i64 %b) {
; CHECK-LABEL: test_lleqsll: ; CHECK-LABEL: test_lleqsll:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsll:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzd r3, r3
; CHECK-BE-NEXT: rldicl r3, r3, 58, 63
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqsll:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzd r3, r3
; CHECK-LE-NEXT: rldicl r3, r3, 58, 63
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, %b %cmp = icmp eq i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqsll_sext(i64 %a, i64 %b) { define i64 @test_lleqsll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_lleqsll_sext: ; CHECK-LABEL: test_lleqsll_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsll_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqsll_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, %b %cmp = icmp eq i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqsll_z(i64 %a) { define i64 @test_lleqsll_z(i64 %a) {
; CHECK-LABEL: test_lleqsll_z: ; CHECK-LABEL: test_lleqsll_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsll_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzd r3, r3
; CHECK-BE-NEXT: rldicl r3, r3, 58, 63
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqsll_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzd r3, r3
; CHECK-LE-NEXT: rldicl r3, r3, 58, 63
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, 0 %cmp = icmp eq i64 %a, 0
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqsll_sext_z(i64 %a) { define i64 @test_lleqsll_sext_z(i64 %a) {
; CHECK-LABEL: test_lleqsll_sext_z: ; CHECK-LABEL: test_lleqsll_sext_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsll_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqsll_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, 0 %cmp = icmp eq i64 %a, 0
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_lleqsll_store(i64 %a, i64 %b) { define void @test_lleqsll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_lleqsll_store: ; CHECK-LABEL: test_lleqsll_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsll_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: cntlzd r3, r3
; CHECK-BE-NEXT: rldicl r3, r3, 58, 63
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqsll_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzd r3, r3
; CHECK-LE-NEXT: rldicl r3, r3, 58, 63
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, %b %cmp = icmp eq i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_lleqsll_sext_store(i64 %a, i64 %b) { define void @test_lleqsll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_lleqsll_sext_store: ; CHECK-LABEL: test_lleqsll_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsll_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqsll_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, %b %cmp = icmp eq i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_lleqsll_z_store(i64 %a) { define void @test_lleqsll_z_store(i64 %a) {
; CHECK-LABEL: test_lleqsll_z_store: ; CHECK-LABEL: test_lleqsll_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsll_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzd r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: rldicl r3, r3, 58, 63
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqsll_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzd r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 58, 63
; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, 0 %cmp = icmp eq i64 %a, 0
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_lleqsll_sext_z_store(i64 %a) { define void @test_lleqsll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_lleqsll_sext_z_store: ; CHECK-LABEL: test_lleqsll_sext_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsll_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqsll_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, 0 %cmp = icmp eq i64 %a, 0
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testCompareslleqss.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i16 0, align 2 @glob = common local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqss(i16 signext %a, i16 signext %b) { define i64 @test_lleqss(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_lleqss: ; CHECK-LABEL: test_lleqss:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqss:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqss:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i16 %a, %b %cmp = icmp eq i16 %a, %b
%conv3 = zext i1 %cmp to i64 %conv3 = zext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqss_sext(i16 signext %a, i16 signext %b) { define i64 @test_lleqss_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_lleqss_sext: ; CHECK-LABEL: test_lleqss_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqss_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqss_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i16 %a, %b %cmp = icmp eq i16 %a, %b
%conv3 = sext i1 %cmp to i64 %conv3 = sext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqss_z(i16 signext %a) { define i64 @test_lleqss_z(i16 signext %a) {
; CHECK-LABEL: test_lleqss_z: ; CHECK-LABEL: test_lleqss_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqss_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqss_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i16 %a, 0 %cmp = icmp eq i16 %a, 0
%conv2 = zext i1 %cmp to i64 %conv2 = zext i1 %cmp to i64
ret i64 %conv2 ret i64 %conv2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqss_sext_z(i16 signext %a) { define i64 @test_lleqss_sext_z(i16 signext %a) {
; CHECK-LABEL: test_lleqss_sext_z: ; CHECK-LABEL: test_lleqss_sext_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqss_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqss_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i16 %a, 0 %cmp = icmp eq i16 %a, 0
%conv2 = sext i1 %cmp to i64 %conv2 = sext i1 %cmp to i64
ret i64 %conv2 ret i64 %conv2
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_lleqss_store(i16 signext %a, i16 signext %b) { define void @test_lleqss_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_lleqss_store: ; CHECK-LABEL: test_lleqss_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqss_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqss_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i16 %a, %b %cmp = icmp eq i16 %a, %b
%conv3 = zext i1 %cmp to i16 %conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2 store i16 %conv3, i16* @glob, align 2
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_lleqss_sext_store(i16 signext %a, i16 signext %b) { define void @test_lleqss_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_lleqss_sext_store: ; CHECK-LABEL: test_lleqss_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqss_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqss_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i16 %a, %b %cmp = icmp eq i16 %a, %b
%conv3 = sext i1 %cmp to i16 %conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2 store i16 %conv3, i16* @glob, align 2
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_lleqss_z_store(i16 signext %a) { define void @test_lleqss_z_store(i16 signext %a) {
; CHECK-LABEL: test_lleqss_z_store: ; CHECK-LABEL: test_lleqss_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: sth r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqss_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqss_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: sth r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i16 %a, 0 %cmp = icmp eq i16 %a, 0
%conv2 = zext i1 %cmp to i16 %conv2 = zext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2 store i16 %conv2, i16* @glob, align 2
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_lleqss_sext_z_store(i16 signext %a) { define void @test_lleqss_sext_z_store(i16 signext %a) {
; CHECK-LABEL: test_lleqss_sext_z_store: ; CHECK-LABEL: test_lleqss_sext_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: sth r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqss_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqss_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: sth r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i16 %a, 0 %cmp = icmp eq i16 %a, 0
%conv2 = sext i1 %cmp to i16 %conv2 = sext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2 store i16 %conv2, i16* @glob, align 2
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesllequc.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i8 0, align 1 @glob = common local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llequc(i8 zeroext %a, i8 zeroext %b) { define i64 @test_llequc(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llequc: ; CHECK-LABEL: test_llequc:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequc:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequc:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i8 %a, %b %cmp = icmp eq i8 %a, %b
%conv3 = zext i1 %cmp to i64 %conv3 = zext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llequc_sext(i8 zeroext %a, i8 zeroext %b) { define i64 @test_llequc_sext(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llequc_sext: ; CHECK-LABEL: test_llequc_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequc_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequc_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i8 %a, %b %cmp = icmp eq i8 %a, %b
%conv3 = sext i1 %cmp to i64 %conv3 = sext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llequc_z(i8 zeroext %a) { define i64 @test_llequc_z(i8 zeroext %a) {
; CHECK-LABEL: test_llequc_z: ; CHECK-LABEL: test_llequc_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequc_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequc_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i8 %a, 0 %cmp = icmp eq i8 %a, 0
%conv2 = zext i1 %cmp to i64 %conv2 = zext i1 %cmp to i64
ret i64 %conv2 ret i64 %conv2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llequc_sext_z(i8 zeroext %a) { define i64 @test_llequc_sext_z(i8 zeroext %a) {
; CHECK-LABEL: test_llequc_sext_z: ; CHECK-LABEL: test_llequc_sext_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequc_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequc_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i8 %a, 0 %cmp = icmp eq i8 %a, 0
%conv2 = sext i1 %cmp to i64 %conv2 = sext i1 %cmp to i64
ret i64 %conv2 ret i64 %conv2
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llequc_store(i8 zeroext %a, i8 zeroext %b) { define void @test_llequc_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llequc_store: ; CHECK-LABEL: test_llequc_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequc_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequc_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: stb r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i8 %a, %b %cmp = icmp eq i8 %a, %b
%conv3 = zext i1 %cmp to i8 %conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1 store i8 %conv3, i8* @glob, align 1
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llequc_sext_store(i8 zeroext %a, i8 zeroext %b) { define void @test_llequc_sext_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llequc_sext_store: ; CHECK-LABEL: test_llequc_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequc_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequc_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: stb r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i8 %a, %b %cmp = icmp eq i8 %a, %b
%conv3 = sext i1 %cmp to i8 %conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1 store i8 %conv3, i8* @glob, align 1
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llequc_z_store(i8 zeroext %a) { define void @test_llequc_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_llequc_z_store: ; CHECK-LABEL: test_llequc_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: stb r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequc_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequc_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: stb r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i8 %a, 0 %cmp = icmp eq i8 %a, 0
%conv2 = zext i1 %cmp to i8 %conv2 = zext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1 store i8 %conv2, i8* @glob, align 1
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llequc_sext_z_store(i8 zeroext %a) { define void @test_llequc_sext_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_llequc_sext_z_store: ; CHECK-LABEL: test_llequc_sext_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: stb r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequc_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequc_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: stb r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i8 %a, 0 %cmp = icmp eq i8 %a, 0
%conv2 = sext i1 %cmp to i8 %conv2 = sext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1 store i8 %conv2, i8* @glob, align 1
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesllequi.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i32 0, align 4 @glob = common local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llequi(i32 zeroext %a, i32 zeroext %b) { define i64 @test_llequi(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llequi: ; CHECK-LABEL: test_llequi:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequi:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequi:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i32 %a, %b %cmp = icmp eq i32 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llequi_sext(i32 zeroext %a, i32 zeroext %b) { define i64 @test_llequi_sext(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llequi_sext: ; CHECK-LABEL: test_llequi_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequi_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequi_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i32 %a, %b %cmp = icmp eq i32 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llequi_z(i32 zeroext %a) { define i64 @test_llequi_z(i32 zeroext %a) {
; CHECK-LABEL: test_llequi_z: ; CHECK-LABEL: test_llequi_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequi_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequi_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i32 %a, 0 %cmp = icmp eq i32 %a, 0
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llequi_sext_z(i32 zeroext %a) { define i64 @test_llequi_sext_z(i32 zeroext %a) {
; CHECK-LABEL: test_llequi_sext_z: ; CHECK-LABEL: test_llequi_sext_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequi_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequi_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i32 %a, 0 %cmp = icmp eq i32 %a, 0
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llequi_store(i32 zeroext %a, i32 zeroext %b) { define void @test_llequi_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llequi_store: ; CHECK-LABEL: test_llequi_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequi_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequi_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i32 %a, %b %cmp = icmp eq i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4 store i32 %conv, i32* @glob, align 4
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llequi_sext_store(i32 zeroext %a, i32 zeroext %b) { define void @test_llequi_sext_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llequi_sext_store: ; CHECK-LABEL: test_llequi_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequi_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequi_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i32 %a, %b %cmp = icmp eq i32 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4 store i32 %sub, i32* @glob, align 4
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llequi_z_store(i32 zeroext %a) { define void @test_llequi_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_llequi_z_store: ; CHECK-LABEL: test_llequi_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: stw r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequi_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequi_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: stw r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i32 %a, 0 %cmp = icmp eq i32 %a, 0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4 store i32 %conv, i32* @glob, align 4
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llequi_sext_z_store(i32 zeroext %a) { define void @test_llequi_sext_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_llequi_sext_z_store: ; CHECK-LABEL: test_llequi_sext_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: stw r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequi_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequi_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: stw r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i32 %a, 0 %cmp = icmp eq i32 %a, 0
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4 store i32 %sub, i32* @glob, align 4
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesllequll.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i64 0, align 8 @glob = common local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llequll(i64 %a, i64 %b) { define i64 @test_llequll(i64 %a, i64 %b) {
; CHECK-LABEL: test_llequll: ; CHECK-LABEL: test_llequll:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequll:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzd r3, r3
; CHECK-BE-NEXT: rldicl r3, r3, 58, 63
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequll:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzd r3, r3
; CHECK-LE-NEXT: rldicl r3, r3, 58, 63
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, %b %cmp = icmp eq i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llequll_sext(i64 %a, i64 %b) { define i64 @test_llequll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_llequll_sext: ; CHECK-LABEL: test_llequll_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequll_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequll_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, %b %cmp = icmp eq i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llequll_z(i64 %a) { define i64 @test_llequll_z(i64 %a) {
; CHECK-LABEL: test_llequll_z: ; CHECK-LABEL: test_llequll_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequll_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzd r3, r3
; CHECK-BE-NEXT: rldicl r3, r3, 58, 63
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequll_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzd r3, r3
; CHECK-LE-NEXT: rldicl r3, r3, 58, 63
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, 0 %cmp = icmp eq i64 %a, 0
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llequll_sext_z(i64 %a) { define i64 @test_llequll_sext_z(i64 %a) {
; CHECK-LABEL: test_llequll_sext_z: ; CHECK-LABEL: test_llequll_sext_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequll_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequll_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, 0 %cmp = icmp eq i64 %a, 0
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llequll_store(i64 %a, i64 %b) { define void @test_llequll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llequll_store: ; CHECK-LABEL: test_llequll_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequll_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: cntlzd r3, r3
; CHECK-BE-NEXT: rldicl r3, r3, 58, 63
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequll_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzd r3, r3
; CHECK-LE-NEXT: rldicl r3, r3, 58, 63
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, %b %cmp = icmp eq i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llequll_sext_store(i64 %a, i64 %b) { define void @test_llequll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llequll_sext_store: ; CHECK-LABEL: test_llequll_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequll_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequll_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, %b %cmp = icmp eq i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llequll_z_store(i64 %a) { define void @test_llequll_z_store(i64 %a) {
; CHECK-LABEL: test_llequll_z_store: ; CHECK-LABEL: test_llequll_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequll_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzd r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: rldicl r3, r3, 58, 63
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequll_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzd r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 58, 63
; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, 0 %cmp = icmp eq i64 %a, 0
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llequll_sext_z_store(i64 %a) { define void @test_llequll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_llequll_sext_z_store: ; CHECK-LABEL: test_llequll_sext_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequll_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequll_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, 0 %cmp = icmp eq i64 %a, 0
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesllequs.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i16 0, align 2 @glob = common local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llequs(i16 zeroext %a, i16 zeroext %b) { define i64 @test_llequs(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llequs: ; CHECK-LABEL: test_llequs:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequs:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequs:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i16 %a, %b %cmp = icmp eq i16 %a, %b
%conv3 = zext i1 %cmp to i64 %conv3 = zext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llequs_sext(i16 zeroext %a, i16 zeroext %b) { define i64 @test_llequs_sext(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llequs_sext: ; CHECK-LABEL: test_llequs_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequs_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequs_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i16 %a, %b %cmp = icmp eq i16 %a, %b
%conv3 = sext i1 %cmp to i64 %conv3 = sext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llequs_z(i16 zeroext %a) { define i64 @test_llequs_z(i16 zeroext %a) {
; CHECK-LABEL: test_llequs_z: ; CHECK-LABEL: test_llequs_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequs_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequs_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i16 %a, 0 %cmp = icmp eq i16 %a, 0
%conv2 = zext i1 %cmp to i64 %conv2 = zext i1 %cmp to i64
ret i64 %conv2 ret i64 %conv2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llequs_sext_z(i16 zeroext %a) { define i64 @test_llequs_sext_z(i16 zeroext %a) {
; CHECK-LABEL: test_llequs_sext_z: ; CHECK-LABEL: test_llequs_sext_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequs_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequs_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i16 %a, 0 %cmp = icmp eq i16 %a, 0
%conv2 = sext i1 %cmp to i64 %conv2 = sext i1 %cmp to i64
ret i64 %conv2 ret i64 %conv2
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llequs_store(i16 zeroext %a, i16 zeroext %b) { define void @test_llequs_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llequs_store: ; CHECK-LABEL: test_llequs_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequs_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequs_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i16 %a, %b %cmp = icmp eq i16 %a, %b
%conv3 = zext i1 %cmp to i16 %conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2 store i16 %conv3, i16* @glob, align 2
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llequs_sext_store(i16 zeroext %a, i16 zeroext %b) { define void @test_llequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llequs_sext_store: ; CHECK-LABEL: test_llequs_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequs_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequs_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i16 %a, %b %cmp = icmp eq i16 %a, %b
%conv3 = sext i1 %cmp to i16 %conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2 store i16 %conv3, i16* @glob, align 2
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llequs_z_store(i16 zeroext %a) { define void @test_llequs_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_llequs_z_store: ; CHECK-LABEL: test_llequs_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: sth r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequs_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequs_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: sth r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i16 %a, 0 %cmp = icmp eq i16 %a, 0
%conv2 = zext i1 %cmp to i16 %conv2 = zext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2 store i16 %conv2, i16* @glob, align 2
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llequs_sext_z_store(i16 zeroext %a) { define void @test_llequs_sext_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_llequs_sext_z_store: ; CHECK-LABEL: test_llequs_sext_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: sth r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequs_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequs_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzw r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: srwi r3, r3, 5
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: sth r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i16 %a, 0 %cmp = icmp eq i16 %a, 0
%conv2 = sext i1 %cmp to i16 %conv2 = sext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2 store i16 %conv2, i16* @glob, align 2
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesllgesc.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i8 0, align 1 @glob = common local_unnamed_addr global i8 0, align 1
define i64 @test_llgesc(i8 signext %a, i8 signext %b) { define i64 @test_llgesc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llgesc: ; CHECK-LABEL: test_llgesc:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgesc:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llgesc:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i8 %a, %b %cmp = icmp sge i8 %a, %b
%conv3 = zext i1 %cmp to i64 %conv3 = zext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
define i64 @test_llgesc_sext(i8 signext %a, i8 signext %b) { define i64 @test_llgesc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llgesc_sext: ; CHECK-LABEL: test_llgesc_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgesc_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llgesc_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i8 %a, %b %cmp = icmp sge i8 %a, %b
%conv3 = sext i1 %cmp to i64 %conv3 = sext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
define void @test_llgesc_store(i8 signext %a, i8 signext %b) { define void @test_llgesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llgesc_store: ; CHECK-LABEL: test_llgesc_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgesc_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llgesc_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: stb r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i8 %a, %b %cmp = icmp sge i8 %a, %b
%conv3 = zext i1 %cmp to i8 %conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1 store i8 %conv3, i8* @glob, align 1
ret void ret void
} }
define void @test_llgesc_sext_store(i8 signext %a, i8 signext %b) { define void @test_llgesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llgesc_sext_store: ; CHECK-LABEL: test_llgesc_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgesc_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llgesc_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: stb r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i8 %a, %b %cmp = icmp sge i8 %a, %b
%conv3 = sext i1 %cmp to i8 %conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1 store i8 %conv3, i8* @glob, align 1
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesllgesi.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i32 0, align 4 @glob = common local_unnamed_addr global i32 0, align 4
define i64 @test_llgesi(i32 signext %a, i32 signext %b) { define i64 @test_llgesi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llgesi: ; CHECK-LABEL: test_llgesi:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgesi:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llgesi:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i32 %a, %b %cmp = icmp sge i32 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
define i64 @test_llgesi_sext(i32 signext %a, i32 signext %b) { define i64 @test_llgesi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llgesi_sext: ; CHECK-LABEL: test_llgesi_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgesi_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llgesi_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i32 %a, %b %cmp = icmp sge i32 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
define void @test_llgesi_store(i32 signext %a, i32 signext %b) { define void @test_llgesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llgesi_store: ; CHECK-LABEL: test_llgesi_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgesi_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llgesi_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i32 %a, %b %cmp = icmp sge i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4 store i32 %conv, i32* @glob, align 4
ret void ret void
} }
define void @test_llgesi_sext_store(i32 signext %a, i32 signext %b) { define void @test_llgesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llgesi_sext_store: ; CHECK-LABEL: test_llgesi_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgesi_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llgesi_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i32 %a, %b %cmp = icmp sge i32 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4 store i32 %sub, i32* @glob, align 4
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesllgesll.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i64 0, align 8 @glob = common local_unnamed_addr global i64 0, align 8
define i64 @test_llgesll(i64 %a, i64 %b) { define i64 @test_llgesll(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgesll: ; CHECK-LABEL: test_llgesll:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r3, 63 ; CHECK-NEXT: sradi r5, r3, 63
; CHECK-NEXT: rldicl r6, r4, 1, 63 ; CHECK-NEXT: rldicl r6, r4, 1, 63
; CHECK-NEXT: subfc r3, r4, r3 ; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: adde r3, r5, r6 ; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgesll:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r3, 63
; CHECK-BE-NEXT: rldicl r6, r4, 1, 63
; CHECK-BE-NEXT: subfc r3, r4, r3
; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llgesll:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r3, 63
; CHECK-LE-NEXT: rldicl r6, r4, 1, 63
; CHECK-LE-NEXT: subfc r3, r4, r3
; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i64 %a, %b %cmp = icmp sge i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
define i64 @test_llgesll_sext(i64 %a, i64 %b) { define i64 @test_llgesll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgesll_sext: ; CHECK-LABEL: test_llgesll_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r3, 63 ; CHECK-NEXT: sradi r5, r3, 63
; CHECK-NEXT: rldicl r6, r4, 1, 63 ; CHECK-NEXT: rldicl r6, r4, 1, 63
; CHECK-NEXT: subfc r3, r4, r3 ; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: adde r3, r5, r6 ; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgesll_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r3, 63
; CHECK-BE-NEXT: rldicl r6, r4, 1, 63
; CHECK-BE-NEXT: subfc r3, r4, r3
; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llgesll_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r3, 63
; CHECK-LE-NEXT: rldicl r6, r4, 1, 63
; CHECK-LE-NEXT: subfc r3, r4, r3
; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i64 %a, %b %cmp = icmp sge i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
define i64 @test_llgesll_z(i64 %a) { define i64 @test_llgesll_z(i64 %a) {
; CHECK-LABEL: test_llgesll_z: ; CHECK-LABEL: test_llgesll_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: not r3, r3 ; CHECK-NEXT: not r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgesll_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: not r3, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llgesll_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: not r3, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sgt i64 %a, -1 %cmp = icmp sgt i64 %a, -1
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
define i64 @test_llgesll_sext_z(i64 %a) { define i64 @test_llgesll_sext_z(i64 %a) {
; CHECK-LABEL: test_llgesll_sext_z: ; CHECK-LABEL: test_llgesll_sext_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: not r3, r3 ; CHECK-NEXT: not r3, r3
; CHECK-NEXT: sradi r3, r3, 63 ; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgesll_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: not r3, r3
; CHECK-BE-NEXT: sradi r3, r3, 63
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llgesll_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: not r3, r3
; CHECK-LE-NEXT: sradi r3, r3, 63
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sgt i64 %a, -1 %cmp = icmp sgt i64 %a, -1
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
define void @test_llgesll_store(i64 %a, i64 %b) { define void @test_llgesll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgesll_store: ; CHECK-LABEL: test_llgesll_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK: sradi r6, r3, 63 ; CHECK-NEXT: sradi r6, r3, 63
; CHECK: subfc r3, r4, r3 ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK: rldicl r3, r4, 1, 63 ; CHECK-NEXT: subfc r3, r4, r3
; CHECK: adde r3, r6, r3 ; CHECK-NEXT: rldicl r3, r4, 1, 63
; CHECK: std r3, ; CHECK-NEXT: adde r3, r6, r3
; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgesll_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sradi r6, r3, 63
; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-BE-NEXT: subfc r3, r4, r3
; CHECK-BE-NEXT: rldicl r3, r4, 1, 63
; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: std r3, 0(r5)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llgesll_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r3, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subfc r3, r4, r3
; CHECK-LE-NEXT: rldicl r3, r4, 1, 63
; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i64 %a, %b %cmp = icmp sge i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
define void @test_llgesll_sext_store(i64 %a, i64 %b) { define void @test_llgesll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgesll_sext_store: ; CHECK-LABEL: test_llgesll_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r6, r3, 63 ; CHECK-NEXT: sradi r6, r3, 63
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: subfc r3, r4, r3 ; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: rldicl r3, r4, 1, 63 ; CHECK-NEXT: rldicl r3, r4, 1, 63
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: adde r3, r6, r3 ; CHECK-NEXT: adde r3, r6, r3
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgesll_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r6, r3, 63
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: subfc r3, r4, r3
; CHECK-BE-NEXT: rldicl r3, r4, 1, 63
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llgesll_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r3, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subfc r3, r4, r3
; CHECK-LE-NEXT: rldicl r3, r4, 1, 63
; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i64 %a, %b %cmp = icmp sge i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
define void @test_llgesll_z_store(i64 %a) { define void @test_llgesll_z_store(i64 %a) {
; CHECK-LABEL: test_llgesll_z_store: ; CHECK-LABEL: test_llgesll_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: not r3, r3 ; CHECK-NEXT: not r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgesll_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: not r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llgesll_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: not r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sgt i64 %a, -1 %cmp = icmp sgt i64 %a, -1
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
define void @test_llgesll_sext_z_store(i64 %a) { define void @test_llgesll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_llgesll_sext_z_store: ; CHECK-LABEL: test_llgesll_sext_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: not r3, r3 ; CHECK-NEXT: not r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: sradi r3, r3, 63 ; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgesll_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: not r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: sradi r3, r3, 63
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llgesll_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: not r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: sradi r3, r3, 63
; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sgt i64 %a, -1 %cmp = icmp sgt i64 %a, -1
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesllgess.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i16 0, align 2 @glob = common local_unnamed_addr global i16 0, align 2
define i64 @test_llgess(i16 signext %a, i16 signext %b) { define i64 @test_llgess(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llgess: ; CHECK-LABEL: test_llgess:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgess:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llgess:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i16 %a, %b %cmp = icmp sge i16 %a, %b
%conv3 = zext i1 %cmp to i64 %conv3 = zext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
define i64 @test_llgess_sext(i16 signext %a, i16 signext %b) { define i64 @test_llgess_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llgess_sext: ; CHECK-LABEL: test_llgess_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgess_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llgess_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i16 %a, %b %cmp = icmp sge i16 %a, %b
%conv3 = sext i1 %cmp to i64 %conv3 = sext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
define void @test_llgess_store(i16 signext %a, i16 signext %b) { define void @test_llgess_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llgess_store: ; CHECK-LABEL: test_llgess_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgess_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llgess_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i16 %a, %b %cmp = icmp sge i16 %a, %b
%conv3 = zext i1 %cmp to i16 %conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2 store i16 %conv3, i16* @glob, align 2
ret void ret void
} }
define void @test_llgess_sext_store(i16 signext %a, i16 signext %b) { define void @test_llgess_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llgess_sext_store: ; CHECK-LABEL: test_llgess_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgess_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llgess_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i16 %a, %b %cmp = icmp sge i16 %a, %b
%conv3 = sext i1 %cmp to i16 %conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2 store i16 %conv3, i16* @glob, align 2
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesllgtsll.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i64 0, align 8 @glob = common local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtsll(i64 %a, i64 %b) { define i64 @test_llgtsll(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgtsll: ; CHECK-LABEL: test_llgtsll:
▲ Show 20 Lines • Show All 122 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/PowerPC/testComparesllgtuc.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i8 0, align 1 @glob = common local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtuc(i8 zeroext %a, i8 zeroext %b) { define i64 @test_llgtuc(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llgtuc: ; CHECK-LABEL: test_llgtuc:
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llvm/trunk/test/CodeGen/PowerPC/testComparesllgtui.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i32 0, align 4 @glob = common local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtui(i32 zeroext %a, i32 zeroext %b) { define i64 @test_llgtui(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llgtui: ; CHECK-LABEL: test_llgtui:
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llvm/trunk/test/CodeGen/PowerPC/testComparesllgtus.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i16 0, align 2 @glob = common local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtus(i16 zeroext %a, i16 zeroext %b) { define i64 @test_llgtus(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llgtus: ; CHECK-LABEL: test_llgtus:
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llvm/trunk/test/CodeGen/PowerPC/testCompareslllesc.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i8 0, align 1 @glob = common local_unnamed_addr global i8 0, align 1
define i64 @test_lllesc(i8 signext %a, i8 signext %b) { define i64 @test_lllesc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lllesc: ; CHECK-LABEL: test_lllesc:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lllesc:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lllesc:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i8 %a, %b %cmp = icmp sle i8 %a, %b
%conv3 = zext i1 %cmp to i64 %conv3 = zext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
define i64 @test_lllesc_sext(i8 signext %a, i8 signext %b) { define i64 @test_lllesc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lllesc_sext: ; CHECK-LABEL: test_lllesc_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lllesc_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lllesc_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i8 %a, %b %cmp = icmp sle i8 %a, %b
%conv3 = sext i1 %cmp to i64 %conv3 = sext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
define void @test_lllesc_store(i8 signext %a, i8 signext %b) { define void @test_lllesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lllesc_store: ; CHECK-LABEL: test_lllesc_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lllesc_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lllesc_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: stb r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i8 %a, %b %cmp = icmp sle i8 %a, %b
%conv3 = zext i1 %cmp to i8 %conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1 store i8 %conv3, i8* @glob, align 1
ret void ret void
} }
define void @test_lllesc_sext_store(i8 signext %a, i8 signext %b) { define void @test_lllesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lllesc_sext_store: ; CHECK-LABEL: test_lllesc_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lllesc_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lllesc_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: stb r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i8 %a, %b %cmp = icmp sle i8 %a, %b
%conv3 = sext i1 %cmp to i8 %conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1 store i8 %conv3, i8* @glob, align 1
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testCompareslllesi.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i32 0, align 4 @glob = common local_unnamed_addr global i32 0, align 4
define i64 @test_lllesi(i32 signext %a, i32 signext %b) { define i64 @test_lllesi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lllesi: ; CHECK-LABEL: test_lllesi:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lllesi:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lllesi:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i32 %a, %b %cmp = icmp sle i32 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
define i64 @test_lllesi_sext(i32 signext %a, i32 signext %b) { define i64 @test_lllesi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lllesi_sext: ; CHECK-LABEL: test_lllesi_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lllesi_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lllesi_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i32 %a, %b %cmp = icmp sle i32 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
define void @test_lllesi_store(i32 signext %a, i32 signext %b) { define void @test_lllesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lllesi_store: ; CHECK-LABEL: test_lllesi_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lllesi_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lllesi_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i32 %a, %b %cmp = icmp sle i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4 store i32 %conv, i32* @glob, align 4
ret void ret void
} }
define void @test_lllesi_sext_store(i32 signext %a, i32 signext %b) { define void @test_lllesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lllesi_sext_store: ; CHECK-LABEL: test_lllesi_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lllesi_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lllesi_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i32 %a, %b %cmp = icmp sle i32 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4 store i32 %sub, i32* @glob, align 4
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testCompareslllesll.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i64 0, align 8 @glob = common local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_lllesll(i64 %a, i64 %b) { define i64 @test_lllesll(i64 %a, i64 %b) {
; CHECK-LABEL: test_lllesll: ; CHECK-LABEL: test_lllesll:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r4, 63 ; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63 ; CHECK-NEXT: rldicl r6, r3, 1, 63
; CHECK-NEXT: subfc r3, r3, r4 ; CHECK-NEXT: subfc r3, r3, r4
; CHECK-NEXT: adde r3, r5, r6 ; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lllesll:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r4, 63
; CHECK-BE-NEXT: rldicl r6, r3, 1, 63
; CHECK-BE-NEXT: subfc r3, r3, r4
; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lllesll:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r4, 63
; CHECK-LE-NEXT: rldicl r6, r3, 1, 63
; CHECK-LE-NEXT: subfc r3, r3, r4
; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i64 %a, %b %cmp = icmp sle i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_lllesll_sext(i64 %a, i64 %b) { define i64 @test_lllesll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_lllesll_sext: ; CHECK-LABEL: test_lllesll_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r4, 63 ; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63 ; CHECK-NEXT: rldicl r6, r3, 1, 63
; CHECK-NEXT: subfc r3, r3, r4 ; CHECK-NEXT: subfc r3, r3, r4
; CHECK-NEXT: adde r3, r5, r6 ; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lllesll_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r4, 63
; CHECK-BE-NEXT: rldicl r6, r3, 1, 63
; CHECK-BE-NEXT: subfc r3, r3, r4
; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lllesll_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r4, 63
; CHECK-LE-NEXT: rldicl r6, r3, 1, 63
; CHECK-LE-NEXT: subfc r3, r3, r4
; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i64 %a, %b %cmp = icmp sle i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_lllesll_z(i64 %a) { define i64 @test_lllesll_z(i64 %a) {
; CHECK-LABEL: test_lllesll_z: ; CHECK-LABEL: test_lllesll_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi r4, r3, -1 ; CHECK-NEXT: addi r4, r3, -1
; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lllesll_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addi r4, r3, -1
; CHECK-BE-NEXT: or r3, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lllesll_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addi r4, r3, -1
; CHECK-LE-NEXT: or r3, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp slt i64 %a, 1 %cmp = icmp slt i64 %a, 1
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_lllesll_sext_z(i64 %a) { define i64 @test_lllesll_sext_z(i64 %a) {
; CHECK-LABEL: test_lllesll_sext_z: ; CHECK-LABEL: test_lllesll_sext_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi r4, r3, -1 ; CHECK-NEXT: addi r4, r3, -1
; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: sradi r3, r3, 63 ; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lllesll_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addi r4, r3, -1
; CHECK-BE-NEXT: or r3, r4, r3
; CHECK-BE-NEXT: sradi r3, r3, 63
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lllesll_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addi r4, r3, -1
; CHECK-LE-NEXT: or r3, r4, r3
; CHECK-LE-NEXT: sradi r3, r3, 63
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp slt i64 %a, 1 %cmp = icmp slt i64 %a, 1
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_lllesll_store(i64 %a, i64 %b) { define void @test_lllesll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_lllesll_store: ; CHECK-LABEL: test_lllesll_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sradi r6, r4, 63 ; CHECK-NEXT: sradi r6, r4, 63
; CHECK-NEXT: ld r5, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: subfc r4, r3, r4 ; CHECK-NEXT: subfc r4, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: adde r3, r6, r3 ; CHECK-NEXT: adde r3, r6, r3
; CHECK-NEXT: std r3, 0(r5) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lllesll_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sradi r6, r4, 63
; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-BE-NEXT: subfc r4, r3, r4
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: std r3, 0(r5)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lllesll_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r4, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subfc r4, r3, r4
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i64 %a, %b %cmp = icmp sle i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_lllesll_sext_store(i64 %a, i64 %b) { define void @test_lllesll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_lllesll_sext_store: ; CHECK-LABEL: test_lllesll_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r6, r4, 63 ; CHECK-NEXT: sradi r6, r4, 63
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: subfc r4, r3, r4 ; CHECK-NEXT: subfc r4, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: adde r3, r6, r3 ; CHECK-NEXT: adde r3, r6, r3
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lllesll_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r6, r4, 63
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: subfc r4, r3, r4
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lllesll_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r4, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subfc r4, r3, r4
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i64 %a, %b %cmp = icmp sle i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_lllesll_z_store(i64 %a) { define void @test_lllesll_z_store(i64 %a) {
; CHECK-LABEL: test_lllesll_z_store: ; CHECK-LABEL: test_lllesll_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addi r5, r3, -1 ; CHECK-NEXT: addi r5, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: or r3, r5, r3 ; CHECK-NEXT: or r3, r5, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lllesll_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: addi r5, r3, -1
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: or r3, r5, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lllesll_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addi r5, r3, -1
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: or r3, r5, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp slt i64 %a, 1 %cmp = icmp slt i64 %a, 1
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_lllesll_sext_z_store(i64 %a) { define void @test_lllesll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_lllesll_sext_z_store: ; CHECK-LABEL: test_lllesll_sext_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addi r5, r3, -1 ; CHECK-NEXT: addi r5, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: or r3, r5, r3 ; CHECK-NEXT: or r3, r5, r3
; CHECK-NEXT: sradi r3, r3, 63 ; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lllesll_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: addi r5, r3, -1
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: or r3, r5, r3
; CHECK-BE-NEXT: sradi r3, r3, 63
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lllesll_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addi r5, r3, -1
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: or r3, r5, r3
; CHECK-LE-NEXT: sradi r3, r3, 63
; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp slt i64 %a, 1 %cmp = icmp slt i64 %a, 1
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesllless.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i16 0, align 2 @glob = common local_unnamed_addr global i16 0, align 2
define i64 @test_llless(i16 signext %a, i16 signext %b) { define i64 @test_llless(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llless: ; CHECK-LABEL: test_llless:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llless:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llless:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i16 %a, %b %cmp = icmp sle i16 %a, %b
%conv3 = zext i1 %cmp to i64 %conv3 = zext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
define i64 @test_llless_sext(i16 signext %a, i16 signext %b) { define i64 @test_llless_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llless_sext: ; CHECK-LABEL: test_llless_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llless_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llless_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i16 %a, %b %cmp = icmp sle i16 %a, %b
%conv3 = sext i1 %cmp to i64 %conv3 = sext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
define void @test_llless_store(i16 signext %a, i16 signext %b) { define void @test_llless_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llless_store: ; CHECK-LABEL: test_llless_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llless_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llless_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i16 %a, %b %cmp = icmp sle i16 %a, %b
%conv3 = zext i1 %cmp to i16 %conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2 store i16 %conv3, i16* @glob, align 2
ret void ret void
} }
define void @test_llless_sext_store(i16 signext %a, i16 signext %b) { define void @test_llless_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llless_sext_store: ; CHECK-LABEL: test_llless_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llless_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llless_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i16 %a, %b %cmp = icmp sle i16 %a, %b
%conv3 = sext i1 %cmp to i16 %conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2 store i16 %conv3, i16* @glob, align 2
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesllltui.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc --relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i32 0, align 4 @glob = common local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llltui(i32 zeroext %a, i32 zeroext %b) { define i64 @test_llltui(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llltui: ; CHECK-LABEL: test_llltui:
▲ Show 20 Lines • Show All 96 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/PowerPC/testComparesllnesll.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i64 0, align 8 @glob = common local_unnamed_addr global i64 0, align 8
define i64 @test_llnesll(i64 %a, i64 %b) { define i64 @test_llnesll(i64 %a, i64 %b) {
; CHECK-LABEL: test_llnesll: ; CHECK-LABEL: test_llnesll:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addic r4, r3, -1 ; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3 ; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llnesll:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: addic r4, r3, -1
; CHECK-BE-NEXT: subfe r3, r4, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llnesll:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addic r4, r3, -1
; CHECK-LE-NEXT: subfe r3, r4, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i64 %a, %b %cmp = icmp ne i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
define i64 @test_llnesll_sext(i64 %a, i64 %b) { define i64 @test_llnesll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_llnesll_sext: ; CHECK-LABEL: test_llnesll_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llnesll_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: subfic r3, r3, 0
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llnesll_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: subfic r3, r3, 0
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i64 %a, %b %cmp = icmp ne i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
define i64 @test_llnesll_z(i64 %a) { define i64 @test_llnesll_z(i64 %a) {
; CHECK-LABEL: test_llnesll_z: ; CHECK-LABEL: test_llnesll_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addic r4, r3, -1 ; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3 ; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llnesll_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addic r4, r3, -1
; CHECK-BE-NEXT: subfe r3, r4, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llnesll_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addic r4, r3, -1
; CHECK-LE-NEXT: subfe r3, r4, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i64 %a, 0 %cmp = icmp ne i64 %a, 0
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
define i64 @test_llnesll_sext_z(i64 %a) { define i64 @test_llnesll_sext_z(i64 %a) {
; CHECK-LABEL: test_llnesll_sext_z: ; CHECK-LABEL: test_llnesll_sext_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llnesll_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: subfic r3, r3, 0
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llnesll_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: subfic r3, r3, 0
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i64 %a, 0 %cmp = icmp ne i64 %a, 0
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
define void @test_llnesll_store(i64 %a, i64 %b) { define void @test_llnesll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llnesll_store: ; CHECK-LABEL: test_llnesll_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: addic r5, r3, -1 ; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r5, r3 ; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llnesll_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: addic r5, r3, -1
; CHECK-BE-NEXT: subfe r3, r5, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llnesll_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: addic r4, r3, -1
; CHECK-LE-NEXT: subfe r3, r4, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i64 %a, %b %cmp = icmp ne i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
define void @test_llnesll_sext_store(i64 %a, i64 %b) { define void @test_llnesll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llnesll_sext_store: ; CHECK-LABEL: test_llnesll_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llnesll_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: subfic r3, r3, 0
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llnesll_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subfic r3, r3, 0
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i64 %a, %b %cmp = icmp ne i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
define void @test_llnesll_z_store(i64 %a) { define void @test_llnesll_z_store(i64 %a) {
; CHECK-LABEL: test_llnesll_z_store: ; CHECK-LABEL: test_llnesll_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addic r5, r3, -1 ; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: subfe r3, r5, r3 ; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llnesll_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: addic r5, r3, -1
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: subfe r3, r5, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llnesll_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addic r5, r3, -1
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: subfe r3, r5, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i64 %a, 0 %cmp = icmp ne i64 %a, 0
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
define void @test_llnesll_sext_z_store(i64 %a) { define void @test_llnesll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_llnesll_sext_z_store: ; CHECK-LABEL: test_llnesll_sext_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llnesll_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: subfic r3, r3, 0
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llnesll_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: subfic r3, r3, 0
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i64 %a, 0 %cmp = icmp ne i64 %a, 0
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/testComparesllneull.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i64 0, align 8 @glob = common local_unnamed_addr global i64 0, align 8
define i64 @test_llneull(i64 %a, i64 %b) { define i64 @test_llneull(i64 %a, i64 %b) {
; CHECK-LABEL: test_llneull: ; CHECK-LABEL: test_llneull:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addic r4, r3, -1 ; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3 ; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llneull:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: addic r4, r3, -1
; CHECK-BE-NEXT: subfe r3, r4, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llneull:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addic r4, r3, -1
; CHECK-LE-NEXT: subfe r3, r4, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i64 %a, %b %cmp = icmp ne i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
define i64 @test_llneull_sext(i64 %a, i64 %b) { define i64 @test_llneull_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_llneull_sext: ; CHECK-LABEL: test_llneull_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llneull_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: subfic r3, r3, 0
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llneull_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: subfic r3, r3, 0
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i64 %a, %b %cmp = icmp ne i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
define i64 @test_llneull_z(i64 %a) { define i64 @test_llneull_z(i64 %a) {
; CHECK-LABEL: test_llneull_z: ; CHECK-LABEL: test_llneull_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addic r4, r3, -1 ; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3 ; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llneull_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addic r4, r3, -1
; CHECK-BE-NEXT: subfe r3, r4, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llneull_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addic r4, r3, -1
; CHECK-LE-NEXT: subfe r3, r4, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i64 %a, 0 %cmp = icmp ne i64 %a, 0
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
define i64 @test_llneull_sext_z(i64 %a) { define i64 @test_llneull_sext_z(i64 %a) {
; CHECK-LABEL: test_llneull_sext_z: ; CHECK-LABEL: test_llneull_sext_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llneull_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: subfic r3, r3, 0
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llneull_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: subfic r3, r3, 0
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i64 %a, 0 %cmp = icmp ne i64 %a, 0
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
define void @test_llneull_store(i64 %a, i64 %b) { define void @test_llneull_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llneull_store: ; CHECK-LABEL: test_llneull_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: addic r5, r3, -1 ; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r5, r3 ; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llneull_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: addic r5, r3, -1
; CHECK-BE-NEXT: subfe r3, r5, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llneull_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: addic r4, r3, -1
; CHECK-LE-NEXT: subfe r3, r4, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i64 %a, %b %cmp = icmp ne i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
define void @test_llneull_sext_store(i64 %a, i64 %b) { define void @test_llneull_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llneull_sext_store: ; CHECK-LABEL: test_llneull_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llneull_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: subfic r3, r3, 0
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llneull_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subfic r3, r3, 0
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i64 %a, %b %cmp = icmp ne i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
define void @test_llneull_z_store(i64 %a) { define void @test_llneull_z_store(i64 %a) {
; CHECK-LABEL: test_llneull_z_store: ; CHECK-LABEL: test_llneull_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addic r5, r3, -1 ; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: subfe r3, r5, r3 ; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llneull_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: addic r5, r3, -1
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: subfe r3, r5, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llneull_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addic r5, r3, -1
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: subfe r3, r5, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i64 %a, 0 %cmp = icmp ne i64 %a, 0
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
define void @test_llneull_sext_z_store(i64 %a) { define void @test_llneull_sext_z_store(i64 %a) {
; CHECK-LABEL: test_llneull_sext_z_store: ; CHECK-LABEL: test_llneull_sext_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llneull_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: subfic r3, r3, 0
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llneull_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: subfic r3, r3, 0
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp ne i64 %a, 0 %cmp = icmp ne i64 %a, 0
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/toc-float.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 <%s | FileCheck -check-prefix=CHECK-P9 %s ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 <%s | FileCheck -check-prefix=CHECK-P9 %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 <%s | FileCheck -check-prefix=CHECK-P8 %s ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 <%s | FileCheck -check-prefix=CHECK-P8 %s
; As the constant could be represented as float, a float is ; As the constant could be represented as float, a float is
; loaded from constant pool. ; loaded from constant pool.
define double @doubleConstant1() { define double @doubleConstant1() {
ret double 1.400000e+01 ret double 1.400000e+01
; CHECK-LABEL: doubleConstant1: ; CHECK-LABEL: doubleConstant1:
; CHECK-P9: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha ; CHECK-P9: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
▲ Show 20 Lines • Show All 96 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -relocation-model=pic -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -mattr=-direct-move | FileCheck %s ; RUN: -mcpu=pwr8 -mattr=-direct-move | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -relocation-model=pic -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -mattr=-direct-move | FileCheck %s ; RUN: -mcpu=pwr8 -mattr=-direct-move | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -mattr=-direct-move | FileCheck %s -check-prefix=CHECK-P9 ; RUN: -mcpu=pwr9 -mattr=-direct-move | FileCheck %s -check-prefix=CHECK-P9
@d = common global double 0.000000e+00, align 8 @d = common global double 0.000000e+00, align 8
@f = common global float 0.000000e+00, align 4 @f = common global float 0.000000e+00, align 4
@i = common global i32 0, align 4 @i = common global i32 0, align 4
@ui = common global i32 0, align 4 @ui = common global i32 0, align 4
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llvm/trunk/test/CodeGen/PowerPC/xray-tail-call-sled.ll

; RUN: llc -filetype=asm -o - -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -filetype=asm -relocation-model=pic -o - -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
define i32 @callee() nounwind noinline uwtable "function-instrument"="xray-always" { define i32 @callee() nounwind noinline uwtable "function-instrument"="xray-always" {
; CHECK-LABEL: .Ltmp0: ; CHECK-LABEL: .Ltmp0:
; CHECK: b .Ltmp1 ; CHECK: b .Ltmp1
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: std 0, -8(1) ; CHECK-NEXT: std 0, -8(1)
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: bl __xray_FunctionEntry ; CHECK-NEXT: bl __xray_FunctionEntry
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