Add support for AArch64 UDF instruction

[dnsampaio]

Summary

UDF

Permanently Undefined generates an Undefined Instruction exception (ESR_ELx.EC = 0b000000).
The encodings for UDF used in this section are defined as permanently undefined in the ARMv8-A architecture.
https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/udf-permanently-undefined

[javed.absar]

lib/Target/AArch64/AArch64InstrFormats.td

4095

The 'uimm16' is generic and should be pulled up to where others (e.g. uimmm6) are defined.

test/MC/AArch64/udf.s

14 ↗

(On Diff #169803)

Some of these look unnecessary (just bounaries and a value in between is enough)

[dnsampaio]

To send patch....

lib/Target/AArch64/AArch64InstrFormats.td

4095

I can't if to reuse the existing ParserMatchClass = Imm0_65535Operand. I followed the same pattern of the // Move immediate., that defined the immediate types just before the instructions.

[dnsampaio]

Fixed the tests as to check boundaries, and one value in the middle.
Changed tests ordering as they generated empty lines not treated by FileCheck.

[nhaehnle]

lib/Target/AArch64/AArch64InstrFormats.td

4095

Note that at least the TableGen frontend allows you to inline expressions such as AsmImmRange<0, 65535> directly into the let statement.

The generated records will be de-duplicated, except in the case of an explicit instantiation (like the existing def Imm0_65535Operand).

I don't know if existing backends would stumble over a mixture of both explicit and implicit instantiations for ParserMatchClass, but consistently using inline AsmImmRange expressions everywhere should work.

(Just my 2c of TableGen info, do with it whatever you like, as I'm not working on AArch64 ;))

[dnsampaio]

lib/Target/AArch64/AArch64InstrFormats.td

4095

I don't believe the de-duplication works very well then.
If I do change let ParserMatchClass = Imm0_65535Operand to let ParserMatchClass = AsmImmRange<0x0, 0xffff>; I get

In file included from /work/bf/LLVM/local/src/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp:5449:0:
lib/Target/AArch64/AArch64GenAsmMatcher.inc:7354:3: error: redefinition of 'MCK_Imm0_65535'
   MCK_Imm0_65535, // user defined class 'anonymous_1075'
   ^
lib/Target/AArch64/AArch64GenAsmMatcher.inc:7139:3: note: 'MCK_Imm0_65535' previously defined here
   MCK_Imm0_65535, // user defined class 'Imm0_65535Operand'
   ^
lib/Target/AArch64/AArch64GenAsmMatcher.inc: In function 'unsigned int validateOperandClass(llvm::MCParsedAsmOperand&, {anonymous}::MatchClassKind)':
lib/Target/AArch64/AArch64GenAsmMatcher.inc:10405:3: error: duplicate case value
   case MCK_Imm0_65535: {
   ^
lib/Target/AArch64/AArch64GenAsmMatcher.inc:8644:3: error: previously used here
   case MCK_Imm0_65535: {
   ^
lib/Target/AArch64/AArch64GenAsmMatcher.inc: In function 'const char* getMatchClassName({anonymous}::MatchClassKind)':
lib/Target/AArch64/AArch64GenAsmMatcher.inc:11852:3: error: duplicate case value
   case MCK_Imm0_65535: return "MCK_Imm0_65535";
   ^
lib/Target/AArch64/AArch64GenAsmMatcher.inc:11637:3: error: previously used here
   case MCK_Imm0_65535: return "MCK_Imm0_65535";
   ^
lib/Target/AArch64/AArch64GenAsmMatcher.inc:11445:10: warning: enumeration value 'MCK_Imm0_65535' not handled in switch [-Wswitch]
   switch (Kind) {

[dnsampaio]

No custom decoding is required

[nhaehnle]

lib/Target/AArch64/AArch64InstrFormats.td

4095

Yeah, that confirms my suspicion that things break when you mix explicit with implicit definitions. The redefinition comes from the fact that you still have a named def that is equivalent to the anonymous def that's generated by the inline mention.

[dnsampaio]

Ping.

[dnsampaio]

Refactoring.

[javed.absar]

Could you add assembler/disassembler tests for udf ?

lib/Target/AArch64/AArch64InstrFormats.td

300

maybe the formatting should be similar to surrounding code ( [{.*}] one same line).

[dnsampaio]

Re-inserted the missing tests. Small refactoring as to look alike neighbor code.

[dnsampaio]

Added blank lines at end of test files.

lib/Target/AArch64/AArch64InstrFormats.td

 
 class SImmOperand<int width> : AsmOperandClass {
   let Name = "SImm" # width;
   let DiagnosticType = "InvalidMemoryIndexedSImm" # width;
   let RenderMethod = "addImmOperands";
   let PredicateMethod = "isSImm<" # width # ">";
 }
 
+
+class AsmImmRange<int Low, int High> : AsmOperandClass {
+  let Name = "Imm" # Low # "_" # High;
+  let DiagnosticType = "InvalidImm" # Low # "_" # High;
+  let RenderMethod = "addImmOperands";
+  let PredicateMethod = "isImmInRange<" # Low # "," # High # ">";
+}
+
 // Authenticated loads for v8.3 can have scaled 10-bit immediate offsets.
 def SImm10s8Operand : SImmScaledMemoryIndexed<10, 8>;
 def simm10Scaled : Operand<i64> {
   let ParserMatchClass = SImm10s8Operand;
   let DecoderMethod = "DecodeSImm<10>";
   let PrintMethod = "printImmScale<8>";
 }
 
 def simm9s16 : Operand<i64> {
   let ParserMatchClass = SImmScaledMemoryIndexed<9, 16>;
   let DecoderMethod = "DecodeSImm<9>";
   let PrintMethod = "printImmScale<16>";
 }
 
 // uimm6 predicate - True if the immediate is in the range [0, 63].
 def UImm6Operand : AsmOperandClass {
   let Name = "UImm6";
   let DiagnosticType = "InvalidImm0_63";
 }
 
 def uimm6 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm < 64; }]> {
   let ParserMatchClass = UImm6Operand;
 }
 
+def uimm16 : Operand<i16>, ImmLeaf<i16, [{
+  return ((uint32_t)Imm) < 65536;
+}]>{
+  let ParserMatchClass = AsmImmRange<0, 65535>;
+  let PrintMethod = "printImm";
+}
+
 def SImm9Operand : SImmOperand<9>;
 def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> {
   let ParserMatchClass = SImm9Operand;
   let DecoderMethod = "DecodeSImm<9>";
 }
 
 def SImm8Operand : SImmOperand<8>;
 def simm8 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -128 && Imm < 127; }]> {

 }
 def simm4s16 : Operand<i64>, ImmLeaf<i64,
 [{ return Imm >=-128  && Imm <= 112 && (Imm % 16) == 0x0; }]> {
   let PrintMethod = "printImmScale<16>";
   let ParserMatchClass = SImm4s16Operand;
   let DecoderMethod = "DecodeSImm<4>";
 }
 
-class AsmImmRange<int Low, int High> : AsmOperandClass {
-  let Name = "Imm" # Low # "_" # High;
-  let DiagnosticType = "InvalidImm" # Low # "_" # High;
-  let RenderMethod = "addImmOperands";
-  let PredicateMethod = "isImmInRange<" # Low # "," # High # ">";
-}
-
 def Imm1_8Operand : AsmImmRange<1, 8>;
 def Imm1_16Operand : AsmImmRange<1, 16>;
 def Imm1_32Operand : AsmImmRange<1, 32>;
 def Imm1_64Operand : AsmImmRange<1, 64>;
 
 class BranchTarget<int N> : AsmOperandClass {
   let Name = "BranchTarget" # N;
   let DiagnosticType = "InvalidLabel";

 def logical_imm32_not : Operand<i32> {
   let ParserMatchClass = LogicalImm32NotOperand;
 }
 def logical_imm64_not : Operand<i64> {
   let ParserMatchClass = LogicalImm64NotOperand;
 }
 
 // imm0_65535 predicate - True if the immediate is in the range [0,65535].
-def Imm0_65535Operand : AsmImmRange<0, 65535>;
 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
   return ((uint32_t)Imm) < 65536;
 }]> {
-  let ParserMatchClass = Imm0_65535Operand;
+  let ParserMatchClass = AsmImmRange<0, 65535>;
   let PrintMethod = "printImmHex";
 }
 
 // imm0_255 predicate - True if the immediate is in the range [0,255].
 def Imm0_255Operand : AsmImmRange<0,255>;
 
 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{
   return ((uint32_t)Imm) < 256;
class ADRI<bit page, string asm, Operand adr, list<dag> pattern>
   let DecoderMethod = "DecodeAdrInstruction";
 }
 
 //---
 // Move immediate.
 //---
 
 def movimm32_imm : Operand<i32> {
-  let ParserMatchClass = Imm0_65535Operand;
+  let ParserMatchClass = AsmImmRange<0, 65535>;
   let EncoderMethod = "getMoveWideImmOpValue";
   let PrintMethod = "printImm";
 }
 def movimm32_shift : Operand<i32> {
   let PrintMethod = "printShifter";
   let ParserMatchClass = MovImm32ShifterOperand;
 }
 def movimm64_shift : Operand<i32> {
class ExceptionGeneration<bits<3> op1, bits<2> ll, string asm>
   bits<16> imm;
   let Inst{31-24} = 0b11010100;
   let Inst{23-21} = op1;
   let Inst{20-5}  = imm;
   let Inst{4-2}   = 0b000;
   let Inst{1-0}   = ll;
 }
 
+//---
+// UDF : Permanently UNDEFINED instructions.  Format: Opc = 0x0000, 16 bit imm.
+//--
+let hasSideEffects = 1, isTrap = 1, mayLoad = 0, mayStore = 0 in {
+class UDFType<bits<16> opc, string asm>
+  : I<(outs), (ins uimm16:$imm),
+       asm, "\t$imm", "", []>,
+    Sched<[]> {
+  bits<16> imm;
+  let Inst{31-16} = opc;
+  let Inst{15-0} = imm;
+}
+}
 let Predicates = [HasFPARMv8] in {
 
 //---
 // Floating point to integer conversion
 //---
 
 class BaseFPToIntegerUnscaled<bits<2> type, bits<2> rmode, bits<3> opcode,
                       RegisterClass srcType, RegisterClass dstType,

lib/Target/AArch64/AArch64InstrInfo.td

 def SMC   : ExceptionGeneration<0b000, 0b11, "smc">;
 def SVC   : ExceptionGeneration<0b000, 0b01, "svc">;
 
 // DCPSn defaults to an immediate operand of zero if unspecified.
 def : InstAlias<"dcps1", (DCPS1 0)>;
 def : InstAlias<"dcps2", (DCPS2 0)>;
 def : InstAlias<"dcps3", (DCPS3 0)>;
 
+def UDF : UDFType<0, "udf">;
+
 //===----------------------------------------------------------------------===//
 // Load instructions.
 //===----------------------------------------------------------------------===//
 
 // Pair (indexed, offset)
 defm LDPW : LoadPairOffset<0b00, 0, GPR32z, simm7s4, "ldp">;
 defm LDPX : LoadPairOffset<0b10, 0, GPR64z, simm7s8, "ldp">;
 defm LDPS : LoadPairOffset<0b00, 1, FPR32Op, simm7s4, "ldp">;