Add support for AArch64 UDF instruction

[dnsampaio]

Summary

UDF

Permanently Undefined generates an Undefined Instruction exception (ESR_ELx.EC = 0b000000).
The encodings for UDF used in this section are defined as permanently undefined in the ARMv8-A architecture.
https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/udf-permanently-undefined

[javed.absar]

lib/Target/AArch64/AArch64InstrFormats.td

4088

The 'uimm16' is generic and should be pulled up to where others (e.g. uimmm6) are defined.

test/MC/AArch64/udf.s

14

Some of these look unnecessary (just bounaries and a value in between is enough)

[dnsampaio]

To send patch....

lib/Target/AArch64/AArch64InstrFormats.td

4088

I can't if to reuse the existing ParserMatchClass = Imm0_65535Operand. I followed the same pattern of the // Move immediate., that defined the immediate types just before the instructions.

[dnsampaio]

Fixed the tests as to check boundaries, and one value in the middle.
Changed tests ordering as they generated empty lines not treated by FileCheck.

[nhaehnle]

lib/Target/AArch64/AArch64InstrFormats.td

4088

Note that at least the TableGen frontend allows you to inline expressions such as AsmImmRange<0, 65535> directly into the let statement.

The generated records will be de-duplicated, except in the case of an explicit instantiation (like the existing def Imm0_65535Operand).

I don't know if existing backends would stumble over a mixture of both explicit and implicit instantiations for ParserMatchClass, but consistently using inline AsmImmRange expressions everywhere should work.

(Just my 2c of TableGen info, do with it whatever you like, as I'm not working on AArch64 ;))

[dnsampaio]

lib/Target/AArch64/AArch64InstrFormats.td

4088

I don't believe the de-duplication works very well then.
If I do change let ParserMatchClass = Imm0_65535Operand to let ParserMatchClass = AsmImmRange<0x0, 0xffff>; I get

In file included from /work/bf/LLVM/local/src/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp:5449:0:
lib/Target/AArch64/AArch64GenAsmMatcher.inc:7354:3: error: redefinition of 'MCK_Imm0_65535'
   MCK_Imm0_65535, // user defined class 'anonymous_1075'
   ^
lib/Target/AArch64/AArch64GenAsmMatcher.inc:7139:3: note: 'MCK_Imm0_65535' previously defined here
   MCK_Imm0_65535, // user defined class 'Imm0_65535Operand'
   ^
lib/Target/AArch64/AArch64GenAsmMatcher.inc: In function 'unsigned int validateOperandClass(llvm::MCParsedAsmOperand&, {anonymous}::MatchClassKind)':
lib/Target/AArch64/AArch64GenAsmMatcher.inc:10405:3: error: duplicate case value
   case MCK_Imm0_65535: {
   ^
lib/Target/AArch64/AArch64GenAsmMatcher.inc:8644:3: error: previously used here
   case MCK_Imm0_65535: {
   ^
lib/Target/AArch64/AArch64GenAsmMatcher.inc: In function 'const char* getMatchClassName({anonymous}::MatchClassKind)':
lib/Target/AArch64/AArch64GenAsmMatcher.inc:11852:3: error: duplicate case value
   case MCK_Imm0_65535: return "MCK_Imm0_65535";
   ^
lib/Target/AArch64/AArch64GenAsmMatcher.inc:11637:3: error: previously used here
   case MCK_Imm0_65535: return "MCK_Imm0_65535";
   ^
lib/Target/AArch64/AArch64GenAsmMatcher.inc:11445:10: warning: enumeration value 'MCK_Imm0_65535' not handled in switch [-Wswitch]
   switch (Kind) {

[dnsampaio]

No custom decoding is required

[nhaehnle]

lib/Target/AArch64/AArch64InstrFormats.td

4088

Yeah, that confirms my suspicion that things break when you mix explicit with implicit definitions. The redefinition comes from the fact that you still have a named def that is equivalent to the anonymous def that's generated by the inline mention.

[dnsampaio]

Ping.

[dnsampaio]

Refactoring.

[javed.absar]

Could you add assembler/disassembler tests for udf ?

lib/Target/AArch64/AArch64InstrFormats.td

292

maybe the formatting should be similar to surrounding code ( [{.*}] one same line).

[dnsampaio]

Re-inserted the missing tests. Small refactoring as to look alike neighbor code.

[dnsampaio]

Added blank lines at end of test files.

lib/Target/AArch64/AArch64InstrFormats.td

 }
 
 def uimm6 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm < 64; }]> {
   let ParserMatchClass = UImm6Operand;
 }
 
 def SImm9Operand : SImmOperand<9>;
 def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> {
   let ParserMatchClass = SImm9Operand;
   let DecoderMethod = "DecodeSImm<9>";
 }
 
 def SImm8Operand : SImmOperand<8>;
 def simm8 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -128 && Imm < 127; }]> {
   let ParserMatchClass = SImm8Operand;
   let DecoderMethod = "DecodeSImm<8>";
 }
class ExceptionGeneration<bits<3> op1, bits<2> ll, string asm>
   bits<16> imm;
   let Inst{31-24} = 0b11010100;
   let Inst{23-21} = op1;
   let Inst{20-5}  = imm;
   let Inst{4-2}   = 0b000;
   let Inst{1-0}   = ll;
 }
 
+//---
+// UDF : Permanently UNDEFINED instructions.  Format: Opc = 0x0000, 16 bit imm.
+//--
+def uimm16 : Operand<i16>, ImmLeaf<i16, [{
+  return ((uint32_t)Imm) < 65536;
+}]>{
+  let ParserMatchClass = Imm0_65535Operand;
+  let PrintMethod = "printImm";
+  let DecoderMethod =  "DecodeUImm16";
+}
+
+let hasSideEffects = 1, isTrap = 1, mayLoad = 0, mayStore = 0 in {
+class UDFType<bits<16> opc, string asm>
+  : I<(outs), (ins uimm16:$imm),
+       asm, "\t$imm", "", []>,
+    Sched<[]> {
+  bits<16> imm;
+  let Inst{31-16} = opc;
+  let Inst{15-0} = imm;
+}
+}
 let Predicates = [HasFPARMv8] in {
 
 //---
 // Floating point to integer conversion
 //---
 
 class BaseFPToIntegerUnscaled<bits<2> type, bits<2> rmode, bits<3> opcode,
                       RegisterClass srcType, RegisterClass dstType,

lib/Target/AArch64/AArch64InstrInfo.td

 def SMC   : ExceptionGeneration<0b000, 0b11, "smc">;
 def SVC   : ExceptionGeneration<0b000, 0b01, "svc">;
 
 // DCPSn defaults to an immediate operand of zero if unspecified.
 def : InstAlias<"dcps1", (DCPS1 0)>;
 def : InstAlias<"dcps2", (DCPS2 0)>;
 def : InstAlias<"dcps3", (DCPS3 0)>;
 
+def UDF : UDFType<0, "udf">;
+
 //===----------------------------------------------------------------------===//
 // Load instructions.
 //===----------------------------------------------------------------------===//
 
 // Pair (indexed, offset)
 defm LDPW : LoadPairOffset<0b00, 0, GPR32z, simm7s4, "ldp">;
 defm LDPX : LoadPairOffset<0b10, 0, GPR64z, simm7s8, "ldp">;
 defm LDPS : LoadPairOffset<0b00, 1, FPR32Op, simm7s4, "ldp">;

lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
                                        uint64_t Addr, const void *Decoder);
 
 static DecodeStatus DecodeLoadAllocTagArrayInstruction(MCInst &Inst,
                                                        uint32_t insn,
                                                        uint64_t address,
                                                        const void* Decoder);
 
+static DecodeStatus DecodeUImm16(MCInst &Inst, uint32_t insn, uint64_t Address,
+                                 const void *Decoder);
+
 static bool Check(DecodeStatus &Out, DecodeStatus In) {
   switch (In) {
     case MCDisassembler::Success:
       // Out stays the same.
       return true;
     case MCDisassembler::SoftFail:
       Out = In;
       return true;
if (Inst.getOpcode() == AArch64::MOVKWi ||
       Inst.getOpcode() == AArch64::MOVKXi)
     Inst.addOperand(Inst.getOperand(0));
 
   Inst.addOperand(MCOperand::createImm(imm));
   Inst.addOperand(MCOperand::createImm(shift));
   return Success;
 }
 
+static DecodeStatus DecodeUImm16(MCInst &Inst, uint32_t insn, uint64_t Addr,
+                                 const void *Decoder) {
+  switch (Inst.getOpcode()) {
+  case AArch64::UDF: {
+    unsigned imm = fieldFromInstruction(insn, 0, 15);
+    Inst.addOperand(MCOperand::createImm(imm));
+    return Success;
+  }
+  default:
+    assert(false && Inst.getOpcode() && "Don't know how to treat this opcode");
+    break;
+  }
+  return Success;
+}
+
 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn,
                                                   uint64_t Addr,
                                                   const void *Decoder) {
   unsigned Rt = fieldFromInstruction(insn, 0, 5);
   unsigned Rn = fieldFromInstruction(insn, 5, 5);
   unsigned offset = fieldFromInstruction(insn, 10, 12);
   const AArch64Disassembler *Dis =
       static_cast<const AArch64Disassembler *>(Decoder);

test/MC/AArch64/udf-erros.s

+# RUN: not llvm-mc -assemble -show-encoding -triple=aarch64- %s 2>&1 | FileCheck %s
+
+udf 65536
+# CHECK:{{.*}} immediate must be an integer in range [0, 65535].
+
+udf -1
+# CHECK:{{.*}} immediate must be an integer in range [0, 65535].
+
+udf -768
+# CHECK:{{.*}} immediate must be an integer in range [0, 65535].

test/MC/AArch64/udf.s

+# RUN: llvm-mc -assemble -show-encoding -triple=aarch64- %s | FileCheck %s
+.text
+# CHECK:  .text
+
+udf 0
+# CHECK-NEXT: udf #0      // encoding: [0x00,0x00,0x00,0x00]
+
+udf 1
+# CHECK-NEXT: udf #1      // encoding: [0x01,0x00,0x00,0x00]
+
+udf 16
+# CHECK-NEXT: udf #16     // encoding: [0x10,0x00,0x00,0x00]
+
+udf 32
+# CHECK-NEXT: udf #32     // encoding: [0x20,0x00,0x00,0x00]
+
+udf 48
+# CHECK-NEXT: udf #48     // encoding: [0x30,0x00,0x00,0x00]
+
+udf 65535
+# CHECK-NEXT: udf #65535      // encoding: [0xff,0xff,0x00,0x00]

test/MC/Disassembler/AArch64/udf.txt

+# RUN: llvm-mc -arch aarch64 -disassemble -o - %s | FileCheck %s
+
+# RUN: llvm-mc -arch aarch64 -disassemble -o - %s | \
+# RUN: llvm-mc -assemble -filetype=obj -arch aarch64 -o - | \
+# RUN: llvm-objdump -r -d --triple=arm64- - | \
+# RUN: FileCheck %s -check-prefix=OBJ
+
+# CHECK: .text
+# OBJ: Disassembly of section .text:
+# OBJ-NEXT: $x.0:
+
+[0x00,0x00,0x00,0x00]
+# CHECK-NEXT: udf #0
+# OBJ-NEXT:        0: 00 00 00 00   udf #0
+
+[0x01,0x00,0x00,0x00]
+# CHECK-NEXT: udf #1
+# OBJ-NEXT:        4: 01 00 00 00   udf #1
+
+[0x10,0x00,0x00,0x00]
+# CHECK-NEXT: udf #16
+# OBJ-NEXT:        8: 10 00 00 00   udf #16
+
+[0x20,0x00,0x00,0x00]
+# CHECK-NEXT: udf #32
+# OBJ-NEXT:        c: 20 00 00 00   udf #32
+
+[0x30,0x00,0x00,0x00]
+# CHECK-NEXT: udf #48
+# OBJ-NEXT:       10: 30 00 00 00   udf #48
+
+[0xff,0xff,0x00,0x00]
+# CHECK-NEXT: udf #32767
+# OBJ-NEXT:       14: ff 7f 00 00   udf #32767
+
+[0x00,0xfd,0x00,0x00]
+# CHECK-NEXT: udf #32000
+# OBJ-NEXT:       18: 00 7d 00 00   udf #32000