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Differential D53319

Add support for AArch64 UDF instruction
ClosedPublic

Authored by dnsampaio on Oct 16 2018, 3:17 AM.

Details

Reviewers
DavidSpickett
javed.absar
t.p.northover
Commits
rGa3783b2ac2bc: [AArch64] Add support for UDF instruction
rL345581: [AArch64] Add support for UDF instruction
Summary

UDF

Permanently Undefined generates an Undefined Instruction exception (ESR_ELx.EC = 0b000000).
The encodings for UDF used in this section are defined as permanently undefined in the ARMv8-A architecture.
https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/udf-permanently-undefined

Diff Detail

Repository
rL LLVM

Event Timeline

dnsampaio created this revision.Oct 16 2018, 3:17 AM
Herald added a subscriber: kristof.beyls. · View Herald TranscriptOct 16 2018, 3:18 AM
javed.absar added inline comments.Oct 16 2018, 3:47 AM
lib/Target/AArch64/AArch64InstrFormats.td
4088 ↗(On Diff #169803)

The 'uimm16' is generic and should be pulled up to where others (e.g. uimmm6) are defined.

test/MC/AArch64/udf.s
14 ↗(On Diff #169803)

Some of these look unnecessary (just bounaries and a value in between is enough)

Herald added a subscriber: nhaehnle. · View Herald TranscriptOct 16 2018, 3:47 AM
dnsampaio marked an inline comment as done.Oct 16 2018, 4:29 AM

To send patch....

lib/Target/AArch64/AArch64InstrFormats.td
4088 ↗(On Diff #169803)

I can't if to reuse the existing ParserMatchClass = Imm0_65535Operand. I followed the same pattern of the // Move immediate., that defined the immediate types just before the instructions.

dnsampaio updated this revision to Diff 169809.Oct 16 2018, 4:50 AM

Fixed the tests as to check boundaries, and one value in the middle.
Changed tests ordering as they generated empty lines not treated by FileCheck.

nhaehnle added inline comments.Oct 16 2018, 5:07 AM
lib/Target/AArch64/AArch64InstrFormats.td
4088 ↗(On Diff #169803)

Note that at least the TableGen frontend allows you to inline expressions such as AsmImmRange<0, 65535> directly into the let statement.

The generated records will be de-duplicated, except in the case of an explicit instantiation (like the existing def Imm0_65535Operand).

I don't know if existing backends would stumble over a mixture of both explicit and implicit instantiations for ParserMatchClass, but consistently using inline AsmImmRange expressions everywhere should work.

(Just my 2c of TableGen info, do with it whatever you like, as I'm not working on AArch64 ;))

dnsampaio added inline comments.Oct 16 2018, 10:22 AM
lib/Target/AArch64/AArch64InstrFormats.td
4088 ↗(On Diff #169803)

I don't believe the de-duplication works very well then.
If I do change let ParserMatchClass = Imm0_65535Operand to let ParserMatchClass = AsmImmRange<0x0, 0xffff>; I get

In file included from /work/bf/LLVM/local/src/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp:5449:0:
lib/Target/AArch64/AArch64GenAsmMatcher.inc:7354:3: error: redefinition of 'MCK_Imm0_65535'
   MCK_Imm0_65535, // user defined class 'anonymous_1075'
   ^
lib/Target/AArch64/AArch64GenAsmMatcher.inc:7139:3: note: 'MCK_Imm0_65535' previously defined here
   MCK_Imm0_65535, // user defined class 'Imm0_65535Operand'
   ^
lib/Target/AArch64/AArch64GenAsmMatcher.inc: In function 'unsigned int validateOperandClass(llvm::MCParsedAsmOperand&, {anonymous}::MatchClassKind)':
lib/Target/AArch64/AArch64GenAsmMatcher.inc:10405:3: error: duplicate case value
   case MCK_Imm0_65535: {
   ^
lib/Target/AArch64/AArch64GenAsmMatcher.inc:8644:3: error: previously used here
   case MCK_Imm0_65535: {
   ^
lib/Target/AArch64/AArch64GenAsmMatcher.inc: In function 'const char* getMatchClassName({anonymous}::MatchClassKind)':
lib/Target/AArch64/AArch64GenAsmMatcher.inc:11852:3: error: duplicate case value
   case MCK_Imm0_65535: return "MCK_Imm0_65535";
   ^
lib/Target/AArch64/AArch64GenAsmMatcher.inc:11637:3: error: previously used here
   case MCK_Imm0_65535: return "MCK_Imm0_65535";
   ^
lib/Target/AArch64/AArch64GenAsmMatcher.inc:11445:10: warning: enumeration value 'MCK_Imm0_65535' not handled in switch [-Wswitch]
   switch (Kind) {
dnsampaio updated this revision to Diff 169859.Oct 16 2018, 10:57 AM

No custom decoding is required

nhaehnle added inline comments.Oct 16 2018, 10:59 AM
lib/Target/AArch64/AArch64InstrFormats.td
4088 ↗(On Diff #169803)

Yeah, that confirms my suspicion that things break when you mix explicit with implicit definitions. The redefinition comes from the fact that you still have a named def that is equivalent to the anonymous def that's generated by the inline mention.

dnsampaio added a comment.Oct 19 2018, 9:07 AM

Ping.

dnsampaio updated this revision to Diff 170600.Oct 23 2018, 3:45 AM

Refactoring.

javed.absar added a comment.Oct 29 2018, 3:06 AM

Could you add assembler/disassembler tests for udf ?

lib/Target/AArch64/AArch64InstrFormats.td
300 ↗(On Diff #170600)

maybe the formatting should be similar to surrounding code ( [{.*}] one same line).

dnsampaio marked an inline comment as done.Oct 29 2018, 4:22 AM
dnsampaio updated this revision to Diff 171483.Oct 29 2018, 4:25 AM

Re-inserted the missing tests. Small refactoring as to look alike neighbor code.

dnsampaio updated this revision to Diff 171657.Oct 30 2018, 3:35 AM

Added blank lines at end of test files.

javed.absar accepted this revision.Oct 30 2018, 3:39 AM
This revision is now accepted and ready to land.Oct 30 2018, 3:39 AM
Closed by commit rL345581: [AArch64] Add support for UDF instruction (authored by dnsampaio). · Explain WhyOct 30 2018, 4:09 AM
This revision was automatically updated to reflect the committed changes.
Herald added a subscriber: llvm-commits. · View Herald TranscriptOct 30 2018, 4:09 AM

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AArch64/
37 lines
2 lines
test/
MC/
AArch64/
15 lines
7 lines
Disassembler/
AArch64/
30 lines

Diff 171665

llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td

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class SImmOperand<int width> : AsmOperandClass { class SImmOperand<int width> : AsmOperandClass {
let Name = "SImm" # width; let Name = "SImm" # width;
let DiagnosticType = "InvalidMemoryIndexedSImm" # width; let DiagnosticType = "InvalidMemoryIndexedSImm" # width;
let RenderMethod = "addImmOperands"; let RenderMethod = "addImmOperands";
let PredicateMethod = "isSImm<" # width # ">"; let PredicateMethod = "isSImm<" # width # ">";
} }
class AsmImmRange<int Low, int High> : AsmOperandClass {
let Name = "Imm" # Low # "_" # High;
let DiagnosticType = "InvalidImm" # Low # "_" # High;
let RenderMethod = "addImmOperands";
let PredicateMethod = "isImmInRange<" # Low # "," # High # ">";
}
// Authenticated loads for v8.3 can have scaled 10-bit immediate offsets. // Authenticated loads for v8.3 can have scaled 10-bit immediate offsets.
def SImm10s8Operand : SImmScaledMemoryIndexed<10, 8>; def SImm10s8Operand : SImmScaledMemoryIndexed<10, 8>;
def simm10Scaled : Operand<i64> { def simm10Scaled : Operand<i64> {
let ParserMatchClass = SImm10s8Operand; let ParserMatchClass = SImm10s8Operand;
let DecoderMethod = "DecodeSImm<10>"; let DecoderMethod = "DecodeSImm<10>";
let PrintMethod = "printImmScale<8>"; let PrintMethod = "printImmScale<8>";
} }
def simm9s16 : Operand<i64> { def simm9s16 : Operand<i64> {
let ParserMatchClass = SImmScaledMemoryIndexed<9, 16>; let ParserMatchClass = SImmScaledMemoryIndexed<9, 16>;
let DecoderMethod = "DecodeSImm<9>"; let DecoderMethod = "DecodeSImm<9>";
let PrintMethod = "printImmScale<16>"; let PrintMethod = "printImmScale<16>";
} }
// uimm6 predicate - True if the immediate is in the range [0, 63]. // uimm6 predicate - True if the immediate is in the range [0, 63].
def UImm6Operand : AsmOperandClass { def UImm6Operand : AsmOperandClass {
let Name = "UImm6"; let Name = "UImm6";
let DiagnosticType = "InvalidImm0_63"; let DiagnosticType = "InvalidImm0_63";
} }
def uimm6 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm < 64; }]> { def uimm6 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm < 64; }]> {
let ParserMatchClass = UImm6Operand; let ParserMatchClass = UImm6Operand;
} }
def uimm16 : Operand<i16>, ImmLeaf<i16, [{return Imm >= 0 && Imm < 65536;}]>{
let ParserMatchClass = AsmImmRange<0, 65535>;
}
def SImm9Operand : SImmOperand<9>; def SImm9Operand : SImmOperand<9>;
def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> { def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> {
let ParserMatchClass = SImm9Operand; let ParserMatchClass = SImm9Operand;
let DecoderMethod = "DecodeSImm<9>"; let DecoderMethod = "DecodeSImm<9>";
} }
def SImm8Operand : SImmOperand<8>; def SImm8Operand : SImmOperand<8>;
def simm8 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -128 && Imm < 127; }]> { def simm8 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -128 && Imm < 127; }]> {
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} }
def simm4s16 : Operand<i64>, ImmLeaf<i64, def simm4s16 : Operand<i64>, ImmLeaf<i64,
[{ return Imm >=-128 && Imm <= 112 && (Imm % 16) == 0x0; }]> { [{ return Imm >=-128 && Imm <= 112 && (Imm % 16) == 0x0; }]> {
let PrintMethod = "printImmScale<16>"; let PrintMethod = "printImmScale<16>";
let ParserMatchClass = SImm4s16Operand; let ParserMatchClass = SImm4s16Operand;
let DecoderMethod = "DecodeSImm<4>"; let DecoderMethod = "DecodeSImm<4>";
} }
class AsmImmRange<int Low, int High> : AsmOperandClass {
let Name = "Imm" # Low # "_" # High;
let DiagnosticType = "InvalidImm" # Low # "_" # High;
let RenderMethod = "addImmOperands";
let PredicateMethod = "isImmInRange<" # Low # "," # High # ">";
}
def Imm1_8Operand : AsmImmRange<1, 8>; def Imm1_8Operand : AsmImmRange<1, 8>;
def Imm1_16Operand : AsmImmRange<1, 16>; def Imm1_16Operand : AsmImmRange<1, 16>;
def Imm1_32Operand : AsmImmRange<1, 32>; def Imm1_32Operand : AsmImmRange<1, 32>;
def Imm1_64Operand : AsmImmRange<1, 64>; def Imm1_64Operand : AsmImmRange<1, 64>;
class BranchTarget<int N> : AsmOperandClass { class BranchTarget<int N> : AsmOperandClass {
let Name = "BranchTarget" # N; let Name = "BranchTarget" # N;
let DiagnosticType = "InvalidLabel"; let DiagnosticType = "InvalidLabel";
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def logical_imm32_not : Operand<i32> { def logical_imm32_not : Operand<i32> {
let ParserMatchClass = LogicalImm32NotOperand; let ParserMatchClass = LogicalImm32NotOperand;
} }
def logical_imm64_not : Operand<i64> { def logical_imm64_not : Operand<i64> {
let ParserMatchClass = LogicalImm64NotOperand; let ParserMatchClass = LogicalImm64NotOperand;
} }
// imm0_65535 predicate - True if the immediate is in the range [0,65535]. // imm0_65535 predicate - True if the immediate is in the range [0,65535].
def Imm0_65535Operand : AsmImmRange<0, 65535>;
def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{ def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
return ((uint32_t)Imm) < 65536; return ((uint32_t)Imm) < 65536;
}]> { }]> {
let ParserMatchClass = Imm0_65535Operand; let ParserMatchClass = AsmImmRange<0, 65535>;
let PrintMethod = "printImmHex"; let PrintMethod = "printImmHex";
} }
// imm0_255 predicate - True if the immediate is in the range [0,255]. // imm0_255 predicate - True if the immediate is in the range [0,255].
def Imm0_255Operand : AsmImmRange<0,255>; def Imm0_255Operand : AsmImmRange<0,255>;
def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ def imm0_255 : Operand<i32>, ImmLeaf<i32, [{
return ((uint32_t)Imm) < 256; return ((uint32_t)Imm) < 256;
▲ Show 20 Lines • Show All 1,208 Lines • ▼ Show 20 Linesclass ADRI<bit page, string asm, Operand adr, list<dag> pattern>
let DecoderMethod = "DecodeAdrInstruction"; let DecoderMethod = "DecodeAdrInstruction";
} }
//--- //---
// Move immediate. // Move immediate.
//--- //---
def movimm32_imm : Operand<i32> { def movimm32_imm : Operand<i32> {
let ParserMatchClass = Imm0_65535Operand; let ParserMatchClass = AsmImmRange<0, 65535>;
let EncoderMethod = "getMoveWideImmOpValue"; let EncoderMethod = "getMoveWideImmOpValue";
let PrintMethod = "printImm"; let PrintMethod = "printImm";
} }
def movimm32_shift : Operand<i32> { def movimm32_shift : Operand<i32> {
let PrintMethod = "printShifter"; let PrintMethod = "printShifter";
let ParserMatchClass = MovImm32ShifterOperand; let ParserMatchClass = MovImm32ShifterOperand;
} }
def movimm64_shift : Operand<i32> { def movimm64_shift : Operand<i32> {
▲ Show 20 Lines • Show All 2,128 Lines • ▼ Show 20 Linesclass ExceptionGeneration<bits<3> op1, bits<2> ll, string asm>
bits<16> imm; bits<16> imm;
let Inst{31-24} = 0b11010100; let Inst{31-24} = 0b11010100;
let Inst{23-21} = op1; let Inst{23-21} = op1;
let Inst{20-5} = imm; let Inst{20-5} = imm;
let Inst{4-2} = 0b000; let Inst{4-2} = 0b000;
let Inst{1-0} = ll; let Inst{1-0} = ll;
} }
//---
// UDF : Permanently UNDEFINED instructions. Format: Opc = 0x0000, 16 bit imm.
//--
let hasSideEffects = 1, isTrap = 1, mayLoad = 0, mayStore = 0 in {
class UDFType<bits<16> opc, string asm>
: I<(outs), (ins uimm16:$imm),
asm, "\t$imm", "", []>,
Sched<[]> {
bits<16> imm;
let Inst{31-16} = opc;
let Inst{15-0} = imm;
}
}
let Predicates = [HasFPARMv8] in { let Predicates = [HasFPARMv8] in {
//--- //---
// Floating point to integer conversion // Floating point to integer conversion
//--- //---
class BaseFPToIntegerUnscaled<bits<2> type, bits<2> rmode, bits<3> opcode, class BaseFPToIntegerUnscaled<bits<2> type, bits<2> rmode, bits<3> opcode,
RegisterClass srcType, RegisterClass dstType, RegisterClass srcType, RegisterClass dstType,
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llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td

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def SMC : ExceptionGeneration<0b000, 0b11, "smc">; def SMC : ExceptionGeneration<0b000, 0b11, "smc">;
def SVC : ExceptionGeneration<0b000, 0b01, "svc">; def SVC : ExceptionGeneration<0b000, 0b01, "svc">;
// DCPSn defaults to an immediate operand of zero if unspecified. // DCPSn defaults to an immediate operand of zero if unspecified.
def : InstAlias<"dcps1", (DCPS1 0)>; def : InstAlias<"dcps1", (DCPS1 0)>;
def : InstAlias<"dcps2", (DCPS2 0)>; def : InstAlias<"dcps2", (DCPS2 0)>;
def : InstAlias<"dcps3", (DCPS3 0)>; def : InstAlias<"dcps3", (DCPS3 0)>;
def UDF : UDFType<0, "udf">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Load instructions. // Load instructions.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Pair (indexed, offset) // Pair (indexed, offset)
defm LDPW : LoadPairOffset<0b00, 0, GPR32z, simm7s4, "ldp">; defm LDPW : LoadPairOffset<0b00, 0, GPR32z, simm7s4, "ldp">;
defm LDPX : LoadPairOffset<0b10, 0, GPR64z, simm7s8, "ldp">; defm LDPX : LoadPairOffset<0b10, 0, GPR64z, simm7s8, "ldp">;
defm LDPS : LoadPairOffset<0b00, 1, FPR32Op, simm7s4, "ldp">; defm LDPS : LoadPairOffset<0b00, 1, FPR32Op, simm7s4, "ldp">;
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llvm/trunk/test/MC/AArch64/udf.s

# RUN: llvm-mc -assemble -show-encoding -triple=aarch64- %s | FileCheck %s
# CHECK: .text
# CHECK-NEXT: udf #0 // encoding: [0x00,0x00,0x00,0x00]
# CHECK-NEXT: udf #1 // encoding: [0x01,0x00,0x00,0x00]
# CHECK-NEXT: udf #16 // encoding: [0x10,0x00,0x00,0x00]
# CHECK-NEXT: udf #32 // encoding: [0x20,0x00,0x00,0x00]
# CHECK-NEXT: udf #48 // encoding: [0x30,0x00,0x00,0x00]
# CHECK-NEXT: udf #65535 // encoding: [0xff,0xff,0x00,0x00]
.text
udf 0
udf 1
udf 16
udf 32
udf 48
udf 65535

llvm/trunk/test/MC/AArch64/udf_not.s

# RUN: not llvm-mc -assemble -show-encoding -triple=aarch64- %s 2>&1 | FileCheck %s
udf 65536
udf -1
udf -768
# CHECK:{{.*}} immediate must be an integer in range [0, 65535].
# CHECK:{{.*}} immediate must be an integer in range [0, 65535].
# CHECK:{{.*}} immediate must be an integer in range [0, 65535].

llvm/trunk/test/MC/Disassembler/AArch64/udf.txt

# RUN: llvm-mc -arch aarch64 -disassemble -o - %s | FileCheck %s
# RUN: llvm-mc -arch aarch64 -disassemble -o - %s | \
# RUN: llvm-mc -assemble -filetype=obj -arch aarch64 -o - | \
# RUN: llvm-objdump -r -d --triple=arm64- - | \
# RUN: FileCheck %s -check-prefix=OBJ
[0x00,0x00,0x00,0x00]
[0x01,0x00,0x00,0x00]
[0x10,0x00,0x00,0x00]
[0x20,0x00,0x00,0x00]
[0x30,0x00,0x00,0x00]
[0xff,0xff,0x00,0x00]
[0x00,0xfd,0x00,0x00]
# CHECK: .text
# CHECK-NEXT: udf #0
# CHECK-NEXT: udf #1
# CHECK-NEXT: udf #16
# CHECK-NEXT: udf #32
# CHECK-NEXT: udf #48
# CHECK-NEXT: udf #32767
# CHECK-NEXT: udf #32000
#OBJ: Disassembly of section .text:
#OBJ-NEXT: $x.0:
#OBJ-NEXT: 0: 00 00 00 00 udf #0
#OBJ-NEXT: 4: 01 00 00 00 udf #1
#OBJ-NEXT: 8: 10 00 00 00 udf #16
#OBJ-NEXT: c: 20 00 00 00 udf #32
#OBJ-NEXT: 10: 30 00 00 00 udf #48
#OBJ-NEXT: 14: ff 7f 00 00 udf #32767
#OBJ-NEXT: 18: 00 7d 00 00 udf #32000