[AArch64] Swap comparison operands if that enables some folding.

[aadg]

Summary

AArch64 can fold some shift+extend operations on the RHS operand of
comparisons, so swap the operands if that makes sense.

This provides a fix for https://bugs.llvm.org/show_bug.cgi?id=38751

[SjoerdMeijer]

lib/Target/AArch64/AArch64ISelLowering.cpp

1802

Had a quick first look, so sorry for some question about testing.... If the shift amount is in the range [0,31] and [0,64], are the edge cases tested (also values just outside this range)? Also, can Shift be negative here?

1879

Nit, feel free to ignore: perhaps the example can be given in terms of ISD nodes because that's what we're transforming here. And then TheLHS can perhaps be given a more meaningful name.

[aadg]

lib/Target/AArch64/AArch64ISelLowering.cpp

1802

The ARMARM definitely states Shift has to be in [0:31] (32bits variant) or [0:63] (64 bits variant), so it can not be negative.
You however point rightfully that testcases for the out-of-range cases for the upper bound are missing --- I'll add them right away.

1879

I think it's best to have the example in terms of what we are trying to achieve at the ISA level as this gives the reader the "why" we want to do it. The how we actually do it is what the code does.
Regarding TheLHS, it's a pattern often found in the code base and denotes what is the LHS (theLHS) under consideration at this point in the code, as it might differ from a high level LHS. I'm open to a better naming though if you have suggestions

[aadg]

lib/Target/AArch64/AArch64ISelLowering.cpp

1802

After thinking about it a bit more, testing the out of bound case for upper range is ... UB. But there are definitely some testcases missing, and those will be added.

[SjoerdMeijer]

lib/Target/AArch64/AArch64ISelLowering.cpp

1802

After thinking about it a bit more, testing the out of bound case for upper range is ... UB.

Ah yes, of course. I was thinking it could inhibit this rewrite.

1879

I think it's best to have the example in terms of what we are trying to achieve at the ISA

Fair enough.

Regarding TheLHS, it's a pattern often found in the code base and denotes what is the LHS (theLHS)

Sure, but we have 2 variables TheLHS and LHS here, which could be a bit confusing. Anyway, as I said, I was nitpicking, so please ignore.

[aadg]

Address previous review comments by adding missing testcases.

[SjoerdMeijer]

Looks fine to me

lib/Target/AArch64/AArch64ISelLowering.cpp

 static bool isLegalArithImmed(uint64_t C) {
   // Matches AArch64DAGToDAGISel::SelectArithImmed().
   bool IsLegal = (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0);
   LLVM_DEBUG(dbgs() << "Is imm " << C
                     << " legal: " << (IsLegal ? "yes\n" : "no\n"));
   return IsLegal;
 }
 
+// Can a (CMP op1, (sub 0, op2) be turned into a CMN instruction on
+// the grounds that "op1 - (-op2) == op1 + op2" ? Not always, the C and V flags
+// can be set differently by this operation. It comes down to whether
+// "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then
+// everything is fine. If not then the optimization is wrong. Thus general
+// comparisons are only valid if op2 != 0.
+//
+// So, finally, the only LLVM-native comparisons that don't mention C and V
+// are SETEQ and SETNE. They're the only ones we can safely use CMN for in
+// the absence of information about op2.
+static bool isCMN(SDValue Op, ISD::CondCode CC) {
+  return Op.getOpcode() == ISD::SUB && isNullConstant(Op.getOperand(0)) &&
+         (CC == ISD::SETEQ || CC == ISD::SETNE);
+}
+
 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
                               const SDLoc &dl, SelectionDAG &DAG) {
   EVT VT = LHS.getValueType();
   const bool FullFP16 =
     static_cast<const AArch64Subtarget &>(DAG.getSubtarget()).hasFullFP16();
 
   if (VT.isFloatingPoint()) {
     assert(VT != MVT::f128);
     if (VT == MVT::f16 && !FullFP16) {
       LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, LHS);
       RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, RHS);
       VT = MVT::f32;
     }
     return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
   }
 
   // The CMP instruction is just an alias for SUBS, and representing it as
   // SUBS means that it's possible to get CSE with subtract operations.
   // A later phase can perform the optimization of setting the destination
   // register to WZR/XZR if it ends up being unused.
   unsigned Opcode = AArch64ISD::SUBS;
 
-  if (RHS.getOpcode() == ISD::SUB && isNullConstant(RHS.getOperand(0)) &&
-      (CC == ISD::SETEQ || CC == ISD::SETNE)) {
-    // We'd like to combine a (CMP op1, (sub 0, op2) into a CMN instruction on
-    // the grounds that "op1 - (-op2) == op1 + op2". However, the C and V flags
-    // can be set differently by this operation. It comes down to whether
-    // "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then
-    // everything is fine. If not then the optimization is wrong. Thus general
-    // comparisons are only valid if op2 != 0.
-
-    // So, finally, the only LLVM-native comparisons that don't mention C and V
-    // are SETEQ and SETNE. They're the only ones we can safely use CMN for in
-    // the absence of information about op2.
+  if (isCMN(RHS, CC)) {
+    // Can we combine a (CMP op1, (sub 0, op2) into a CMN instruction ?
     Opcode = AArch64ISD::ADDS;
     RHS = RHS.getOperand(1);
   } else if (LHS.getOpcode() == ISD::AND && isNullConstant(RHS) &&
              !isUnsignedIntSetCC(CC)) {
     // Similarly, (CMP (and X, Y), 0) can be implemented with a TST
     // (a.k.a. ANDS) except that the flags are only guaranteed to work for one
     // of the signed comparisons.
     Opcode = AArch64ISD::ANDS;
if (!isConjunctionDisjunctionTree(Val, CanNegate))
     return SDValue();
 
   return emitConjunctionDisjunctionTreeRec(DAG, Val, OutCC, false, SDValue(),
                                            AArch64CC::AL);
 }
 
 /// @}
 
+/// Returns how profitable it is to fold a comparison's operand's shift and/or
+/// extension operations.
+static unsigned getCmpOperandFoldingProfit(SDValue Op) {
+  auto isSupportedExtend = [&](SDValue V) {
+    if (V.getOpcode() == ISD::SIGN_EXTEND_INREG)
+      return true;
+
+    if (V.getOpcode() == ISD::AND)
+      if (ConstantSDNode *MaskCst = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
+        uint64_t Mask = MaskCst->getZExtValue();
+        return (Mask == 0xFF || Mask == 0xFFFF || Mask == 0xFFFFFFFF);
+      }
+
+    return false;
+  };
+
+  if (!Op.hasOneUse())
+    return 0;
+
+  if (isSupportedExtend(Op))
+    return 1;
+
+  unsigned Opc = Op.getOpcode();
+  if (Opc == ISD::SHL || Opc == ISD::SRL || Opc == ISD::SRA)
+    if (ConstantSDNode *ShiftCst = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
+      uint64_t Shift = ShiftCst->getZExtValue();
+      if (isSupportedExtend(Op.getOperand(0)))
+        return (Shift <= 4) ? 2 : 1;
+      EVT VT = Op.getValueType();
+      if ((VT == MVT::i32 && Shift <= 31) || (VT == MVT::i64 && Shift <= 63))
+        return 1;
+    }
+
+  return 0;
+}
+
 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
                              SDValue &AArch64cc, SelectionDAG &DAG,
                              const SDLoc &dl) {
   if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
     EVT VT = RHS.getValueType();
     uint64_t C = RHSC->getZExtValue();
     if (!isLegalArithImmed(C)) {
       // Constant does not fit, try adjusting it by one?
if (!isLegalArithImmed(C)) {
           CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
           C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
           RHS = DAG.getConstant(C, dl, VT);
         }
         break;
       }
     }
   }
+
+  // Comparisons are canonicalized so that the RHS operand is simpler than the
+  // LHS one, the extreme case being when RHS is an immediate. However, AArch64
+  // can fold some shift+extend operations on the RHS operand, so swap the
+  // operands if that can be done.
+  //
+  // For example:
+  //    lsl     w13, w11, #1
+  //    cmp     w13, w12
+  // can be turned into:
+  //    cmp     w12, w11, lsl #1
+  if (!isa<ConstantSDNode>(RHS) ||
+      !isLegalArithImmed(cast<ConstantSDNode>(RHS)->getZExtValue())) {
+    SDValue TheLHS = isCMN(LHS, CC) ? LHS.getOperand(1) : LHS;
+
+    if (getCmpOperandFoldingProfit(TheLHS) > getCmpOperandFoldingProfit(RHS)) {
+      std::swap(LHS, RHS);
+      CC = ISD::getSetCCSwappedOperands(CC);
+    }
+  }
+
   SDValue Cmp;
   AArch64CC::CondCode AArch64CC;
   if ((CC == ISD::SETEQ || CC == ISD::SETNE) && isa<ConstantSDNode>(RHS)) {
     const ConstantSDNode *RHSC = cast<ConstantSDNode>(RHS);
 
     // The imm operand of ADDS is an unsigned immediate, in the range 0 to 4095.
     // For the i8 operand, the largest immediate is 255, so this can be easily
     // encoded in the compare instruction. For the i16 operand, however, the

test/CodeGen/AArch64/and-mask-removal.ll

entry:
   %0 = add i16 %x, 16882
   %1 = icmp ule i16 %0, -24837
   br i1 %1, label %ret_true, label %ret_false
 ret_false:
   ret i1 false
 ret_true:
   ret i1 true
 ; CHECK-LABEL: test16_2
-; CHECK: and
+; CHECK: mov  [[CST:w[0-9]+]], #16882
+; CHECK: add  [[ADD:w[0-9]+]], w0, [[CST]]
+; CHECK: cmp  {{.*}}, [[ADD]], uxth
 ; CHECK: ret
 }
 
 define zeroext i1 @test16_3(i16 zeroext %x)  align 2 {
 entry:
   %0 = add i16 %x, 29283
   %1 = icmp ne i16 %0, 16947
   br i1 %1, label %ret_true, label %ret_false
entry:
   %0 = add i16 %x, -35551
   %1 = icmp uge i16 %0, 15677
   br i1 %1, label %ret_true, label %ret_false
 ret_false:
   ret i1 false
 ret_true:
   ret i1 true
 ; CHECK-LABEL: test16_4
-; CHECK: and
+; CHECK: mov  [[CST:w[0-9]+]], #29985
+; CHECK: add  [[ADD:w[0-9]+]], w0, [[CST]]
+; CHECK: cmp  {{.*}}, [[ADD]], uxth
 ; CHECK: ret
 }
 
 define zeroext i1 @test16_5(i16 zeroext %x)  align 2 {
 entry:
   %0 = add i16 %x, -25214
   %1 = icmp ne i16 %0, -1932
   br i1 %1, label %ret_true, label %ret_false
entry:
   %0 = add i16 %x, 9272
   %1 = icmp uge i16 %0, -42916
   br i1 %1, label %ret_true, label %ret_false
 ret_false:
   ret i1 false
 ret_true:
   ret i1 true
 ; CHECK-LABEL: test16_7
-; CHECK: and
+; CHECK: mov  [[CST:w[0-9]+]], #9272
+; CHECK: add  [[ADD:w[0-9]+]], w0, [[CST]]
+; CHECK: cmp  {{.*}}, [[ADD]], uxth
 ; CHECK: ret
 }
 
 define zeroext i1 @test16_8(i16 zeroext %x)  align 2 {
 entry:
   %0 = add i16 %x, -63749
   %1 = icmp ne i16 %0, 6706
   br i1 %1, label %ret_true, label %ret_false

test/CodeGen/AArch64/lack-of-signed-truncation-check.ll

; CHECK-NEXT:    ret
   %tmp1 = ashr exact i16 %tmp0, 8 ; 16-8
   %tmp2 = icmp ne i16 %tmp1, %x
   ret i1 %tmp2
 }
 
 define i1 @shifts_necmp_i32_i16(i32 %x) nounwind {
 ; CHECK-LABEL: shifts_necmp_i32_i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sxth w8, w0
-; CHECK-NEXT:    cmp w8, w0
+; CHECK-NEXT:    cmp w0, w0, sxth
 ; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret
   %tmp0 = shl i32 %x, 16 ; 32-16
   %tmp1 = ashr exact i32 %tmp0, 16 ; 32-16
   %tmp2 = icmp ne i32 %tmp1, %x
   ret i1 %tmp2
 }
 
 define i1 @shifts_necmp_i32_i8(i32 %x) nounwind {
 ; CHECK-LABEL: shifts_necmp_i32_i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sxtb w8, w0
-; CHECK-NEXT:    cmp w8, w0
+; CHECK-NEXT:    cmp w0, w0, sxtb
 ; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret
   %tmp0 = shl i32 %x, 24 ; 32-8
   %tmp1 = ashr exact i32 %tmp0, 24 ; 32-8
   %tmp2 = icmp ne i32 %tmp1, %x
   ret i1 %tmp2
 }
 
 define i1 @shifts_necmp_i64_i32(i64 %x) nounwind {
 ; CHECK-LABEL: shifts_necmp_i64_i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sxtw x8, w0
-; CHECK-NEXT:    cmp x8, x0
+; CHECK-NEXT:    cmp x0, w0, sxtw
 ; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret
   %tmp0 = shl i64 %x, 32 ; 64-32
   %tmp1 = ashr exact i64 %tmp0, 32 ; 64-32
   %tmp2 = icmp ne i64 %tmp1, %x
   ret i1 %tmp2
 }
 
 define i1 @shifts_necmp_i64_i16(i64 %x) nounwind {
 ; CHECK-LABEL: shifts_necmp_i64_i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sxth x8, w0
-; CHECK-NEXT:    cmp x8, x0
+; CHECK-NEXT:    cmp x0, w0, sxth
 ; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret
   %tmp0 = shl i64 %x, 48 ; 64-16
   %tmp1 = ashr exact i64 %tmp0, 48 ; 64-16
   %tmp2 = icmp ne i64 %tmp1, %x
   ret i1 %tmp2
 }
 
 define i1 @shifts_necmp_i64_i8(i64 %x) nounwind {
 ; CHECK-LABEL: shifts_necmp_i64_i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sxtb x8, w0
-; CHECK-NEXT:    cmp x8, x0
+; CHECK-NEXT:    cmp x0, w0, sxtb
 ; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret
   %tmp0 = shl i64 %x, 56 ; 64-8
   %tmp1 = ashr exact i64 %tmp0, 56 ; 64-8
   %tmp2 = icmp ne i64 %tmp1, %x
   ret i1 %tmp2
 }
 
; CHECK-NEXT:    ret
   %tmp0 = add i16 %x, -128 ; ~0U << (8-1)
   %tmp1 = icmp ult i16 %tmp0, -256 ; ~0U << 8
   ret i1 %tmp1
 }
 
 define i1 @add_ultcmp_i32_i16(i32 %x) nounwind {
 ; CHECK-LABEL: add_ultcmp_i32_i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sxth w8, w0
-; CHECK-NEXT:    cmp w8, w0
+; CHECK-NEXT:    cmp w0, w0, sxth
 ; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret
   %tmp0 = add i32 %x, -32768 ; ~0U << (16-1)
   %tmp1 = icmp ult i32 %tmp0, -65536 ; ~0U << 16
   ret i1 %tmp1
 }
 
 define i1 @add_ultcmp_i32_i8(i32 %x) nounwind {
 ; CHECK-LABEL: add_ultcmp_i32_i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sxtb w8, w0
-; CHECK-NEXT:    cmp w8, w0
+; CHECK-NEXT:    cmp w0, w0, sxtb
 ; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret
   %tmp0 = add i32 %x, -128 ; ~0U << (8-1)
   %tmp1 = icmp ult i32 %tmp0, -256 ; ~0U << 8
   ret i1 %tmp1
 }
 
 define i1 @add_ultcmp_i64_i32(i64 %x) nounwind {
 ; CHECK-LABEL: add_ultcmp_i64_i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sxtw x8, w0
-; CHECK-NEXT:    cmp x8, x0
+; CHECK-NEXT:    cmp x0, w0, sxtw
 ; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret
   %tmp0 = add i64 %x, -2147483648 ; ~0U << (32-1)
   %tmp1 = icmp ult i64 %tmp0, -4294967296 ; ~0U << 32
   ret i1 %tmp1
 }
 
 define i1 @add_ultcmp_i64_i16(i64 %x) nounwind {
 ; CHECK-LABEL: add_ultcmp_i64_i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sxth x8, w0
-; CHECK-NEXT:    cmp x8, x0
+; CHECK-NEXT:    cmp x0, w0, sxth
 ; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret
   %tmp0 = add i64 %x, -32768 ; ~0U << (16-1)
   %tmp1 = icmp ult i64 %tmp0, -65536 ; ~0U << 16
   ret i1 %tmp1
 }
 
 define i1 @add_ultcmp_i64_i8(i64 %x) nounwind {
 ; CHECK-LABEL: add_ultcmp_i64_i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sxtb x8, w0
-; CHECK-NEXT:    cmp x8, x0
+; CHECK-NEXT:    cmp x0, w0, sxtb
 ; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret
   %tmp0 = add i64 %x, -128 ; ~0U << (8-1)
   %tmp1 = icmp ult i64 %tmp0, -256 ; ~0U << 8
   ret i1 %tmp1
 }
 
 ; Slightly more canonical variant
; CHECK-NEXT:    ret
   %tmp0 = add i16 %x, 128 ; 1U << (8-1)
   %tmp1 = icmp uge i16 %tmp0, 256 ; 1U << 8
   ret i1 %tmp1
 }
 
 define i1 @add_ugecmp_i32_i16(i32 %x) nounwind {
 ; CHECK-LABEL: add_ugecmp_i32_i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sxth w8, w0
-; CHECK-NEXT:    cmp w8, w0
+; CHECK-NEXT:    cmp w0, w0, sxth
 ; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret
   %tmp0 = add i32 %x, 32768 ; 1U << (16-1)
   %tmp1 = icmp uge i32 %tmp0, 65536 ; 1U << 16
   ret i1 %tmp1
 }
 
 define i1 @add_ugecmp_i32_i8(i32 %x) nounwind {
 ; CHECK-LABEL: add_ugecmp_i32_i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sxtb w8, w0
-; CHECK-NEXT:    cmp w8, w0
+; CHECK-NEXT:    cmp w0, w0, sxtb
 ; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret
   %tmp0 = add i32 %x, 128 ; 1U << (8-1)
   %tmp1 = icmp uge i32 %tmp0, 256 ; 1U << 8
   ret i1 %tmp1
 }
 
 define i1 @add_ugecmp_i64_i32(i64 %x) nounwind {
 ; CHECK-LABEL: add_ugecmp_i64_i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sxtw x8, w0
-; CHECK-NEXT:    cmp x8, x0
+; CHECK-NEXT:    cmp x0, w0, sxtw
 ; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret
   %tmp0 = add i64 %x, 2147483648 ; 1U << (32-1)
   %tmp1 = icmp uge i64 %tmp0, 4294967296 ; 1U << 32
   ret i1 %tmp1
 }
 
 define i1 @add_ugecmp_i64_i16(i64 %x) nounwind {
 ; CHECK-LABEL: add_ugecmp_i64_i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sxth x8, w0
-; CHECK-NEXT:    cmp x8, x0
+; CHECK-NEXT:    cmp x0, w0, sxth
 ; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret
   %tmp0 = add i64 %x, 32768 ; 1U << (16-1)
   %tmp1 = icmp uge i64 %tmp0, 65536 ; 1U << 16
   ret i1 %tmp1
 }
 
 define i1 @add_ugecmp_i64_i8(i64 %x) nounwind {
 ; CHECK-LABEL: add_ugecmp_i64_i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sxtb x8, w0
-; CHECK-NEXT:    cmp x8, x0
+; CHECK-NEXT:    cmp x0, w0, sxtb
 ; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret
   %tmp0 = add i64 %x, 128 ; 1U << (8-1)
   %tmp1 = icmp uge i64 %tmp0, 256 ; 1U << 8
   ret i1 %tmp1
 }
 
 ; Slightly more canonical variant

test/CodeGen/AArch64/sat-add.ll

; CHECK-NEXT:    ret
   %c = icmp ugt i8 %x, -43
   %r = select i1 %c, i8 -1, i8 %a
   ret i8 %r
 }
 
 define i16 @unsigned_sat_constant_i16_using_min(i16 %x) {
 ; CHECK-LABEL: unsigned_sat_constant_i16_using_min:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    and w8, w0, #0xffff
-; CHECK-NEXT:    mov w9, #65493
-; CHECK-NEXT:    cmp w8, w9
+; CHECK-NEXT:    mov w8, #65493
+; CHECK-NEXT:    cmp w8, w0, uxth
 ; CHECK-NEXT:    mov w8, #-43
-; CHECK-NEXT:    csel w8, w0, w8, lo
+; CHECK-NEXT:    csel w8, w0, w8, hi
 ; CHECK-NEXT:    add w0, w8, #42 // =42
 ; CHECK-NEXT:    ret
   %c = icmp ult i16 %x, -43
   %s = select i1 %c, i16 %x, i16 -43
   %r = add i16 %s, 42
   ret i16 %r
 }
 
; CHECK-NEXT:    ret
   %c = icmp ugt i16 %x, %a
   %r = select i1 %c, i16 -1, i16 %a
   ret i16 %r
 }
 
 define i16 @unsigned_sat_constant_i16_using_cmp_notval(i16 %x) {
 ; CHECK-LABEL: unsigned_sat_constant_i16_using_cmp_notval:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    and w8, w0, #0xffff
-; CHECK-NEXT:    mov w10, #65493
-; CHECK-NEXT:    add w9, w0, #42 // =42
-; CHECK-NEXT:    cmp w8, w10
-; CHECK-NEXT:    csinv w0, w9, wzr, ls
+; CHECK-NEXT:    mov w9, #65493
+; CHECK-NEXT:    add w8, w0, #42 // =42
+; CHECK-NEXT:    cmp w9, w0, uxth
+; CHECK-NEXT:    csinv w0, w8, wzr, hs
 ; CHECK-NEXT:    ret
   %a = add i16 %x, 42
   %c = icmp ugt i16 %x, -43
   %r = select i1 %c, i16 -1, i16 %a
   ret i16 %r
 }
 
 define i32 @unsigned_sat_constant_i32_using_min(i32 %x) {

test/CodeGen/AArch64/signed-truncation-check.ll

; CHECK-NEXT:    ret
   %tmp1 = ashr exact i16 %tmp0, 8 ; 16-8
   %tmp2 = icmp eq i16 %tmp1, %x
   ret i1 %tmp2
 }
 
 define i1 @shifts_eqcmp_i32_i16(i32 %x) nounwind {
 ; CHECK-LABEL: shifts_eqcmp_i32_i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sxth w8, w0
-; CHECK-NEXT:    cmp w8, w0
+; CHECK-NEXT:    cmp w0, w0, sxth
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %tmp0 = shl i32 %x, 16 ; 32-16
   %tmp1 = ashr exact i32 %tmp0, 16 ; 32-16
   %tmp2 = icmp eq i32 %tmp1, %x
   ret i1 %tmp2
 }
 
 define i1 @shifts_eqcmp_i32_i8(i32 %x) nounwind {
 ; CHECK-LABEL: shifts_eqcmp_i32_i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sxtb w8, w0
-; CHECK-NEXT:    cmp w8, w0
+; CHECK-NEXT:    cmp w0, w0, sxtb
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %tmp0 = shl i32 %x, 24 ; 32-8
   %tmp1 = ashr exact i32 %tmp0, 24 ; 32-8
   %tmp2 = icmp eq i32 %tmp1, %x
   ret i1 %tmp2
 }
 
 define i1 @shifts_eqcmp_i64_i32(i64 %x) nounwind {
 ; CHECK-LABEL: shifts_eqcmp_i64_i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sxtw x8, w0
-; CHECK-NEXT:    cmp x8, x0
+; CHECK-NEXT:    cmp x0, w0, sxtw
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %tmp0 = shl i64 %x, 32 ; 64-32
   %tmp1 = ashr exact i64 %tmp0, 32 ; 64-32
   %tmp2 = icmp eq i64 %tmp1, %x
   ret i1 %tmp2
 }
 
 define i1 @shifts_eqcmp_i64_i16(i64 %x) nounwind {
 ; CHECK-LABEL: shifts_eqcmp_i64_i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sxth x8, w0
-; CHECK-NEXT:    cmp x8, x0
+; CHECK-NEXT:    cmp x0, w0, sxth
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %tmp0 = shl i64 %x, 48 ; 64-16
   %tmp1 = ashr exact i64 %tmp0, 48 ; 64-16
   %tmp2 = icmp eq i64 %tmp1, %x
   ret i1 %tmp2
 }
 
 define i1 @shifts_eqcmp_i64_i8(i64 %x) nounwind {
 ; CHECK-LABEL: shifts_eqcmp_i64_i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sxtb x8, w0
-; CHECK-NEXT:    cmp x8, x0
+; CHECK-NEXT:    cmp x0, w0, sxtb
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %tmp0 = shl i64 %x, 56 ; 64-8
   %tmp1 = ashr exact i64 %tmp0, 56 ; 64-8
   %tmp2 = icmp eq i64 %tmp1, %x
   ret i1 %tmp2
 }
 
; CHECK-NEXT:    ret
   %tmp0 = add i16 %x, -128 ; ~0U << (8-1)
   %tmp1 = icmp uge i16 %tmp0, -256 ; ~0U << 8
   ret i1 %tmp1
 }
 
 define i1 @add_ugecmp_i32_i16(i32 %x) nounwind {
 ; CHECK-LABEL: add_ugecmp_i32_i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sxth w8, w0
-; CHECK-NEXT:    cmp w8, w0
+; CHECK-NEXT:    cmp w0, w0, sxth
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %tmp0 = add i32 %x, -32768 ; ~0U << (16-1)
   %tmp1 = icmp uge i32 %tmp0, -65536 ; ~0U << 16
   ret i1 %tmp1
 }
 
 define i1 @add_ugecmp_i32_i8(i32 %x) nounwind {
 ; CHECK-LABEL: add_ugecmp_i32_i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sxtb w8, w0
-; CHECK-NEXT:    cmp w8, w0
+; CHECK-NEXT:    cmp w0, w0, sxtb
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %tmp0 = add i32 %x, -128 ; ~0U << (8-1)
   %tmp1 = icmp uge i32 %tmp0, -256 ; ~0U << 8
   ret i1 %tmp1
 }
 
 define i1 @add_ugecmp_i64_i32(i64 %x) nounwind {
 ; CHECK-LABEL: add_ugecmp_i64_i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sxtw x8, w0
-; CHECK-NEXT:    cmp x8, x0
+; CHECK-NEXT:    cmp x0, w0, sxtw
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %tmp0 = add i64 %x, -2147483648 ; ~0U << (32-1)
   %tmp1 = icmp uge i64 %tmp0, -4294967296 ; ~0U << 32
   ret i1 %tmp1
 }
 
 define i1 @add_ugecmp_i64_i16(i64 %x) nounwind {
 ; CHECK-LABEL: add_ugecmp_i64_i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sxth x8, w0
-; CHECK-NEXT:    cmp x8, x0
+; CHECK-NEXT:    cmp x0, w0, sxth
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %tmp0 = add i64 %x, -32768 ; ~0U << (16-1)
   %tmp1 = icmp uge i64 %tmp0, -65536 ; ~0U << 16
   ret i1 %tmp1
 }
 
 define i1 @add_ugecmp_i64_i8(i64 %x) nounwind {
 ; CHECK-LABEL: add_ugecmp_i64_i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sxtb x8, w0
-; CHECK-NEXT:    cmp x8, x0
+; CHECK-NEXT:    cmp x0, w0, sxtb
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %tmp0 = add i64 %x, -128 ; ~0U << (8-1)
   %tmp1 = icmp uge i64 %tmp0, -256 ; ~0U << 8
   ret i1 %tmp1
 }
 
 ; Slightly more canonical variant
; CHECK-NEXT:    ret
   %tmp0 = add i16 %x, 128 ; 1U << (8-1)
   %tmp1 = icmp ult i16 %tmp0, 256 ; 1U << 8
   ret i1 %tmp1
 }
 
 define i1 @add_ultcmp_i32_i16(i32 %x) nounwind {
 ; CHECK-LABEL: add_ultcmp_i32_i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sxth w8, w0
-; CHECK-NEXT:    cmp w8, w0
+; CHECK-NEXT:    cmp w0, w0, sxth
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %tmp0 = add i32 %x, 32768 ; 1U << (16-1)
   %tmp1 = icmp ult i32 %tmp0, 65536 ; 1U << 16
   ret i1 %tmp1
 }
 
 define i1 @add_ultcmp_i32_i8(i32 %x) nounwind {
 ; CHECK-LABEL: add_ultcmp_i32_i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sxtb w8, w0
-; CHECK-NEXT:    cmp w8, w0
+; CHECK-NEXT:    cmp w0, w0, sxtb
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %tmp0 = add i32 %x, 128 ; 1U << (8-1)
   %tmp1 = icmp ult i32 %tmp0, 256 ; 1U << 8
   ret i1 %tmp1
 }
 
 define i1 @add_ultcmp_i64_i32(i64 %x) nounwind {
 ; CHECK-LABEL: add_ultcmp_i64_i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sxtw x8, w0
-; CHECK-NEXT:    cmp x8, x0
+; CHECK-NEXT:    cmp x0, w0, sxtw
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %tmp0 = add i64 %x, 2147483648 ; 1U << (32-1)
   %tmp1 = icmp ult i64 %tmp0, 4294967296 ; 1U << 32
   ret i1 %tmp1
 }
 
 define i1 @add_ultcmp_i64_i16(i64 %x) nounwind {
 ; CHECK-LABEL: add_ultcmp_i64_i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sxth x8, w0
-; CHECK-NEXT:    cmp x8, x0
+; CHECK-NEXT:    cmp x0, w0, sxth
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %tmp0 = add i64 %x, 32768 ; 1U << (16-1)
   %tmp1 = icmp ult i64 %tmp0, 65536 ; 1U << 16
   ret i1 %tmp1
 }
 
 define i1 @add_ultcmp_i64_i8(i64 %x) nounwind {
 ; CHECK-LABEL: add_ultcmp_i64_i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sxtb x8, w0
-; CHECK-NEXT:    cmp x8, x0
+; CHECK-NEXT:    cmp x0, w0, sxtb
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %tmp0 = add i64 %x, 128 ; 1U << (8-1)
   %tmp1 = icmp ult i64 %tmp0, 256 ; 1U << 8
   ret i1 %tmp1
 }
 
 ; Slightly more canonical variant

test/CodeGen/AArch64/swap-compare-operands.ll

+; RUN: llc < %s -mtriple=arm64 | FileCheck %s
+
+define i64 @testSwapCmpWithLSL(i64 %a, i64 %b, i64 %c, i64 %d) {
+; CHECK-LABEL testSwapCmpWithLSL:
+; CHECK:      cmp     x1, x0, lsl #10
+; CHECK-NEXT: csel    x0, x2, x3, gt
+entry:
+  %shl = shl i64 %a, 10
+  %cmp = icmp slt i64 %shl, %b
+  %retval = select i1 %cmp, i64 %c, i64 %d
+  ret i64 %retval
+}
+
+define i64 @testSwapCmpWithLSR(i64 %a, i64 %b, i64 %c, i64 %d) {
+; CHECK-LABEL testSwapCmpWithLSR:
+; CHECK:      cmp     x1, x0, lsr #5
+; CHECK-NEXT: csel    x0, x2, x3, gt
+entry:
+  %lshr = lshr i64 %a, 5
+  %cmp = icmp slt i64 %lshr, %b
+  %retval = select i1 %cmp, i64 %c, i64 %d
+  ret i64 %retval
+}
+
+define i64 @testSwapCmpWithASR(i64 %a, i64 %b, i64 %c, i64 %d) {
+; CHECK-LABEL testSwapCmpWithASR:
+; CHECK:      cmp     x1, x0, asr #7
+; CHECK-NEXT: csel    x0, x2, x3, gt
+entry:
+  %ashr = ashr i64 %a, 7
+  %cmp = icmp slt i64 %ashr, %b
+  %retval = select i1 %cmp, i64 %c, i64 %d
+  ret i64 %retval
+}
+
+define i1 @testSwapCmpWithShiftedZeroExtend32_64(i32 %a, i64 %b) {
+; CHECK-LABEL testSwapCmpWithShiftedZeroExtend32_64
+; CHECK:      cmp    x1, w0, uxtw #2
+; CHECK-NEXT: cset   w0, lo
+entry:
+  %a64 = zext i32 %a to i64
+  %shl.0 = shl i64 %a64, 2
+  %cmp = icmp ugt i64 %shl.0, %b
+  ret i1 %cmp
+}
+
+define i1 @testSwapCmpWithShiftedZeroExtend16_64(i16 %a, i64 %b) {
+; CHECK-LABEL testSwapCmpWithShiftedZeroExtend16_64
+; CHECK:      cmp    x1, w0, uxth #2
+; CHECK-NEXT: cset   w0, lo
+entry:
+  %a64 = zext i16 %a to i64
+  %shl.0 = shl i64 %a64, 2
+  %cmp = icmp ugt i64 %shl.0, %b
+  ret i1 %cmp
+}
+
+define i1 @testSwapCmpWithShiftedZeroExtend8_64(i8 %a, i64 %b) {
+; CHECK-LABEL testSwapCmpWithShiftedZeroExtend8_64
+; CHECK:      cmp    x1, w0, uxtb #4
+; CHECK-NEXT: cset    w0, lo
+entry:
+  %a64 = zext i8 %a to i64
+  %shl.2 = shl i64 %a64, 4
+  %cmp = icmp ugt i64 %shl.2, %b
+  ret i1 %cmp
+}
+
+define i1 @testSwapCmpWithShiftedZeroExtend16_32(i16 %a, i32 %b) {
+; CHECK-LABEL testSwapCmpWithShiftedZeroExtend8_64
+; CHECK:      cmp    w1, w0, uxth #3
+; CHECK-NEXT: cset    w0, lo
+entry:
+  %a32 = zext i16 %a to i32
+  %shl = shl i32 %a32, 3
+  %cmp = icmp ugt i32 %shl, %b
+  ret i1 %cmp
+}
+
+define i1 @testSwapCmpWithShiftedZeroExtend8_32(i8 %a, i32 %b) {
+; CHECK-LABEL testSwapCmpWithShiftedZeroExtend8_64
+; CHECK:      cmp    w1, w0, uxtb #4
+; CHECK-NEXT: cset    w0, lo
+entry:
+  %a32 = zext i8 %a to i32
+  %shl = shl i32 %a32, 4
+  %cmp = icmp ugt i32 %shl, %b
+  ret i1 %cmp
+}
+
+define i1 @testSwapCmpWithTooLargeShiftedZeroExtend8_32(i8 %a, i32 %b) {
+; CHECK-LABEL testSwapCmpWithTooLargeShiftedZeroExtend8_64
+; CHECK:      and    [[REG:w[0-9]+]], w0, #0xff
+; CHECK:      cmp    w1, [[REG]], lsl #5
+; CHECK-NEXT: cset   w0, lo
+entry:
+  %a32 = zext i8 %a to i32
+  %shl = shl i32 %a32, 5
+  %cmp = icmp ugt i32 %shl, %b
+  ret i1 %cmp
+}
+
+define i1 @testSwapCmpWithZeroExtend8_32(i8 %a, i32 %b) {
+; CHECK-LABEL testSwapCmpWithZeroExtend8_64
+; CHECK:      cmp    w1, w0, uxtb
+; CHECK-NEXT: cset   w0, lo
+entry:
+  %a32 = zext i8 %a to i32
+  %cmp = icmp ugt i32 %a32, %b
+  ret i1 %cmp
+}
+
+define i1 @testSwapCmpWithShiftedSignExtend32_64(i32 %a, i64 %b) {
+; CHECK-LABEL testSwapCmpWithShiftedZeroExtend32_64
+; CHECK:      cmp    x1, w0, sxtw #2
+; CHECK-NEXT: cset   w0, lo
+entry:
+  %a64 = sext i32 %a to i64
+  %shl.0 = shl i64 %a64, 2
+  %cmp = icmp ugt i64 %shl.0, %b
+  ret i1 %cmp
+}
+
+define i1 @testSwapCmpWithShiftedSignExtend16_64(i16 %a, i64 %b) {
+; CHECK-LABEL testSwapCmpWithShiftedZeroExtend16_64
+; CHECK:      cmp    x1, w0, sxth #2
+; CHECK-NEXT: cset   w0, lo
+entry:
+  %a64 = sext i16 %a to i64
+  %shl.0 = shl i64 %a64, 2
+  %cmp = icmp ugt i64 %shl.0, %b
+  ret i1 %cmp
+}
+
+define i1 @testSwapCmpWithShiftedSignExtend8_64(i8 %a, i64 %b) {
+; CHECK-LABEL testSwapCmpWithShiftedSignExtend8_64
+; CHECK:      cmp    x1, w0, sxtb #4
+; CHECK-NEXT: cset    w0, lo
+entry:
+  %a64 = sext i8 %a to i64
+  %shl.2 = shl i64 %a64, 4
+  %cmp = icmp ugt i64 %shl.2, %b
+  ret i1 %cmp
+}
+
+define i1 @testSwapCmpWithShiftedSignExtend16_32(i16 %a, i32 %b) {
+; CHECK-LABEL testSwapCmpWithShiftedSignExtend8_64
+; CHECK:      cmp    w1, w0, sxth #3
+; CHECK-NEXT: cset    w0, lo
+entry:
+  %a32 = sext i16 %a to i32
+  %shl = shl i32 %a32, 3
+  %cmp = icmp ugt i32 %shl, %b
+  ret i1 %cmp
+}
+
+define i1 @testSwapCmpWithShiftedSignExtend8_32(i8 %a, i32 %b) {
+; CHECK-LABEL testSwapCmpWithShiftedSignExtend8_64
+; CHECK:      cmp    w1, w0, sxtb #4
+; CHECK-NEXT: cset   w0, lo
+entry:
+  %a32 = sext i8 %a to i32
+  %shl = shl i32 %a32, 4
+  %cmp = icmp ugt i32 %shl, %b
+  ret i1 %cmp
+}
+
+define i1 @testSwapCmpWithTooLargeShiftedSignExtend8_32(i8 %a, i32 %b) {
+; CHECK-LABEL testSwapCmpWithTooLargeShiftedSignExtend8_64
+; CHECK:      sxtb   [[REG:w[0-9]+]], w0
+; CHECK-NEXT: cmp    w1, [[REG]], lsl #5
+; CHECK-NEXT: cset   w0, lo
+entry:
+  %a32 = sext i8 %a to i32
+  %shl = shl i32 %a32, 5
+  %cmp = icmp ugt i32 %shl, %b
+  ret i1 %cmp
+}
+
+define i1 @testSwapCmpWithSignExtend8_32(i8 %a, i32 %b) {
+; CHECK-LABEL testSwapCmpWithSignExtend8_64
+; CHECK:      cmp    w1, w0, sxtb
+; CHECK-NEXT: cset   w0, lo
+entry:
+  %a32 = sext i8 %a to i32
+  %cmp = icmp ugt i32 %a32, %b
+  ret i1 %cmp
+}
+
+define i64 @testSwapCmnWithLSL(i64 %a, i64 %b, i64 %c, i64 %d) {
+; CHECK-LABEL testSwapCmnWithLSL:
+; CHECK: cmn    x1, x0, lsl #10
+entry:
+  %shl = shl i64 %a, 10
+  %na = sub i64 0, %shl
+  %cmp = icmp ne i64 %na, %b
+  %add = add nsw i64 %d, %c
+  %mul = mul nsw i64 %d, %c
+  %retval = select i1 %cmp, i64 %add, i64 %mul
+  ret i64 %retval
+}
+
+define i64 @testSwapCmnWithLSR(i64 %a, i64 %b, i64 %c, i64 %d) {
+; CHECK-LABEL testSwapCmnWithLSR:
+; CHECK: cmn    x1, x0, lsr #5
+entry:
+  %lshr = lshr i64 %a, 5
+  %na = sub i64 0, %lshr
+  %cmp = icmp ne i64 %na, %b
+  %add = add nsw i64 %d, %c
+  %mul = mul nsw i64 %d, %c
+  %retval = select i1 %cmp, i64 %add, i64 %mul
+  ret i64 %retval
+}
+
+define i64 @testSwapCmnWithASR(i64 %a, i64 %b, i64 %c, i64 %d) {
+; CHECK-LABEL testSwapCmnWithASR:
+; CHECK: cmn    x1, x0, asr #3
+entry:
+  %lshr = ashr i64 %a, 3
+  %na = sub i64 0, %lshr
+  %cmp = icmp ne i64 %na, %b
+  %add = add nsw i64 %d, %c
+  %mul = mul nsw i64 %d, %c
+  %retval = select i1 %cmp, i64 %add, i64 %mul
+  ret i64 %retval
+}
+
+define i64 @testSwapCmpToCmnWithZeroExtend(i32 %a32, i16 %a16, i8 %a8, i64 %b64, i32 %b32) {
+; CHECK-LABEL testSwapCmpToCmnWithZeroExtend:
+t0:
+  %conv0 = zext i32 %a32 to i64
+  %shl0 = shl i64 %conv0, 1
+  %na0 = sub i64 0, %shl0
+  %cmp0 = icmp ne i64 %na0, %b64
+; CHECK: cmn    x3, w0, uxtw #1
+  br i1 %cmp0, label %t1, label %end
+
+t1:
+  %conv1 = zext i16 %a16 to i64
+  %shl1 = shl i64 %conv1, 4
+  %na1 = sub i64 0, %shl1
+  %cmp1 = icmp ne i64 %na1, %b64
+; CHECK: cmn    x3, w1, uxth #4
+  br i1 %cmp1, label %t2, label %end
+
+t2:
+  %conv2 = zext i8 %a8 to i64
+  %shl2 = shl i64 %conv2, 3
+  %na2 = sub i64 0, %shl2
+  %cmp2 = icmp ne i64 %na2, %b64
+; CHECK: cmn    x3, w2, uxtb #3
+  br i1 %cmp2, label %t3, label %end
+
+t3:
+  %conv3 = zext i16 %a16 to i32
+  %shl3 = shl i32 %conv3, 2
+  %na3 = sub i32 0, %shl3
+  %cmp3 = icmp ne i32 %na3, %b32
+; CHECK: cmn    w4, w1, uxth #2
+  br i1 %cmp3, label %t4, label %end
+
+t4:
+  %conv4 = zext i8 %a8 to i32
+  %shl4 = shl i32 %conv4, 1
+  %na4 = sub i32 0, %shl4
+  %cmp4 = icmp ne i32 %na4, %b32
+; CHECK: cmn    w4, w2, uxtb #1
+  br i1 %cmp4, label %t5, label %end
+
+t5:
+  %conv5 = zext i8 %a8 to i32
+  %shl5 = shl i32 %conv5, 5
+  %na5 = sub i32 0, %shl5
+  %cmp5 = icmp ne i32 %na5, %b32
+; CHECK: and    [[REG:w[0-9]+]], w2, #0xff
+; CHECK: cmn    w4, [[REG]], lsl #5
+  br i1 %cmp5, label %t6, label %end
+
+t6:
+  %conv6 = zext i8 %a8 to i32
+  %na6 = sub i32 0, %conv6
+  %cmp6 = icmp ne i32 %na6, %b32
+; CHECK: cmn    w4, w2, uxtb
+  br i1 %cmp6, label %t7, label %end
+
+t7:
+  ret i64 0
+
+end:
+  ret i64 1
+}
+define i64 @testSwapCmpToCmnWithSignExtend(i32 %a32, i16 %a16, i8 %a8, i64 %b64, i32 %b32) {
+; CHECK-LABEL testSwapCmpToCmnWithSignExtend:
+t0:
+  %conv0 = sext i32 %a32 to i64
+  %shl0 = shl i64 %conv0, 1
+  %na0 = sub i64 0, %shl0
+  %cmp0 = icmp ne i64 %na0, %b64
+; CHECK: cmn     x3, w0, sxtw #1
+  br i1 %cmp0, label %t1, label %end
+
+t1:
+  %conv1 = sext i16 %a16 to i64
+  %shl1 = shl i64 %conv1, 4
+  %na1 = sub i64 0, %shl1
+  %cmp1 = icmp ne i64 %na1, %b64
+; CHECK: cmn     x3, w1, sxth #4
+  br i1 %cmp1, label %t2, label %end
+
+t2:
+  %conv2 = sext i8 %a8 to i64
+  %shl2 = shl i64 %conv2, 3
+  %na2 = sub i64 0, %shl2
+  %cmp2 = icmp ne i64 %na2, %b64
+; CHECK: cmn     x3, w2, sxtb #3
+  br i1 %cmp2, label %t3, label %end
+
+t3:
+  %conv3 = sext i16 %a16 to i32
+  %shl3 = shl i32 %conv3, 2
+  %na3 = sub i32 0, %shl3
+  %cmp3 = icmp ne i32 %na3, %b32
+; CHECK: cmn     w4, w1, sxth #2
+  br i1 %cmp3, label %t4, label %end
+
+t4:
+  %conv4 = sext i8 %a8 to i32
+  %shl4 = shl i32 %conv4, 1
+  %na4 = sub i32 0, %shl4
+  %cmp4 = icmp ne i32 %na4, %b32
+; CHECK: cmn     w4, w2, sxtb #1
+  br i1 %cmp4, label %t5, label %end
+
+t5:
+  %conv5 = sext i8 %a8 to i32
+  %shl5 = shl i32 %conv5, 5
+  %na5 = sub i32 0, %shl5
+  %cmp5 = icmp ne i32 %na5, %b32
+; CHECK: sxtb    [[REG:w[0-9]+]], w2
+; CHECK: cmn     w4, [[REG]], lsl #5
+  br i1 %cmp5, label %t6, label %end
+
+t6:
+  %conv6 = sext i8 %a8 to i32
+  %na6 = sub i32 0, %conv6
+  %cmp6 = icmp ne i32 %na6, %b32
+; CHECK: cmn     w4, w2, sxtb
+  br i1 %cmp6, label %t7, label %end
+
+t7:
+  ret i64 0
+
+end:
+  ret i64 1
+}